1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, NVIDIA Corporation.
7 #include <linux/delay.h>
8 #include <linux/host1x.h>
9 #include <linux/iommu.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/of_platform.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/reset.h>
18 #include <soc/tegra/pmc.h>
35 struct tegra_drm_client client;
36 struct host1x_channel *channel;
39 struct reset_control *rst;
41 /* Platform configuration */
42 const struct vic_config *config;
45 static inline struct vic *to_vic(struct tegra_drm_client *client)
47 return container_of(client, struct vic, client);
50 static void vic_writel(struct vic *vic, u32 value, unsigned int offset)
52 writel(value, vic->regs + offset);
55 static int vic_runtime_resume(struct device *dev)
57 struct vic *vic = dev_get_drvdata(dev);
60 err = clk_prepare_enable(vic->clk);
66 err = reset_control_deassert(vic->rst);
75 clk_disable_unprepare(vic->clk);
79 static int vic_runtime_suspend(struct device *dev)
81 struct vic *vic = dev_get_drvdata(dev);
84 err = reset_control_assert(vic->rst);
88 usleep_range(2000, 4000);
90 clk_disable_unprepare(vic->clk);
97 static int vic_boot(struct vic *vic)
99 #ifdef CONFIG_IOMMU_API
100 struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev);
102 u32 fce_ucode_size, fce_bin_data_offset;
109 #ifdef CONFIG_IOMMU_API
110 if (vic->config->supports_sid && spec) {
113 value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) |
114 TRANSCFG_ATT(0, TRANSCFG_SID_HW);
115 vic_writel(vic, value, VIC_TFBIF_TRANSCFG);
117 if (spec->num_ids > 0) {
118 value = spec->ids[0] & 0xffff;
121 * STREAMID0 is used for input/output buffers.
122 * Initialize it to SID_VIC in case context isolation
123 * is not enabled, and SID_VIC is used for both firmware
126 * If context isolation is enabled, it will be
127 * overridden by the SETSTREAMID opcode as part of
130 vic_writel(vic, value, VIC_THI_STREAMID0);
132 /* STREAMID1 is used for firmware loading. */
133 vic_writel(vic, value, VIC_THI_STREAMID1);
138 /* setup clockgating registers */
139 vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |
141 CG_WAKEUP_DLY_CNT(4),
142 NV_PVIC_MISC_PRI_VIC_CG);
144 err = falcon_boot(&vic->falcon);
148 hdr = vic->falcon.firmware.virt;
149 fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
151 /* Old VIC firmware needs kernel help with setting up FCE microcode. */
152 if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) {
153 hdr = vic->falcon.firmware.virt +
154 *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
155 fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
157 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
159 falcon_execute_method(
160 &vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
161 (vic->falcon.firmware.iova + fce_bin_data_offset) >> 8);
164 err = falcon_wait_idle(&vic->falcon);
167 "failed to set application ID and FCE base\n");
176 static int vic_init(struct host1x_client *client)
178 struct tegra_drm_client *drm = host1x_to_drm_client(client);
179 struct drm_device *dev = dev_get_drvdata(client->host);
180 struct tegra_drm *tegra = dev->dev_private;
181 struct vic *vic = to_vic(drm);
184 err = host1x_client_iommu_attach(client);
185 if (err < 0 && err != -ENODEV) {
186 dev_err(vic->dev, "failed to attach to domain: %d\n", err);
190 vic->channel = host1x_channel_request(client);
196 client->syncpts[0] = host1x_syncpt_request(client, 0);
197 if (!client->syncpts[0]) {
202 err = tegra_drm_register_client(tegra, drm);
207 * Inherit the DMA parameters (such as maximum segment size) from the
208 * parent host1x device.
210 client->dev->dma_parms = client->host->dma_parms;
215 host1x_syncpt_put(client->syncpts[0]);
217 host1x_channel_put(vic->channel);
219 host1x_client_iommu_detach(client);
224 static int vic_exit(struct host1x_client *client)
226 struct tegra_drm_client *drm = host1x_to_drm_client(client);
227 struct drm_device *dev = dev_get_drvdata(client->host);
228 struct tegra_drm *tegra = dev->dev_private;
229 struct vic *vic = to_vic(drm);
232 /* avoid a dangling pointer just in case this disappears */
233 client->dev->dma_parms = NULL;
235 err = tegra_drm_unregister_client(tegra, drm);
239 host1x_syncpt_put(client->syncpts[0]);
240 host1x_channel_put(vic->channel);
241 host1x_client_iommu_detach(client);
244 dma_unmap_single(vic->dev, vic->falcon.firmware.phys,
245 vic->falcon.firmware.size, DMA_TO_DEVICE);
246 tegra_drm_free(tegra, vic->falcon.firmware.size,
247 vic->falcon.firmware.virt,
248 vic->falcon.firmware.iova);
250 dma_free_coherent(vic->dev, vic->falcon.firmware.size,
251 vic->falcon.firmware.virt,
252 vic->falcon.firmware.iova);
258 static const struct host1x_client_ops vic_client_ops = {
263 static int vic_load_firmware(struct vic *vic)
265 struct host1x_client *client = &vic->client.base;
266 struct tegra_drm *tegra = vic->client.drm;
272 if (vic->falcon.firmware.virt)
275 err = falcon_read_firmware(&vic->falcon, vic->config->firmware);
279 size = vic->falcon.firmware.size;
281 if (!client->group) {
282 virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL);
284 err = dma_mapping_error(vic->dev, iova);
288 virt = tegra_drm_alloc(tegra, size, &iova);
291 vic->falcon.firmware.virt = virt;
292 vic->falcon.firmware.iova = iova;
294 err = falcon_load_firmware(&vic->falcon);
299 * In this case we have received an IOVA from the shared domain, so we
300 * need to make sure to get the physical address so that the DMA API
301 * knows what memory pages to flush the cache for.
306 phys = dma_map_single(vic->dev, virt, size, DMA_TO_DEVICE);
308 err = dma_mapping_error(vic->dev, phys);
312 vic->falcon.firmware.phys = phys;
319 dma_free_coherent(vic->dev, size, virt, iova);
321 tegra_drm_free(tegra, size, virt, iova);
326 static int vic_open_channel(struct tegra_drm_client *client,
327 struct tegra_drm_context *context)
329 struct vic *vic = to_vic(client);
332 err = pm_runtime_resume_and_get(vic->dev);
336 err = vic_load_firmware(vic);
344 context->channel = host1x_channel_get(vic->channel);
345 if (!context->channel) {
353 pm_runtime_put(vic->dev);
357 static void vic_close_channel(struct tegra_drm_context *context)
359 struct vic *vic = to_vic(context->client);
361 host1x_channel_put(context->channel);
363 pm_runtime_put(vic->dev);
366 static const struct tegra_drm_client_ops vic_ops = {
367 .open_channel = vic_open_channel,
368 .close_channel = vic_close_channel,
369 .submit = tegra_drm_submit,
372 #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
374 static const struct vic_config vic_t124_config = {
375 .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
377 .supports_sid = false,
380 #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
382 static const struct vic_config vic_t210_config = {
383 .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
385 .supports_sid = false,
388 #define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin"
390 static const struct vic_config vic_t186_config = {
391 .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE,
393 .supports_sid = true,
396 #define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
398 static const struct vic_config vic_t194_config = {
399 .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE,
401 .supports_sid = true,
404 static const struct of_device_id tegra_vic_of_match[] = {
405 { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
406 { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
407 { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
408 { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
411 MODULE_DEVICE_TABLE(of, tegra_vic_of_match);
413 static int vic_probe(struct platform_device *pdev)
415 struct device *dev = &pdev->dev;
416 struct host1x_syncpt **syncpts;
417 struct resource *regs;
421 /* inherit DMA mask from host1x parent */
422 err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask);
424 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
428 vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL);
432 vic->config = of_device_get_match_data(dev);
434 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
438 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
440 dev_err(&pdev->dev, "failed to get registers\n");
444 vic->regs = devm_ioremap_resource(dev, regs);
445 if (IS_ERR(vic->regs))
446 return PTR_ERR(vic->regs);
448 vic->clk = devm_clk_get(dev, NULL);
449 if (IS_ERR(vic->clk)) {
450 dev_err(&pdev->dev, "failed to get clock\n");
451 return PTR_ERR(vic->clk);
454 if (!dev->pm_domain) {
455 vic->rst = devm_reset_control_get(dev, "vic");
456 if (IS_ERR(vic->rst)) {
457 dev_err(&pdev->dev, "failed to get reset\n");
458 return PTR_ERR(vic->rst);
462 vic->falcon.dev = dev;
463 vic->falcon.regs = vic->regs;
465 err = falcon_init(&vic->falcon);
469 platform_set_drvdata(pdev, vic);
471 INIT_LIST_HEAD(&vic->client.base.list);
472 vic->client.base.ops = &vic_client_ops;
473 vic->client.base.dev = dev;
474 vic->client.base.class = HOST1X_CLASS_VIC;
475 vic->client.base.syncpts = syncpts;
476 vic->client.base.num_syncpts = 1;
479 INIT_LIST_HEAD(&vic->client.list);
480 vic->client.version = vic->config->version;
481 vic->client.ops = &vic_ops;
483 err = host1x_client_register(&vic->client.base);
485 dev_err(dev, "failed to register host1x client: %d\n", err);
489 pm_runtime_enable(&pdev->dev);
490 if (!pm_runtime_enabled(&pdev->dev)) {
491 err = vic_runtime_resume(&pdev->dev);
493 goto unregister_client;
499 host1x_client_unregister(&vic->client.base);
501 falcon_exit(&vic->falcon);
506 static int vic_remove(struct platform_device *pdev)
508 struct vic *vic = platform_get_drvdata(pdev);
511 err = host1x_client_unregister(&vic->client.base);
513 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
518 if (pm_runtime_enabled(&pdev->dev))
519 pm_runtime_disable(&pdev->dev);
521 vic_runtime_suspend(&pdev->dev);
523 falcon_exit(&vic->falcon);
528 static const struct dev_pm_ops vic_pm_ops = {
529 SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL)
532 struct platform_driver tegra_vic_driver = {
535 .of_match_table = tegra_vic_of_match,
539 .remove = vic_remove,
542 #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)
543 MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE);
545 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
546 MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
548 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
549 MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE);
551 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
552 MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE);