1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, NVIDIA Corporation.
7 #include <linux/delay.h>
8 #include <linux/host1x.h>
9 #include <linux/iommu.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/of_platform.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/reset.h>
18 #include <soc/tegra/pmc.h>
35 struct tegra_drm_client client;
36 struct host1x_channel *channel;
39 struct reset_control *rst;
41 /* Platform configuration */
42 const struct vic_config *config;
45 static inline struct vic *to_vic(struct tegra_drm_client *client)
47 return container_of(client, struct vic, client);
50 static void vic_writel(struct vic *vic, u32 value, unsigned int offset)
52 writel(value, vic->regs + offset);
55 static int vic_runtime_resume(struct device *dev)
57 struct vic *vic = dev_get_drvdata(dev);
60 err = clk_prepare_enable(vic->clk);
66 err = reset_control_deassert(vic->rst);
75 clk_disable_unprepare(vic->clk);
79 static int vic_runtime_suspend(struct device *dev)
81 struct vic *vic = dev_get_drvdata(dev);
84 err = reset_control_assert(vic->rst);
88 usleep_range(2000, 4000);
90 clk_disable_unprepare(vic->clk);
97 static int vic_boot(struct vic *vic)
99 #ifdef CONFIG_IOMMU_API
100 struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev);
102 u32 fce_ucode_size, fce_bin_data_offset;
109 #ifdef CONFIG_IOMMU_API
110 if (vic->config->supports_sid && spec) {
113 value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) |
114 TRANSCFG_ATT(0, TRANSCFG_SID_HW);
115 vic_writel(vic, value, VIC_TFBIF_TRANSCFG);
117 if (spec->num_ids > 0) {
118 value = spec->ids[0] & 0xffff;
121 * STREAMID0 is used for input/output buffers.
122 * Initialize it to SID_VIC in case context isolation
123 * is not enabled, and SID_VIC is used for both firmware
126 * If context isolation is enabled, it will be
127 * overridden by the SETSTREAMID opcode as part of
130 vic_writel(vic, value, VIC_THI_STREAMID0);
132 /* STREAMID1 is used for firmware loading. */
133 vic_writel(vic, value, VIC_THI_STREAMID1);
138 /* setup clockgating registers */
139 vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |
141 CG_WAKEUP_DLY_CNT(4),
142 NV_PVIC_MISC_PRI_VIC_CG);
144 err = falcon_boot(&vic->falcon);
148 hdr = vic->falcon.firmware.virt;
149 fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
151 falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1);
153 /* Old VIC firmware needs kernel help with setting up FCE microcode. */
154 if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) {
155 hdr = vic->falcon.firmware.virt +
156 *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
157 fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
159 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
161 falcon_execute_method(
162 &vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
163 (vic->falcon.firmware.iova + fce_bin_data_offset) >> 8);
166 err = falcon_wait_idle(&vic->falcon);
169 "failed to set application ID and FCE base\n");
178 static int vic_init(struct host1x_client *client)
180 struct tegra_drm_client *drm = host1x_to_drm_client(client);
181 struct drm_device *dev = dev_get_drvdata(client->host);
182 struct tegra_drm *tegra = dev->dev_private;
183 struct vic *vic = to_vic(drm);
186 err = host1x_client_iommu_attach(client);
187 if (err < 0 && err != -ENODEV) {
188 dev_err(vic->dev, "failed to attach to domain: %d\n", err);
192 vic->channel = host1x_channel_request(client);
198 client->syncpts[0] = host1x_syncpt_request(client, 0);
199 if (!client->syncpts[0]) {
204 err = tegra_drm_register_client(tegra, drm);
209 * Inherit the DMA parameters (such as maximum segment size) from the
210 * parent host1x device.
212 client->dev->dma_parms = client->host->dma_parms;
217 host1x_syncpt_put(client->syncpts[0]);
219 host1x_channel_put(vic->channel);
221 host1x_client_iommu_detach(client);
226 static int vic_exit(struct host1x_client *client)
228 struct tegra_drm_client *drm = host1x_to_drm_client(client);
229 struct drm_device *dev = dev_get_drvdata(client->host);
230 struct tegra_drm *tegra = dev->dev_private;
231 struct vic *vic = to_vic(drm);
234 /* avoid a dangling pointer just in case this disappears */
235 client->dev->dma_parms = NULL;
237 err = tegra_drm_unregister_client(tegra, drm);
241 host1x_syncpt_put(client->syncpts[0]);
242 host1x_channel_put(vic->channel);
243 host1x_client_iommu_detach(client);
246 dma_unmap_single(vic->dev, vic->falcon.firmware.phys,
247 vic->falcon.firmware.size, DMA_TO_DEVICE);
248 tegra_drm_free(tegra, vic->falcon.firmware.size,
249 vic->falcon.firmware.virt,
250 vic->falcon.firmware.iova);
252 dma_free_coherent(vic->dev, vic->falcon.firmware.size,
253 vic->falcon.firmware.virt,
254 vic->falcon.firmware.iova);
260 static const struct host1x_client_ops vic_client_ops = {
265 static int vic_load_firmware(struct vic *vic)
267 struct host1x_client *client = &vic->client.base;
268 struct tegra_drm *tegra = vic->client.drm;
274 if (vic->falcon.firmware.virt)
277 err = falcon_read_firmware(&vic->falcon, vic->config->firmware);
281 size = vic->falcon.firmware.size;
283 if (!client->group) {
284 virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL);
286 err = dma_mapping_error(vic->dev, iova);
290 virt = tegra_drm_alloc(tegra, size, &iova);
293 vic->falcon.firmware.virt = virt;
294 vic->falcon.firmware.iova = iova;
296 err = falcon_load_firmware(&vic->falcon);
301 * In this case we have received an IOVA from the shared domain, so we
302 * need to make sure to get the physical address so that the DMA API
303 * knows what memory pages to flush the cache for.
308 phys = dma_map_single(vic->dev, virt, size, DMA_TO_DEVICE);
310 err = dma_mapping_error(vic->dev, phys);
314 vic->falcon.firmware.phys = phys;
321 dma_free_coherent(vic->dev, size, virt, iova);
323 tegra_drm_free(tegra, size, virt, iova);
328 static int vic_open_channel(struct tegra_drm_client *client,
329 struct tegra_drm_context *context)
331 struct vic *vic = to_vic(client);
334 err = pm_runtime_resume_and_get(vic->dev);
338 err = vic_load_firmware(vic);
346 context->channel = host1x_channel_get(vic->channel);
347 if (!context->channel) {
355 pm_runtime_put(vic->dev);
359 static void vic_close_channel(struct tegra_drm_context *context)
361 struct vic *vic = to_vic(context->client);
363 host1x_channel_put(context->channel);
365 pm_runtime_put(vic->dev);
368 static const struct tegra_drm_client_ops vic_ops = {
369 .open_channel = vic_open_channel,
370 .close_channel = vic_close_channel,
371 .submit = tegra_drm_submit,
374 #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
376 static const struct vic_config vic_t124_config = {
377 .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
379 .supports_sid = false,
382 #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
384 static const struct vic_config vic_t210_config = {
385 .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
387 .supports_sid = false,
390 #define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin"
392 static const struct vic_config vic_t186_config = {
393 .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE,
395 .supports_sid = true,
398 #define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
400 static const struct vic_config vic_t194_config = {
401 .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE,
403 .supports_sid = true,
406 static const struct of_device_id tegra_vic_of_match[] = {
407 { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
408 { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
409 { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
410 { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
413 MODULE_DEVICE_TABLE(of, tegra_vic_of_match);
415 static int vic_probe(struct platform_device *pdev)
417 struct device *dev = &pdev->dev;
418 struct host1x_syncpt **syncpts;
419 struct resource *regs;
423 /* inherit DMA mask from host1x parent */
424 err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask);
426 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
430 vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL);
434 vic->config = of_device_get_match_data(dev);
436 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
440 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
442 dev_err(&pdev->dev, "failed to get registers\n");
446 vic->regs = devm_ioremap_resource(dev, regs);
447 if (IS_ERR(vic->regs))
448 return PTR_ERR(vic->regs);
450 vic->clk = devm_clk_get(dev, NULL);
451 if (IS_ERR(vic->clk)) {
452 dev_err(&pdev->dev, "failed to get clock\n");
453 return PTR_ERR(vic->clk);
456 if (!dev->pm_domain) {
457 vic->rst = devm_reset_control_get(dev, "vic");
458 if (IS_ERR(vic->rst)) {
459 dev_err(&pdev->dev, "failed to get reset\n");
460 return PTR_ERR(vic->rst);
464 vic->falcon.dev = dev;
465 vic->falcon.regs = vic->regs;
467 err = falcon_init(&vic->falcon);
471 platform_set_drvdata(pdev, vic);
473 INIT_LIST_HEAD(&vic->client.base.list);
474 vic->client.base.ops = &vic_client_ops;
475 vic->client.base.dev = dev;
476 vic->client.base.class = HOST1X_CLASS_VIC;
477 vic->client.base.syncpts = syncpts;
478 vic->client.base.num_syncpts = 1;
481 INIT_LIST_HEAD(&vic->client.list);
482 vic->client.version = vic->config->version;
483 vic->client.ops = &vic_ops;
485 err = host1x_client_register(&vic->client.base);
487 dev_err(dev, "failed to register host1x client: %d\n", err);
491 pm_runtime_enable(&pdev->dev);
492 if (!pm_runtime_enabled(&pdev->dev)) {
493 err = vic_runtime_resume(&pdev->dev);
495 goto unregister_client;
501 host1x_client_unregister(&vic->client.base);
503 falcon_exit(&vic->falcon);
508 static int vic_remove(struct platform_device *pdev)
510 struct vic *vic = platform_get_drvdata(pdev);
513 err = host1x_client_unregister(&vic->client.base);
515 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
520 if (pm_runtime_enabled(&pdev->dev))
521 pm_runtime_disable(&pdev->dev);
523 vic_runtime_suspend(&pdev->dev);
525 falcon_exit(&vic->falcon);
530 static const struct dev_pm_ops vic_pm_ops = {
531 SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL)
534 struct platform_driver tegra_vic_driver = {
537 .of_match_table = tegra_vic_of_match,
541 .remove = vic_remove,
544 #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)
545 MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE);
547 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
548 MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
550 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
551 MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE);
553 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
554 MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE);