1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 NVIDIA Corporation
7 #include <linux/clk-provider.h>
8 #include <linux/debugfs.h>
9 #include <linux/gpio.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/reset.h>
17 #include <soc/tegra/pmc.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_dp_helper.h>
21 #include <drm/drm_panel.h>
22 #include <drm/drm_scdc_helper.h>
30 #define SOR_REKEY 0x38
32 struct tegra_sor_hdmi_settings {
33 unsigned long frequency;
52 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
54 .frequency = 54000000,
66 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
67 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
69 .frequency = 75000000,
81 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
82 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
84 .frequency = 150000000,
96 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
97 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
99 .frequency = 300000000,
107 .bg_vref_level = 0xa,
111 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
112 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
114 .frequency = 600000000,
122 .bg_vref_level = 0x8,
126 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
127 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
131 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
133 .frequency = 75000000,
141 .bg_vref_level = 0x8,
145 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
146 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
148 .frequency = 150000000,
156 .bg_vref_level = 0x8,
160 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
161 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
163 .frequency = 300000000,
171 .bg_vref_level = 0xf,
175 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
176 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
178 .frequency = 600000000,
186 .bg_vref_level = 0xe,
190 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
191 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
196 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
198 .frequency = 54000000,
210 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
211 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
213 .frequency = 75000000,
225 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
226 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
228 .frequency = 150000000,
234 .tx_pu_value = 0x66 /* 0 */,
239 .sparepll = 0x00, /* 0x34 */
240 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
241 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
243 .frequency = 300000000,
255 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
256 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
258 .frequency = 600000000,
270 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
271 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
275 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
277 .frequency = 54000000,
289 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
290 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
292 .frequency = 75000000,
304 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
305 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
307 .frequency = 150000000,
313 .tx_pu_value = 0x66 /* 0 */,
318 .sparepll = 0x00, /* 0x34 */
319 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
320 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
322 .frequency = 300000000,
334 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
335 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
337 .frequency = 600000000,
349 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
350 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
354 struct tegra_sor_regs {
355 unsigned int head_state0;
356 unsigned int head_state1;
357 unsigned int head_state2;
358 unsigned int head_state3;
359 unsigned int head_state4;
360 unsigned int head_state5;
365 unsigned int dp_padctl0;
366 unsigned int dp_padctl2;
369 struct tegra_sor_soc {
375 const struct tegra_sor_regs *regs;
378 const struct tegra_sor_hdmi_settings *settings;
379 unsigned int num_settings;
386 struct tegra_sor_ops {
388 int (*probe)(struct tegra_sor *sor);
389 int (*remove)(struct tegra_sor *sor);
393 struct host1x_client client;
394 struct tegra_output output;
397 const struct tegra_sor_soc *soc;
402 struct reset_control *rst;
403 struct clk *clk_parent;
404 struct clk *clk_safe;
412 struct drm_dp_aux *aux;
414 struct drm_info_list *debugfs_files;
416 const struct tegra_sor_ops *ops;
417 enum tegra_io_pad pad;
420 struct tegra_sor_hdmi_settings *settings;
421 unsigned int num_settings;
423 struct regulator *avdd_io_supply;
424 struct regulator *vdd_pll_supply;
425 struct regulator *hdmi_supply;
427 struct delayed_work scdc;
430 struct tegra_hda_format format;
433 struct tegra_sor_state {
434 struct drm_connector_state base;
436 unsigned int link_speed;
441 static inline struct tegra_sor_state *
442 to_sor_state(struct drm_connector_state *state)
444 return container_of(state, struct tegra_sor_state, base);
447 struct tegra_sor_config {
460 static inline struct tegra_sor *
461 host1x_client_to_sor(struct host1x_client *client)
463 return container_of(client, struct tegra_sor, client);
466 static inline struct tegra_sor *to_sor(struct tegra_output *output)
468 return container_of(output, struct tegra_sor, output);
471 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
473 u32 value = readl(sor->regs + (offset << 2));
475 trace_sor_readl(sor->dev, offset, value);
480 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
483 trace_sor_writel(sor->dev, offset, value);
484 writel(value, sor->regs + (offset << 2));
487 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
491 clk_disable_unprepare(sor->clk);
493 err = clk_set_parent(sor->clk_out, parent);
497 err = clk_prepare_enable(sor->clk);
504 struct tegra_clk_sor_pad {
506 struct tegra_sor *sor;
509 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
511 return container_of(hw, struct tegra_clk_sor_pad, hw);
514 static const char * const tegra_clk_sor_pad_parents[] = {
515 "pll_d2_out0", "pll_dp"
518 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
520 struct tegra_clk_sor_pad *pad = to_pad(hw);
521 struct tegra_sor *sor = pad->sor;
524 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
525 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
529 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
533 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
537 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
542 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
544 struct tegra_clk_sor_pad *pad = to_pad(hw);
545 struct tegra_sor *sor = pad->sor;
549 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
551 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
552 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
553 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
557 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
558 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
566 static const struct clk_ops tegra_clk_sor_pad_ops = {
567 .set_parent = tegra_clk_sor_pad_set_parent,
568 .get_parent = tegra_clk_sor_pad_get_parent,
571 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
574 struct tegra_clk_sor_pad *pad;
575 struct clk_init_data init;
578 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
580 return ERR_PTR(-ENOMEM);
586 init.parent_names = tegra_clk_sor_pad_parents;
587 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
588 init.ops = &tegra_clk_sor_pad_ops;
590 pad->hw.init = &init;
592 clk = devm_clk_register(sor->dev, &pad->hw);
597 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
598 struct drm_dp_link *link)
605 /* setup lane parameters */
606 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
607 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
608 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
609 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
610 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
612 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
613 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
614 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
615 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
616 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
618 value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
619 SOR_LANE_POSTCURSOR_LANE2(0x00) |
620 SOR_LANE_POSTCURSOR_LANE1(0x00) |
621 SOR_LANE_POSTCURSOR_LANE0(0x00);
622 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
624 /* disable LVDS mode */
625 tegra_sor_writel(sor, 0, SOR_LVDS);
627 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
628 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
629 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
630 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
631 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
633 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
634 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
635 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
636 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
638 usleep_range(10, 100);
640 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
641 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
642 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
643 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
645 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
649 for (i = 0, value = 0; i < link->num_lanes; i++) {
650 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
651 SOR_DP_TPG_SCRAMBLER_NONE |
652 SOR_DP_TPG_PATTERN_TRAIN1;
653 value = (value << 8) | lane;
656 tegra_sor_writel(sor, value, SOR_DP_TPG);
658 pattern = DP_TRAINING_PATTERN_1;
660 err = drm_dp_aux_train(sor->aux, link, pattern);
664 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
665 value |= SOR_DP_SPARE_SEQ_ENABLE;
666 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
667 value |= SOR_DP_SPARE_MACRO_SOR_CLK;
668 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
670 for (i = 0, value = 0; i < link->num_lanes; i++) {
671 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
672 SOR_DP_TPG_SCRAMBLER_NONE |
673 SOR_DP_TPG_PATTERN_TRAIN2;
674 value = (value << 8) | lane;
677 tegra_sor_writel(sor, value, SOR_DP_TPG);
679 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
681 err = drm_dp_aux_train(sor->aux, link, pattern);
685 for (i = 0, value = 0; i < link->num_lanes; i++) {
686 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
687 SOR_DP_TPG_SCRAMBLER_GALIOS |
688 SOR_DP_TPG_PATTERN_NONE;
689 value = (value << 8) | lane;
692 tegra_sor_writel(sor, value, SOR_DP_TPG);
694 pattern = DP_TRAINING_PATTERN_DISABLE;
696 err = drm_dp_aux_train(sor->aux, link, pattern);
703 static void tegra_sor_super_update(struct tegra_sor *sor)
705 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
706 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
707 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
710 static void tegra_sor_update(struct tegra_sor *sor)
712 tegra_sor_writel(sor, 0, SOR_STATE0);
713 tegra_sor_writel(sor, 1, SOR_STATE0);
714 tegra_sor_writel(sor, 0, SOR_STATE0);
717 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
721 value = tegra_sor_readl(sor, SOR_PWM_DIV);
722 value &= ~SOR_PWM_DIV_MASK;
723 value |= 0x400; /* period */
724 tegra_sor_writel(sor, value, SOR_PWM_DIV);
726 value = tegra_sor_readl(sor, SOR_PWM_CTL);
727 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
728 value |= 0x400; /* duty cycle */
729 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
730 value |= SOR_PWM_CTL_TRIGGER;
731 tegra_sor_writel(sor, value, SOR_PWM_CTL);
733 timeout = jiffies + msecs_to_jiffies(timeout);
735 while (time_before(jiffies, timeout)) {
736 value = tegra_sor_readl(sor, SOR_PWM_CTL);
737 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
740 usleep_range(25, 100);
746 static int tegra_sor_attach(struct tegra_sor *sor)
748 unsigned long value, timeout;
750 /* wake up in normal mode */
751 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
752 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
753 value |= SOR_SUPER_STATE_MODE_NORMAL;
754 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
755 tegra_sor_super_update(sor);
758 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
759 value |= SOR_SUPER_STATE_ATTACHED;
760 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
761 tegra_sor_super_update(sor);
763 timeout = jiffies + msecs_to_jiffies(250);
765 while (time_before(jiffies, timeout)) {
766 value = tegra_sor_readl(sor, SOR_TEST);
767 if ((value & SOR_TEST_ATTACHED) != 0)
770 usleep_range(25, 100);
776 static int tegra_sor_wakeup(struct tegra_sor *sor)
778 unsigned long value, timeout;
780 timeout = jiffies + msecs_to_jiffies(250);
782 /* wait for head to wake up */
783 while (time_before(jiffies, timeout)) {
784 value = tegra_sor_readl(sor, SOR_TEST);
785 value &= SOR_TEST_HEAD_MODE_MASK;
787 if (value == SOR_TEST_HEAD_MODE_AWAKE)
790 usleep_range(25, 100);
796 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
800 value = tegra_sor_readl(sor, SOR_PWR);
801 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
802 tegra_sor_writel(sor, value, SOR_PWR);
804 timeout = jiffies + msecs_to_jiffies(timeout);
806 while (time_before(jiffies, timeout)) {
807 value = tegra_sor_readl(sor, SOR_PWR);
808 if ((value & SOR_PWR_TRIGGER) == 0)
811 usleep_range(25, 100);
817 struct tegra_sor_params {
818 /* number of link clocks per line */
819 unsigned int num_clocks;
820 /* ratio between input and output */
822 /* precision factor */
825 unsigned int active_polarity;
826 unsigned int active_count;
827 unsigned int active_frac;
828 unsigned int tu_size;
832 static int tegra_sor_compute_params(struct tegra_sor *sor,
833 struct tegra_sor_params *params,
834 unsigned int tu_size)
836 u64 active_sym, active_count, frac, approx;
837 u32 active_polarity, active_frac = 0;
838 const u64 f = params->precision;
841 active_sym = params->ratio * tu_size;
842 active_count = div_u64(active_sym, f) * f;
843 frac = active_sym - active_count;
846 if (frac >= (f / 2)) {
854 frac = div_u64(f * f, frac); /* 1/fraction */
855 if (frac <= (15 * f)) {
856 active_frac = div_u64(frac, f);
862 active_frac = active_polarity ? 1 : 15;
866 if (active_frac == 1)
869 if (active_polarity == 1) {
871 approx = active_count + (active_frac * (f - 1)) * f;
872 approx = div_u64(approx, active_frac * f);
874 approx = active_count + f;
878 approx = active_count + div_u64(f, active_frac);
880 approx = active_count;
883 error = div_s64(active_sym - approx, tu_size);
884 error *= params->num_clocks;
886 if (error <= 0 && abs(error) < params->error) {
887 params->active_count = div_u64(active_count, f);
888 params->active_polarity = active_polarity;
889 params->active_frac = active_frac;
890 params->error = abs(error);
891 params->tu_size = tu_size;
900 static int tegra_sor_compute_config(struct tegra_sor *sor,
901 const struct drm_display_mode *mode,
902 struct tegra_sor_config *config,
903 struct drm_dp_link *link)
905 const u64 f = 100000, link_rate = link->rate * 1000;
906 const u64 pclk = mode->clock * 1000;
907 u64 input, output, watermark, num;
908 struct tegra_sor_params params;
909 u32 num_syms_per_line;
912 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
915 output = link_rate * 8 * link->num_lanes;
916 input = pclk * config->bits_per_pixel;
921 memset(¶ms, 0, sizeof(params));
922 params.ratio = div64_u64(input * f, output);
923 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
924 params.precision = f;
925 params.error = 64 * f;
928 for (i = params.tu_size; i >= 32; i--)
929 if (tegra_sor_compute_params(sor, ¶ms, i))
932 if (params.active_frac == 0) {
933 config->active_polarity = 0;
934 config->active_count = params.active_count;
936 if (!params.active_polarity)
937 config->active_count--;
939 config->tu_size = params.tu_size;
940 config->active_frac = 1;
942 config->active_polarity = params.active_polarity;
943 config->active_count = params.active_count;
944 config->active_frac = params.active_frac;
945 config->tu_size = params.tu_size;
949 "polarity: %d active count: %d tu size: %d active frac: %d\n",
950 config->active_polarity, config->active_count,
951 config->tu_size, config->active_frac);
953 watermark = params.ratio * config->tu_size * (f - params.ratio);
954 watermark = div_u64(watermark, f);
956 watermark = div_u64(watermark + params.error, f);
957 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
958 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
959 (link->num_lanes * 8);
961 if (config->watermark > 30) {
962 config->watermark = 30;
964 "unable to compute TU size, forcing watermark to %u\n",
966 } else if (config->watermark > num_syms_per_line) {
967 config->watermark = num_syms_per_line;
968 dev_err(sor->dev, "watermark too high, forcing to %u\n",
972 /* compute the number of symbols per horizontal blanking interval */
973 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
974 config->hblank_symbols = div_u64(num, pclk);
976 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
977 config->hblank_symbols -= 3;
979 config->hblank_symbols -= 12 / link->num_lanes;
981 /* compute the number of symbols per vertical blanking interval */
982 num = (mode->hdisplay - 25) * link_rate;
983 config->vblank_symbols = div_u64(num, pclk);
984 config->vblank_symbols -= 36 / link->num_lanes + 4;
986 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
987 config->vblank_symbols);
992 static void tegra_sor_apply_config(struct tegra_sor *sor,
993 const struct tegra_sor_config *config)
997 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
998 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
999 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1000 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1002 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1003 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1004 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1006 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1007 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1009 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1010 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1012 if (config->active_polarity)
1013 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1015 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1017 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1018 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1019 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1021 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1022 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1023 value |= config->hblank_symbols & 0xffff;
1024 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1026 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1027 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1028 value |= config->vblank_symbols & 0xffff;
1029 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1032 static void tegra_sor_mode_set(struct tegra_sor *sor,
1033 const struct drm_display_mode *mode,
1034 struct tegra_sor_state *state)
1036 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1037 unsigned int vbe, vse, hbe, hse, vbs, hbs;
1040 value = tegra_sor_readl(sor, SOR_STATE1);
1041 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1042 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1043 value &= ~SOR_STATE_ASY_OWNER_MASK;
1045 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1046 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1048 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1049 value &= ~SOR_STATE_ASY_HSYNCPOL;
1051 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1052 value |= SOR_STATE_ASY_HSYNCPOL;
1054 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1055 value &= ~SOR_STATE_ASY_VSYNCPOL;
1057 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1058 value |= SOR_STATE_ASY_VSYNCPOL;
1060 switch (state->bpc) {
1062 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1066 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1070 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1074 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1078 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1082 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1086 tegra_sor_writel(sor, value, SOR_STATE1);
1089 * TODO: The video timing programming below doesn't seem to match the
1090 * register definitions.
1093 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1094 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1096 /* sync end = sync width - 1 */
1097 vse = mode->vsync_end - mode->vsync_start - 1;
1098 hse = mode->hsync_end - mode->hsync_start - 1;
1100 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1101 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1103 /* blank end = sync end + back porch */
1104 vbe = vse + (mode->vtotal - mode->vsync_end);
1105 hbe = hse + (mode->htotal - mode->hsync_end);
1107 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1108 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1110 /* blank start = blank end + active */
1111 vbs = vbe + mode->vdisplay;
1112 hbs = hbe + mode->hdisplay;
1114 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1115 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1117 /* XXX interlacing support */
1118 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1121 static int tegra_sor_detach(struct tegra_sor *sor)
1123 unsigned long value, timeout;
1125 /* switch to safe mode */
1126 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1127 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1128 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1129 tegra_sor_super_update(sor);
1131 timeout = jiffies + msecs_to_jiffies(250);
1133 while (time_before(jiffies, timeout)) {
1134 value = tegra_sor_readl(sor, SOR_PWR);
1135 if (value & SOR_PWR_MODE_SAFE)
1139 if ((value & SOR_PWR_MODE_SAFE) == 0)
1143 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1144 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1145 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1146 tegra_sor_super_update(sor);
1149 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1150 value &= ~SOR_SUPER_STATE_ATTACHED;
1151 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1152 tegra_sor_super_update(sor);
1154 timeout = jiffies + msecs_to_jiffies(250);
1156 while (time_before(jiffies, timeout)) {
1157 value = tegra_sor_readl(sor, SOR_TEST);
1158 if ((value & SOR_TEST_ATTACHED) == 0)
1161 usleep_range(25, 100);
1164 if ((value & SOR_TEST_ATTACHED) != 0)
1170 static int tegra_sor_power_down(struct tegra_sor *sor)
1172 unsigned long value, timeout;
1175 value = tegra_sor_readl(sor, SOR_PWR);
1176 value &= ~SOR_PWR_NORMAL_STATE_PU;
1177 value |= SOR_PWR_TRIGGER;
1178 tegra_sor_writel(sor, value, SOR_PWR);
1180 timeout = jiffies + msecs_to_jiffies(250);
1182 while (time_before(jiffies, timeout)) {
1183 value = tegra_sor_readl(sor, SOR_PWR);
1184 if ((value & SOR_PWR_TRIGGER) == 0)
1187 usleep_range(25, 100);
1190 if ((value & SOR_PWR_TRIGGER) != 0)
1193 /* switch to safe parent clock */
1194 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1196 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1200 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1201 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1202 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1203 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1205 /* stop lane sequencer */
1206 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
1207 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
1208 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1210 timeout = jiffies + msecs_to_jiffies(250);
1212 while (time_before(jiffies, timeout)) {
1213 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1214 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1217 usleep_range(25, 100);
1220 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1223 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1224 value |= SOR_PLL2_PORT_POWERDOWN;
1225 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1227 usleep_range(20, 100);
1229 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1230 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1231 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1233 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1234 value |= SOR_PLL2_SEQ_PLLCAPPD;
1235 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1236 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1238 usleep_range(20, 100);
1243 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1247 timeout = jiffies + msecs_to_jiffies(timeout);
1249 while (time_before(jiffies, timeout)) {
1250 value = tegra_sor_readl(sor, SOR_CRCA);
1251 if (value & SOR_CRCA_VALID)
1254 usleep_range(100, 200);
1260 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1262 struct drm_info_node *node = s->private;
1263 struct tegra_sor *sor = node->info_ent->data;
1264 struct drm_crtc *crtc = sor->output.encoder.crtc;
1265 struct drm_device *drm = node->minor->dev;
1269 drm_modeset_lock_all(drm);
1271 if (!crtc || !crtc->state->active) {
1276 value = tegra_sor_readl(sor, SOR_STATE1);
1277 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1278 tegra_sor_writel(sor, value, SOR_STATE1);
1280 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1281 value |= SOR_CRC_CNTRL_ENABLE;
1282 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1284 value = tegra_sor_readl(sor, SOR_TEST);
1285 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1286 tegra_sor_writel(sor, value, SOR_TEST);
1288 err = tegra_sor_crc_wait(sor, 100);
1292 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1293 value = tegra_sor_readl(sor, SOR_CRCB);
1295 seq_printf(s, "%08x\n", value);
1298 drm_modeset_unlock_all(drm);
1302 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1304 static const struct debugfs_reg32 tegra_sor_regs[] = {
1305 DEBUGFS_REG32(SOR_CTXSW),
1306 DEBUGFS_REG32(SOR_SUPER_STATE0),
1307 DEBUGFS_REG32(SOR_SUPER_STATE1),
1308 DEBUGFS_REG32(SOR_STATE0),
1309 DEBUGFS_REG32(SOR_STATE1),
1310 DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1311 DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1312 DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1313 DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1314 DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1315 DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1316 DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1317 DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1318 DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1319 DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1320 DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1321 DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1322 DEBUGFS_REG32(SOR_CRC_CNTRL),
1323 DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1324 DEBUGFS_REG32(SOR_CLK_CNTRL),
1325 DEBUGFS_REG32(SOR_CAP),
1326 DEBUGFS_REG32(SOR_PWR),
1327 DEBUGFS_REG32(SOR_TEST),
1328 DEBUGFS_REG32(SOR_PLL0),
1329 DEBUGFS_REG32(SOR_PLL1),
1330 DEBUGFS_REG32(SOR_PLL2),
1331 DEBUGFS_REG32(SOR_PLL3),
1332 DEBUGFS_REG32(SOR_CSTM),
1333 DEBUGFS_REG32(SOR_LVDS),
1334 DEBUGFS_REG32(SOR_CRCA),
1335 DEBUGFS_REG32(SOR_CRCB),
1336 DEBUGFS_REG32(SOR_BLANK),
1337 DEBUGFS_REG32(SOR_SEQ_CTL),
1338 DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1339 DEBUGFS_REG32(SOR_SEQ_INST(0)),
1340 DEBUGFS_REG32(SOR_SEQ_INST(1)),
1341 DEBUGFS_REG32(SOR_SEQ_INST(2)),
1342 DEBUGFS_REG32(SOR_SEQ_INST(3)),
1343 DEBUGFS_REG32(SOR_SEQ_INST(4)),
1344 DEBUGFS_REG32(SOR_SEQ_INST(5)),
1345 DEBUGFS_REG32(SOR_SEQ_INST(6)),
1346 DEBUGFS_REG32(SOR_SEQ_INST(7)),
1347 DEBUGFS_REG32(SOR_SEQ_INST(8)),
1348 DEBUGFS_REG32(SOR_SEQ_INST(9)),
1349 DEBUGFS_REG32(SOR_SEQ_INST(10)),
1350 DEBUGFS_REG32(SOR_SEQ_INST(11)),
1351 DEBUGFS_REG32(SOR_SEQ_INST(12)),
1352 DEBUGFS_REG32(SOR_SEQ_INST(13)),
1353 DEBUGFS_REG32(SOR_SEQ_INST(14)),
1354 DEBUGFS_REG32(SOR_SEQ_INST(15)),
1355 DEBUGFS_REG32(SOR_PWM_DIV),
1356 DEBUGFS_REG32(SOR_PWM_CTL),
1357 DEBUGFS_REG32(SOR_VCRC_A0),
1358 DEBUGFS_REG32(SOR_VCRC_A1),
1359 DEBUGFS_REG32(SOR_VCRC_B0),
1360 DEBUGFS_REG32(SOR_VCRC_B1),
1361 DEBUGFS_REG32(SOR_CCRC_A0),
1362 DEBUGFS_REG32(SOR_CCRC_A1),
1363 DEBUGFS_REG32(SOR_CCRC_B0),
1364 DEBUGFS_REG32(SOR_CCRC_B1),
1365 DEBUGFS_REG32(SOR_EDATA_A0),
1366 DEBUGFS_REG32(SOR_EDATA_A1),
1367 DEBUGFS_REG32(SOR_EDATA_B0),
1368 DEBUGFS_REG32(SOR_EDATA_B1),
1369 DEBUGFS_REG32(SOR_COUNT_A0),
1370 DEBUGFS_REG32(SOR_COUNT_A1),
1371 DEBUGFS_REG32(SOR_COUNT_B0),
1372 DEBUGFS_REG32(SOR_COUNT_B1),
1373 DEBUGFS_REG32(SOR_DEBUG_A0),
1374 DEBUGFS_REG32(SOR_DEBUG_A1),
1375 DEBUGFS_REG32(SOR_DEBUG_B0),
1376 DEBUGFS_REG32(SOR_DEBUG_B1),
1377 DEBUGFS_REG32(SOR_TRIG),
1378 DEBUGFS_REG32(SOR_MSCHECK),
1379 DEBUGFS_REG32(SOR_XBAR_CTRL),
1380 DEBUGFS_REG32(SOR_XBAR_POL),
1381 DEBUGFS_REG32(SOR_DP_LINKCTL0),
1382 DEBUGFS_REG32(SOR_DP_LINKCTL1),
1383 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1384 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1385 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1386 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1387 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1388 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1389 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1390 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1391 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1392 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1393 DEBUGFS_REG32(SOR_DP_CONFIG0),
1394 DEBUGFS_REG32(SOR_DP_CONFIG1),
1395 DEBUGFS_REG32(SOR_DP_MN0),
1396 DEBUGFS_REG32(SOR_DP_MN1),
1397 DEBUGFS_REG32(SOR_DP_PADCTL0),
1398 DEBUGFS_REG32(SOR_DP_PADCTL1),
1399 DEBUGFS_REG32(SOR_DP_PADCTL2),
1400 DEBUGFS_REG32(SOR_DP_DEBUG0),
1401 DEBUGFS_REG32(SOR_DP_DEBUG1),
1402 DEBUGFS_REG32(SOR_DP_SPARE0),
1403 DEBUGFS_REG32(SOR_DP_SPARE1),
1404 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1405 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1406 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1407 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1408 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1409 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1410 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1411 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1412 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1413 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1414 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1415 DEBUGFS_REG32(SOR_DP_TPG),
1416 DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1417 DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1418 DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1419 DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1422 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1424 struct drm_info_node *node = s->private;
1425 struct tegra_sor *sor = node->info_ent->data;
1426 struct drm_crtc *crtc = sor->output.encoder.crtc;
1427 struct drm_device *drm = node->minor->dev;
1431 drm_modeset_lock_all(drm);
1433 if (!crtc || !crtc->state->active) {
1438 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1439 unsigned int offset = tegra_sor_regs[i].offset;
1441 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1442 offset, tegra_sor_readl(sor, offset));
1446 drm_modeset_unlock_all(drm);
1450 static const struct drm_info_list debugfs_files[] = {
1451 { "crc", tegra_sor_show_crc, 0, NULL },
1452 { "regs", tegra_sor_show_regs, 0, NULL },
1455 static int tegra_sor_late_register(struct drm_connector *connector)
1457 struct tegra_output *output = connector_to_output(connector);
1458 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1459 struct drm_minor *minor = connector->dev->primary;
1460 struct dentry *root = connector->debugfs_entry;
1461 struct tegra_sor *sor = to_sor(output);
1464 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1466 if (!sor->debugfs_files)
1469 for (i = 0; i < count; i++)
1470 sor->debugfs_files[i].data = sor;
1472 err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1479 kfree(sor->debugfs_files);
1480 sor->debugfs_files = NULL;
1485 static void tegra_sor_early_unregister(struct drm_connector *connector)
1487 struct tegra_output *output = connector_to_output(connector);
1488 unsigned int count = ARRAY_SIZE(debugfs_files);
1489 struct tegra_sor *sor = to_sor(output);
1491 drm_debugfs_remove_files(sor->debugfs_files, count,
1492 connector->dev->primary);
1493 kfree(sor->debugfs_files);
1494 sor->debugfs_files = NULL;
1497 static void tegra_sor_connector_reset(struct drm_connector *connector)
1499 struct tegra_sor_state *state;
1501 state = kzalloc(sizeof(*state), GFP_KERNEL);
1505 if (connector->state) {
1506 __drm_atomic_helper_connector_destroy_state(connector->state);
1507 kfree(connector->state);
1510 __drm_atomic_helper_connector_reset(connector, &state->base);
1513 static enum drm_connector_status
1514 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1516 struct tegra_output *output = connector_to_output(connector);
1517 struct tegra_sor *sor = to_sor(output);
1520 return drm_dp_aux_detect(sor->aux);
1522 return tegra_output_connector_detect(connector, force);
1525 static struct drm_connector_state *
1526 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1528 struct tegra_sor_state *state = to_sor_state(connector->state);
1529 struct tegra_sor_state *copy;
1531 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1535 __drm_atomic_helper_connector_duplicate_state(connector, ©->base);
1540 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1541 .reset = tegra_sor_connector_reset,
1542 .detect = tegra_sor_connector_detect,
1543 .fill_modes = drm_helper_probe_single_connector_modes,
1544 .destroy = tegra_output_connector_destroy,
1545 .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1546 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1547 .late_register = tegra_sor_late_register,
1548 .early_unregister = tegra_sor_early_unregister,
1551 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1553 struct tegra_output *output = connector_to_output(connector);
1554 struct tegra_sor *sor = to_sor(output);
1558 drm_dp_aux_enable(sor->aux);
1560 err = tegra_output_connector_get_modes(connector);
1563 drm_dp_aux_disable(sor->aux);
1568 static enum drm_mode_status
1569 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1570 struct drm_display_mode *mode)
1575 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1576 .get_modes = tegra_sor_connector_get_modes,
1577 .mode_valid = tegra_sor_connector_mode_valid,
1580 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1581 .destroy = tegra_output_encoder_destroy,
1584 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1586 struct tegra_output *output = encoder_to_output(encoder);
1587 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1588 struct tegra_sor *sor = to_sor(output);
1593 drm_panel_disable(output->panel);
1595 err = tegra_sor_detach(sor);
1597 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1599 tegra_sor_writel(sor, 0, SOR_STATE1);
1600 tegra_sor_update(sor);
1603 * The following accesses registers of the display controller, so make
1604 * sure it's only executed when the output is attached to one.
1607 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1608 value &= ~SOR_ENABLE(0);
1609 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1611 tegra_dc_commit(dc);
1614 err = tegra_sor_power_down(sor);
1616 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1619 err = drm_dp_aux_disable(sor->aux);
1621 dev_err(sor->dev, "failed to disable DP: %d\n", err);
1624 err = tegra_io_pad_power_disable(sor->pad);
1626 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
1629 drm_panel_unprepare(output->panel);
1631 pm_runtime_put(sor->dev);
1635 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1636 unsigned int *value)
1638 unsigned int hfp, hsw, hbp, a = 0, b;
1640 hfp = mode->hsync_start - mode->hdisplay;
1641 hsw = mode->hsync_end - mode->hsync_start;
1642 hbp = mode->htotal - mode->hsync_end;
1644 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1648 pr_info("a: %u, b: %u\n", a, b);
1649 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1651 if (a + hsw + hbp <= 11) {
1652 a = 1 + 11 - hsw - hbp;
1653 pr_info("a: %u\n", a);
1662 if (mode->hdisplay < 16)
1676 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1678 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1679 struct tegra_output *output = encoder_to_output(encoder);
1680 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1681 struct tegra_sor *sor = to_sor(output);
1682 struct tegra_sor_config config;
1683 struct tegra_sor_state *state;
1684 struct drm_dp_link link;
1690 state = to_sor_state(output->connector.state);
1692 pm_runtime_get_sync(sor->dev);
1695 drm_panel_prepare(output->panel);
1697 err = drm_dp_aux_enable(sor->aux);
1699 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1701 err = drm_dp_link_probe(sor->aux, &link);
1703 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1707 /* switch to safe parent clock */
1708 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1710 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1712 memset(&config, 0, sizeof(config));
1713 config.bits_per_pixel = state->bpc * 3;
1715 err = tegra_sor_compute_config(sor, mode, &config, &link);
1717 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
1719 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1720 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1721 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1722 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1724 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1725 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1726 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1727 usleep_range(20, 100);
1729 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
1730 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1731 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
1733 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1734 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1735 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1737 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1738 value |= SOR_PLL2_SEQ_PLLCAPPD;
1739 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1740 value |= SOR_PLL2_LVDS_ENABLE;
1741 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1743 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1744 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
1747 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1748 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1751 usleep_range(250, 1000);
1754 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1755 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1756 value &= ~SOR_PLL2_PORT_POWERDOWN;
1757 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1763 /* set safe link bandwidth (1.62 Gbps) */
1764 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1765 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1766 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1767 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1770 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1771 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1772 SOR_PLL2_BANDGAP_POWERDOWN;
1773 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1775 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1776 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1777 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1779 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1780 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1781 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1784 err = tegra_io_pad_power_enable(sor->pad);
1786 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
1788 usleep_range(5, 100);
1791 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1792 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1793 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1795 usleep_range(20, 100);
1798 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1799 value &= ~SOR_PLL0_VCOPD;
1800 value &= ~SOR_PLL0_PWR;
1801 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1803 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1804 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1805 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1807 usleep_range(200, 1000);
1810 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1811 value &= ~SOR_PLL2_PORT_POWERDOWN;
1812 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1814 /* XXX not in TRM */
1815 for (value = 0, i = 0; i < 5; i++)
1816 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
1817 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1819 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1820 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1822 /* switch to DP parent clock */
1823 err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1825 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1827 /* power DP lanes */
1828 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1830 if (link.num_lanes <= 2)
1831 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1833 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1835 if (link.num_lanes <= 1)
1836 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1838 value |= SOR_DP_PADCTL_PD_TXD_1;
1840 if (link.num_lanes == 0)
1841 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1843 value |= SOR_DP_PADCTL_PD_TXD_0;
1845 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1847 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1848 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1849 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
1850 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1852 /* start lane sequencer */
1853 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1854 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1855 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1858 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1859 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1862 usleep_range(250, 1000);
1865 /* set link bandwidth */
1866 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1867 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1868 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1869 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1871 tegra_sor_apply_config(sor, &config);
1874 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1875 value |= SOR_DP_LINKCTL_ENABLE;
1876 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1877 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1879 for (i = 0, value = 0; i < 4; i++) {
1880 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1881 SOR_DP_TPG_SCRAMBLER_GALIOS |
1882 SOR_DP_TPG_PATTERN_NONE;
1883 value = (value << 8) | lane;
1886 tegra_sor_writel(sor, value, SOR_DP_TPG);
1888 /* enable pad calibration logic */
1889 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1890 value |= SOR_DP_PADCTL_PAD_CAL_PD;
1891 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1893 err = drm_dp_link_probe(sor->aux, &link);
1895 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1897 err = drm_dp_link_power_up(sor->aux, &link);
1899 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
1901 err = drm_dp_link_configure(sor->aux, &link);
1903 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
1905 rate = drm_dp_link_rate_to_bw_code(link.rate);
1906 lanes = link.num_lanes;
1908 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1909 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1910 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1911 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1913 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1914 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1915 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1917 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1918 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1920 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1922 /* disable training pattern generator */
1924 for (i = 0; i < link.num_lanes; i++) {
1925 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1926 SOR_DP_TPG_SCRAMBLER_GALIOS |
1927 SOR_DP_TPG_PATTERN_NONE;
1928 value = (value << 8) | lane;
1931 tegra_sor_writel(sor, value, SOR_DP_TPG);
1933 err = tegra_sor_dp_train_fast(sor, &link);
1935 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1937 dev_dbg(sor->dev, "fast link training succeeded\n");
1939 err = tegra_sor_power_up(sor, 250);
1941 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1943 /* CSTM (LVDS, link A/B, upper) */
1944 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1946 tegra_sor_writel(sor, value, SOR_CSTM);
1948 /* use DP-A protocol */
1949 value = tegra_sor_readl(sor, SOR_STATE1);
1950 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1951 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1952 tegra_sor_writel(sor, value, SOR_STATE1);
1954 tegra_sor_mode_set(sor, mode, state);
1957 err = tegra_sor_setup_pwm(sor, 250);
1959 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1961 tegra_sor_update(sor);
1963 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1964 value |= SOR_ENABLE(0);
1965 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1967 tegra_dc_commit(dc);
1969 err = tegra_sor_attach(sor);
1971 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1973 err = tegra_sor_wakeup(sor);
1975 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1978 drm_panel_enable(output->panel);
1982 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1983 struct drm_crtc_state *crtc_state,
1984 struct drm_connector_state *conn_state)
1986 struct tegra_output *output = encoder_to_output(encoder);
1987 struct tegra_sor_state *state = to_sor_state(conn_state);
1988 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1989 unsigned long pclk = crtc_state->mode.clock * 1000;
1990 struct tegra_sor *sor = to_sor(output);
1991 struct drm_display_info *info;
1994 info = &output->connector.display_info;
1997 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1998 * the pixel clock must be corrected accordingly.
2000 if (pclk >= 340000000) {
2001 state->link_speed = 20;
2002 state->pclk = pclk / 2;
2004 state->link_speed = 10;
2008 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
2011 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
2015 switch (info->bpc) {
2018 state->bpc = info->bpc;
2022 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
2030 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
2031 .disable = tegra_sor_edp_disable,
2032 .enable = tegra_sor_edp_enable,
2033 .atomic_check = tegra_sor_encoder_atomic_check,
2036 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
2041 for (i = size; i > 0; i--)
2042 value = (value << 8) | ptr[i - 1];
2047 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
2048 const void *data, size_t size)
2050 const u8 *ptr = data;
2051 unsigned long offset;
2056 case HDMI_INFOFRAME_TYPE_AVI:
2057 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
2060 case HDMI_INFOFRAME_TYPE_AUDIO:
2061 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
2064 case HDMI_INFOFRAME_TYPE_VENDOR:
2065 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
2069 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
2074 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
2075 INFOFRAME_HEADER_VERSION(ptr[1]) |
2076 INFOFRAME_HEADER_LEN(ptr[2]);
2077 tegra_sor_writel(sor, value, offset);
2081 * Each subpack contains 7 bytes, divided into:
2082 * - subpack_low: bytes 0 - 3
2083 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
2085 for (i = 3, j = 0; i < size; i += 7, j += 8) {
2086 size_t rem = size - i, num = min_t(size_t, rem, 4);
2088 value = tegra_sor_hdmi_subpack(&ptr[i], num);
2089 tegra_sor_writel(sor, value, offset++);
2091 num = min_t(size_t, rem - num, 3);
2093 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
2094 tegra_sor_writel(sor, value, offset++);
2099 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
2100 const struct drm_display_mode *mode)
2102 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
2103 struct hdmi_avi_infoframe frame;
2107 /* disable AVI infoframe */
2108 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2109 value &= ~INFOFRAME_CTRL_SINGLE;
2110 value &= ~INFOFRAME_CTRL_OTHER;
2111 value &= ~INFOFRAME_CTRL_ENABLE;
2112 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2114 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2115 &sor->output.connector, mode);
2117 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2121 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
2123 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
2127 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2129 /* enable AVI infoframe */
2130 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2131 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2132 value |= INFOFRAME_CTRL_ENABLE;
2133 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2138 static void tegra_sor_write_eld(struct tegra_sor *sor)
2140 size_t length = drm_eld_size(sor->output.connector.eld), i;
2142 for (i = 0; i < length; i++)
2143 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
2144 SOR_AUDIO_HDA_ELD_BUFWR);
2147 * The HDA codec will always report an ELD buffer size of 96 bytes and
2148 * the HDA codec driver will check that each byte read from the buffer
2149 * is valid. Therefore every byte must be written, even if no 96 bytes
2150 * were parsed from EDID.
2152 for (i = length; i < 96; i++)
2153 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
2156 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
2160 tegra_sor_write_eld(sor);
2162 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
2163 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
2166 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
2168 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
2171 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2173 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2174 struct hdmi_audio_infoframe frame;
2178 err = hdmi_audio_infoframe_init(&frame);
2180 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2184 frame.channels = sor->format.channels;
2186 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2188 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2192 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2194 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2195 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2196 value |= INFOFRAME_CTRL_ENABLE;
2197 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2202 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2206 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2208 /* select HDA audio input */
2209 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2210 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2212 /* inject null samples */
2213 if (sor->format.channels != 2)
2214 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2216 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2218 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2220 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2222 /* enable advertising HBR capability */
2223 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2225 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2227 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2228 SOR_HDMI_SPARE_CTS_RESET(1) |
2229 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2230 tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2233 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2234 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2236 /* allow packet to be sent */
2237 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2238 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2240 /* reset N counter and enable lookup */
2241 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2242 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2244 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2245 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2246 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2248 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2249 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2251 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2252 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2254 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2255 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2257 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2258 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2259 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2261 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2262 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2263 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2265 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2266 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2267 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2269 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2270 value &= ~SOR_HDMI_AUDIO_N_RESET;
2271 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2273 tegra_sor_hdmi_enable_audio_infoframe(sor);
2276 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2280 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2281 value &= ~INFOFRAME_CTRL_ENABLE;
2282 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2285 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2287 tegra_sor_hdmi_disable_audio_infoframe(sor);
2290 static struct tegra_sor_hdmi_settings *
2291 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2295 for (i = 0; i < sor->num_settings; i++)
2296 if (frequency <= sor->settings[i].frequency)
2297 return &sor->settings[i];
2302 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2306 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2307 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2308 value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2309 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2312 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2314 struct i2c_adapter *ddc = sor->output.ddc;
2316 drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2317 drm_scdc_set_scrambling(ddc, false);
2319 tegra_sor_hdmi_disable_scrambling(sor);
2322 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2324 if (sor->scdc_enabled) {
2325 cancel_delayed_work_sync(&sor->scdc);
2326 tegra_sor_hdmi_scdc_disable(sor);
2330 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2334 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2335 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2336 value |= SOR_HDMI2_CTRL_SCRAMBLE;
2337 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2340 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2342 struct i2c_adapter *ddc = sor->output.ddc;
2344 drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2345 drm_scdc_set_scrambling(ddc, true);
2347 tegra_sor_hdmi_enable_scrambling(sor);
2350 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2352 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2353 struct i2c_adapter *ddc = sor->output.ddc;
2355 if (!drm_scdc_get_scrambling_status(ddc)) {
2356 DRM_DEBUG_KMS("SCDC not scrambled\n");
2357 tegra_sor_hdmi_scdc_enable(sor);
2360 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2363 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2365 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2366 struct drm_display_mode *mode;
2368 mode = &sor->output.encoder.crtc->state->adjusted_mode;
2370 if (mode->clock >= 340000 && scdc->supported) {
2371 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2372 tegra_sor_hdmi_scdc_enable(sor);
2373 sor->scdc_enabled = true;
2377 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2379 struct tegra_output *output = encoder_to_output(encoder);
2380 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2381 struct tegra_sor *sor = to_sor(output);
2385 tegra_sor_audio_unprepare(sor);
2386 tegra_sor_hdmi_scdc_stop(sor);
2388 err = tegra_sor_detach(sor);
2390 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2392 tegra_sor_writel(sor, 0, SOR_STATE1);
2393 tegra_sor_update(sor);
2395 /* disable display to SOR clock */
2396 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2398 if (!sor->soc->has_nvdisplay)
2399 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2401 value &= ~SOR_ENABLE(sor->index);
2403 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2405 tegra_dc_commit(dc);
2407 err = tegra_sor_power_down(sor);
2409 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2411 err = tegra_io_pad_power_disable(sor->pad);
2413 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2415 pm_runtime_put(sor->dev);
2418 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2420 struct tegra_output *output = encoder_to_output(encoder);
2421 unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2422 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2423 struct tegra_sor_hdmi_settings *settings;
2424 struct tegra_sor *sor = to_sor(output);
2425 struct tegra_sor_state *state;
2426 struct drm_display_mode *mode;
2427 unsigned long rate, pclk;
2428 unsigned int div, i;
2432 state = to_sor_state(output->connector.state);
2433 mode = &encoder->crtc->state->adjusted_mode;
2434 pclk = mode->clock * 1000;
2436 pm_runtime_get_sync(sor->dev);
2438 /* switch to safe parent clock */
2439 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2441 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2445 div = clk_get_rate(sor->clk) / 1000000 * 4;
2447 err = tegra_io_pad_power_enable(sor->pad);
2449 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2451 usleep_range(20, 100);
2453 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2454 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2455 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2457 usleep_range(20, 100);
2459 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2460 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2461 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2463 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2464 value &= ~SOR_PLL0_VCOPD;
2465 value &= ~SOR_PLL0_PWR;
2466 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2468 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2469 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2470 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2472 usleep_range(200, 400);
2474 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2475 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2476 value &= ~SOR_PLL2_PORT_POWERDOWN;
2477 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2479 usleep_range(20, 100);
2481 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2482 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2483 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2484 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2487 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2488 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2491 usleep_range(250, 1000);
2494 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2495 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2496 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2499 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2500 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2503 usleep_range(250, 1000);
2506 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2507 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2508 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2510 if (mode->clock < 340000) {
2511 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2512 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2514 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2515 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2518 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2519 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2521 /* SOR pad PLL stabilization time */
2522 usleep_range(250, 1000);
2524 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2525 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2526 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2527 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2529 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2530 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2531 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2532 value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2533 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2534 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2536 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2537 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2538 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2540 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2541 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2542 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2543 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2545 if (!sor->soc->has_nvdisplay) {
2546 /* program the reference clock */
2547 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2548 tegra_sor_writel(sor, value, SOR_REFCLK);
2551 /* XXX not in TRM */
2552 for (value = 0, i = 0; i < 5; i++)
2553 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2554 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2556 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2557 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2559 /* switch to parent clock */
2560 err = clk_set_parent(sor->clk, sor->clk_parent);
2562 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2566 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2568 dev_err(sor->dev, "failed to set pad clock: %d\n", err);
2572 /* adjust clock rate for HDMI 2.0 modes */
2573 rate = clk_get_rate(sor->clk_parent);
2575 if (mode->clock >= 340000)
2578 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2580 clk_set_rate(sor->clk, rate);
2582 if (!sor->soc->has_nvdisplay) {
2583 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2585 /* XXX is this the proper check? */
2586 if (mode->clock < 75000)
2587 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2589 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2592 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2594 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2595 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2596 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2598 if (!dc->soc->has_nvdisplay) {
2599 /* H_PULSE2 setup */
2600 pulse_start = h_ref_to_sync +
2601 (mode->hsync_end - mode->hsync_start) +
2602 (mode->htotal - mode->hsync_end) - 10;
2604 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2605 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2606 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2608 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2609 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2611 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2612 value |= H_PULSE2_ENABLE;
2613 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2616 /* infoframe setup */
2617 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2619 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2621 /* XXX HDMI audio support not implemented yet */
2622 tegra_sor_hdmi_disable_audio_infoframe(sor);
2624 /* use single TMDS protocol */
2625 value = tegra_sor_readl(sor, SOR_STATE1);
2626 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2627 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2628 tegra_sor_writel(sor, value, SOR_STATE1);
2630 /* power up pad calibration */
2631 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2632 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2633 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2635 /* production settings */
2636 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2638 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2639 mode->clock * 1000);
2643 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2644 value &= ~SOR_PLL0_ICHPMP_MASK;
2645 value &= ~SOR_PLL0_FILTER_MASK;
2646 value &= ~SOR_PLL0_VCOCAP_MASK;
2647 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2648 value |= SOR_PLL0_FILTER(settings->filter);
2649 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2650 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2652 /* XXX not in TRM */
2653 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2654 value &= ~SOR_PLL1_LOADADJ_MASK;
2655 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2656 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2657 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2658 value |= SOR_PLL1_TMDS_TERM;
2659 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2661 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2662 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2663 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2664 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2665 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2666 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2667 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2668 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2669 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2670 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2672 value = settings->drive_current[3] << 24 |
2673 settings->drive_current[2] << 16 |
2674 settings->drive_current[1] << 8 |
2675 settings->drive_current[0] << 0;
2676 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2678 value = settings->preemphasis[3] << 24 |
2679 settings->preemphasis[2] << 16 |
2680 settings->preemphasis[1] << 8 |
2681 settings->preemphasis[0] << 0;
2682 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2684 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2685 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2686 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2687 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2688 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2690 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2691 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2692 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2693 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2695 /* power down pad calibration */
2696 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2697 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2698 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2700 if (!dc->soc->has_nvdisplay) {
2701 /* miscellaneous display controller settings */
2702 value = VSYNC_H_POSITION(1);
2703 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2706 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2707 value &= ~DITHER_CONTROL_MASK;
2708 value &= ~BASE_COLOR_SIZE_MASK;
2710 switch (state->bpc) {
2712 value |= BASE_COLOR_SIZE_666;
2716 value |= BASE_COLOR_SIZE_888;
2720 value |= BASE_COLOR_SIZE_101010;
2724 value |= BASE_COLOR_SIZE_121212;
2728 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2729 value |= BASE_COLOR_SIZE_888;
2733 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2735 /* XXX set display head owner */
2736 value = tegra_sor_readl(sor, SOR_STATE1);
2737 value &= ~SOR_STATE_ASY_OWNER_MASK;
2738 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2739 tegra_sor_writel(sor, value, SOR_STATE1);
2741 err = tegra_sor_power_up(sor, 250);
2743 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2745 /* configure dynamic range of output */
2746 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2747 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2748 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2749 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2751 /* configure colorspace */
2752 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2753 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2754 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2755 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2757 tegra_sor_mode_set(sor, mode, state);
2759 tegra_sor_update(sor);
2761 /* program preamble timing in SOR (XXX) */
2762 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2763 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2764 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2766 err = tegra_sor_attach(sor);
2768 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2770 /* enable display to SOR clock and generate HDMI preamble */
2771 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2773 if (!sor->soc->has_nvdisplay)
2774 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA;
2776 value |= SOR_ENABLE(sor->index);
2778 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2780 if (dc->soc->has_nvdisplay) {
2781 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2782 value &= ~PROTOCOL_MASK;
2783 value |= PROTOCOL_SINGLE_TMDS_A;
2784 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2787 tegra_dc_commit(dc);
2789 err = tegra_sor_wakeup(sor);
2791 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2793 tegra_sor_hdmi_scdc_start(sor);
2794 tegra_sor_audio_prepare(sor);
2797 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2798 .disable = tegra_sor_hdmi_disable,
2799 .enable = tegra_sor_hdmi_enable,
2800 .atomic_check = tegra_sor_encoder_atomic_check,
2803 static int tegra_sor_init(struct host1x_client *client)
2805 struct drm_device *drm = dev_get_drvdata(client->parent);
2806 const struct drm_encoder_helper_funcs *helpers = NULL;
2807 struct tegra_sor *sor = host1x_client_to_sor(client);
2808 int connector = DRM_MODE_CONNECTOR_Unknown;
2809 int encoder = DRM_MODE_ENCODER_NONE;
2814 if (sor->soc->supports_hdmi) {
2815 connector = DRM_MODE_CONNECTOR_HDMIA;
2816 encoder = DRM_MODE_ENCODER_TMDS;
2817 helpers = &tegra_sor_hdmi_helpers;
2818 } else if (sor->soc->supports_lvds) {
2819 connector = DRM_MODE_CONNECTOR_LVDS;
2820 encoder = DRM_MODE_ENCODER_LVDS;
2823 if (sor->soc->supports_edp) {
2824 connector = DRM_MODE_CONNECTOR_eDP;
2825 encoder = DRM_MODE_ENCODER_TMDS;
2826 helpers = &tegra_sor_edp_helpers;
2827 } else if (sor->soc->supports_dp) {
2828 connector = DRM_MODE_CONNECTOR_DisplayPort;
2829 encoder = DRM_MODE_ENCODER_TMDS;
2833 sor->output.dev = sor->dev;
2835 drm_connector_init(drm, &sor->output.connector,
2836 &tegra_sor_connector_funcs,
2838 drm_connector_helper_add(&sor->output.connector,
2839 &tegra_sor_connector_helper_funcs);
2840 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2842 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
2844 drm_encoder_helper_add(&sor->output.encoder, helpers);
2846 drm_connector_attach_encoder(&sor->output.connector,
2847 &sor->output.encoder);
2848 drm_connector_register(&sor->output.connector);
2850 err = tegra_output_init(drm, &sor->output);
2852 dev_err(client->dev, "failed to initialize output: %d\n", err);
2856 tegra_output_find_possible_crtcs(&sor->output, drm);
2859 err = drm_dp_aux_attach(sor->aux, &sor->output);
2861 dev_err(sor->dev, "failed to attach DP: %d\n", err);
2867 * XXX: Remove this reset once proper hand-over from firmware to
2868 * kernel is possible.
2871 err = reset_control_acquire(sor->rst);
2873 dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
2878 err = reset_control_assert(sor->rst);
2880 dev_err(sor->dev, "failed to assert SOR reset: %d\n",
2886 err = clk_prepare_enable(sor->clk);
2888 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2892 usleep_range(1000, 3000);
2895 err = reset_control_deassert(sor->rst);
2897 dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
2902 reset_control_release(sor->rst);
2905 err = clk_prepare_enable(sor->clk_safe);
2909 err = clk_prepare_enable(sor->clk_dp);
2914 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
2915 * is used for interoperability between the HDA codec driver and the
2918 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
2919 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
2920 tegra_sor_writel(sor, value, SOR_INT_MASK);
2925 static int tegra_sor_exit(struct host1x_client *client)
2927 struct tegra_sor *sor = host1x_client_to_sor(client);
2930 tegra_sor_writel(sor, 0, SOR_INT_MASK);
2931 tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2933 tegra_output_exit(&sor->output);
2936 err = drm_dp_aux_detach(sor->aux);
2938 dev_err(sor->dev, "failed to detach DP: %d\n", err);
2943 clk_disable_unprepare(sor->clk_safe);
2944 clk_disable_unprepare(sor->clk_dp);
2945 clk_disable_unprepare(sor->clk);
2950 static const struct host1x_client_ops sor_client_ops = {
2951 .init = tegra_sor_init,
2952 .exit = tegra_sor_exit,
2955 static const struct tegra_sor_ops tegra_sor_edp_ops = {
2959 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2963 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2964 if (IS_ERR(sor->avdd_io_supply)) {
2965 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2966 PTR_ERR(sor->avdd_io_supply));
2967 return PTR_ERR(sor->avdd_io_supply);
2970 err = regulator_enable(sor->avdd_io_supply);
2972 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2977 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2978 if (IS_ERR(sor->vdd_pll_supply)) {
2979 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2980 PTR_ERR(sor->vdd_pll_supply));
2981 return PTR_ERR(sor->vdd_pll_supply);
2984 err = regulator_enable(sor->vdd_pll_supply);
2986 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2991 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2992 if (IS_ERR(sor->hdmi_supply)) {
2993 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2994 PTR_ERR(sor->hdmi_supply));
2995 return PTR_ERR(sor->hdmi_supply);
2998 err = regulator_enable(sor->hdmi_supply);
3000 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
3004 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3009 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
3011 regulator_disable(sor->hdmi_supply);
3012 regulator_disable(sor->vdd_pll_supply);
3013 regulator_disable(sor->avdd_io_supply);
3018 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3020 .probe = tegra_sor_hdmi_probe,
3021 .remove = tegra_sor_hdmi_remove,
3024 static const u8 tegra124_sor_xbar_cfg[5] = {
3028 static const struct tegra_sor_regs tegra124_sor_regs = {
3029 .head_state0 = 0x05,
3030 .head_state1 = 0x07,
3031 .head_state2 = 0x09,
3032 .head_state3 = 0x0b,
3033 .head_state4 = 0x0d,
3034 .head_state5 = 0x0f,
3043 static const struct tegra_sor_soc tegra124_sor = {
3044 .supports_edp = true,
3045 .supports_lvds = true,
3046 .supports_hdmi = false,
3047 .supports_dp = false,
3048 .regs = &tegra124_sor_regs,
3049 .has_nvdisplay = false,
3050 .xbar_cfg = tegra124_sor_xbar_cfg,
3053 static const struct tegra_sor_regs tegra210_sor_regs = {
3054 .head_state0 = 0x05,
3055 .head_state1 = 0x07,
3056 .head_state2 = 0x09,
3057 .head_state3 = 0x0b,
3058 .head_state4 = 0x0d,
3059 .head_state5 = 0x0f,
3068 static const struct tegra_sor_soc tegra210_sor = {
3069 .supports_edp = true,
3070 .supports_lvds = false,
3071 .supports_hdmi = false,
3072 .supports_dp = false,
3073 .regs = &tegra210_sor_regs,
3074 .has_nvdisplay = false,
3075 .xbar_cfg = tegra124_sor_xbar_cfg,
3078 static const u8 tegra210_sor_xbar_cfg[5] = {
3082 static const struct tegra_sor_soc tegra210_sor1 = {
3083 .supports_edp = false,
3084 .supports_lvds = false,
3085 .supports_hdmi = true,
3086 .supports_dp = true,
3088 .regs = &tegra210_sor_regs,
3089 .has_nvdisplay = false,
3091 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3092 .settings = tegra210_sor_hdmi_defaults,
3094 .xbar_cfg = tegra210_sor_xbar_cfg,
3097 static const struct tegra_sor_regs tegra186_sor_regs = {
3098 .head_state0 = 0x151,
3099 .head_state1 = 0x154,
3100 .head_state2 = 0x157,
3101 .head_state3 = 0x15a,
3102 .head_state4 = 0x15d,
3103 .head_state5 = 0x160,
3108 .dp_padctl0 = 0x168,
3109 .dp_padctl2 = 0x16a,
3112 static const struct tegra_sor_soc tegra186_sor = {
3113 .supports_edp = false,
3114 .supports_lvds = false,
3115 .supports_hdmi = false,
3116 .supports_dp = true,
3118 .regs = &tegra186_sor_regs,
3119 .has_nvdisplay = true,
3121 .xbar_cfg = tegra124_sor_xbar_cfg,
3124 static const struct tegra_sor_soc tegra186_sor1 = {
3125 .supports_edp = false,
3126 .supports_lvds = false,
3127 .supports_hdmi = true,
3128 .supports_dp = true,
3130 .regs = &tegra186_sor_regs,
3131 .has_nvdisplay = true,
3133 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3134 .settings = tegra186_sor_hdmi_defaults,
3136 .xbar_cfg = tegra124_sor_xbar_cfg,
3139 static const struct tegra_sor_regs tegra194_sor_regs = {
3140 .head_state0 = 0x151,
3141 .head_state1 = 0x155,
3142 .head_state2 = 0x159,
3143 .head_state3 = 0x15d,
3144 .head_state4 = 0x161,
3145 .head_state5 = 0x165,
3150 .dp_padctl0 = 0x16e,
3151 .dp_padctl2 = 0x16f,
3154 static const struct tegra_sor_soc tegra194_sor = {
3155 .supports_edp = true,
3156 .supports_lvds = false,
3157 .supports_hdmi = true,
3158 .supports_dp = true,
3160 .regs = &tegra194_sor_regs,
3161 .has_nvdisplay = true,
3163 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3164 .settings = tegra194_sor_hdmi_defaults,
3166 .xbar_cfg = tegra210_sor_xbar_cfg,
3169 static const struct of_device_id tegra_sor_of_match[] = {
3170 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3171 { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 },
3172 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3173 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3174 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3175 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3178 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3180 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3182 struct device_node *np = sor->dev->of_node;
3188 if (sor->soc->has_nvdisplay) {
3189 err = of_property_read_u32(np, "nvidia,interface", &value);
3196 * override the default that we already set for Tegra210 and
3199 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3202 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3204 /* fall back to default per-SoC XBAR configuration */
3205 for (i = 0; i < 5; i++)
3206 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3208 /* copy cells to SOR XBAR configuration */
3209 for (i = 0; i < 5; i++)
3210 sor->xbar_cfg[i] = xbar_cfg[i];
3216 static irqreturn_t tegra_sor_irq(int irq, void *data)
3218 struct tegra_sor *sor = data;
3221 value = tegra_sor_readl(sor, SOR_INT_STATUS);
3222 tegra_sor_writel(sor, value, SOR_INT_STATUS);
3224 if (value & SOR_INT_CODEC_SCRATCH0) {
3225 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3227 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3228 unsigned int format;
3230 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3232 tegra_hda_parse_format(format, &sor->format);
3234 tegra_sor_hdmi_audio_enable(sor);
3236 tegra_sor_hdmi_audio_disable(sor);
3243 static int tegra_sor_probe(struct platform_device *pdev)
3245 struct device_node *np;
3246 struct tegra_sor *sor;
3247 struct resource *regs;
3250 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3254 sor->soc = of_device_get_match_data(&pdev->dev);
3255 sor->output.dev = sor->dev = &pdev->dev;
3257 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3258 sor->soc->num_settings *
3259 sizeof(*sor->settings),
3264 sor->num_settings = sor->soc->num_settings;
3266 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3268 sor->aux = drm_dp_aux_find_by_of_node(np);
3272 return -EPROBE_DEFER;
3276 if (sor->soc->supports_hdmi) {
3277 sor->ops = &tegra_sor_hdmi_ops;
3278 sor->pad = TEGRA_IO_PAD_HDMI;
3279 } else if (sor->soc->supports_lvds) {
3280 dev_err(&pdev->dev, "LVDS not supported yet\n");
3283 dev_err(&pdev->dev, "unknown (non-DP) support\n");
3287 if (sor->soc->supports_edp) {
3288 sor->ops = &tegra_sor_edp_ops;
3289 sor->pad = TEGRA_IO_PAD_LVDS;
3290 } else if (sor->soc->supports_dp) {
3291 dev_err(&pdev->dev, "DisplayPort not supported yet\n");
3294 dev_err(&pdev->dev, "unknown (DP) support\n");
3299 err = tegra_sor_parse_dt(sor);
3303 err = tegra_output_probe(&sor->output);
3305 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
3309 if (sor->ops && sor->ops->probe) {
3310 err = sor->ops->probe(sor);
3312 dev_err(&pdev->dev, "failed to probe %s: %d\n",
3313 sor->ops->name, err);
3318 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3319 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3320 if (IS_ERR(sor->regs)) {
3321 err = PTR_ERR(sor->regs);
3325 err = platform_get_irq(pdev, 0);
3327 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
3333 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3334 dev_name(sor->dev), sor);
3336 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3340 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3341 if (IS_ERR(sor->rst)) {
3342 err = PTR_ERR(sor->rst);
3344 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3345 dev_err(&pdev->dev, "failed to get reset control: %d\n",
3351 * At this point, the reset control is most likely being used
3352 * by the generic power domain implementation. With any luck
3353 * the power domain will have taken care of resetting the SOR
3354 * and we don't have to do anything.
3359 sor->clk = devm_clk_get(&pdev->dev, NULL);
3360 if (IS_ERR(sor->clk)) {
3361 err = PTR_ERR(sor->clk);
3362 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3366 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3367 struct device_node *np = pdev->dev.of_node;
3371 * For backwards compatibility with Tegra210 device trees,
3372 * fall back to the old clock name "source" if the new "out"
3373 * clock is not available.
3375 if (of_property_match_string(np, "clock-names", "out") < 0)
3380 sor->clk_out = devm_clk_get(&pdev->dev, name);
3381 if (IS_ERR(sor->clk_out)) {
3382 err = PTR_ERR(sor->clk_out);
3383 dev_err(sor->dev, "failed to get %s clock: %d\n",
3388 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3389 sor->clk_out = sor->clk;
3392 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3393 if (IS_ERR(sor->clk_parent)) {
3394 err = PTR_ERR(sor->clk_parent);
3395 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3399 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3400 if (IS_ERR(sor->clk_safe)) {
3401 err = PTR_ERR(sor->clk_safe);
3402 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3406 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3407 if (IS_ERR(sor->clk_dp)) {
3408 err = PTR_ERR(sor->clk_dp);
3409 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3414 * Starting with Tegra186, the BPMP provides an implementation for
3415 * the pad output clock, so we have to look it up from device tree.
3417 sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3418 if (IS_ERR(sor->clk_pad)) {
3419 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3420 err = PTR_ERR(sor->clk_pad);
3425 * If the pad output clock is not available, then we assume
3426 * we're on Tegra210 or earlier and have to provide our own
3429 sor->clk_pad = NULL;
3433 * The bootloader may have set up the SOR such that it's module clock
3434 * is sourced by one of the display PLLs. However, that doesn't work
3435 * without properly having set up other bits of the SOR.
3437 err = clk_set_parent(sor->clk_out, sor->clk_safe);
3439 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3443 platform_set_drvdata(pdev, sor);
3444 pm_runtime_enable(&pdev->dev);
3447 * On Tegra210 and earlier, provide our own implementation for the
3450 if (!sor->clk_pad) {
3451 err = pm_runtime_get_sync(&pdev->dev);
3453 dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
3458 sor->clk_pad = tegra_clk_sor_pad_register(sor,
3460 pm_runtime_put(&pdev->dev);
3463 if (IS_ERR(sor->clk_pad)) {
3464 err = PTR_ERR(sor->clk_pad);
3465 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
3470 INIT_LIST_HEAD(&sor->client.list);
3471 sor->client.ops = &sor_client_ops;
3472 sor->client.dev = &pdev->dev;
3474 err = host1x_client_register(&sor->client);
3476 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3484 if (sor->ops && sor->ops->remove)
3485 sor->ops->remove(sor);
3487 tegra_output_remove(&sor->output);
3491 static int tegra_sor_remove(struct platform_device *pdev)
3493 struct tegra_sor *sor = platform_get_drvdata(pdev);
3496 pm_runtime_disable(&pdev->dev);
3498 err = host1x_client_unregister(&sor->client);
3500 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3505 if (sor->ops && sor->ops->remove) {
3506 err = sor->ops->remove(sor);
3508 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
3511 tegra_output_remove(&sor->output);
3517 static int tegra_sor_suspend(struct device *dev)
3519 struct tegra_sor *sor = dev_get_drvdata(dev);
3523 err = reset_control_assert(sor->rst);
3525 dev_err(dev, "failed to assert reset: %d\n", err);
3529 reset_control_release(sor->rst);
3532 usleep_range(1000, 2000);
3534 clk_disable_unprepare(sor->clk);
3539 static int tegra_sor_resume(struct device *dev)
3541 struct tegra_sor *sor = dev_get_drvdata(dev);
3544 err = clk_prepare_enable(sor->clk);
3546 dev_err(dev, "failed to enable clock: %d\n", err);
3550 usleep_range(1000, 2000);
3553 err = reset_control_acquire(sor->rst);
3555 dev_err(dev, "failed to acquire reset: %d\n", err);
3556 clk_disable_unprepare(sor->clk);
3560 err = reset_control_deassert(sor->rst);
3562 dev_err(dev, "failed to deassert reset: %d\n", err);
3563 reset_control_release(sor->rst);
3564 clk_disable_unprepare(sor->clk);
3573 static const struct dev_pm_ops tegra_sor_pm_ops = {
3574 SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
3577 struct platform_driver tegra_sor_driver = {
3579 .name = "tegra-sor",
3580 .of_match_table = tegra_sor_of_match,
3581 .pm = &tegra_sor_pm_ops,
3583 .probe = tegra_sor_probe,
3584 .remove = tegra_sor_remove,