1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
6 #include <linux/iommu.h>
8 #include <drm/drm_atomic.h>
9 #include <drm/drm_atomic_helper.h>
10 #include <drm/drm_fourcc.h>
11 #include <drm/drm_gem_atomic_helper.h>
12 #include <drm/drm_plane_helper.h>
17 static void tegra_plane_destroy(struct drm_plane *plane)
19 struct tegra_plane *p = to_tegra_plane(plane);
21 drm_plane_cleanup(plane);
25 static void tegra_plane_reset(struct drm_plane *plane)
27 struct tegra_plane *p = to_tegra_plane(plane);
28 struct tegra_plane_state *state;
32 __drm_atomic_helper_plane_destroy_state(plane->state);
37 state = kzalloc(sizeof(*state), GFP_KERNEL);
39 plane->state = &state->base;
40 plane->state->plane = plane;
41 plane->state->zpos = p->index;
42 plane->state->normalized_zpos = p->index;
44 for (i = 0; i < 3; i++)
45 state->iova[i] = DMA_MAPPING_ERROR;
49 static struct drm_plane_state *
50 tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
52 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
53 struct tegra_plane_state *copy;
56 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
60 __drm_atomic_helper_plane_duplicate_state(plane, ©->base);
61 copy->tiling = state->tiling;
62 copy->format = state->format;
63 copy->swap = state->swap;
64 copy->reflect_x = state->reflect_x;
65 copy->reflect_y = state->reflect_y;
66 copy->opaque = state->opaque;
68 for (i = 0; i < 2; i++)
69 copy->blending[i] = state->blending[i];
71 for (i = 0; i < 3; i++) {
72 copy->iova[i] = DMA_MAPPING_ERROR;
79 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
80 struct drm_plane_state *state)
82 __drm_atomic_helper_plane_destroy_state(state);
86 static bool tegra_plane_supports_sector_layout(struct drm_plane *plane)
88 struct drm_crtc *crtc;
90 drm_for_each_crtc(crtc, plane->dev) {
91 if (plane->possible_crtcs & drm_crtc_mask(crtc)) {
92 struct tegra_dc *dc = to_tegra_dc(crtc);
94 if (!dc->soc->supports_sector_layout)
102 static bool tegra_plane_format_mod_supported(struct drm_plane *plane,
106 const struct drm_format_info *info = drm_format_info(format);
108 if (modifier == DRM_FORMAT_MOD_LINEAR)
111 /* check for the sector layout bit */
112 if ((modifier >> 56) == DRM_FORMAT_MOD_VENDOR_NVIDIA) {
113 if (modifier & DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT) {
114 if (!tegra_plane_supports_sector_layout(plane))
119 if (info->num_planes == 1)
125 const struct drm_plane_funcs tegra_plane_funcs = {
126 .update_plane = drm_atomic_helper_update_plane,
127 .disable_plane = drm_atomic_helper_disable_plane,
128 .destroy = tegra_plane_destroy,
129 .reset = tegra_plane_reset,
130 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
131 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
132 .format_mod_supported = tegra_plane_format_mod_supported,
135 static int tegra_dc_pin(struct tegra_dc *dc, struct tegra_plane_state *state)
137 struct iommu_domain *domain = iommu_get_domain_for_dev(dc->dev);
141 for (i = 0; i < state->base.fb->format->num_planes; i++) {
142 struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i);
143 dma_addr_t phys_addr, *phys;
144 struct sg_table *sgt;
147 * If we're not attached to a domain, we already stored the
148 * physical address when the buffer was allocated. If we're
149 * part of a group that's shared between all display
150 * controllers, we've also already mapped the framebuffer
151 * through the SMMU. In both cases we can short-circuit the
152 * code below and retrieve the stored IOV address.
154 if (!domain || dc->client.group)
159 sgt = host1x_bo_pin(dc->dev, &bo->base, phys);
166 err = dma_map_sgtable(dc->dev, sgt, DMA_TO_DEVICE, 0);
171 * The display controller needs contiguous memory, so
172 * fail if the buffer is discontiguous and we fail to
173 * map its SG table to a single contiguous chunk of
174 * I/O virtual memory.
176 if (sgt->nents > 1) {
181 state->iova[i] = sg_dma_address(sgt->sgl);
184 state->iova[i] = phys_addr;
191 dev_err(dc->dev, "failed to map plane %u: %d\n", i, err);
194 struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i);
195 struct sg_table *sgt = state->sgt[i];
198 dma_unmap_sgtable(dc->dev, sgt, DMA_TO_DEVICE, 0);
200 host1x_bo_unpin(dc->dev, &bo->base, sgt);
201 state->iova[i] = DMA_MAPPING_ERROR;
202 state->sgt[i] = NULL;
208 static void tegra_dc_unpin(struct tegra_dc *dc, struct tegra_plane_state *state)
212 for (i = 0; i < state->base.fb->format->num_planes; i++) {
213 struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i);
214 struct sg_table *sgt = state->sgt[i];
217 dma_unmap_sgtable(dc->dev, sgt, DMA_TO_DEVICE, 0);
219 host1x_bo_unpin(dc->dev, &bo->base, sgt);
220 state->iova[i] = DMA_MAPPING_ERROR;
221 state->sgt[i] = NULL;
225 int tegra_plane_prepare_fb(struct drm_plane *plane,
226 struct drm_plane_state *state)
228 struct tegra_dc *dc = to_tegra_dc(state->crtc);
233 drm_gem_plane_helper_prepare_fb(plane, state);
235 return tegra_dc_pin(dc, to_tegra_plane_state(state));
238 void tegra_plane_cleanup_fb(struct drm_plane *plane,
239 struct drm_plane_state *state)
241 struct tegra_dc *dc = to_tegra_dc(state->crtc);
244 tegra_dc_unpin(dc, to_tegra_plane_state(state));
247 int tegra_plane_state_add(struct tegra_plane *plane,
248 struct drm_plane_state *state)
250 struct drm_crtc_state *crtc_state;
251 struct tegra_dc_state *tegra;
254 /* Propagate errors from allocation or locking failures. */
255 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
256 if (IS_ERR(crtc_state))
257 return PTR_ERR(crtc_state);
259 /* Check plane state for visibility and calculate clipping bounds */
260 err = drm_atomic_helper_check_plane_state(state, crtc_state,
261 0, INT_MAX, true, true);
265 tegra = to_dc_state(crtc_state);
267 tegra->planes |= WIN_A_ACT_REQ << plane->index;
272 int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap)
274 /* assume no swapping of fetched data */
276 *swap = BYTE_SWAP_NOSWAP;
279 case DRM_FORMAT_ARGB4444:
280 *format = WIN_COLOR_DEPTH_B4G4R4A4;
283 case DRM_FORMAT_ARGB1555:
284 *format = WIN_COLOR_DEPTH_B5G5R5A1;
287 case DRM_FORMAT_RGB565:
288 *format = WIN_COLOR_DEPTH_B5G6R5;
291 case DRM_FORMAT_RGBA5551:
292 *format = WIN_COLOR_DEPTH_A1B5G5R5;
295 case DRM_FORMAT_ARGB8888:
296 *format = WIN_COLOR_DEPTH_B8G8R8A8;
299 case DRM_FORMAT_ABGR8888:
300 *format = WIN_COLOR_DEPTH_R8G8B8A8;
303 case DRM_FORMAT_ABGR4444:
304 *format = WIN_COLOR_DEPTH_R4G4B4A4;
307 case DRM_FORMAT_ABGR1555:
308 *format = WIN_COLOR_DEPTH_R5G5B5A;
311 case DRM_FORMAT_BGRA5551:
312 *format = WIN_COLOR_DEPTH_AR5G5B5;
315 case DRM_FORMAT_XRGB1555:
316 *format = WIN_COLOR_DEPTH_B5G5R5X1;
319 case DRM_FORMAT_RGBX5551:
320 *format = WIN_COLOR_DEPTH_X1B5G5R5;
323 case DRM_FORMAT_XBGR1555:
324 *format = WIN_COLOR_DEPTH_R5G5B5X1;
327 case DRM_FORMAT_BGRX5551:
328 *format = WIN_COLOR_DEPTH_X1R5G5B5;
331 case DRM_FORMAT_BGR565:
332 *format = WIN_COLOR_DEPTH_R5G6B5;
335 case DRM_FORMAT_BGRA8888:
336 *format = WIN_COLOR_DEPTH_A8R8G8B8;
339 case DRM_FORMAT_RGBA8888:
340 *format = WIN_COLOR_DEPTH_A8B8G8R8;
343 case DRM_FORMAT_XRGB8888:
344 *format = WIN_COLOR_DEPTH_B8G8R8X8;
347 case DRM_FORMAT_XBGR8888:
348 *format = WIN_COLOR_DEPTH_R8G8B8X8;
351 case DRM_FORMAT_UYVY:
352 *format = WIN_COLOR_DEPTH_YCbCr422;
355 case DRM_FORMAT_YUYV:
359 *format = WIN_COLOR_DEPTH_YCbCr422;
360 *swap = BYTE_SWAP_SWAP2;
363 case DRM_FORMAT_YUV420:
364 *format = WIN_COLOR_DEPTH_YCbCr420P;
367 case DRM_FORMAT_YUV422:
368 *format = WIN_COLOR_DEPTH_YCbCr422P;
378 bool tegra_plane_format_is_yuv(unsigned int format, bool *planar)
381 case WIN_COLOR_DEPTH_YCbCr422:
382 case WIN_COLOR_DEPTH_YUV422:
388 case WIN_COLOR_DEPTH_YCbCr420P:
389 case WIN_COLOR_DEPTH_YUV420P:
390 case WIN_COLOR_DEPTH_YCbCr422P:
391 case WIN_COLOR_DEPTH_YUV422P:
392 case WIN_COLOR_DEPTH_YCbCr422R:
393 case WIN_COLOR_DEPTH_YUV422R:
394 case WIN_COLOR_DEPTH_YCbCr422RA:
395 case WIN_COLOR_DEPTH_YUV422RA:
408 static bool __drm_format_has_alpha(u32 format)
411 case DRM_FORMAT_ARGB1555:
412 case DRM_FORMAT_RGBA5551:
413 case DRM_FORMAT_ABGR8888:
414 case DRM_FORMAT_ARGB8888:
421 static int tegra_plane_format_get_alpha(unsigned int opaque,
424 if (tegra_plane_format_is_yuv(opaque, NULL)) {
430 case WIN_COLOR_DEPTH_B5G5R5X1:
431 *alpha = WIN_COLOR_DEPTH_B5G5R5A1;
434 case WIN_COLOR_DEPTH_X1B5G5R5:
435 *alpha = WIN_COLOR_DEPTH_A1B5G5R5;
438 case WIN_COLOR_DEPTH_R8G8B8X8:
439 *alpha = WIN_COLOR_DEPTH_R8G8B8A8;
442 case WIN_COLOR_DEPTH_B8G8R8X8:
443 *alpha = WIN_COLOR_DEPTH_B8G8R8A8;
446 case WIN_COLOR_DEPTH_B5G6R5:
455 * This is applicable to Tegra20 and Tegra30 only where the opaque formats can
456 * be emulated using the alpha formats and alpha blending disabled.
458 static int tegra_plane_setup_opacity(struct tegra_plane *tegra,
459 struct tegra_plane_state *state)
464 switch (state->format) {
465 case WIN_COLOR_DEPTH_B5G5R5A1:
466 case WIN_COLOR_DEPTH_A1B5G5R5:
467 case WIN_COLOR_DEPTH_R8G8B8A8:
468 case WIN_COLOR_DEPTH_B8G8R8A8:
469 state->opaque = false;
473 err = tegra_plane_format_get_alpha(state->format, &format);
477 state->format = format;
478 state->opaque = true;
485 static int tegra_plane_check_transparency(struct tegra_plane *tegra,
486 struct tegra_plane_state *state)
488 struct drm_plane_state *old, *plane_state;
489 struct drm_plane *plane;
491 old = drm_atomic_get_old_plane_state(state->base.state, &tegra->base);
493 /* check if zpos / transparency changed */
494 if (old->normalized_zpos == state->base.normalized_zpos &&
495 to_tegra_plane_state(old)->opaque == state->opaque)
498 /* include all sibling planes into this commit */
499 drm_for_each_plane(plane, tegra->base.dev) {
500 struct tegra_plane *p = to_tegra_plane(plane);
502 /* skip this plane and planes on different CRTCs */
503 if (p == tegra || p->dc != tegra->dc)
506 plane_state = drm_atomic_get_plane_state(state->base.state,
508 if (IS_ERR(plane_state))
509 return PTR_ERR(plane_state);
515 static unsigned int tegra_plane_get_overlap_index(struct tegra_plane *plane,
516 struct tegra_plane *other)
518 unsigned int index = 0, i;
520 WARN_ON(plane == other);
522 for (i = 0; i < 3; i++) {
523 if (i == plane->index)
526 if (i == other->index)
535 static void tegra_plane_update_transparency(struct tegra_plane *tegra,
536 struct tegra_plane_state *state)
538 struct drm_plane_state *new;
539 struct drm_plane *plane;
542 for_each_new_plane_in_state(state->base.state, plane, new, i) {
543 struct tegra_plane *p = to_tegra_plane(plane);
546 /* skip this plane and planes on different CRTCs */
547 if (p == tegra || p->dc != tegra->dc)
550 index = tegra_plane_get_overlap_index(tegra, p);
552 if (new->fb && __drm_format_has_alpha(new->fb->format->format))
553 state->blending[index].alpha = true;
555 state->blending[index].alpha = false;
557 if (new->normalized_zpos > state->base.normalized_zpos)
558 state->blending[index].top = true;
560 state->blending[index].top = false;
563 * Missing framebuffer means that plane is disabled, in this
564 * case mark B / C window as top to be able to differentiate
565 * windows indices order in regards to zPos for the middle
566 * window X / Y registers programming.
569 state->blending[index].top = (index == 1);
573 static int tegra_plane_setup_transparency(struct tegra_plane *tegra,
574 struct tegra_plane_state *state)
576 struct tegra_plane_state *tegra_state;
577 struct drm_plane_state *new;
578 struct drm_plane *plane;
582 * If planes zpos / transparency changed, sibling planes blending
583 * state may require adjustment and in this case they will be included
584 * into this atom commit, otherwise blending state is unchanged.
586 err = tegra_plane_check_transparency(tegra, state);
591 * All planes are now in the atomic state, walk them up and update
592 * transparency state for each plane.
594 drm_for_each_plane(plane, tegra->base.dev) {
595 struct tegra_plane *p = to_tegra_plane(plane);
597 /* skip planes on different CRTCs */
598 if (p->dc != tegra->dc)
601 new = drm_atomic_get_new_plane_state(state->base.state, plane);
602 tegra_state = to_tegra_plane_state(new);
605 * There is no need to update blending state for the disabled
609 tegra_plane_update_transparency(p, tegra_state);
615 int tegra_plane_setup_legacy_state(struct tegra_plane *tegra,
616 struct tegra_plane_state *state)
620 err = tegra_plane_setup_opacity(tegra, state);
624 err = tegra_plane_setup_transparency(tegra, state);