1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 NVIDIA Corporation
7 #include <linux/delay.h>
8 #include <linux/interrupt.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/pinctrl/pinctrl.h>
14 #include <linux/pinctrl/pinmux.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/reset.h>
19 #include <linux/workqueue.h>
21 #include <drm/drm_dp_helper.h>
22 #include <drm/drm_panel.h>
29 static DEFINE_MUTEX(dpaux_lock);
30 static LIST_HEAD(dpaux_list);
32 struct tegra_dpaux_soc {
39 struct drm_dp_aux aux;
42 const struct tegra_dpaux_soc *soc;
47 struct tegra_output *output;
49 struct reset_control *rst;
50 struct clk *clk_parent;
53 struct regulator *vdd;
55 struct completion complete;
56 struct work_struct work;
57 struct list_head list;
59 #ifdef CONFIG_GENERIC_PINCONF
60 struct pinctrl_dev *pinctrl;
61 struct pinctrl_desc desc;
65 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
67 return container_of(aux, struct tegra_dpaux, aux);
70 static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
72 return container_of(work, struct tegra_dpaux, work);
75 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
78 u32 value = readl(dpaux->regs + (offset << 2));
80 trace_dpaux_readl(dpaux->dev, offset, value);
85 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
86 u32 value, unsigned int offset)
88 trace_dpaux_writel(dpaux->dev, offset, value);
89 writel(value, dpaux->regs + (offset << 2));
92 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
97 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
98 size_t num = min_t(size_t, size - i * 4, 4);
101 for (j = 0; j < num; j++)
102 value |= buffer[i * 4 + j] << (j * 8);
104 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
108 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
113 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
114 size_t num = min_t(size_t, size - i * 4, 4);
117 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
119 for (j = 0; j < num; j++)
120 buffer[i * 4 + j] = value >> (j * 8);
124 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
125 struct drm_dp_aux_msg *msg)
127 unsigned long timeout = msecs_to_jiffies(250);
128 struct tegra_dpaux *dpaux = to_dpaux(aux);
129 unsigned long status;
134 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
139 * Allow zero-sized messages only for I2C, in which case they specify
140 * address-only transactions.
143 switch (msg->request & ~DP_AUX_I2C_MOT) {
144 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
145 case DP_AUX_I2C_WRITE:
146 case DP_AUX_I2C_READ:
147 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
154 /* For non-zero-sized messages, set the CMDLEN field. */
155 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
158 switch (msg->request & ~DP_AUX_I2C_MOT) {
159 case DP_AUX_I2C_WRITE:
160 if (msg->request & DP_AUX_I2C_MOT)
161 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
163 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
167 case DP_AUX_I2C_READ:
168 if (msg->request & DP_AUX_I2C_MOT)
169 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
171 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
175 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
176 if (msg->request & DP_AUX_I2C_MOT)
177 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
179 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
183 case DP_AUX_NATIVE_WRITE:
184 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
187 case DP_AUX_NATIVE_READ:
188 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
195 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
196 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
198 if ((msg->request & DP_AUX_I2C_READ) == 0) {
199 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
203 /* start transaction */
204 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
205 value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
206 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
208 status = wait_for_completion_timeout(&dpaux->complete, timeout);
212 /* read status and clear errors */
213 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
214 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
216 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
219 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
220 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
221 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
224 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
226 reply = DP_AUX_NATIVE_REPLY_ACK;
230 reply = DP_AUX_NATIVE_REPLY_NACK;
234 reply = DP_AUX_NATIVE_REPLY_DEFER;
238 reply = DP_AUX_I2C_REPLY_NACK;
242 reply = DP_AUX_I2C_REPLY_DEFER;
246 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
247 if (msg->request & DP_AUX_I2C_READ) {
248 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
251 * There might be a smarter way to do this, but since
252 * the DP helpers will already retry transactions for
253 * an -EBUSY return value, simply reuse that instead.
255 if (count != msg->size) {
260 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
271 static void tegra_dpaux_hotplug(struct work_struct *work)
273 struct tegra_dpaux *dpaux = work_to_dpaux(work);
276 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
279 static irqreturn_t tegra_dpaux_irq(int irq, void *data)
281 struct tegra_dpaux *dpaux = data;
282 irqreturn_t ret = IRQ_HANDLED;
285 /* clear interrupts */
286 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
287 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
289 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
290 schedule_work(&dpaux->work);
292 if (value & DPAUX_INTR_IRQ_EVENT) {
293 /* TODO: handle this */
296 if (value & DPAUX_INTR_AUX_DONE)
297 complete(&dpaux->complete);
302 enum tegra_dpaux_functions {
303 DPAUX_PADCTL_FUNC_AUX,
304 DPAUX_PADCTL_FUNC_I2C,
305 DPAUX_PADCTL_FUNC_OFF,
308 static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
310 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
312 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
314 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
317 static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
319 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
321 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
323 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
326 static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
331 case DPAUX_PADCTL_FUNC_AUX:
332 value = DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
333 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
334 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
335 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
336 DPAUX_HYBRID_PADCTL_MODE_AUX;
339 case DPAUX_PADCTL_FUNC_I2C:
340 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
341 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
342 DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
343 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
344 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
345 DPAUX_HYBRID_PADCTL_MODE_I2C;
348 case DPAUX_PADCTL_FUNC_OFF:
349 tegra_dpaux_pad_power_down(dpaux);
356 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
357 tegra_dpaux_pad_power_up(dpaux);
362 #ifdef CONFIG_GENERIC_PINCONF
363 static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
364 PINCTRL_PIN(0, "DP_AUX_CHx_P"),
365 PINCTRL_PIN(1, "DP_AUX_CHx_N"),
368 static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
370 static const char * const tegra_dpaux_groups[] = {
374 static const char * const tegra_dpaux_functions[] = {
380 static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
382 return ARRAY_SIZE(tegra_dpaux_groups);
385 static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
388 return tegra_dpaux_groups[group];
391 static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
392 unsigned group, const unsigned **pins,
395 *pins = tegra_dpaux_pin_numbers;
396 *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
401 static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
402 .get_groups_count = tegra_dpaux_get_groups_count,
403 .get_group_name = tegra_dpaux_get_group_name,
404 .get_group_pins = tegra_dpaux_get_group_pins,
405 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
406 .dt_free_map = pinconf_generic_dt_free_map,
409 static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
411 return ARRAY_SIZE(tegra_dpaux_functions);
414 static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
415 unsigned int function)
417 return tegra_dpaux_functions[function];
420 static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
421 unsigned int function,
422 const char * const **groups,
423 unsigned * const num_groups)
425 *num_groups = ARRAY_SIZE(tegra_dpaux_groups);
426 *groups = tegra_dpaux_groups;
431 static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
432 unsigned int function, unsigned int group)
434 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
436 return tegra_dpaux_pad_config(dpaux, function);
439 static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
440 .get_functions_count = tegra_dpaux_get_functions_count,
441 .get_function_name = tegra_dpaux_get_function_name,
442 .get_function_groups = tegra_dpaux_get_function_groups,
443 .set_mux = tegra_dpaux_set_mux,
447 static int tegra_dpaux_probe(struct platform_device *pdev)
449 struct tegra_dpaux *dpaux;
450 struct resource *regs;
454 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
458 dpaux->soc = of_device_get_match_data(&pdev->dev);
459 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
460 init_completion(&dpaux->complete);
461 INIT_LIST_HEAD(&dpaux->list);
462 dpaux->dev = &pdev->dev;
464 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
465 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
466 if (IS_ERR(dpaux->regs))
467 return PTR_ERR(dpaux->regs);
469 dpaux->irq = platform_get_irq(pdev, 0);
470 if (dpaux->irq < 0) {
471 dev_err(&pdev->dev, "failed to get IRQ\n");
475 if (!pdev->dev.pm_domain) {
476 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
477 if (IS_ERR(dpaux->rst)) {
479 "failed to get reset control: %ld\n",
480 PTR_ERR(dpaux->rst));
481 return PTR_ERR(dpaux->rst);
485 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
486 if (IS_ERR(dpaux->clk)) {
487 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
488 PTR_ERR(dpaux->clk));
489 return PTR_ERR(dpaux->clk);
492 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
493 if (IS_ERR(dpaux->clk_parent)) {
494 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
495 PTR_ERR(dpaux->clk_parent));
496 return PTR_ERR(dpaux->clk_parent);
499 err = clk_set_rate(dpaux->clk_parent, 270000000);
501 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
506 dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
507 if (IS_ERR(dpaux->vdd)) {
508 if (PTR_ERR(dpaux->vdd) != -ENODEV) {
509 if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER)
511 "failed to get VDD supply: %ld\n",
512 PTR_ERR(dpaux->vdd));
514 return PTR_ERR(dpaux->vdd);
520 platform_set_drvdata(pdev, dpaux);
521 pm_runtime_enable(&pdev->dev);
522 pm_runtime_get_sync(&pdev->dev);
524 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
525 dev_name(dpaux->dev), dpaux);
527 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
532 disable_irq(dpaux->irq);
534 dpaux->aux.transfer = tegra_dpaux_transfer;
535 dpaux->aux.dev = &pdev->dev;
537 drm_dp_aux_init(&dpaux->aux);
540 * Assume that by default the DPAUX/I2C pads will be used for HDMI,
541 * so power them up and configure them in I2C mode.
543 * The DPAUX code paths reconfigure the pads in AUX mode, but there
544 * is no possibility to perform the I2C mode configuration in the
547 err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
551 #ifdef CONFIG_GENERIC_PINCONF
552 dpaux->desc.name = dev_name(&pdev->dev);
553 dpaux->desc.pins = tegra_dpaux_pins;
554 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
555 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
556 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
557 dpaux->desc.owner = THIS_MODULE;
559 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
560 if (IS_ERR(dpaux->pinctrl)) {
561 dev_err(&pdev->dev, "failed to register pincontrol\n");
562 return PTR_ERR(dpaux->pinctrl);
565 /* enable and clear all interrupts */
566 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
567 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
568 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
569 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
571 mutex_lock(&dpaux_lock);
572 list_add_tail(&dpaux->list, &dpaux_list);
573 mutex_unlock(&dpaux_lock);
578 static int tegra_dpaux_remove(struct platform_device *pdev)
580 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
582 cancel_work_sync(&dpaux->work);
584 /* make sure pads are powered down when not in use */
585 tegra_dpaux_pad_power_down(dpaux);
587 pm_runtime_put_sync(&pdev->dev);
588 pm_runtime_disable(&pdev->dev);
590 mutex_lock(&dpaux_lock);
591 list_del(&dpaux->list);
592 mutex_unlock(&dpaux_lock);
598 static int tegra_dpaux_suspend(struct device *dev)
600 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
604 err = reset_control_assert(dpaux->rst);
606 dev_err(dev, "failed to assert reset: %d\n", err);
611 usleep_range(1000, 2000);
613 clk_disable_unprepare(dpaux->clk_parent);
614 clk_disable_unprepare(dpaux->clk);
619 static int tegra_dpaux_resume(struct device *dev)
621 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
624 err = clk_prepare_enable(dpaux->clk);
626 dev_err(dev, "failed to enable clock: %d\n", err);
630 err = clk_prepare_enable(dpaux->clk_parent);
632 dev_err(dev, "failed to enable parent clock: %d\n", err);
636 usleep_range(1000, 2000);
639 err = reset_control_deassert(dpaux->rst);
641 dev_err(dev, "failed to deassert reset: %d\n", err);
645 usleep_range(1000, 2000);
651 clk_disable_unprepare(dpaux->clk_parent);
653 clk_disable_unprepare(dpaux->clk);
658 static const struct dev_pm_ops tegra_dpaux_pm_ops = {
659 SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
662 static const struct tegra_dpaux_soc tegra124_dpaux_soc = {
668 static const struct tegra_dpaux_soc tegra210_dpaux_soc = {
674 static const struct tegra_dpaux_soc tegra194_dpaux_soc = {
680 static const struct of_device_id tegra_dpaux_of_match[] = {
681 { .compatible = "nvidia,tegra194-dpaux", .data = &tegra194_dpaux_soc },
682 { .compatible = "nvidia,tegra186-dpaux", .data = &tegra210_dpaux_soc },
683 { .compatible = "nvidia,tegra210-dpaux", .data = &tegra210_dpaux_soc },
684 { .compatible = "nvidia,tegra124-dpaux", .data = &tegra124_dpaux_soc },
687 MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
689 struct platform_driver tegra_dpaux_driver = {
691 .name = "tegra-dpaux",
692 .of_match_table = tegra_dpaux_of_match,
693 .pm = &tegra_dpaux_pm_ops,
695 .probe = tegra_dpaux_probe,
696 .remove = tegra_dpaux_remove,
699 struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
701 struct tegra_dpaux *dpaux;
703 mutex_lock(&dpaux_lock);
705 list_for_each_entry(dpaux, &dpaux_list, list)
706 if (np == dpaux->dev->of_node) {
707 mutex_unlock(&dpaux_lock);
711 mutex_unlock(&dpaux_lock);
716 int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
718 struct tegra_dpaux *dpaux = to_dpaux(aux);
719 unsigned long timeout;
722 err = drm_dp_aux_register(aux);
726 output->connector.polled = DRM_CONNECTOR_POLL_HPD;
727 dpaux->output = output;
730 enum drm_connector_status status;
733 err = regulator_enable(dpaux->vdd);
738 timeout = jiffies + msecs_to_jiffies(250);
740 while (time_before(jiffies, timeout)) {
741 status = drm_dp_aux_detect(aux);
743 if (status == connector_status_connected)
746 usleep_range(1000, 2000);
749 if (status != connector_status_connected)
753 enable_irq(dpaux->irq);
757 int drm_dp_aux_detach(struct drm_dp_aux *aux)
759 struct tegra_dpaux *dpaux = to_dpaux(aux);
760 unsigned long timeout;
763 drm_dp_aux_unregister(aux);
764 disable_irq(dpaux->irq);
766 if (dpaux->output->panel) {
767 enum drm_connector_status status;
770 err = regulator_disable(dpaux->vdd);
775 timeout = jiffies + msecs_to_jiffies(250);
777 while (time_before(jiffies, timeout)) {
778 status = drm_dp_aux_detect(aux);
780 if (status == connector_status_disconnected)
783 usleep_range(1000, 2000);
786 if (status != connector_status_disconnected)
789 dpaux->output = NULL;
795 enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
797 struct tegra_dpaux *dpaux = to_dpaux(aux);
800 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
802 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
803 return connector_status_connected;
805 return connector_status_disconnected;
808 int drm_dp_aux_enable(struct drm_dp_aux *aux)
810 struct tegra_dpaux *dpaux = to_dpaux(aux);
812 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
815 int drm_dp_aux_disable(struct drm_dp_aux *aux)
817 struct tegra_dpaux *dpaux = to_dpaux(aux);
819 tegra_dpaux_pad_power_down(dpaux);