1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 NVIDIA Corporation
7 #include <linux/delay.h>
8 #include <linux/gpio.h>
9 #include <linux/interrupt.h>
11 #include <linux/of_gpio.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/pinctrl/pinctrl.h>
14 #include <linux/pinctrl/pinmux.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/platform_device.h>
17 #include <linux/reset.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/workqueue.h>
21 #include <drm/drm_dp_helper.h>
22 #include <drm/drm_panel.h>
28 static DEFINE_MUTEX(dpaux_lock);
29 static LIST_HEAD(dpaux_list);
32 struct drm_dp_aux aux;
38 struct tegra_output *output;
40 struct reset_control *rst;
41 struct clk *clk_parent;
44 struct regulator *vdd;
46 struct completion complete;
47 struct work_struct work;
48 struct list_head list;
50 #ifdef CONFIG_GENERIC_PINCONF
51 struct pinctrl_dev *pinctrl;
52 struct pinctrl_desc desc;
56 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
58 return container_of(aux, struct tegra_dpaux, aux);
61 static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
63 return container_of(work, struct tegra_dpaux, work);
66 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
69 u32 value = readl(dpaux->regs + (offset << 2));
71 trace_dpaux_readl(dpaux->dev, offset, value);
76 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
77 u32 value, unsigned int offset)
79 trace_dpaux_writel(dpaux->dev, offset, value);
80 writel(value, dpaux->regs + (offset << 2));
83 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
88 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
89 size_t num = min_t(size_t, size - i * 4, 4);
92 for (j = 0; j < num; j++)
93 value |= buffer[i * 4 + j] << (j * 8);
95 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
99 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
104 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
105 size_t num = min_t(size_t, size - i * 4, 4);
108 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
110 for (j = 0; j < num; j++)
111 buffer[i * 4 + j] = value >> (j * 8);
115 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
116 struct drm_dp_aux_msg *msg)
118 unsigned long timeout = msecs_to_jiffies(250);
119 struct tegra_dpaux *dpaux = to_dpaux(aux);
120 unsigned long status;
124 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
129 * Allow zero-sized messages only for I2C, in which case they specify
130 * address-only transactions.
133 switch (msg->request & ~DP_AUX_I2C_MOT) {
134 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
135 case DP_AUX_I2C_WRITE:
136 case DP_AUX_I2C_READ:
137 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
144 /* For non-zero-sized messages, set the CMDLEN field. */
145 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
148 switch (msg->request & ~DP_AUX_I2C_MOT) {
149 case DP_AUX_I2C_WRITE:
150 if (msg->request & DP_AUX_I2C_MOT)
151 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
153 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
157 case DP_AUX_I2C_READ:
158 if (msg->request & DP_AUX_I2C_MOT)
159 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
161 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
165 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
166 if (msg->request & DP_AUX_I2C_MOT)
167 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
169 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
173 case DP_AUX_NATIVE_WRITE:
174 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
177 case DP_AUX_NATIVE_READ:
178 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
185 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
186 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
188 if ((msg->request & DP_AUX_I2C_READ) == 0) {
189 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
193 /* start transaction */
194 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
195 value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
196 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
198 status = wait_for_completion_timeout(&dpaux->complete, timeout);
202 /* read status and clear errors */
203 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
204 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
206 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
209 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
210 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
211 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
214 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
216 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
220 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
224 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
228 msg->reply = DP_AUX_I2C_REPLY_NACK;
232 msg->reply = DP_AUX_I2C_REPLY_DEFER;
236 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
237 if (msg->request & DP_AUX_I2C_READ) {
238 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
240 if (WARN_ON(count != msg->size))
241 count = min_t(size_t, count, msg->size);
243 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
251 static void tegra_dpaux_hotplug(struct work_struct *work)
253 struct tegra_dpaux *dpaux = work_to_dpaux(work);
256 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
259 static irqreturn_t tegra_dpaux_irq(int irq, void *data)
261 struct tegra_dpaux *dpaux = data;
262 irqreturn_t ret = IRQ_HANDLED;
265 /* clear interrupts */
266 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
267 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
269 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
270 schedule_work(&dpaux->work);
272 if (value & DPAUX_INTR_IRQ_EVENT) {
273 /* TODO: handle this */
276 if (value & DPAUX_INTR_AUX_DONE)
277 complete(&dpaux->complete);
282 enum tegra_dpaux_functions {
283 DPAUX_PADCTL_FUNC_AUX,
284 DPAUX_PADCTL_FUNC_I2C,
285 DPAUX_PADCTL_FUNC_OFF,
288 static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
290 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
292 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
294 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
297 static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
299 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
301 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
303 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
306 static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
311 case DPAUX_PADCTL_FUNC_AUX:
312 value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
313 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
314 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
315 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
316 DPAUX_HYBRID_PADCTL_MODE_AUX;
319 case DPAUX_PADCTL_FUNC_I2C:
320 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
321 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
322 DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
323 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
324 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
325 DPAUX_HYBRID_PADCTL_MODE_I2C;
328 case DPAUX_PADCTL_FUNC_OFF:
329 tegra_dpaux_pad_power_down(dpaux);
336 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
337 tegra_dpaux_pad_power_up(dpaux);
342 #ifdef CONFIG_GENERIC_PINCONF
343 static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
344 PINCTRL_PIN(0, "DP_AUX_CHx_P"),
345 PINCTRL_PIN(1, "DP_AUX_CHx_N"),
348 static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
350 static const char * const tegra_dpaux_groups[] = {
354 static const char * const tegra_dpaux_functions[] = {
360 static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
362 return ARRAY_SIZE(tegra_dpaux_groups);
365 static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
368 return tegra_dpaux_groups[group];
371 static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
372 unsigned group, const unsigned **pins,
375 *pins = tegra_dpaux_pin_numbers;
376 *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
381 static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
382 .get_groups_count = tegra_dpaux_get_groups_count,
383 .get_group_name = tegra_dpaux_get_group_name,
384 .get_group_pins = tegra_dpaux_get_group_pins,
385 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
386 .dt_free_map = pinconf_generic_dt_free_map,
389 static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
391 return ARRAY_SIZE(tegra_dpaux_functions);
394 static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
395 unsigned int function)
397 return tegra_dpaux_functions[function];
400 static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
401 unsigned int function,
402 const char * const **groups,
403 unsigned * const num_groups)
405 *num_groups = ARRAY_SIZE(tegra_dpaux_groups);
406 *groups = tegra_dpaux_groups;
411 static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
412 unsigned int function, unsigned int group)
414 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
416 return tegra_dpaux_pad_config(dpaux, function);
419 static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
420 .get_functions_count = tegra_dpaux_get_functions_count,
421 .get_function_name = tegra_dpaux_get_function_name,
422 .get_function_groups = tegra_dpaux_get_function_groups,
423 .set_mux = tegra_dpaux_set_mux,
427 static int tegra_dpaux_probe(struct platform_device *pdev)
429 struct tegra_dpaux *dpaux;
430 struct resource *regs;
434 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
438 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
439 init_completion(&dpaux->complete);
440 INIT_LIST_HEAD(&dpaux->list);
441 dpaux->dev = &pdev->dev;
443 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
444 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
445 if (IS_ERR(dpaux->regs))
446 return PTR_ERR(dpaux->regs);
448 dpaux->irq = platform_get_irq(pdev, 0);
449 if (dpaux->irq < 0) {
450 dev_err(&pdev->dev, "failed to get IRQ\n");
454 if (!pdev->dev.pm_domain) {
455 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
456 if (IS_ERR(dpaux->rst)) {
458 "failed to get reset control: %ld\n",
459 PTR_ERR(dpaux->rst));
460 return PTR_ERR(dpaux->rst);
464 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
465 if (IS_ERR(dpaux->clk)) {
466 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
467 PTR_ERR(dpaux->clk));
468 return PTR_ERR(dpaux->clk);
471 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
472 if (IS_ERR(dpaux->clk_parent)) {
473 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
474 PTR_ERR(dpaux->clk_parent));
475 return PTR_ERR(dpaux->clk_parent);
478 err = clk_set_rate(dpaux->clk_parent, 270000000);
480 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
485 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
486 if (IS_ERR(dpaux->vdd)) {
487 dev_err(&pdev->dev, "failed to get VDD supply: %ld\n",
488 PTR_ERR(dpaux->vdd));
489 return PTR_ERR(dpaux->vdd);
492 platform_set_drvdata(pdev, dpaux);
493 pm_runtime_enable(&pdev->dev);
494 pm_runtime_get_sync(&pdev->dev);
496 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
497 dev_name(dpaux->dev), dpaux);
499 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
504 disable_irq(dpaux->irq);
506 dpaux->aux.transfer = tegra_dpaux_transfer;
507 dpaux->aux.dev = &pdev->dev;
509 err = drm_dp_aux_register(&dpaux->aux);
514 * Assume that by default the DPAUX/I2C pads will be used for HDMI,
515 * so power them up and configure them in I2C mode.
517 * The DPAUX code paths reconfigure the pads in AUX mode, but there
518 * is no possibility to perform the I2C mode configuration in the
521 err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
525 #ifdef CONFIG_GENERIC_PINCONF
526 dpaux->desc.name = dev_name(&pdev->dev);
527 dpaux->desc.pins = tegra_dpaux_pins;
528 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
529 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
530 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
531 dpaux->desc.owner = THIS_MODULE;
533 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
534 if (IS_ERR(dpaux->pinctrl)) {
535 dev_err(&pdev->dev, "failed to register pincontrol\n");
536 return PTR_ERR(dpaux->pinctrl);
539 /* enable and clear all interrupts */
540 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
541 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
542 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
543 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
545 mutex_lock(&dpaux_lock);
546 list_add_tail(&dpaux->list, &dpaux_list);
547 mutex_unlock(&dpaux_lock);
552 static int tegra_dpaux_remove(struct platform_device *pdev)
554 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
556 cancel_work_sync(&dpaux->work);
558 /* make sure pads are powered down when not in use */
559 tegra_dpaux_pad_power_down(dpaux);
561 pm_runtime_put(&pdev->dev);
562 pm_runtime_disable(&pdev->dev);
564 drm_dp_aux_unregister(&dpaux->aux);
566 mutex_lock(&dpaux_lock);
567 list_del(&dpaux->list);
568 mutex_unlock(&dpaux_lock);
574 static int tegra_dpaux_suspend(struct device *dev)
576 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
580 err = reset_control_assert(dpaux->rst);
582 dev_err(dev, "failed to assert reset: %d\n", err);
587 usleep_range(1000, 2000);
589 clk_disable_unprepare(dpaux->clk_parent);
590 clk_disable_unprepare(dpaux->clk);
595 static int tegra_dpaux_resume(struct device *dev)
597 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
600 err = clk_prepare_enable(dpaux->clk);
602 dev_err(dev, "failed to enable clock: %d\n", err);
606 err = clk_prepare_enable(dpaux->clk_parent);
608 dev_err(dev, "failed to enable parent clock: %d\n", err);
612 usleep_range(1000, 2000);
615 err = reset_control_deassert(dpaux->rst);
617 dev_err(dev, "failed to deassert reset: %d\n", err);
621 usleep_range(1000, 2000);
627 clk_disable_unprepare(dpaux->clk_parent);
629 clk_disable_unprepare(dpaux->clk);
634 static const struct dev_pm_ops tegra_dpaux_pm_ops = {
635 SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
638 static const struct of_device_id tegra_dpaux_of_match[] = {
639 { .compatible = "nvidia,tegra194-dpaux", },
640 { .compatible = "nvidia,tegra186-dpaux", },
641 { .compatible = "nvidia,tegra210-dpaux", },
642 { .compatible = "nvidia,tegra124-dpaux", },
645 MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
647 struct platform_driver tegra_dpaux_driver = {
649 .name = "tegra-dpaux",
650 .of_match_table = tegra_dpaux_of_match,
651 .pm = &tegra_dpaux_pm_ops,
653 .probe = tegra_dpaux_probe,
654 .remove = tegra_dpaux_remove,
657 struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
659 struct tegra_dpaux *dpaux;
661 mutex_lock(&dpaux_lock);
663 list_for_each_entry(dpaux, &dpaux_list, list)
664 if (np == dpaux->dev->of_node) {
665 mutex_unlock(&dpaux_lock);
669 mutex_unlock(&dpaux_lock);
674 int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
676 struct tegra_dpaux *dpaux = to_dpaux(aux);
677 unsigned long timeout;
680 output->connector.polled = DRM_CONNECTOR_POLL_HPD;
681 dpaux->output = output;
683 err = regulator_enable(dpaux->vdd);
687 timeout = jiffies + msecs_to_jiffies(250);
689 while (time_before(jiffies, timeout)) {
690 enum drm_connector_status status;
692 status = drm_dp_aux_detect(aux);
693 if (status == connector_status_connected) {
694 enable_irq(dpaux->irq);
698 usleep_range(1000, 2000);
704 int drm_dp_aux_detach(struct drm_dp_aux *aux)
706 struct tegra_dpaux *dpaux = to_dpaux(aux);
707 unsigned long timeout;
710 disable_irq(dpaux->irq);
712 err = regulator_disable(dpaux->vdd);
716 timeout = jiffies + msecs_to_jiffies(250);
718 while (time_before(jiffies, timeout)) {
719 enum drm_connector_status status;
721 status = drm_dp_aux_detect(aux);
722 if (status == connector_status_disconnected) {
723 dpaux->output = NULL;
727 usleep_range(1000, 2000);
733 enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
735 struct tegra_dpaux *dpaux = to_dpaux(aux);
738 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
740 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
741 return connector_status_connected;
743 return connector_status_disconnected;
746 int drm_dp_aux_enable(struct drm_dp_aux *aux)
748 struct tegra_dpaux *dpaux = to_dpaux(aux);
750 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
753 int drm_dp_aux_disable(struct drm_dp_aux *aux)
755 struct tegra_dpaux *dpaux = to_dpaux(aux);
757 tegra_dpaux_pad_power_down(dpaux);
762 int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding)
766 err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
774 int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
777 u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
778 u8 status[DP_LINK_STATUS_SIZE], values[4];
782 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
786 if (tp == DP_TRAINING_PATTERN_DISABLE)
789 for (i = 0; i < link->num_lanes; i++)
790 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
791 DP_TRAIN_PRE_EMPH_LEVEL_0 |
792 DP_TRAIN_MAX_SWING_REACHED |
793 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
795 err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values,
800 usleep_range(500, 1000);
802 err = drm_dp_dpcd_read_link_status(aux, status);
807 case DP_TRAINING_PATTERN_1:
808 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
813 case DP_TRAINING_PATTERN_2:
814 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
820 dev_err(aux->dev, "unsupported training pattern %u\n", tp);
824 err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0);