drivers/gpu/drm/tegra/dc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Avionic Design GmbH
   4  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/iommu.h>
  10 #include <linux/of_device.h>
  11 #include <linux/pm_runtime.h>
  12 #include <linux/reset.h>
  13
  14 #include <soc/tegra/pmc.h>
  15
  16 #include "dc.h"
  17 #include "drm.h"
  18 #include "gem.h"
  19 #include "hub.h"
  20 #include "plane.h"
  21
  22 #include <drm/drm_atomic.h>
  23 #include <drm/drm_atomic_helper.h>
  24 #include <drm/drm_plane_helper.h>
  25
  26 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
  27 {
  28         stats->frames = 0;
  29         stats->vblank = 0;
  30         stats->underflow = 0;
  31         stats->overflow = 0;
  32 }
  33
  34 /* Reads the active copy of a register. */
  35 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
  36 {
  37         u32 value;
  38
  39         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
  40         value = tegra_dc_readl(dc, offset);
  41         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
  42
  43         return value;
  44 }
  45
  46 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
  47                                               unsigned int offset)
  48 {
  49         if (offset >= 0x500 && offset <= 0x638) {
  50                 offset = 0x000 + (offset - 0x500);
  51                 return plane->offset + offset;
  52         }
  53
  54         if (offset >= 0x700 && offset <= 0x719) {
  55                 offset = 0x180 + (offset - 0x700);
  56                 return plane->offset + offset;
  57         }
  58
  59         if (offset >= 0x800 && offset <= 0x839) {
  60                 offset = 0x1c0 + (offset - 0x800);
  61                 return plane->offset + offset;
  62         }
  63
  64         dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
  65
  66         return plane->offset + offset;
  67 }
  68
  69 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
  70                                     unsigned int offset)
  71 {
  72         return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
  73 }
  74
  75 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
  76                                       unsigned int offset)
  77 {
  78         tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
  79 }
  80
  81 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
  82 {
  83         struct device_node *np = dc->dev->of_node;
  84         struct of_phandle_iterator it;
  85         int err;
  86
  87         of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
  88                 if (it.node == dev->of_node)
  89                         return true;
  90
  91         return false;
  92 }
  93
  94 /*
  95  * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
  96  * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
  97  * Latching happens mmediately if the display controller is in STOP mode or
  98  * on the next frame boundary otherwise.
  99  *
 100  * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
 101  * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
 102  * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
 103  * into the ACTIVE copy, either immediately if the display controller is in
 104  * STOP mode, or at the next frame boundary otherwise.
 105  */
 106 void tegra_dc_commit(struct tegra_dc *dc)
 107 {
 108         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 109         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 110 }
 111
 112 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 113                                   unsigned int bpp)
 114 {
 115         fixed20_12 outf = dfixed_init(out);
 116         fixed20_12 inf = dfixed_init(in);
 117         u32 dda_inc;
 118         int max;
 119
 120         if (v)
 121                 max = 15;
 122         else {
 123                 switch (bpp) {
 124                 case 2:
 125                         max = 8;
 126                         break;
 127
 128                 default:
 129                         WARN_ON_ONCE(1);
 130                         /* fallthrough */
 131                 case 4:
 132                         max = 4;
 133                         break;
 134                 }
 135         }
 136
 137         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 138         inf.full -= dfixed_const(1);
 139
 140         dda_inc = dfixed_div(inf, outf);
 141         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 142
 143         return dda_inc;
 144 }
 145
 146 static inline u32 compute_initial_dda(unsigned int in)
 147 {
 148         fixed20_12 inf = dfixed_init(in);
 149         return dfixed_frac(inf);
 150 }
 151
 152 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
 153 {
 154         u32 background[3] = {
 155                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 156                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 157                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 158         };
 159         u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
 160                          BLEND_COLOR_KEY_NONE;
 161         u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
 162         struct tegra_plane_state *state;
 163         u32 blending[2];
 164         unsigned int i;
 165
 166         /* disable blending for non-overlapping case */
 167         tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
 168         tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
 169
 170         state = to_tegra_plane_state(plane->base.state);
 171
 172         if (state->opaque) {
 173                 /*
 174                  * Since custom fix-weight blending isn't utilized and weight
 175                  * of top window is set to max, we can enforce dependent
 176                  * blending which in this case results in transparent bottom
 177                  * window if top window is opaque and if top window enables
 178                  * alpha blending, then bottom window is getting alpha value
 179                  * of 1 minus the sum of alpha components of the overlapping
 180                  * plane.
 181                  */
 182                 background[0] |= BLEND_CONTROL_DEPENDENT;
 183                 background[1] |= BLEND_CONTROL_DEPENDENT;
 184
 185                 /*
 186                  * The region where three windows overlap is the intersection
 187                  * of the two regions where two windows overlap. It contributes
 188                  * to the area if all of the windows on top of it have an alpha
 189                  * component.
 190                  */
 191                 switch (state->base.normalized_zpos) {
 192                 case 0:
 193                         if (state->blending[0].alpha &&
 194                             state->blending[1].alpha)
 195                                 background[2] |= BLEND_CONTROL_DEPENDENT;
 196                         break;
 197
 198                 case 1:
 199                         background[2] |= BLEND_CONTROL_DEPENDENT;
 200                         break;
 201                 }
 202         } else {
 203                 /*
 204                  * Enable alpha blending if pixel format has an alpha
 205                  * component.
 206                  */
 207                 foreground |= BLEND_CONTROL_ALPHA;
 208
 209                 /*
 210                  * If any of the windows on top of this window is opaque, it
 211                  * will completely conceal this window within that area. If
 212                  * top window has an alpha component, it is blended over the
 213                  * bottom window.
 214                  */
 215                 for (i = 0; i < 2; i++) {
 216                         if (state->blending[i].alpha &&
 217                             state->blending[i].top)
 218                                 background[i] |= BLEND_CONTROL_DEPENDENT;
 219                 }
 220
 221                 switch (state->base.normalized_zpos) {
 222                 case 0:
 223                         if (state->blending[0].alpha &&
 224                             state->blending[1].alpha)
 225                                 background[2] |= BLEND_CONTROL_DEPENDENT;
 226                         break;
 227
 228                 case 1:
 229                         /*
 230                          * When both middle and topmost windows have an alpha,
 231                          * these windows a mixed together and then the result
 232                          * is blended over the bottom window.
 233                          */
 234                         if (state->blending[0].alpha &&
 235                             state->blending[0].top)
 236                                 background[2] |= BLEND_CONTROL_ALPHA;
 237
 238                         if (state->blending[1].alpha &&
 239                             state->blending[1].top)
 240                                 background[2] |= BLEND_CONTROL_ALPHA;
 241                         break;
 242                 }
 243         }
 244
 245         switch (state->base.normalized_zpos) {
 246         case 0:
 247                 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
 248                 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
 249                 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
 250                 break;
 251
 252         case 1:
 253                 /*
 254                  * If window B / C is topmost, then X / Y registers are
 255                  * matching the order of blending[...] state indices,
 256                  * otherwise a swap is required.
 257                  */
 258                 if (!state->blending[0].top && state->blending[1].top) {
 259                         blending[0] = foreground;
 260                         blending[1] = background[1];
 261                 } else {
 262                         blending[0] = background[0];
 263                         blending[1] = foreground;
 264                 }
 265
 266                 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
 267                 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
 268                 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
 269                 break;
 270
 271         case 2:
 272                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
 273                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
 274                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
 275                 break;
 276         }
 277 }
 278
 279 static void tegra_plane_setup_blending(struct tegra_plane *plane,
 280                                        const struct tegra_dc_window *window)
 281 {
 282         u32 value;
 283
 284         value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 285                 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 286                 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 287         tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
 288
 289         value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 290                 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 291                 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 292         tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
 293
 294         value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
 295         tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
 296 }
 297
 298 static bool
 299 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
 300                                      const struct tegra_dc_window *window)
 301 {
 302         struct tegra_dc *dc = plane->dc;
 303
 304         if (window->src.w == window->dst.w)
 305                 return false;
 306
 307         if (plane->index == 0 && dc->soc->has_win_a_without_filters)
 308                 return false;
 309
 310         return true;
 311 }
 312
 313 static bool
 314 tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
 315                                    const struct tegra_dc_window *window)
 316 {
 317         struct tegra_dc *dc = plane->dc;
 318
 319         if (window->src.h == window->dst.h)
 320                 return false;
 321
 322         if (plane->index == 0 && dc->soc->has_win_a_without_filters)
 323                 return false;
 324
 325         if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
 326                 return false;
 327
 328         return true;
 329 }
 330
 331 static void tegra_dc_setup_window(struct tegra_plane *plane,
 332                                   const struct tegra_dc_window *window)
 333 {
 334         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 335         struct tegra_dc *dc = plane->dc;
 336         bool yuv, planar;
 337         u32 value;
 338
 339         /*
 340          * For YUV planar modes, the number of bytes per pixel takes into
 341          * account only the luma component and therefore is 1.
 342          */
 343         yuv = tegra_plane_format_is_yuv(window->format, &planar);
 344         if (!yuv)
 345                 bpp = window->bits_per_pixel / 8;
 346         else
 347                 bpp = planar ? 1 : 2;
 348
 349         tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
 350         tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
 351
 352         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 353         tegra_plane_writel(plane, value, DC_WIN_POSITION);
 354
 355         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 356         tegra_plane_writel(plane, value, DC_WIN_SIZE);
 357
 358         h_offset = window->src.x * bpp;
 359         v_offset = window->src.y;
 360         h_size = window->src.w * bpp;
 361         v_size = window->src.h;
 362
 363         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 364         tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
 365
 366         /*
 367          * For DDA computations the number of bytes per pixel for YUV planar
 368          * modes needs to take into account all Y, U and V components.
 369          */
 370         if (yuv && planar)
 371                 bpp = 2;
 372
 373         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 374         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 375
 376         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 377         tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
 378
 379         h_dda = compute_initial_dda(window->src.x);
 380         v_dda = compute_initial_dda(window->src.y);
 381
 382         tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
 383         tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
 384
 385         tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
 386         tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
 387
 388         tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
 389
 390         if (yuv && planar) {
 391                 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
 392                 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
 393                 value = window->stride[1] << 16 | window->stride[0];
 394                 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
 395         } else {
 396                 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
 397         }
 398
 399         if (window->bottom_up)
 400                 v_offset += window->src.h - 1;
 401
 402         tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 403         tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 404
 405         if (dc->soc->supports_block_linear) {
 406                 unsigned long height = window->tiling.value;
 407
 408                 switch (window->tiling.mode) {
 409                 case TEGRA_BO_TILING_MODE_PITCH:
 410                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 411                         break;
 412
 413                 case TEGRA_BO_TILING_MODE_TILED:
 414                         value = DC_WINBUF_SURFACE_KIND_TILED;
 415                         break;
 416
 417                 case TEGRA_BO_TILING_MODE_BLOCK:
 418                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 419                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 420                         break;
 421                 }
 422
 423                 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
 424         } else {
 425                 switch (window->tiling.mode) {
 426                 case TEGRA_BO_TILING_MODE_PITCH:
 427                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 428                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 429                         break;
 430
 431                 case TEGRA_BO_TILING_MODE_TILED:
 432                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 433                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 434                         break;
 435
 436                 case TEGRA_BO_TILING_MODE_BLOCK:
 437                         /*
 438                          * No need to handle this here because ->atomic_check
 439                          * will already have filtered it out.
 440                          */
 441                         break;
 442                 }
 443
 444                 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
 445         }
 446
 447         value = WIN_ENABLE;
 448
 449         if (yuv) {
 450                 /* setup default colorspace conversion coefficients */
 451                 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
 452                 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
 453                 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
 454                 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
 455                 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
 456                 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
 457                 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
 458                 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
 459
 460                 value |= CSC_ENABLE;
 461         } else if (window->bits_per_pixel < 24) {
 462                 value |= COLOR_EXPAND;
 463         }
 464
 465         if (window->bottom_up)
 466                 value |= V_DIRECTION;
 467
 468         if (tegra_plane_use_horizontal_filtering(plane, window)) {
 469                 /*
 470                  * Enable horizontal 6-tap filter and set filtering
 471                  * coefficients to the default values defined in TRM.
 472                  */
 473                 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
 474                 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
 475                 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
 476                 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
 477                 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
 478                 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
 479                 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
 480                 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
 481                 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
 482                 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
 483                 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
 484                 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
 485                 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
 486                 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
 487                 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
 488                 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
 489
 490                 value |= H_FILTER;
 491         }
 492
 493         if (tegra_plane_use_vertical_filtering(plane, window)) {
 494                 unsigned int i, k;
 495
 496                 /*
 497                  * Enable vertical 2-tap filter and set filtering
 498                  * coefficients to the default values defined in TRM.
 499                  */
 500                 for (i = 0, k = 128; i < 16; i++, k -= 8)
 501                         tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
 502
 503                 value |= V_FILTER;
 504         }
 505
 506         tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
 507
 508         if (dc->soc->has_legacy_blending)
 509                 tegra_plane_setup_blending_legacy(plane);
 510         else
 511                 tegra_plane_setup_blending(plane, window);
 512 }
 513
 514 static const u32 tegra20_primary_formats[] = {
 515         DRM_FORMAT_ARGB4444,
 516         DRM_FORMAT_ARGB1555,
 517         DRM_FORMAT_RGB565,
 518         DRM_FORMAT_RGBA5551,
 519         DRM_FORMAT_ABGR8888,
 520         DRM_FORMAT_ARGB8888,
 521         /* non-native formats */
 522         DRM_FORMAT_XRGB1555,
 523         DRM_FORMAT_RGBX5551,
 524         DRM_FORMAT_XBGR8888,
 525         DRM_FORMAT_XRGB8888,
 526 };
 527
 528 static const u64 tegra20_modifiers[] = {
 529         DRM_FORMAT_MOD_LINEAR,
 530         DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
 531         DRM_FORMAT_MOD_INVALID
 532 };
 533
 534 static const u32 tegra114_primary_formats[] = {
 535         DRM_FORMAT_ARGB4444,
 536         DRM_FORMAT_ARGB1555,
 537         DRM_FORMAT_RGB565,
 538         DRM_FORMAT_RGBA5551,
 539         DRM_FORMAT_ABGR8888,
 540         DRM_FORMAT_ARGB8888,
 541         /* new on Tegra114 */
 542         DRM_FORMAT_ABGR4444,
 543         DRM_FORMAT_ABGR1555,
 544         DRM_FORMAT_BGRA5551,
 545         DRM_FORMAT_XRGB1555,
 546         DRM_FORMAT_RGBX5551,
 547         DRM_FORMAT_XBGR1555,
 548         DRM_FORMAT_BGRX5551,
 549         DRM_FORMAT_BGR565,
 550         DRM_FORMAT_BGRA8888,
 551         DRM_FORMAT_RGBA8888,
 552         DRM_FORMAT_XRGB8888,
 553         DRM_FORMAT_XBGR8888,
 554 };
 555
 556 static const u32 tegra124_primary_formats[] = {
 557         DRM_FORMAT_ARGB4444,
 558         DRM_FORMAT_ARGB1555,
 559         DRM_FORMAT_RGB565,
 560         DRM_FORMAT_RGBA5551,
 561         DRM_FORMAT_ABGR8888,
 562         DRM_FORMAT_ARGB8888,
 563         /* new on Tegra114 */
 564         DRM_FORMAT_ABGR4444,
 565         DRM_FORMAT_ABGR1555,
 566         DRM_FORMAT_BGRA5551,
 567         DRM_FORMAT_XRGB1555,
 568         DRM_FORMAT_RGBX5551,
 569         DRM_FORMAT_XBGR1555,
 570         DRM_FORMAT_BGRX5551,
 571         DRM_FORMAT_BGR565,
 572         DRM_FORMAT_BGRA8888,
 573         DRM_FORMAT_RGBA8888,
 574         DRM_FORMAT_XRGB8888,
 575         DRM_FORMAT_XBGR8888,
 576         /* new on Tegra124 */
 577         DRM_FORMAT_RGBX8888,
 578         DRM_FORMAT_BGRX8888,
 579 };
 580
 581 static const u64 tegra124_modifiers[] = {
 582         DRM_FORMAT_MOD_LINEAR,
 583         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
 584         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
 585         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
 586         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
 587         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
 588         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
 589         DRM_FORMAT_MOD_INVALID
 590 };
 591
 592 static int tegra_plane_atomic_check(struct drm_plane *plane,
 593                                     struct drm_plane_state *state)
 594 {
 595         struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
 596         unsigned int rotation = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_Y;
 597         struct tegra_bo_tiling *tiling = &plane_state->tiling;
 598         struct tegra_plane *tegra = to_tegra_plane(plane);
 599         struct tegra_dc *dc = to_tegra_dc(state->crtc);
 600         int err;
 601
 602         /* no need for further checks if the plane is being disabled */
 603         if (!state->crtc)
 604                 return 0;
 605
 606         err = tegra_plane_format(state->fb->format->format,
 607                                  &plane_state->format,
 608                                  &plane_state->swap);
 609         if (err < 0)
 610                 return err;
 611
 612         /*
 613          * Tegra20 and Tegra30 are special cases here because they support
 614          * only variants of specific formats with an alpha component, but not
 615          * the corresponding opaque formats. However, the opaque formats can
 616          * be emulated by disabling alpha blending for the plane.
 617          */
 618         if (dc->soc->has_legacy_blending) {
 619                 err = tegra_plane_setup_legacy_state(tegra, plane_state);
 620                 if (err < 0)
 621                         return err;
 622         }
 623
 624         err = tegra_fb_get_tiling(state->fb, tiling);
 625         if (err < 0)
 626                 return err;
 627
 628         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 629             !dc->soc->supports_block_linear) {
 630                 DRM_ERROR("hardware doesn't support block linear mode\n");
 631                 return -EINVAL;
 632         }
 633
 634         rotation = drm_rotation_simplify(state->rotation, rotation);
 635
 636         if (rotation & DRM_MODE_REFLECT_Y)
 637                 plane_state->bottom_up = true;
 638         else
 639                 plane_state->bottom_up = false;
 640
 641         /*
 642          * Tegra doesn't support different strides for U and V planes so we
 643          * error out if the user tries to display a framebuffer with such a
 644          * configuration.
 645          */
 646         if (state->fb->format->num_planes > 2) {
 647                 if (state->fb->pitches[2] != state->fb->pitches[1]) {
 648                         DRM_ERROR("unsupported UV-plane configuration\n");
 649                         return -EINVAL;
 650                 }
 651         }
 652
 653         err = tegra_plane_state_add(tegra, state);
 654         if (err < 0)
 655                 return err;
 656
 657         return 0;
 658 }
 659
 660 static void tegra_plane_atomic_disable(struct drm_plane *plane,
 661                                        struct drm_plane_state *old_state)
 662 {
 663         struct tegra_plane *p = to_tegra_plane(plane);
 664         u32 value;
 665
 666         /* rien ne va plus */
 667         if (!old_state || !old_state->crtc)
 668                 return;
 669
 670         value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
 671         value &= ~WIN_ENABLE;
 672         tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
 673 }
 674
 675 static void tegra_plane_atomic_update(struct drm_plane *plane,
 676                                       struct drm_plane_state *old_state)
 677 {
 678         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 679         struct drm_framebuffer *fb = plane->state->fb;
 680         struct tegra_plane *p = to_tegra_plane(plane);
 681         struct tegra_dc_window window;
 682         unsigned int i;
 683
 684         /* rien ne va plus */
 685         if (!plane->state->crtc || !plane->state->fb)
 686                 return;
 687
 688         if (!plane->state->visible)
 689                 return tegra_plane_atomic_disable(plane, old_state);
 690
 691         memset(&window, 0, sizeof(window));
 692         window.src.x = plane->state->src.x1 >> 16;
 693         window.src.y = plane->state->src.y1 >> 16;
 694         window.src.w = drm_rect_width(&plane->state->src) >> 16;
 695         window.src.h = drm_rect_height(&plane->state->src) >> 16;
 696         window.dst.x = plane->state->dst.x1;
 697         window.dst.y = plane->state->dst.y1;
 698         window.dst.w = drm_rect_width(&plane->state->dst);
 699         window.dst.h = drm_rect_height(&plane->state->dst);
 700         window.bits_per_pixel = fb->format->cpp[0] * 8;
 701         window.bottom_up = tegra_fb_is_bottom_up(fb) || state->bottom_up;
 702
 703         /* copy from state */
 704         window.zpos = plane->state->normalized_zpos;
 705         window.tiling = state->tiling;
 706         window.format = state->format;
 707         window.swap = state->swap;
 708
 709         for (i = 0; i < fb->format->num_planes; i++) {
 710                 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
 711
 712                 window.base[i] = bo->paddr + fb->offsets[i];
 713
 714                 /*
 715                  * Tegra uses a shared stride for UV planes. Framebuffers are
 716                  * already checked for this in the tegra_plane_atomic_check()
 717                  * function, so it's safe to ignore the V-plane pitch here.
 718                  */
 719                 if (i < 2)
 720                         window.stride[i] = fb->pitches[i];
 721         }
 722
 723         tegra_dc_setup_window(p, &window);
 724 }
 725
 726 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
 727         .atomic_check = tegra_plane_atomic_check,
 728         .atomic_disable = tegra_plane_atomic_disable,
 729         .atomic_update = tegra_plane_atomic_update,
 730 };
 731
 732 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
 733 {
 734         /*
 735          * Ideally this would use drm_crtc_mask(), but that would require the
 736          * CRTC to already be in the mode_config's list of CRTCs. However, it
 737          * will only be added to that list in the drm_crtc_init_with_planes()
 738          * (in tegra_dc_init()), which in turn requires registration of these
 739          * planes. So we have ourselves a nice little chicken and egg problem
 740          * here.
 741          *
 742          * We work around this by manually creating the mask from the number
 743          * of CRTCs that have been registered, and should therefore always be
 744          * the same as drm_crtc_index() after registration.
 745          */
 746         return 1 << drm->mode_config.num_crtc;
 747 }
 748
 749 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
 750                                                     struct tegra_dc *dc)
 751 {
 752         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
 753         enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
 754         struct tegra_plane *plane;
 755         unsigned int num_formats;
 756         const u64 *modifiers;
 757         const u32 *formats;
 758         int err;
 759
 760         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 761         if (!plane)
 762                 return ERR_PTR(-ENOMEM);
 763
 764         /* Always use window A as primary window */
 765         plane->offset = 0xa00;
 766         plane->index = 0;
 767         plane->dc = dc;
 768
 769         num_formats = dc->soc->num_primary_formats;
 770         formats = dc->soc->primary_formats;
 771         modifiers = dc->soc->modifiers;
 772
 773         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 774                                        &tegra_plane_funcs, formats,
 775                                        num_formats, modifiers, type, NULL);
 776         if (err < 0) {
 777                 kfree(plane);
 778                 return ERR_PTR(err);
 779         }
 780
 781         drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
 782         drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
 783
 784         err = drm_plane_create_rotation_property(&plane->base,
 785                                                  DRM_MODE_ROTATE_0,
 786                                                  DRM_MODE_ROTATE_0 |
 787                                                  DRM_MODE_REFLECT_Y);
 788         if (err < 0)
 789                 dev_err(dc->dev, "failed to create rotation property: %d\n",
 790                         err);
 791
 792         return &plane->base;
 793 }
 794
 795 static const u32 tegra_cursor_plane_formats[] = {
 796         DRM_FORMAT_RGBA8888,
 797 };
 798
 799 static int tegra_cursor_atomic_check(struct drm_plane *plane,
 800                                      struct drm_plane_state *state)
 801 {
 802         struct tegra_plane *tegra = to_tegra_plane(plane);
 803         int err;
 804
 805         /* no need for further checks if the plane is being disabled */
 806         if (!state->crtc)
 807                 return 0;
 808
 809         /* scaling not supported for cursor */
 810         if ((state->src_w >> 16 != state->crtc_w) ||
 811             (state->src_h >> 16 != state->crtc_h))
 812                 return -EINVAL;
 813
 814         /* only square cursors supported */
 815         if (state->src_w != state->src_h)
 816                 return -EINVAL;
 817
 818         if (state->crtc_w != 32 && state->crtc_w != 64 &&
 819             state->crtc_w != 128 && state->crtc_w != 256)
 820                 return -EINVAL;
 821
 822         err = tegra_plane_state_add(tegra, state);
 823         if (err < 0)
 824                 return err;
 825
 826         return 0;
 827 }
 828
 829 static void tegra_cursor_atomic_update(struct drm_plane *plane,
 830                                        struct drm_plane_state *old_state)
 831 {
 832         struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
 833         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 834         struct drm_plane_state *state = plane->state;
 835         u32 value = CURSOR_CLIP_DISPLAY;
 836
 837         /* rien ne va plus */
 838         if (!plane->state->crtc || !plane->state->fb)
 839                 return;
 840
 841         switch (state->crtc_w) {
 842         case 32:
 843                 value |= CURSOR_SIZE_32x32;
 844                 break;
 845
 846         case 64:
 847                 value |= CURSOR_SIZE_64x64;
 848                 break;
 849
 850         case 128:
 851                 value |= CURSOR_SIZE_128x128;
 852                 break;
 853
 854         case 256:
 855                 value |= CURSOR_SIZE_256x256;
 856                 break;
 857
 858         default:
 859                 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
 860                      state->crtc_h);
 861                 return;
 862         }
 863
 864         value |= (bo->paddr >> 10) & 0x3fffff;
 865         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
 866
 867 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 868         value = (bo->paddr >> 32) & 0x3;
 869         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
 870 #endif
 871
 872         /* enable cursor and set blend mode */
 873         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 874         value |= CURSOR_ENABLE;
 875         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 876
 877         value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 878         value &= ~CURSOR_DST_BLEND_MASK;
 879         value &= ~CURSOR_SRC_BLEND_MASK;
 880         value |= CURSOR_MODE_NORMAL;
 881         value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 882         value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 883         value |= CURSOR_ALPHA;
 884         tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 885
 886         /* position the cursor */
 887         value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
 888         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
 889 }
 890
 891 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
 892                                         struct drm_plane_state *old_state)
 893 {
 894         struct tegra_dc *dc;
 895         u32 value;
 896
 897         /* rien ne va plus */
 898         if (!old_state || !old_state->crtc)
 899                 return;
 900
 901         dc = to_tegra_dc(old_state->crtc);
 902
 903         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 904         value &= ~CURSOR_ENABLE;
 905         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 906 }
 907
 908 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
 909         .atomic_check = tegra_cursor_atomic_check,
 910         .atomic_update = tegra_cursor_atomic_update,
 911         .atomic_disable = tegra_cursor_atomic_disable,
 912 };
 913
 914 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
 915                                                       struct tegra_dc *dc)
 916 {
 917         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
 918         struct tegra_plane *plane;
 919         unsigned int num_formats;
 920         const u32 *formats;
 921         int err;
 922
 923         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 924         if (!plane)
 925                 return ERR_PTR(-ENOMEM);
 926
 927         /*
 928          * This index is kind of fake. The cursor isn't a regular plane, but
 929          * its update and activation request bits in DC_CMD_STATE_CONTROL do
 930          * use the same programming. Setting this fake index here allows the
 931          * code in tegra_add_plane_state() to do the right thing without the
 932          * need to special-casing the cursor plane.
 933          */
 934         plane->index = 6;
 935         plane->dc = dc;
 936
 937         num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
 938         formats = tegra_cursor_plane_formats;
 939
 940         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 941                                        &tegra_plane_funcs, formats,
 942                                        num_formats, NULL,
 943                                        DRM_PLANE_TYPE_CURSOR, NULL);
 944         if (err < 0) {
 945                 kfree(plane);
 946                 return ERR_PTR(err);
 947         }
 948
 949         drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
 950
 951         return &plane->base;
 952 }
 953
 954 static const u32 tegra20_overlay_formats[] = {
 955         DRM_FORMAT_ARGB4444,
 956         DRM_FORMAT_ARGB1555,
 957         DRM_FORMAT_RGB565,
 958         DRM_FORMAT_RGBA5551,
 959         DRM_FORMAT_ABGR8888,
 960         DRM_FORMAT_ARGB8888,
 961         /* non-native formats */
 962         DRM_FORMAT_XRGB1555,
 963         DRM_FORMAT_RGBX5551,
 964         DRM_FORMAT_XBGR8888,
 965         DRM_FORMAT_XRGB8888,
 966         /* planar formats */
 967         DRM_FORMAT_UYVY,
 968         DRM_FORMAT_YUYV,
 969         DRM_FORMAT_YUV420,
 970         DRM_FORMAT_YUV422,
 971 };
 972
 973 static const u32 tegra114_overlay_formats[] = {
 974         DRM_FORMAT_ARGB4444,
 975         DRM_FORMAT_ARGB1555,
 976         DRM_FORMAT_RGB565,
 977         DRM_FORMAT_RGBA5551,
 978         DRM_FORMAT_ABGR8888,
 979         DRM_FORMAT_ARGB8888,
 980         /* new on Tegra114 */
 981         DRM_FORMAT_ABGR4444,
 982         DRM_FORMAT_ABGR1555,
 983         DRM_FORMAT_BGRA5551,
 984         DRM_FORMAT_XRGB1555,
 985         DRM_FORMAT_RGBX5551,
 986         DRM_FORMAT_XBGR1555,
 987         DRM_FORMAT_BGRX5551,
 988         DRM_FORMAT_BGR565,
 989         DRM_FORMAT_BGRA8888,
 990         DRM_FORMAT_RGBA8888,
 991         DRM_FORMAT_XRGB8888,
 992         DRM_FORMAT_XBGR8888,
 993         /* planar formats */
 994         DRM_FORMAT_UYVY,
 995         DRM_FORMAT_YUYV,
 996         DRM_FORMAT_YUV420,
 997         DRM_FORMAT_YUV422,
 998 };
 999
1000 static const u32 tegra124_overlay_formats[] = {
1001         DRM_FORMAT_ARGB4444,
1002         DRM_FORMAT_ARGB1555,
1003         DRM_FORMAT_RGB565,
1004         DRM_FORMAT_RGBA5551,
1005         DRM_FORMAT_ABGR8888,
1006         DRM_FORMAT_ARGB8888,
1007         /* new on Tegra114 */
1008         DRM_FORMAT_ABGR4444,
1009         DRM_FORMAT_ABGR1555,
1010         DRM_FORMAT_BGRA5551,
1011         DRM_FORMAT_XRGB1555,
1012         DRM_FORMAT_RGBX5551,
1013         DRM_FORMAT_XBGR1555,
1014         DRM_FORMAT_BGRX5551,
1015         DRM_FORMAT_BGR565,
1016         DRM_FORMAT_BGRA8888,
1017         DRM_FORMAT_RGBA8888,
1018         DRM_FORMAT_XRGB8888,
1019         DRM_FORMAT_XBGR8888,
1020         /* new on Tegra124 */
1021         DRM_FORMAT_RGBX8888,
1022         DRM_FORMAT_BGRX8888,
1023         /* planar formats */
1024         DRM_FORMAT_UYVY,
1025         DRM_FORMAT_YUYV,
1026         DRM_FORMAT_YUV420,
1027         DRM_FORMAT_YUV422,
1028 };
1029
1030 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1031                                                        struct tegra_dc *dc,
1032                                                        unsigned int index,
1033                                                        bool cursor)
1034 {
1035         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1036         struct tegra_plane *plane;
1037         unsigned int num_formats;
1038         enum drm_plane_type type;
1039         const u32 *formats;
1040         int err;
1041
1042         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1043         if (!plane)
1044                 return ERR_PTR(-ENOMEM);
1045
1046         plane->offset = 0xa00 + 0x200 * index;
1047         plane->index = index;
1048         plane->dc = dc;
1049
1050         num_formats = dc->soc->num_overlay_formats;
1051         formats = dc->soc->overlay_formats;
1052
1053         if (!cursor)
1054                 type = DRM_PLANE_TYPE_OVERLAY;
1055         else
1056                 type = DRM_PLANE_TYPE_CURSOR;
1057
1058         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1059                                        &tegra_plane_funcs, formats,
1060                                        num_formats, NULL, type, NULL);
1061         if (err < 0) {
1062                 kfree(plane);
1063                 return ERR_PTR(err);
1064         }
1065
1066         drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1067         drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1068
1069         err = drm_plane_create_rotation_property(&plane->base,
1070                                                  DRM_MODE_ROTATE_0,
1071                                                  DRM_MODE_ROTATE_0 |
1072                                                  DRM_MODE_REFLECT_Y);
1073         if (err < 0)
1074                 dev_err(dc->dev, "failed to create rotation property: %d\n",
1075                         err);
1076
1077         return &plane->base;
1078 }
1079
1080 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1081                                                     struct tegra_dc *dc)
1082 {
1083         struct drm_plane *plane, *primary = NULL;
1084         unsigned int i, j;
1085
1086         for (i = 0; i < dc->soc->num_wgrps; i++) {
1087                 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1088
1089                 if (wgrp->dc == dc->pipe) {
1090                         for (j = 0; j < wgrp->num_windows; j++) {
1091                                 unsigned int index = wgrp->windows[j];
1092
1093                                 plane = tegra_shared_plane_create(drm, dc,
1094                                                                   wgrp->index,
1095                                                                   index);
1096                                 if (IS_ERR(plane))
1097                                         return plane;
1098
1099                                 /*
1100                                  * Choose the first shared plane owned by this
1101                                  * head as the primary plane.
1102                                  */
1103                                 if (!primary) {
1104                                         plane->type = DRM_PLANE_TYPE_PRIMARY;
1105                                         primary = plane;
1106                                 }
1107                         }
1108                 }
1109         }
1110
1111         return primary;
1112 }
1113
1114 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1115                                              struct tegra_dc *dc)
1116 {
1117         struct drm_plane *planes[2], *primary;
1118         unsigned int planes_num;
1119         unsigned int i;
1120         int err;
1121
1122         primary = tegra_primary_plane_create(drm, dc);
1123         if (IS_ERR(primary))
1124                 return primary;
1125
1126         if (dc->soc->supports_cursor)
1127                 planes_num = 2;
1128         else
1129                 planes_num = 1;
1130
1131         for (i = 0; i < planes_num; i++) {
1132                 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1133                                                           false);
1134                 if (IS_ERR(planes[i])) {
1135                         err = PTR_ERR(planes[i]);
1136
1137                         while (i--)
1138                                 tegra_plane_funcs.destroy(planes[i]);
1139
1140                         tegra_plane_funcs.destroy(primary);
1141                         return ERR_PTR(err);
1142                 }
1143         }
1144
1145         return primary;
1146 }
1147
1148 static void tegra_dc_destroy(struct drm_crtc *crtc)
1149 {
1150         drm_crtc_cleanup(crtc);
1151 }
1152
1153 static void tegra_crtc_reset(struct drm_crtc *crtc)
1154 {
1155         struct tegra_dc_state *state;
1156
1157         if (crtc->state)
1158                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1159
1160         kfree(crtc->state);
1161         crtc->state = NULL;
1162
1163         state = kzalloc(sizeof(*state), GFP_KERNEL);
1164         if (state) {
1165                 crtc->state = &state->base;
1166                 crtc->state->crtc = crtc;
1167         }
1168
1169         drm_crtc_vblank_reset(crtc);
1170 }
1171
1172 static struct drm_crtc_state *
1173 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1174 {
1175         struct tegra_dc_state *state = to_dc_state(crtc->state);
1176         struct tegra_dc_state *copy;
1177
1178         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1179         if (!copy)
1180                 return NULL;
1181
1182         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1183         copy->clk = state->clk;
1184         copy->pclk = state->pclk;
1185         copy->div = state->div;
1186         copy->planes = state->planes;
1187
1188         return &copy->base;
1189 }
1190
1191 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1192                                             struct drm_crtc_state *state)
1193 {
1194         __drm_atomic_helper_crtc_destroy_state(state);
1195         kfree(state);
1196 }
1197
1198 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1199
1200 static const struct debugfs_reg32 tegra_dc_regs[] = {
1201         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1202         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1203         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1204         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1205         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1206         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1207         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1208         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1209         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1210         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1211         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1212         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1213         DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1214         DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1215         DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1216         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1217         DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1218         DEBUGFS_REG32(DC_CMD_INT_STATUS),
1219         DEBUGFS_REG32(DC_CMD_INT_MASK),
1220         DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1221         DEBUGFS_REG32(DC_CMD_INT_TYPE),
1222         DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1223         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1224         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1225         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1226         DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1227         DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1228         DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1229         DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1230         DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1231         DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1232         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1233         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1234         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1235         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1236         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1237         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1238         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1239         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1240         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1241         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1242         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1243         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1244         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1245         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1246         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1247         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1248         DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1249         DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1250         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1251         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1252         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1253         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1254         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1255         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1256         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1257         DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1258         DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1259         DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1260         DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1261         DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1262         DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1263         DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1264         DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1265         DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1266         DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1267         DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1268         DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1269         DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1270         DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1271         DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1272         DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1273         DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1274         DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1275         DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1276         DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1277         DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1278         DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1279         DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1280         DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1281         DEBUGFS_REG32(DC_DISP_ACTIVE),
1282         DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1283         DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1284         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1285         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1286         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1287         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1288         DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1289         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1290         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1291         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1292         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1293         DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1294         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1295         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1296         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1297         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1298         DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1299         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1300         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1301         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1302         DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1303         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1304         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1305         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1306         DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1307         DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1308         DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1309         DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1310         DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1311         DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1312         DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1313         DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1314         DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1315         DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1316         DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1317         DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1318         DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1319         DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1320         DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1321         DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1322         DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1323         DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1324         DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1325         DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1326         DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1327         DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1328         DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1329         DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1330         DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1331         DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1332         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1333         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1334         DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1335         DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1336         DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1337         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1338         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1339         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1340         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1341         DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1342         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1343         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1344         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1345         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1346         DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1347         DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1348         DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1349         DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1350         DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1351         DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1352         DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1353         DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1354         DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1355         DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1356         DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1357         DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1358         DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1359         DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1360         DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1361         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1362         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1363         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1364         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1365         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1366         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1367         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1368         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1369         DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1370         DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1371         DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1372         DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1373         DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1374         DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1375         DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1376         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1377         DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1378         DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1379         DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1380         DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1381         DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1382         DEBUGFS_REG32(DC_WIN_POSITION),
1383         DEBUGFS_REG32(DC_WIN_SIZE),
1384         DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1385         DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1386         DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1387         DEBUGFS_REG32(DC_WIN_DDA_INC),
1388         DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1389         DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1390         DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1391         DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1392         DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1393         DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1394         DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1395         DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1396         DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1397         DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1398         DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1399         DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1400         DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1401         DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1402         DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1403         DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1404         DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1405         DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1406         DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1407         DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1408         DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1409         DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1410         DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1411         DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1412         DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1413 };
1414
1415 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1416 {
1417         struct drm_info_node *node = s->private;
1418         struct tegra_dc *dc = node->info_ent->data;
1419         unsigned int i;
1420         int err = 0;
1421
1422         drm_modeset_lock(&dc->base.mutex, NULL);
1423
1424         if (!dc->base.state->active) {
1425                 err = -EBUSY;
1426                 goto unlock;
1427         }
1428
1429         for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1430                 unsigned int offset = tegra_dc_regs[i].offset;
1431
1432                 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1433                            offset, tegra_dc_readl(dc, offset));
1434         }
1435
1436 unlock:
1437         drm_modeset_unlock(&dc->base.mutex);
1438         return err;
1439 }
1440
1441 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1442 {
1443         struct drm_info_node *node = s->private;
1444         struct tegra_dc *dc = node->info_ent->data;
1445         int err = 0;
1446         u32 value;
1447
1448         drm_modeset_lock(&dc->base.mutex, NULL);
1449
1450         if (!dc->base.state->active) {
1451                 err = -EBUSY;
1452                 goto unlock;
1453         }
1454
1455         value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1456         tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1457         tegra_dc_commit(dc);
1458
1459         drm_crtc_wait_one_vblank(&dc->base);
1460         drm_crtc_wait_one_vblank(&dc->base);
1461
1462         value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1463         seq_printf(s, "%08x\n", value);
1464
1465         tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1466
1467 unlock:
1468         drm_modeset_unlock(&dc->base.mutex);
1469         return err;
1470 }
1471
1472 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1473 {
1474         struct drm_info_node *node = s->private;
1475         struct tegra_dc *dc = node->info_ent->data;
1476
1477         seq_printf(s, "frames: %lu\n", dc->stats.frames);
1478         seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1479         seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1480         seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1481
1482         return 0;
1483 }
1484
1485 static struct drm_info_list debugfs_files[] = {
1486         { "regs", tegra_dc_show_regs, 0, NULL },
1487         { "crc", tegra_dc_show_crc, 0, NULL },
1488         { "stats", tegra_dc_show_stats, 0, NULL },
1489 };
1490
1491 static int tegra_dc_late_register(struct drm_crtc *crtc)
1492 {
1493         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1494         struct drm_minor *minor = crtc->dev->primary;
1495         struct dentry *root;
1496         struct tegra_dc *dc = to_tegra_dc(crtc);
1497         int err;
1498
1499 #ifdef CONFIG_DEBUG_FS
1500         root = crtc->debugfs_entry;
1501 #else
1502         root = NULL;
1503 #endif
1504
1505         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1506                                     GFP_KERNEL);
1507         if (!dc->debugfs_files)
1508                 return -ENOMEM;
1509
1510         for (i = 0; i < count; i++)
1511                 dc->debugfs_files[i].data = dc;
1512
1513         err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1514         if (err < 0)
1515                 goto free;
1516
1517         return 0;
1518
1519 free:
1520         kfree(dc->debugfs_files);
1521         dc->debugfs_files = NULL;
1522
1523         return err;
1524 }
1525
1526 static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1527 {
1528         unsigned int count = ARRAY_SIZE(debugfs_files);
1529         struct drm_minor *minor = crtc->dev->primary;
1530         struct tegra_dc *dc = to_tegra_dc(crtc);
1531
1532         drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1533         kfree(dc->debugfs_files);
1534         dc->debugfs_files = NULL;
1535 }
1536
1537 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1538 {
1539         struct tegra_dc *dc = to_tegra_dc(crtc);
1540
1541         /* XXX vblank syncpoints don't work with nvdisplay yet */
1542         if (dc->syncpt && !dc->soc->has_nvdisplay)
1543                 return host1x_syncpt_read(dc->syncpt);
1544
1545         /* fallback to software emulated VBLANK counter */
1546         return (u32)drm_crtc_vblank_count(&dc->base);
1547 }
1548
1549 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1550 {
1551         struct tegra_dc *dc = to_tegra_dc(crtc);
1552         u32 value;
1553
1554         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1555         value |= VBLANK_INT;
1556         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1557
1558         return 0;
1559 }
1560
1561 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1562 {
1563         struct tegra_dc *dc = to_tegra_dc(crtc);
1564         u32 value;
1565
1566         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1567         value &= ~VBLANK_INT;
1568         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1569 }
1570
1571 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1572         .page_flip = drm_atomic_helper_page_flip,
1573         .set_config = drm_atomic_helper_set_config,
1574         .destroy = tegra_dc_destroy,
1575         .reset = tegra_crtc_reset,
1576         .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1577         .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1578         .late_register = tegra_dc_late_register,
1579         .early_unregister = tegra_dc_early_unregister,
1580         .get_vblank_counter = tegra_dc_get_vblank_counter,
1581         .enable_vblank = tegra_dc_enable_vblank,
1582         .disable_vblank = tegra_dc_disable_vblank,
1583 };
1584
1585 static int tegra_dc_set_timings(struct tegra_dc *dc,
1586                                 struct drm_display_mode *mode)
1587 {
1588         unsigned int h_ref_to_sync = 1;
1589         unsigned int v_ref_to_sync = 1;
1590         unsigned long value;
1591
1592         if (!dc->soc->has_nvdisplay) {
1593                 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1594
1595                 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1596                 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1597         }
1598
1599         value = ((mode->vsync_end - mode->vsync_start) << 16) |
1600                 ((mode->hsync_end - mode->hsync_start) <<  0);
1601         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1602
1603         value = ((mode->vtotal - mode->vsync_end) << 16) |
1604                 ((mode->htotal - mode->hsync_end) <<  0);
1605         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1606
1607         value = ((mode->vsync_start - mode->vdisplay) << 16) |
1608                 ((mode->hsync_start - mode->hdisplay) <<  0);
1609         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1610
1611         value = (mode->vdisplay << 16) | mode->hdisplay;
1612         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1613
1614         return 0;
1615 }
1616
1617 /**
1618  * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1619  *     state
1620  * @dc: display controller
1621  * @crtc_state: CRTC atomic state
1622  * @clk: parent clock for display controller
1623  * @pclk: pixel clock
1624  * @div: shift clock divider
1625  *
1626  * Returns:
1627  * 0 on success or a negative error-code on failure.
1628  */
1629 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1630                                struct drm_crtc_state *crtc_state,
1631                                struct clk *clk, unsigned long pclk,
1632                                unsigned int div)
1633 {
1634         struct tegra_dc_state *state = to_dc_state(crtc_state);
1635
1636         if (!clk_has_parent(dc->clk, clk))
1637                 return -EINVAL;
1638
1639         state->clk = clk;
1640         state->pclk = pclk;
1641         state->div = div;
1642
1643         return 0;
1644 }
1645
1646 static void tegra_dc_commit_state(struct tegra_dc *dc,
1647                                   struct tegra_dc_state *state)
1648 {
1649         u32 value;
1650         int err;
1651
1652         err = clk_set_parent(dc->clk, state->clk);
1653         if (err < 0)
1654                 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1655
1656         /*
1657          * Outputs may not want to change the parent clock rate. This is only
1658          * relevant to Tegra20 where only a single display PLL is available.
1659          * Since that PLL would typically be used for HDMI, an internal LVDS
1660          * panel would need to be driven by some other clock such as PLL_P
1661          * which is shared with other peripherals. Changing the clock rate
1662          * should therefore be avoided.
1663          */
1664         if (state->pclk > 0) {
1665                 err = clk_set_rate(state->clk, state->pclk);
1666                 if (err < 0)
1667                         dev_err(dc->dev,
1668                                 "failed to set clock rate to %lu Hz\n",
1669                                 state->pclk);
1670         }
1671
1672         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1673                       state->div);
1674         DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1675
1676         if (!dc->soc->has_nvdisplay) {
1677                 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1678                 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1679         }
1680
1681         err = clk_set_rate(dc->clk, state->pclk);
1682         if (err < 0)
1683                 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1684                         dc->clk, state->pclk, err);
1685 }
1686
1687 static void tegra_dc_stop(struct tegra_dc *dc)
1688 {
1689         u32 value;
1690
1691         /* stop the display controller */
1692         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1693         value &= ~DISP_CTRL_MODE_MASK;
1694         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1695
1696         tegra_dc_commit(dc);
1697 }
1698
1699 static bool tegra_dc_idle(struct tegra_dc *dc)
1700 {
1701         u32 value;
1702
1703         value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1704
1705         return (value & DISP_CTRL_MODE_MASK) == 0;
1706 }
1707
1708 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1709 {
1710         timeout = jiffies + msecs_to_jiffies(timeout);
1711
1712         while (time_before(jiffies, timeout)) {
1713                 if (tegra_dc_idle(dc))
1714                         return 0;
1715
1716                 usleep_range(1000, 2000);
1717         }
1718
1719         dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1720         return -ETIMEDOUT;
1721 }
1722
1723 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1724                                       struct drm_crtc_state *old_state)
1725 {
1726         struct tegra_dc *dc = to_tegra_dc(crtc);
1727         u32 value;
1728
1729         if (!tegra_dc_idle(dc)) {
1730                 tegra_dc_stop(dc);
1731
1732                 /*
1733                  * Ignore the return value, there isn't anything useful to do
1734                  * in case this fails.
1735                  */
1736                 tegra_dc_wait_idle(dc, 100);
1737         }
1738
1739         /*
1740          * This should really be part of the RGB encoder driver, but clearing
1741          * these bits has the side-effect of stopping the display controller.
1742          * When that happens no VBLANK interrupts will be raised. At the same
1743          * time the encoder is disabled before the display controller, so the
1744          * above code is always going to timeout waiting for the controller
1745          * to go idle.
1746          *
1747          * Given the close coupling between the RGB encoder and the display
1748          * controller doing it here is still kind of okay. None of the other
1749          * encoder drivers require these bits to be cleared.
1750          *
1751          * XXX: Perhaps given that the display controller is switched off at
1752          * this point anyway maybe clearing these bits isn't even useful for
1753          * the RGB encoder?
1754          */
1755         if (dc->rgb) {
1756                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1757                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1758                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1759                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1760         }
1761
1762         tegra_dc_stats_reset(&dc->stats);
1763         drm_crtc_vblank_off(crtc);
1764
1765         spin_lock_irq(&crtc->dev->event_lock);
1766
1767         if (crtc->state->event) {
1768                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1769                 crtc->state->event = NULL;
1770         }
1771
1772         spin_unlock_irq(&crtc->dev->event_lock);
1773
1774         pm_runtime_put_sync(dc->dev);
1775 }
1776
1777 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1778                                      struct drm_crtc_state *old_state)
1779 {
1780         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1781         struct tegra_dc_state *state = to_dc_state(crtc->state);
1782         struct tegra_dc *dc = to_tegra_dc(crtc);
1783         u32 value;
1784
1785         pm_runtime_get_sync(dc->dev);
1786
1787         /* initialize display controller */
1788         if (dc->syncpt) {
1789                 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1790
1791                 if (dc->soc->has_nvdisplay)
1792                         enable = 1 << 31;
1793                 else
1794                         enable = 1 << 8;
1795
1796                 value = SYNCPT_CNTRL_NO_STALL;
1797                 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1798
1799                 value = enable | syncpt;
1800                 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1801         }
1802
1803         if (dc->soc->has_nvdisplay) {
1804                 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1805                         DSC_OBUF_UF_INT;
1806                 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1807
1808                 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1809                         DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1810                         HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1811                         REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1812                         VBLANK_INT | FRAME_END_INT;
1813                 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1814
1815                 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1816                         FRAME_END_INT;
1817                 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1818
1819                 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1820                 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1821
1822                 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1823         } else {
1824                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1825                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1826                 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1827
1828                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1829                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1830                 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1831
1832                 /* initialize timer */
1833                 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1834                         WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1835                 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1836
1837                 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1838                         WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1839                 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1840
1841                 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1842                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1843                 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1844
1845                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1846                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1847                 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1848         }
1849
1850         if (dc->soc->supports_background_color)
1851                 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1852         else
1853                 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1854
1855         /* apply PLL and pixel clock changes */
1856         tegra_dc_commit_state(dc, state);
1857
1858         /* program display mode */
1859         tegra_dc_set_timings(dc, mode);
1860
1861         /* interlacing isn't supported yet, so disable it */
1862         if (dc->soc->supports_interlacing) {
1863                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1864                 value &= ~INTERLACE_ENABLE;
1865                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1866         }
1867
1868         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1869         value &= ~DISP_CTRL_MODE_MASK;
1870         value |= DISP_CTRL_MODE_C_DISPLAY;
1871         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1872
1873         if (!dc->soc->has_nvdisplay) {
1874                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1875                 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1876                          PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1877                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1878         }
1879
1880         /* enable underflow reporting and display red for missing pixels */
1881         if (dc->soc->has_nvdisplay) {
1882                 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1883                 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1884         }
1885
1886         tegra_dc_commit(dc);
1887
1888         drm_crtc_vblank_on(crtc);
1889 }
1890
1891 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1892                                     struct drm_crtc_state *old_crtc_state)
1893 {
1894         unsigned long flags;
1895
1896         if (crtc->state->event) {
1897                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1898
1899                 if (drm_crtc_vblank_get(crtc) != 0)
1900                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
1901                 else
1902                         drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1903
1904                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1905
1906                 crtc->state->event = NULL;
1907         }
1908 }
1909
1910 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1911                                     struct drm_crtc_state *old_crtc_state)
1912 {
1913         struct tegra_dc_state *state = to_dc_state(crtc->state);
1914         struct tegra_dc *dc = to_tegra_dc(crtc);
1915         u32 value;
1916
1917         value = state->planes << 8 | GENERAL_UPDATE;
1918         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1919         value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1920
1921         value = state->planes | GENERAL_ACT_REQ;
1922         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1923         value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1924 }
1925
1926 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1927         .atomic_begin = tegra_crtc_atomic_begin,
1928         .atomic_flush = tegra_crtc_atomic_flush,
1929         .atomic_enable = tegra_crtc_atomic_enable,
1930         .atomic_disable = tegra_crtc_atomic_disable,
1931 };
1932
1933 static irqreturn_t tegra_dc_irq(int irq, void *data)
1934 {
1935         struct tegra_dc *dc = data;
1936         unsigned long status;
1937
1938         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1939         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1940
1941         if (status & FRAME_END_INT) {
1942                 /*
1943                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1944                 */
1945                 dc->stats.frames++;
1946         }
1947
1948         if (status & VBLANK_INT) {
1949                 /*
1950                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1951                 */
1952                 drm_crtc_handle_vblank(&dc->base);
1953                 dc->stats.vblank++;
1954         }
1955
1956         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1957                 /*
1958                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1959                 */
1960                 dc->stats.underflow++;
1961         }
1962
1963         if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1964                 /*
1965                 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1966                 */
1967                 dc->stats.overflow++;
1968         }
1969
1970         if (status & HEAD_UF_INT) {
1971                 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
1972                 dc->stats.underflow++;
1973         }
1974
1975         return IRQ_HANDLED;
1976 }
1977
1978 static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
1979 {
1980         unsigned int i;
1981
1982         if (!dc->soc->wgrps)
1983                 return true;
1984
1985         for (i = 0; i < dc->soc->num_wgrps; i++) {
1986                 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1987
1988                 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
1989                         return true;
1990         }
1991
1992         return false;
1993 }
1994
1995 static int tegra_dc_init(struct host1x_client *client)
1996 {
1997         struct drm_device *drm = dev_get_drvdata(client->parent);
1998         unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1999         struct tegra_dc *dc = host1x_client_to_dc(client);
2000         struct tegra_drm *tegra = drm->dev_private;
2001         struct drm_plane *primary = NULL;
2002         struct drm_plane *cursor = NULL;
2003         int err;
2004
2005         /*
2006          * XXX do not register DCs with no window groups because we cannot
2007          * assign a primary plane to them, which in turn will cause KMS to
2008          * crash.
2009          */
2010         if (!tegra_dc_has_window_groups(dc))
2011                 return 0;
2012
2013         dc->syncpt = host1x_syncpt_request(client, flags);
2014         if (!dc->syncpt)
2015                 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2016
2017         dc->group = host1x_client_iommu_attach(client, true);
2018         if (IS_ERR(dc->group)) {
2019                 err = PTR_ERR(dc->group);
2020                 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2021                 return err;
2022         }
2023
2024         if (dc->soc->wgrps)
2025                 primary = tegra_dc_add_shared_planes(drm, dc);
2026         else
2027                 primary = tegra_dc_add_planes(drm, dc);
2028
2029         if (IS_ERR(primary)) {
2030                 err = PTR_ERR(primary);
2031                 goto cleanup;
2032         }
2033
2034         if (dc->soc->supports_cursor) {
2035                 cursor = tegra_dc_cursor_plane_create(drm, dc);
2036                 if (IS_ERR(cursor)) {
2037                         err = PTR_ERR(cursor);
2038                         goto cleanup;
2039                 }
2040         } else {
2041                 /* dedicate one overlay to mouse cursor */
2042                 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2043                 if (IS_ERR(cursor)) {
2044                         err = PTR_ERR(cursor);
2045                         goto cleanup;
2046                 }
2047         }
2048
2049         err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2050                                         &tegra_crtc_funcs, NULL);
2051         if (err < 0)
2052                 goto cleanup;
2053
2054         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2055
2056         /*
2057          * Keep track of the minimum pitch alignment across all display
2058          * controllers.
2059          */
2060         if (dc->soc->pitch_align > tegra->pitch_align)
2061                 tegra->pitch_align = dc->soc->pitch_align;
2062
2063         err = tegra_dc_rgb_init(drm, dc);
2064         if (err < 0 && err != -ENODEV) {
2065                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2066                 goto cleanup;
2067         }
2068
2069         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2070                                dev_name(dc->dev), dc);
2071         if (err < 0) {
2072                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2073                         err);
2074                 goto cleanup;
2075         }
2076
2077         return 0;
2078
2079 cleanup:
2080         if (!IS_ERR_OR_NULL(cursor))
2081                 drm_plane_cleanup(cursor);
2082
2083         if (!IS_ERR(primary))
2084                 drm_plane_cleanup(primary);
2085
2086         host1x_client_iommu_detach(client, dc->group);
2087         host1x_syncpt_free(dc->syncpt);
2088
2089         return err;
2090 }
2091
2092 static int tegra_dc_exit(struct host1x_client *client)
2093 {
2094         struct tegra_dc *dc = host1x_client_to_dc(client);
2095         int err;
2096
2097         if (!tegra_dc_has_window_groups(dc))
2098                 return 0;
2099
2100         devm_free_irq(dc->dev, dc->irq, dc);
2101
2102         err = tegra_dc_rgb_exit(dc);
2103         if (err) {
2104                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2105                 return err;
2106         }
2107
2108         host1x_client_iommu_detach(client, dc->group);
2109         host1x_syncpt_free(dc->syncpt);
2110
2111         return 0;
2112 }
2113
2114 static const struct host1x_client_ops dc_client_ops = {
2115         .init = tegra_dc_init,
2116         .exit = tegra_dc_exit,
2117 };
2118
2119 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2120         .supports_background_color = false,
2121         .supports_interlacing = false,
2122         .supports_cursor = false,
2123         .supports_block_linear = false,
2124         .has_legacy_blending = true,
2125         .pitch_align = 8,
2126         .has_powergate = false,
2127         .coupled_pm = true,
2128         .has_nvdisplay = false,
2129         .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2130         .primary_formats = tegra20_primary_formats,
2131         .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2132         .overlay_formats = tegra20_overlay_formats,
2133         .modifiers = tegra20_modifiers,
2134         .has_win_a_without_filters = true,
2135         .has_win_c_without_vert_filter = true,
2136 };
2137
2138 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2139         .supports_background_color = false,
2140         .supports_interlacing = false,
2141         .supports_cursor = false,
2142         .supports_block_linear = false,
2143         .has_legacy_blending = true,
2144         .pitch_align = 8,
2145         .has_powergate = false,
2146         .coupled_pm = false,
2147         .has_nvdisplay = false,
2148         .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2149         .primary_formats = tegra20_primary_formats,
2150         .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2151         .overlay_formats = tegra20_overlay_formats,
2152         .modifiers = tegra20_modifiers,
2153         .has_win_a_without_filters = false,
2154         .has_win_c_without_vert_filter = false,
2155 };
2156
2157 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2158         .supports_background_color = false,
2159         .supports_interlacing = false,
2160         .supports_cursor = false,
2161         .supports_block_linear = false,
2162         .has_legacy_blending = true,
2163         .pitch_align = 64,
2164         .has_powergate = true,
2165         .coupled_pm = false,
2166         .has_nvdisplay = false,
2167         .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2168         .primary_formats = tegra114_primary_formats,
2169         .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2170         .overlay_formats = tegra114_overlay_formats,
2171         .modifiers = tegra20_modifiers,
2172         .has_win_a_without_filters = false,
2173         .has_win_c_without_vert_filter = false,
2174 };
2175
2176 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2177         .supports_background_color = true,
2178         .supports_interlacing = true,
2179         .supports_cursor = true,
2180         .supports_block_linear = true,
2181         .has_legacy_blending = false,
2182         .pitch_align = 64,
2183         .has_powergate = true,
2184         .coupled_pm = false,
2185         .has_nvdisplay = false,
2186         .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2187         .primary_formats = tegra124_primary_formats,
2188         .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2189         .overlay_formats = tegra124_overlay_formats,
2190         .modifiers = tegra124_modifiers,
2191         .has_win_a_without_filters = false,
2192         .has_win_c_without_vert_filter = false,
2193 };
2194
2195 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2196         .supports_background_color = true,
2197         .supports_interlacing = true,
2198         .supports_cursor = true,
2199         .supports_block_linear = true,
2200         .has_legacy_blending = false,
2201         .pitch_align = 64,
2202         .has_powergate = true,
2203         .coupled_pm = false,
2204         .has_nvdisplay = false,
2205         .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2206         .primary_formats = tegra114_primary_formats,
2207         .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2208         .overlay_formats = tegra114_overlay_formats,
2209         .modifiers = tegra124_modifiers,
2210         .has_win_a_without_filters = false,
2211         .has_win_c_without_vert_filter = false,
2212 };
2213
2214 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2215         {
2216                 .index = 0,
2217                 .dc = 0,
2218                 .windows = (const unsigned int[]) { 0 },
2219                 .num_windows = 1,
2220         }, {
2221                 .index = 1,
2222                 .dc = 1,
2223                 .windows = (const unsigned int[]) { 1 },
2224                 .num_windows = 1,
2225         }, {
2226                 .index = 2,
2227                 .dc = 1,
2228                 .windows = (const unsigned int[]) { 2 },
2229                 .num_windows = 1,
2230         }, {
2231                 .index = 3,
2232                 .dc = 2,
2233                 .windows = (const unsigned int[]) { 3 },
2234                 .num_windows = 1,
2235         }, {
2236                 .index = 4,
2237                 .dc = 2,
2238                 .windows = (const unsigned int[]) { 4 },
2239                 .num_windows = 1,
2240         }, {
2241                 .index = 5,
2242                 .dc = 2,
2243                 .windows = (const unsigned int[]) { 5 },
2244                 .num_windows = 1,
2245         },
2246 };
2247
2248 static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2249         .supports_background_color = true,
2250         .supports_interlacing = true,
2251         .supports_cursor = true,
2252         .supports_block_linear = true,
2253         .has_legacy_blending = false,
2254         .pitch_align = 64,
2255         .has_powergate = false,
2256         .coupled_pm = false,
2257         .has_nvdisplay = true,
2258         .wgrps = tegra186_dc_wgrps,
2259         .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2260 };
2261
2262 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2263         {
2264                 .index = 0,
2265                 .dc = 0,
2266                 .windows = (const unsigned int[]) { 0 },
2267                 .num_windows = 1,
2268         }, {
2269                 .index = 1,
2270                 .dc = 1,
2271                 .windows = (const unsigned int[]) { 1 },
2272                 .num_windows = 1,
2273         }, {
2274                 .index = 2,
2275                 .dc = 1,
2276                 .windows = (const unsigned int[]) { 2 },
2277                 .num_windows = 1,
2278         }, {
2279                 .index = 3,
2280                 .dc = 2,
2281                 .windows = (const unsigned int[]) { 3 },
2282                 .num_windows = 1,
2283         }, {
2284                 .index = 4,
2285                 .dc = 2,
2286                 .windows = (const unsigned int[]) { 4 },
2287                 .num_windows = 1,
2288         }, {
2289                 .index = 5,
2290                 .dc = 2,
2291                 .windows = (const unsigned int[]) { 5 },
2292                 .num_windows = 1,
2293         },
2294 };
2295
2296 static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2297         .supports_background_color = true,
2298         .supports_interlacing = true,
2299         .supports_cursor = true,
2300         .supports_block_linear = true,
2301         .has_legacy_blending = false,
2302         .pitch_align = 64,
2303         .has_powergate = false,
2304         .coupled_pm = false,
2305         .has_nvdisplay = true,
2306         .wgrps = tegra194_dc_wgrps,
2307         .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2308 };
2309
2310 static const struct of_device_id tegra_dc_of_match[] = {
2311         {
2312                 .compatible = "nvidia,tegra194-dc",
2313                 .data = &tegra194_dc_soc_info,
2314         }, {
2315                 .compatible = "nvidia,tegra186-dc",
2316                 .data = &tegra186_dc_soc_info,
2317         }, {
2318                 .compatible = "nvidia,tegra210-dc",
2319                 .data = &tegra210_dc_soc_info,
2320         }, {
2321                 .compatible = "nvidia,tegra124-dc",
2322                 .data = &tegra124_dc_soc_info,
2323         }, {
2324                 .compatible = "nvidia,tegra114-dc",
2325                 .data = &tegra114_dc_soc_info,
2326         }, {
2327                 .compatible = "nvidia,tegra30-dc",
2328                 .data = &tegra30_dc_soc_info,
2329         }, {
2330                 .compatible = "nvidia,tegra20-dc",
2331                 .data = &tegra20_dc_soc_info,
2332         }, {
2333                 /* sentinel */
2334         }
2335 };
2336 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2337
2338 static int tegra_dc_parse_dt(struct tegra_dc *dc)
2339 {
2340         struct device_node *np;
2341         u32 value = 0;
2342         int err;
2343
2344         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2345         if (err < 0) {
2346                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2347
2348                 /*
2349                  * If the nvidia,head property isn't present, try to find the
2350                  * correct head number by looking up the position of this
2351                  * display controller's node within the device tree. Assuming
2352                  * that the nodes are ordered properly in the DTS file and
2353                  * that the translation into a flattened device tree blob
2354                  * preserves that ordering this will actually yield the right
2355                  * head number.
2356                  *
2357                  * If those assumptions don't hold, this will still work for
2358                  * cases where only a single display controller is used.
2359                  */
2360                 for_each_matching_node(np, tegra_dc_of_match) {
2361                         if (np == dc->dev->of_node) {
2362                                 of_node_put(np);
2363                                 break;
2364                         }
2365
2366                         value++;
2367                 }
2368         }
2369
2370         dc->pipe = value;
2371
2372         return 0;
2373 }
2374
2375 static int tegra_dc_match_by_pipe(struct device *dev, void *data)
2376 {
2377         struct tegra_dc *dc = dev_get_drvdata(dev);
2378         unsigned int pipe = (unsigned long)data;
2379
2380         return dc->pipe == pipe;
2381 }
2382
2383 static int tegra_dc_couple(struct tegra_dc *dc)
2384 {
2385         /*
2386          * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2387          * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2388          * POWER_CONTROL registers during CRTC enabling.
2389          */
2390         if (dc->soc->coupled_pm && dc->pipe == 1) {
2391                 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
2392                 struct device_link *link;
2393                 struct device *partner;
2394
2395                 partner = driver_find_device(dc->dev->driver, NULL, NULL,
2396                                              tegra_dc_match_by_pipe);
2397                 if (!partner)
2398                         return -EPROBE_DEFER;
2399
2400                 link = device_link_add(dc->dev, partner, flags);
2401                 if (!link) {
2402                         dev_err(dc->dev, "failed to link controllers\n");
2403                         return -EINVAL;
2404                 }
2405
2406                 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2407         }
2408
2409         return 0;
2410 }
2411
2412 static int tegra_dc_probe(struct platform_device *pdev)
2413 {
2414         struct resource *regs;
2415         struct tegra_dc *dc;
2416         int err;
2417
2418         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2419         if (!dc)
2420                 return -ENOMEM;
2421
2422         dc->soc = of_device_get_match_data(&pdev->dev);
2423
2424         INIT_LIST_HEAD(&dc->list);
2425         dc->dev = &pdev->dev;
2426
2427         err = tegra_dc_parse_dt(dc);
2428         if (err < 0)
2429                 return err;
2430
2431         err = tegra_dc_couple(dc);
2432         if (err < 0)
2433                 return err;
2434
2435         dc->clk = devm_clk_get(&pdev->dev, NULL);
2436         if (IS_ERR(dc->clk)) {
2437                 dev_err(&pdev->dev, "failed to get clock\n");
2438                 return PTR_ERR(dc->clk);
2439         }
2440
2441         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2442         if (IS_ERR(dc->rst)) {
2443                 dev_err(&pdev->dev, "failed to get reset\n");
2444                 return PTR_ERR(dc->rst);
2445         }
2446
2447         /* assert reset and disable clock */
2448         err = clk_prepare_enable(dc->clk);
2449         if (err < 0)
2450                 return err;
2451
2452         usleep_range(2000, 4000);
2453
2454         err = reset_control_assert(dc->rst);
2455         if (err < 0)
2456                 return err;
2457
2458         usleep_range(2000, 4000);
2459
2460         clk_disable_unprepare(dc->clk);
2461
2462         if (dc->soc->has_powergate) {
2463                 if (dc->pipe == 0)
2464                         dc->powergate = TEGRA_POWERGATE_DIS;
2465                 else
2466                         dc->powergate = TEGRA_POWERGATE_DISB;
2467
2468                 tegra_powergate_power_off(dc->powergate);
2469         }
2470
2471         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2472         dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2473         if (IS_ERR(dc->regs))
2474                 return PTR_ERR(dc->regs);
2475
2476         dc->irq = platform_get_irq(pdev, 0);
2477         if (dc->irq < 0) {
2478                 dev_err(&pdev->dev, "failed to get IRQ\n");
2479                 return -ENXIO;
2480         }
2481
2482         err = tegra_dc_rgb_probe(dc);
2483         if (err < 0 && err != -ENODEV) {
2484                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2485                 return err;
2486         }
2487
2488         platform_set_drvdata(pdev, dc);
2489         pm_runtime_enable(&pdev->dev);
2490
2491         INIT_LIST_HEAD(&dc->client.list);
2492         dc->client.ops = &dc_client_ops;
2493         dc->client.dev = &pdev->dev;
2494
2495         err = host1x_client_register(&dc->client);
2496         if (err < 0) {
2497                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2498                         err);
2499                 return err;
2500         }
2501
2502         return 0;
2503 }
2504
2505 static int tegra_dc_remove(struct platform_device *pdev)
2506 {
2507         struct tegra_dc *dc = platform_get_drvdata(pdev);
2508         int err;
2509
2510         err = host1x_client_unregister(&dc->client);
2511         if (err < 0) {
2512                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2513                         err);
2514                 return err;
2515         }
2516
2517         err = tegra_dc_rgb_remove(dc);
2518         if (err < 0) {
2519                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2520                 return err;
2521         }
2522
2523         pm_runtime_disable(&pdev->dev);
2524
2525         return 0;
2526 }
2527
2528 #ifdef CONFIG_PM
2529 static int tegra_dc_suspend(struct device *dev)
2530 {
2531         struct tegra_dc *dc = dev_get_drvdata(dev);
2532         int err;
2533
2534         err = reset_control_assert(dc->rst);
2535         if (err < 0) {
2536                 dev_err(dev, "failed to assert reset: %d\n", err);
2537                 return err;
2538         }
2539
2540         if (dc->soc->has_powergate)
2541                 tegra_powergate_power_off(dc->powergate);
2542
2543         clk_disable_unprepare(dc->clk);
2544
2545         return 0;
2546 }
2547
2548 static int tegra_dc_resume(struct device *dev)
2549 {
2550         struct tegra_dc *dc = dev_get_drvdata(dev);
2551         int err;
2552
2553         if (dc->soc->has_powergate) {
2554                 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2555                                                         dc->rst);
2556                 if (err < 0) {
2557                         dev_err(dev, "failed to power partition: %d\n", err);
2558                         return err;
2559                 }
2560         } else {
2561                 err = clk_prepare_enable(dc->clk);
2562                 if (err < 0) {
2563                         dev_err(dev, "failed to enable clock: %d\n", err);
2564                         return err;
2565                 }
2566
2567                 err = reset_control_deassert(dc->rst);
2568                 if (err < 0) {
2569                         dev_err(dev, "failed to deassert reset: %d\n", err);
2570                         return err;
2571                 }
2572         }
2573
2574         return 0;
2575 }
2576 #endif
2577
2578 static const struct dev_pm_ops tegra_dc_pm_ops = {
2579         SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2580 };
2581
2582 struct platform_driver tegra_dc_driver = {
2583         .driver = {
2584                 .name = "tegra-dc",
2585                 .of_match_table = tegra_dc_of_match,
2586                 .pm = &tegra_dc_pm_ops,
2587         },
2588         .probe = tegra_dc_probe,
2589         .remove = tegra_dc_remove,
2590 };