drivers/gpu/drm/sun4i/sun8i_ui_layer.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) Icenowy Zheng <icenowy@aosc.io>
   4  *
   5  * Based on sun4i_layer.h, which is:
   6  *   Copyright (C) 2015 Free Electrons
   7  *   Copyright (C) 2015 NextThing Co
   8  *
   9  *   Maxime Ripard <maxime.ripard@free-electrons.com>
  10  */
  11
  12 #include <drm/drm_atomic.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_crtc.h>
  15 #include <drm/drm_fb_cma_helper.h>
  16 #include <drm/drm_fourcc.h>
  17 #include <drm/drm_gem_cma_helper.h>
  18 #include <drm/drm_gem_framebuffer_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20 #include <drm/drm_probe_helper.h>
  21
  22 #include "sun8i_mixer.h"
  23 #include "sun8i_ui_layer.h"
  24 #include "sun8i_ui_scaler.h"
  25
  26 static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
  27                                   int overlay, bool enable, unsigned int zpos,
  28                                   unsigned int old_zpos)
  29 {
  30         u32 val, bld_base, ch_base;
  31
  32         bld_base = sun8i_blender_base(mixer);
  33         ch_base = sun8i_channel_base(mixer, channel);
  34
  35         DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n",
  36                          enable ? "En" : "Dis", channel, overlay);
  37
  38         if (enable)
  39                 val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
  40         else
  41                 val = 0;
  42
  43         regmap_update_bits(mixer->engine.regs,
  44                            SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
  45                            SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
  46
  47         if (!enable || zpos != old_zpos) {
  48                 regmap_update_bits(mixer->engine.regs,
  49                                    SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
  50                                    SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
  51                                    0);
  52
  53                 regmap_update_bits(mixer->engine.regs,
  54                                    SUN8I_MIXER_BLEND_ROUTE(bld_base),
  55                                    SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
  56                                    0);
  57         }
  58
  59         if (enable) {
  60                 val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
  61
  62                 regmap_update_bits(mixer->engine.regs,
  63                                    SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
  64                                    val, val);
  65
  66                 val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
  67
  68                 regmap_update_bits(mixer->engine.regs,
  69                                    SUN8I_MIXER_BLEND_ROUTE(bld_base),
  70                                    SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
  71                                    val);
  72         }
  73 }
  74
  75 static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
  76                                        int overlay, struct drm_plane *plane,
  77                                        unsigned int zpos)
  78 {
  79         struct drm_plane_state *state = plane->state;
  80         u32 src_w, src_h, dst_w, dst_h;
  81         u32 bld_base, ch_base;
  82         u32 outsize, insize;
  83         u32 hphase, vphase;
  84
  85         DRM_DEBUG_DRIVER("Updating UI channel %d overlay %d\n",
  86                          channel, overlay);
  87
  88         bld_base = sun8i_blender_base(mixer);
  89         ch_base = sun8i_channel_base(mixer, channel);
  90
  91         src_w = drm_rect_width(&state->src) >> 16;
  92         src_h = drm_rect_height(&state->src) >> 16;
  93         dst_w = drm_rect_width(&state->dst);
  94         dst_h = drm_rect_height(&state->dst);
  95
  96         hphase = state->src.x1 & 0xffff;
  97         vphase = state->src.y1 & 0xffff;
  98
  99         insize = SUN8I_MIXER_SIZE(src_w, src_h);
 100         outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
 101
 102         if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 103                 bool interlaced = false;
 104                 u32 val;
 105
 106                 DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
 107                                  dst_w, dst_h);
 108                 regmap_write(mixer->engine.regs,
 109                              SUN8I_MIXER_GLOBAL_SIZE,
 110                              outsize);
 111                 regmap_write(mixer->engine.regs,
 112                              SUN8I_MIXER_BLEND_OUTSIZE(bld_base), outsize);
 113
 114                 if (state->crtc)
 115                         interlaced = state->crtc->state->adjusted_mode.flags
 116                                 & DRM_MODE_FLAG_INTERLACE;
 117
 118                 if (interlaced)
 119                         val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
 120                 else
 121                         val = 0;
 122
 123                 regmap_update_bits(mixer->engine.regs,
 124                                    SUN8I_MIXER_BLEND_OUTCTL(bld_base),
 125                                    SUN8I_MIXER_BLEND_OUTCTL_INTERLACED,
 126                                    val);
 127
 128                 DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
 129                                  interlaced ? "on" : "off");
 130         }
 131
 132         /* Set height and width */
 133         DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
 134                          state->src.x1 >> 16, state->src.y1 >> 16);
 135         DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
 136         regmap_write(mixer->engine.regs,
 137                      SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch_base, overlay),
 138                      insize);
 139         regmap_write(mixer->engine.regs,
 140                      SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch_base),
 141                      insize);
 142
 143         if (insize != outsize || hphase || vphase) {
 144                 u32 hscale, vscale;
 145
 146                 DRM_DEBUG_DRIVER("HW scaling is enabled\n");
 147
 148                 hscale = state->src_w / state->crtc_w;
 149                 vscale = state->src_h / state->crtc_h;
 150
 151                 sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w,
 152                                       dst_h, hscale, vscale, hphase, vphase);
 153                 sun8i_ui_scaler_enable(mixer, channel, true);
 154         } else {
 155                 DRM_DEBUG_DRIVER("HW scaling is not needed\n");
 156                 sun8i_ui_scaler_enable(mixer, channel, false);
 157         }
 158
 159         /* Set base coordinates */
 160         DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
 161                          state->dst.x1, state->dst.y1);
 162         DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
 163         regmap_write(mixer->engine.regs,
 164                      SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
 165                      SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
 166         regmap_write(mixer->engine.regs,
 167                      SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
 168                      outsize);
 169
 170         return 0;
 171 }
 172
 173 static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel,
 174                                          int overlay, struct drm_plane *plane)
 175 {
 176         struct drm_plane_state *state = plane->state;
 177         const struct drm_format_info *fmt;
 178         u32 val, ch_base, hw_fmt;
 179         int ret;
 180
 181         ch_base = sun8i_channel_base(mixer, channel);
 182
 183         fmt = state->fb->format;
 184         ret = sun8i_mixer_drm_format_to_hw(fmt->format, &hw_fmt);
 185         if (ret || fmt->is_yuv) {
 186                 DRM_DEBUG_DRIVER("Invalid format\n");
 187                 return -EINVAL;
 188         }
 189
 190         val = hw_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
 191         regmap_update_bits(mixer->engine.regs,
 192                            SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
 193                            SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
 194
 195         return 0;
 196 }
 197
 198 static int sun8i_ui_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
 199                                         int overlay, struct drm_plane *plane)
 200 {
 201         struct drm_plane_state *state = plane->state;
 202         struct drm_framebuffer *fb = state->fb;
 203         struct drm_gem_cma_object *gem;
 204         dma_addr_t paddr;
 205         u32 ch_base;
 206         int bpp;
 207
 208         ch_base = sun8i_channel_base(mixer, channel);
 209
 210         /* Get the physical address of the buffer in memory */
 211         gem = drm_fb_cma_get_gem_obj(fb, 0);
 212
 213         DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
 214
 215         /* Compute the start of the displayed memory */
 216         bpp = fb->format->cpp[0];
 217         paddr = gem->paddr + fb->offsets[0];
 218
 219         /* Fixup framebuffer address for src coordinates */
 220         paddr += (state->src.x1 >> 16) * bpp;
 221         paddr += (state->src.y1 >> 16) * fb->pitches[0];
 222
 223         /* Set the line width */
 224         DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]);
 225         regmap_write(mixer->engine.regs,
 226                      SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, overlay),
 227                      fb->pitches[0]);
 228
 229         DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
 230
 231         regmap_write(mixer->engine.regs,
 232                      SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, overlay),
 233                      lower_32_bits(paddr));
 234
 235         return 0;
 236 }
 237
 238 static int sun8i_ui_layer_atomic_check(struct drm_plane *plane,
 239                                        struct drm_plane_state *state)
 240 {
 241         struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
 242         struct drm_crtc *crtc = state->crtc;
 243         struct drm_crtc_state *crtc_state;
 244         int min_scale, max_scale;
 245
 246         if (!crtc)
 247                 return 0;
 248
 249         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 250         if (WARN_ON(!crtc_state))
 251                 return -EINVAL;
 252
 253         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 254         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 255
 256         if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
 257                 min_scale = SUN8I_UI_SCALER_SCALE_MIN;
 258                 max_scale = SUN8I_UI_SCALER_SCALE_MAX;
 259         }
 260
 261         return drm_atomic_helper_check_plane_state(state, crtc_state,
 262                                                    min_scale, max_scale,
 263                                                    true, true);
 264 }
 265
 266 static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane,
 267                                           struct drm_plane_state *old_state)
 268 {
 269         struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
 270         unsigned int old_zpos = old_state->normalized_zpos;
 271         struct sun8i_mixer *mixer = layer->mixer;
 272
 273         sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
 274                               old_zpos);
 275 }
 276
 277 static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
 278                                          struct drm_plane_state *old_state)
 279 {
 280         struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
 281         unsigned int zpos = plane->state->normalized_zpos;
 282         unsigned int old_zpos = old_state->normalized_zpos;
 283         struct sun8i_mixer *mixer = layer->mixer;
 284
 285         if (!plane->state->visible) {
 286                 sun8i_ui_layer_enable(mixer, layer->channel,
 287                                       layer->overlay, false, 0, old_zpos);
 288                 return;
 289         }
 290
 291         sun8i_ui_layer_update_coord(mixer, layer->channel,
 292                                     layer->overlay, plane, zpos);
 293         sun8i_ui_layer_update_formats(mixer, layer->channel,
 294                                       layer->overlay, plane);
 295         sun8i_ui_layer_update_buffer(mixer, layer->channel,
 296                                      layer->overlay, plane);
 297         sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay,
 298                               true, zpos, old_zpos);
 299 }
 300
 301 static struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = {
 302         .prepare_fb     = drm_gem_fb_prepare_fb,
 303         .atomic_check   = sun8i_ui_layer_atomic_check,
 304         .atomic_disable = sun8i_ui_layer_atomic_disable,
 305         .atomic_update  = sun8i_ui_layer_atomic_update,
 306 };
 307
 308 static const struct drm_plane_funcs sun8i_ui_layer_funcs = {
 309         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 310         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 311         .destroy                = drm_plane_cleanup,
 312         .disable_plane          = drm_atomic_helper_disable_plane,
 313         .reset                  = drm_atomic_helper_plane_reset,
 314         .update_plane           = drm_atomic_helper_update_plane,
 315 };
 316
 317 static const u32 sun8i_ui_layer_formats[] = {
 318         DRM_FORMAT_ABGR1555,
 319         DRM_FORMAT_ABGR4444,
 320         DRM_FORMAT_ABGR8888,
 321         DRM_FORMAT_ARGB1555,
 322         DRM_FORMAT_ARGB4444,
 323         DRM_FORMAT_ARGB8888,
 324         DRM_FORMAT_BGR565,
 325         DRM_FORMAT_BGR888,
 326         DRM_FORMAT_BGRA5551,
 327         DRM_FORMAT_BGRA4444,
 328         DRM_FORMAT_BGRA8888,
 329         DRM_FORMAT_BGRX8888,
 330         DRM_FORMAT_RGB565,
 331         DRM_FORMAT_RGB888,
 332         DRM_FORMAT_RGBA4444,
 333         DRM_FORMAT_RGBA5551,
 334         DRM_FORMAT_RGBA8888,
 335         DRM_FORMAT_RGBX8888,
 336         DRM_FORMAT_XBGR8888,
 337         DRM_FORMAT_XRGB8888,
 338 };
 339
 340 struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
 341                                                struct sun8i_mixer *mixer,
 342                                                int index)
 343 {
 344         enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
 345         int channel = mixer->cfg->vi_num + index;
 346         struct sun8i_ui_layer *layer;
 347         unsigned int plane_cnt;
 348         int ret;
 349
 350         layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
 351         if (!layer)
 352                 return ERR_PTR(-ENOMEM);
 353
 354         if (index == 0)
 355                 type = DRM_PLANE_TYPE_PRIMARY;
 356
 357         /* possible crtcs are set later */
 358         ret = drm_universal_plane_init(drm, &layer->plane, 0,
 359                                        &sun8i_ui_layer_funcs,
 360                                        sun8i_ui_layer_formats,
 361                                        ARRAY_SIZE(sun8i_ui_layer_formats),
 362                                        NULL, type, NULL);
 363         if (ret) {
 364                 dev_err(drm->dev, "Couldn't initialize layer\n");
 365                 return ERR_PTR(ret);
 366         }
 367
 368         plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num;
 369
 370         ret = drm_plane_create_zpos_property(&layer->plane, channel,
 371                                              0, plane_cnt - 1);
 372         if (ret) {
 373                 dev_err(drm->dev, "Couldn't add zpos property\n");
 374                 return ERR_PTR(ret);
 375         }
 376
 377         drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs);
 378         layer->mixer = mixer;
 379         layer->channel = channel;
 380         layer->overlay = 0;
 381
 382         return layer;
 383 }