drivers/gpu/drm/sti/sti_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics SA 2014
   4  * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/hdmi.h>
  11 #include <linux/module.h>
  12 #include <linux/io.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/reset.h>
  15
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_bridge.h>
  18 #include <drm/drm_debugfs.h>
  19 #include <drm/drm_drv.h>
  20 #include <drm/drm_edid.h>
  21 #include <drm/drm_file.h>
  22 #include <drm/drm_print.h>
  23 #include <drm/drm_probe_helper.h>
  24
  25 #include <sound/hdmi-codec.h>
  26
  27 #include "sti_hdmi.h"
  28 #include "sti_hdmi_tx3g4c28phy.h"
  29 #include "sti_vtg.h"
  30
  31 #define HDMI_CFG                        0x0000
  32 #define HDMI_INT_EN                     0x0004
  33 #define HDMI_INT_STA                    0x0008
  34 #define HDMI_INT_CLR                    0x000C
  35 #define HDMI_STA                        0x0010
  36 #define HDMI_ACTIVE_VID_XMIN            0x0100
  37 #define HDMI_ACTIVE_VID_XMAX            0x0104
  38 #define HDMI_ACTIVE_VID_YMIN            0x0108
  39 #define HDMI_ACTIVE_VID_YMAX            0x010C
  40 #define HDMI_DFLT_CHL0_DAT              0x0110
  41 #define HDMI_DFLT_CHL1_DAT              0x0114
  42 #define HDMI_DFLT_CHL2_DAT              0x0118
  43 #define HDMI_AUDIO_CFG                  0x0200
  44 #define HDMI_SPDIF_FIFO_STATUS          0x0204
  45 #define HDMI_SW_DI_1_HEAD_WORD          0x0210
  46 #define HDMI_SW_DI_1_PKT_WORD0          0x0214
  47 #define HDMI_SW_DI_1_PKT_WORD1          0x0218
  48 #define HDMI_SW_DI_1_PKT_WORD2          0x021C
  49 #define HDMI_SW_DI_1_PKT_WORD3          0x0220
  50 #define HDMI_SW_DI_1_PKT_WORD4          0x0224
  51 #define HDMI_SW_DI_1_PKT_WORD5          0x0228
  52 #define HDMI_SW_DI_1_PKT_WORD6          0x022C
  53 #define HDMI_SW_DI_CFG                  0x0230
  54 #define HDMI_SAMPLE_FLAT_MASK           0x0244
  55 #define HDMI_AUDN                       0x0400
  56 #define HDMI_AUD_CTS                    0x0404
  57 #define HDMI_SW_DI_2_HEAD_WORD          0x0600
  58 #define HDMI_SW_DI_2_PKT_WORD0          0x0604
  59 #define HDMI_SW_DI_2_PKT_WORD1          0x0608
  60 #define HDMI_SW_DI_2_PKT_WORD2          0x060C
  61 #define HDMI_SW_DI_2_PKT_WORD3          0x0610
  62 #define HDMI_SW_DI_2_PKT_WORD4          0x0614
  63 #define HDMI_SW_DI_2_PKT_WORD5          0x0618
  64 #define HDMI_SW_DI_2_PKT_WORD6          0x061C
  65 #define HDMI_SW_DI_3_HEAD_WORD          0x0620
  66 #define HDMI_SW_DI_3_PKT_WORD0          0x0624
  67 #define HDMI_SW_DI_3_PKT_WORD1          0x0628
  68 #define HDMI_SW_DI_3_PKT_WORD2          0x062C
  69 #define HDMI_SW_DI_3_PKT_WORD3          0x0630
  70 #define HDMI_SW_DI_3_PKT_WORD4          0x0634
  71 #define HDMI_SW_DI_3_PKT_WORD5          0x0638
  72 #define HDMI_SW_DI_3_PKT_WORD6          0x063C
  73
  74 #define HDMI_IFRAME_SLOT_AVI            1
  75 #define HDMI_IFRAME_SLOT_AUDIO          2
  76 #define HDMI_IFRAME_SLOT_VENDOR         3
  77
  78 #define  XCAT(prefix, x, suffix)        prefix ## x ## suffix
  79 #define  HDMI_SW_DI_N_HEAD_WORD(x)      XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
  80 #define  HDMI_SW_DI_N_PKT_WORD0(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
  81 #define  HDMI_SW_DI_N_PKT_WORD1(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
  82 #define  HDMI_SW_DI_N_PKT_WORD2(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
  83 #define  HDMI_SW_DI_N_PKT_WORD3(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
  84 #define  HDMI_SW_DI_N_PKT_WORD4(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
  85 #define  HDMI_SW_DI_N_PKT_WORD5(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
  86 #define  HDMI_SW_DI_N_PKT_WORD6(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
  87
  88 #define HDMI_SW_DI_MAX_WORD             7
  89
  90 #define HDMI_IFRAME_DISABLED            0x0
  91 #define HDMI_IFRAME_SINGLE_SHOT         0x1
  92 #define HDMI_IFRAME_FIELD               0x2
  93 #define HDMI_IFRAME_FRAME               0x3
  94 #define HDMI_IFRAME_MASK                0x3
  95 #define HDMI_IFRAME_CFG_DI_N(x, n)       ((x) << ((n-1)*4)) /* n from 1 to 6 */
  96
  97 #define HDMI_CFG_DEVICE_EN              BIT(0)
  98 #define HDMI_CFG_HDMI_NOT_DVI           BIT(1)
  99 #define HDMI_CFG_HDCP_EN                BIT(2)
 100 #define HDMI_CFG_ESS_NOT_OESS           BIT(3)
 101 #define HDMI_CFG_H_SYNC_POL_NEG         BIT(4)
 102 #define HDMI_CFG_V_SYNC_POL_NEG         BIT(6)
 103 #define HDMI_CFG_422_EN                 BIT(8)
 104 #define HDMI_CFG_FIFO_OVERRUN_CLR       BIT(12)
 105 #define HDMI_CFG_FIFO_UNDERRUN_CLR      BIT(13)
 106 #define HDMI_CFG_SW_RST_EN              BIT(31)
 107
 108 #define HDMI_INT_GLOBAL                 BIT(0)
 109 #define HDMI_INT_SW_RST                 BIT(1)
 110 #define HDMI_INT_PIX_CAP                BIT(3)
 111 #define HDMI_INT_HOT_PLUG               BIT(4)
 112 #define HDMI_INT_DLL_LCK                BIT(5)
 113 #define HDMI_INT_NEW_FRAME              BIT(6)
 114 #define HDMI_INT_GENCTRL_PKT            BIT(7)
 115 #define HDMI_INT_AUDIO_FIFO_XRUN        BIT(8)
 116 #define HDMI_INT_SINK_TERM_PRESENT      BIT(11)
 117
 118 #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
 119                         | HDMI_INT_DLL_LCK \
 120                         | HDMI_INT_HOT_PLUG \
 121                         | HDMI_INT_GLOBAL)
 122
 123 #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
 124                         | HDMI_INT_AUDIO_FIFO_XRUN \
 125                         | HDMI_INT_GENCTRL_PKT \
 126                         | HDMI_INT_NEW_FRAME \
 127                         | HDMI_INT_DLL_LCK \
 128                         | HDMI_INT_HOT_PLUG \
 129                         | HDMI_INT_PIX_CAP \
 130                         | HDMI_INT_SW_RST \
 131                         | HDMI_INT_GLOBAL)
 132
 133 #define HDMI_STA_SW_RST                 BIT(1)
 134
 135 #define HDMI_AUD_CFG_8CH                BIT(0)
 136 #define HDMI_AUD_CFG_SPDIF_DIV_2        BIT(1)
 137 #define HDMI_AUD_CFG_SPDIF_DIV_3        BIT(2)
 138 #define HDMI_AUD_CFG_SPDIF_CLK_DIV_4    (BIT(1) | BIT(2))
 139 #define HDMI_AUD_CFG_CTS_CLK_256FS      BIT(12)
 140 #define HDMI_AUD_CFG_DTS_INVALID        BIT(16)
 141 #define HDMI_AUD_CFG_ONE_BIT_INVALID    (BIT(18) | BIT(19) | BIT(20) |  BIT(21))
 142 #define HDMI_AUD_CFG_CH12_VALID BIT(28)
 143 #define HDMI_AUD_CFG_CH34_VALID BIT(29)
 144 #define HDMI_AUD_CFG_CH56_VALID BIT(30)
 145 #define HDMI_AUD_CFG_CH78_VALID BIT(31)
 146
 147 /* sample flat mask */
 148 #define HDMI_SAMPLE_FLAT_NO      0
 149 #define HDMI_SAMPLE_FLAT_SP0 BIT(0)
 150 #define HDMI_SAMPLE_FLAT_SP1 BIT(1)
 151 #define HDMI_SAMPLE_FLAT_SP2 BIT(2)
 152 #define HDMI_SAMPLE_FLAT_SP3 BIT(3)
 153 #define HDMI_SAMPLE_FLAT_ALL (HDMI_SAMPLE_FLAT_SP0 | HDMI_SAMPLE_FLAT_SP1 |\
 154                               HDMI_SAMPLE_FLAT_SP2 | HDMI_SAMPLE_FLAT_SP3)
 155
 156 #define HDMI_INFOFRAME_HEADER_TYPE(x)    (((x) & 0xff) <<  0)
 157 #define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) <<  8)
 158 #define HDMI_INFOFRAME_HEADER_LEN(x)     (((x) & 0x0f) << 16)
 159
 160 struct sti_hdmi_connector {
 161         struct drm_connector drm_connector;
 162         struct drm_encoder *encoder;
 163         struct sti_hdmi *hdmi;
 164         struct drm_property *colorspace_property;
 165 };
 166
 167 #define to_sti_hdmi_connector(x) \
 168         container_of(x, struct sti_hdmi_connector, drm_connector)
 169
 170 static const struct drm_prop_enum_list colorspace_mode_names[] = {
 171         { HDMI_COLORSPACE_RGB, "rgb" },
 172         { HDMI_COLORSPACE_YUV422, "yuv422" },
 173         { HDMI_COLORSPACE_YUV444, "yuv444" },
 174 };
 175
 176 u32 hdmi_read(struct sti_hdmi *hdmi, int offset)
 177 {
 178         return readl(hdmi->regs + offset);
 179 }
 180
 181 void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset)
 182 {
 183         writel(val, hdmi->regs + offset);
 184 }
 185
 186 /**
 187  * HDMI interrupt handler threaded
 188  *
 189  * @irq: irq number
 190  * @arg: connector structure
 191  */
 192 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
 193 {
 194         struct sti_hdmi *hdmi = arg;
 195
 196         /* Hot plug/unplug IRQ */
 197         if (hdmi->irq_status & HDMI_INT_HOT_PLUG) {
 198                 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
 199                 if (hdmi->drm_dev)
 200                         drm_helper_hpd_irq_event(hdmi->drm_dev);
 201         }
 202
 203         /* Sw reset and PLL lock are exclusive so we can use the same
 204          * event to signal them
 205          */
 206         if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) {
 207                 hdmi->event_received = true;
 208                 wake_up_interruptible(&hdmi->wait_event);
 209         }
 210
 211         /* Audio FIFO underrun IRQ */
 212         if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN)
 213                 DRM_INFO("Warning: audio FIFO underrun occurs!\n");
 214
 215         return IRQ_HANDLED;
 216 }
 217
 218 /**
 219  * HDMI interrupt handler
 220  *
 221  * @irq: irq number
 222  * @arg: connector structure
 223  */
 224 static irqreturn_t hdmi_irq(int irq, void *arg)
 225 {
 226         struct sti_hdmi *hdmi = arg;
 227
 228         /* read interrupt status */
 229         hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA);
 230
 231         /* clear interrupt status */
 232         hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR);
 233
 234         /* force sync bus write */
 235         hdmi_read(hdmi, HDMI_INT_STA);
 236
 237         return IRQ_WAKE_THREAD;
 238 }
 239
 240 /**
 241  * Set hdmi active area depending on the drm display mode selected
 242  *
 243  * @hdmi: pointer on the hdmi internal structure
 244  */
 245 static void hdmi_active_area(struct sti_hdmi *hdmi)
 246 {
 247         u32 xmin, xmax;
 248         u32 ymin, ymax;
 249
 250         xmin = sti_vtg_get_pixel_number(hdmi->mode, 1);
 251         xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay);
 252         ymin = sti_vtg_get_line_number(hdmi->mode, 0);
 253         ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1);
 254
 255         hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN);
 256         hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX);
 257         hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN);
 258         hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX);
 259 }
 260
 261 /**
 262  * Overall hdmi configuration
 263  *
 264  * @hdmi: pointer on the hdmi internal structure
 265  */
 266 static void hdmi_config(struct sti_hdmi *hdmi)
 267 {
 268         u32 conf;
 269
 270         DRM_DEBUG_DRIVER("\n");
 271
 272         /* Clear overrun and underrun fifo */
 273         conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR;
 274
 275         /* Select encryption type and the framing mode */
 276         conf |= HDMI_CFG_ESS_NOT_OESS;
 277         if (hdmi->hdmi_monitor)
 278                 conf |= HDMI_CFG_HDMI_NOT_DVI;
 279
 280         /* Set Hsync polarity */
 281         if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) {
 282                 DRM_DEBUG_DRIVER("H Sync Negative\n");
 283                 conf |= HDMI_CFG_H_SYNC_POL_NEG;
 284         }
 285
 286         /* Set Vsync polarity */
 287         if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) {
 288                 DRM_DEBUG_DRIVER("V Sync Negative\n");
 289                 conf |= HDMI_CFG_V_SYNC_POL_NEG;
 290         }
 291
 292         /* Enable HDMI */
 293         conf |= HDMI_CFG_DEVICE_EN;
 294
 295         hdmi_write(hdmi, conf, HDMI_CFG);
 296 }
 297
 298 /*
 299  * Helper to reset info frame
 300  *
 301  * @hdmi: pointer on the hdmi internal structure
 302  * @slot: infoframe to reset
 303  */
 304 static void hdmi_infoframe_reset(struct sti_hdmi *hdmi,
 305                                  u32 slot)
 306 {
 307         u32 val, i;
 308         u32 head_offset, pack_offset;
 309
 310         switch (slot) {
 311         case HDMI_IFRAME_SLOT_AVI:
 312                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
 313                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
 314                 break;
 315         case HDMI_IFRAME_SLOT_AUDIO:
 316                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
 317                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
 318                 break;
 319         case HDMI_IFRAME_SLOT_VENDOR:
 320                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
 321                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
 322                 break;
 323         default:
 324                 DRM_ERROR("unsupported infoframe slot: %#x\n", slot);
 325                 return;
 326         }
 327
 328         /* Disable transmission for the selected slot */
 329         val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
 330         val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
 331         hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
 332
 333         /* Reset info frame registers */
 334         hdmi_write(hdmi, 0x0, head_offset);
 335         for (i = 0; i < HDMI_SW_DI_MAX_WORD; i += sizeof(u32))
 336                 hdmi_write(hdmi, 0x0, pack_offset + i);
 337 }
 338
 339 /**
 340  * Helper to concatenate infoframe in 32 bits word
 341  *
 342  * @ptr: pointer on the hdmi internal structure
 343  * @size: size to write
 344  */
 345 static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size)
 346 {
 347         unsigned long value = 0;
 348         size_t i;
 349
 350         for (i = size; i > 0; i--)
 351                 value = (value << 8) | ptr[i - 1];
 352
 353         return value;
 354 }
 355
 356 /**
 357  * Helper to write info frame
 358  *
 359  * @hdmi: pointer on the hdmi internal structure
 360  * @data: infoframe to write
 361  * @size: size to write
 362  */
 363 static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi,
 364                                           const u8 *data,
 365                                           size_t size)
 366 {
 367         const u8 *ptr = data;
 368         u32 val, slot, mode, i;
 369         u32 head_offset, pack_offset;
 370
 371         switch (*ptr) {
 372         case HDMI_INFOFRAME_TYPE_AVI:
 373                 slot = HDMI_IFRAME_SLOT_AVI;
 374                 mode = HDMI_IFRAME_FIELD;
 375                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
 376                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
 377                 break;
 378         case HDMI_INFOFRAME_TYPE_AUDIO:
 379                 slot = HDMI_IFRAME_SLOT_AUDIO;
 380                 mode = HDMI_IFRAME_FRAME;
 381                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
 382                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
 383                 break;
 384         case HDMI_INFOFRAME_TYPE_VENDOR:
 385                 slot = HDMI_IFRAME_SLOT_VENDOR;
 386                 mode = HDMI_IFRAME_FRAME;
 387                 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
 388                 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
 389                 break;
 390         default:
 391                 DRM_ERROR("unsupported infoframe type: %#x\n", *ptr);
 392                 return;
 393         }
 394
 395         /* Disable transmission slot for updated infoframe */
 396         val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
 397         val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
 398         hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
 399
 400         val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++);
 401         val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++);
 402         val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++);
 403         writel(val, hdmi->regs + head_offset);
 404
 405         /*
 406          * Each subpack contains 4 bytes
 407          * The First Bytes of the first subpacket must contain the checksum
 408          * Packet size is increase by one.
 409          */
 410         size = size - HDMI_INFOFRAME_HEADER_SIZE + 1;
 411         for (i = 0; i < size; i += sizeof(u32)) {
 412                 size_t num;
 413
 414                 num = min_t(size_t, size - i, sizeof(u32));
 415                 val = hdmi_infoframe_subpack(ptr, num);
 416                 ptr += sizeof(u32);
 417                 writel(val, hdmi->regs + pack_offset + i);
 418         }
 419
 420         /* Enable transmission slot for updated infoframe */
 421         val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
 422         val |= HDMI_IFRAME_CFG_DI_N(mode, slot);
 423         hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
 424 }
 425
 426 /**
 427  * Prepare and configure the AVI infoframe
 428  *
 429  * AVI infoframe are transmitted at least once per two video field and
 430  * contains information about HDMI transmission mode such as color space,
 431  * colorimetry, ...
 432  *
 433  * @hdmi: pointer on the hdmi internal structure
 434  *
 435  * Return negative value if error occurs
 436  */
 437 static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
 438 {
 439         struct drm_display_mode *mode = &hdmi->mode;
 440         struct hdmi_avi_infoframe infoframe;
 441         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
 442         int ret;
 443
 444         DRM_DEBUG_DRIVER("\n");
 445
 446         ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe,
 447                                                        hdmi->drm_connector, mode);
 448         if (ret < 0) {
 449                 DRM_ERROR("failed to setup AVI infoframe: %d\n", ret);
 450                 return ret;
 451         }
 452
 453         /* fixed infoframe configuration not linked to the mode */
 454         infoframe.colorspace = hdmi->colorspace;
 455         infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 456         infoframe.colorimetry = HDMI_COLORIMETRY_NONE;
 457
 458         ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer));
 459         if (ret < 0) {
 460                 DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
 461                 return ret;
 462         }
 463
 464         hdmi_infoframe_write_infopack(hdmi, buffer, ret);
 465
 466         return 0;
 467 }
 468
 469 /**
 470  * Prepare and configure the AUDIO infoframe
 471  *
 472  * AUDIO infoframe are transmitted once per frame and
 473  * contains information about HDMI transmission mode such as audio codec,
 474  * sample size, ...
 475  *
 476  * @hdmi: pointer on the hdmi internal structure
 477  *
 478  * Return negative value if error occurs
 479  */
 480 static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi)
 481 {
 482         struct hdmi_audio_params *audio = &hdmi->audio;
 483         u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
 484         int ret, val;
 485
 486         DRM_DEBUG_DRIVER("enter %s, AIF %s\n", __func__,
 487                          audio->enabled ? "enable" : "disable");
 488         if (audio->enabled) {
 489                 /* set audio parameters stored*/
 490                 ret = hdmi_audio_infoframe_pack(&audio->cea, buffer,
 491                                                 sizeof(buffer));
 492                 if (ret < 0) {
 493                         DRM_ERROR("failed to pack audio infoframe: %d\n", ret);
 494                         return ret;
 495                 }
 496                 hdmi_infoframe_write_infopack(hdmi, buffer, ret);
 497         } else {
 498                 /*disable audio info frame transmission */
 499                 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
 500                 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK,
 501                                              HDMI_IFRAME_SLOT_AUDIO);
 502                 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
 503         }
 504
 505         return 0;
 506 }
 507
 508 /*
 509  * Prepare and configure the VS infoframe
 510  *
 511  * Vendor Specific infoframe are transmitted once per frame and
 512  * contains vendor specific information.
 513  *
 514  * @hdmi: pointer on the hdmi internal structure
 515  *
 516  * Return negative value if error occurs
 517  */
 518 #define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6
 519 static int hdmi_vendor_infoframe_config(struct sti_hdmi *hdmi)
 520 {
 521         struct drm_display_mode *mode = &hdmi->mode;
 522         struct hdmi_vendor_infoframe infoframe;
 523         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_MAX_SIZE];
 524         int ret;
 525
 526         DRM_DEBUG_DRIVER("\n");
 527
 528         ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe,
 529                                                           hdmi->drm_connector,
 530                                                           mode);
 531         if (ret < 0) {
 532                 /*
 533                  * Going into that statement does not means vendor infoframe
 534                  * fails. It just informed us that vendor infoframe is not
 535                  * needed for the selected mode. Only  4k or stereoscopic 3D
 536                  * mode requires vendor infoframe. So just simply return 0.
 537                  */
 538                 return 0;
 539         }
 540
 541         ret = hdmi_vendor_infoframe_pack(&infoframe, buffer, sizeof(buffer));
 542         if (ret < 0) {
 543                 DRM_ERROR("failed to pack VS infoframe: %d\n", ret);
 544                 return ret;
 545         }
 546
 547         hdmi_infoframe_write_infopack(hdmi, buffer, ret);
 548
 549         return 0;
 550 }
 551
 552 #define HDMI_TIMEOUT_SWRESET  100   /*milliseconds */
 553
 554 /**
 555  * Software reset of the hdmi subsystem
 556  *
 557  * @hdmi: pointer on the hdmi internal structure
 558  *
 559  */
 560 static void hdmi_swreset(struct sti_hdmi *hdmi)
 561 {
 562         u32 val;
 563
 564         DRM_DEBUG_DRIVER("\n");
 565
 566         /* Enable hdmi_audio clock only during hdmi reset */
 567         if (clk_prepare_enable(hdmi->clk_audio))
 568                 DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
 569
 570         /* Sw reset */
 571         hdmi->event_received = false;
 572
 573         val = hdmi_read(hdmi, HDMI_CFG);
 574         val |= HDMI_CFG_SW_RST_EN;
 575         hdmi_write(hdmi, val, HDMI_CFG);
 576
 577         /* Wait reset completed */
 578         wait_event_interruptible_timeout(hdmi->wait_event,
 579                                          hdmi->event_received,
 580                                          msecs_to_jiffies
 581                                          (HDMI_TIMEOUT_SWRESET));
 582
 583         /*
 584          * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
 585          * set to '1' and clk_audio is running.
 586          */
 587         if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0)
 588                 DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
 589
 590         val = hdmi_read(hdmi, HDMI_CFG);
 591         val &= ~HDMI_CFG_SW_RST_EN;
 592         hdmi_write(hdmi, val, HDMI_CFG);
 593
 594         /* Disable hdmi_audio clock. Not used anymore for drm purpose */
 595         clk_disable_unprepare(hdmi->clk_audio);
 596 }
 597
 598 #define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2)
 599 #define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2)
 600 #define DBGFS_DUMP(str, reg) seq_printf(s, "%s  %-25s 0x%08X", str, #reg, \
 601                                         hdmi_read(hdmi, reg))
 602 #define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot))
 603
 604 static void hdmi_dbg_cfg(struct seq_file *s, int val)
 605 {
 606         int tmp;
 607
 608         seq_putc(s, '\t');
 609         tmp = val & HDMI_CFG_HDMI_NOT_DVI;
 610         DBGFS_PRINT_STR("mode:", tmp ? "HDMI" : "DVI");
 611         seq_puts(s, "\t\t\t\t\t");
 612         tmp = val & HDMI_CFG_HDCP_EN;
 613         DBGFS_PRINT_STR("HDCP:", tmp ? "enable" : "disable");
 614         seq_puts(s, "\t\t\t\t\t");
 615         tmp = val & HDMI_CFG_ESS_NOT_OESS;
 616         DBGFS_PRINT_STR("HDCP mode:", tmp ? "ESS enable" : "OESS enable");
 617         seq_puts(s, "\t\t\t\t\t");
 618         tmp = val & HDMI_CFG_H_SYNC_POL_NEG;
 619         DBGFS_PRINT_STR("Hsync polarity:", tmp ? "inverted" : "normal");
 620         seq_puts(s, "\t\t\t\t\t");
 621         tmp = val & HDMI_CFG_V_SYNC_POL_NEG;
 622         DBGFS_PRINT_STR("Vsync polarity:", tmp ? "inverted" : "normal");
 623         seq_puts(s, "\t\t\t\t\t");
 624         tmp = val & HDMI_CFG_422_EN;
 625         DBGFS_PRINT_STR("YUV422 format:", tmp ? "enable" : "disable");
 626 }
 627
 628 static void hdmi_dbg_sta(struct seq_file *s, int val)
 629 {
 630         int tmp;
 631
 632         seq_putc(s, '\t');
 633         tmp = (val & HDMI_STA_DLL_LCK);
 634         DBGFS_PRINT_STR("pll:", tmp ? "locked" : "not locked");
 635         seq_puts(s, "\t\t\t\t\t");
 636         tmp = (val & HDMI_STA_HOT_PLUG);
 637         DBGFS_PRINT_STR("hdmi cable:", tmp ? "connected" : "not connected");
 638 }
 639
 640 static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val)
 641 {
 642         int tmp;
 643         char *const en_di[] = {"no transmission",
 644                                "single transmission",
 645                                "once every field",
 646                                "once every frame"};
 647
 648         seq_putc(s, '\t');
 649         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1));
 650         DBGFS_PRINT_STR("Data island 1:", en_di[tmp]);
 651         seq_puts(s, "\t\t\t\t\t");
 652         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4;
 653         DBGFS_PRINT_STR("Data island 2:", en_di[tmp]);
 654         seq_puts(s, "\t\t\t\t\t");
 655         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8;
 656         DBGFS_PRINT_STR("Data island 3:", en_di[tmp]);
 657         seq_puts(s, "\t\t\t\t\t");
 658         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12;
 659         DBGFS_PRINT_STR("Data island 4:", en_di[tmp]);
 660         seq_puts(s, "\t\t\t\t\t");
 661         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16;
 662         DBGFS_PRINT_STR("Data island 5:", en_di[tmp]);
 663         seq_puts(s, "\t\t\t\t\t");
 664         tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20;
 665         DBGFS_PRINT_STR("Data island 6:", en_di[tmp]);
 666 }
 667
 668 static int hdmi_dbg_show(struct seq_file *s, void *data)
 669 {
 670         struct drm_info_node *node = s->private;
 671         struct sti_hdmi *hdmi = (struct sti_hdmi *)node->info_ent->data;
 672
 673         seq_printf(s, "HDMI: (vaddr = 0x%p)", hdmi->regs);
 674         DBGFS_DUMP("\n", HDMI_CFG);
 675         hdmi_dbg_cfg(s, hdmi_read(hdmi, HDMI_CFG));
 676         DBGFS_DUMP("", HDMI_INT_EN);
 677         DBGFS_DUMP("\n", HDMI_STA);
 678         hdmi_dbg_sta(s, hdmi_read(hdmi, HDMI_STA));
 679         DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN);
 680         seq_putc(s, '\t');
 681         DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMIN));
 682         DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX);
 683         seq_putc(s, '\t');
 684         DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMAX));
 685         DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN);
 686         seq_putc(s, '\t');
 687         DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMIN));
 688         DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX);
 689         seq_putc(s, '\t');
 690         DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMAX));
 691         DBGFS_DUMP("", HDMI_SW_DI_CFG);
 692         hdmi_dbg_sw_di_cfg(s, hdmi_read(hdmi, HDMI_SW_DI_CFG));
 693
 694         DBGFS_DUMP("\n", HDMI_AUDIO_CFG);
 695         DBGFS_DUMP("\n", HDMI_SPDIF_FIFO_STATUS);
 696         DBGFS_DUMP("\n", HDMI_AUDN);
 697
 698         seq_printf(s, "\n AVI Infoframe (Data Island slot N=%d):",
 699                    HDMI_IFRAME_SLOT_AVI);
 700         DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI);
 701         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI);
 702         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI);
 703         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI);
 704         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI);
 705         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI);
 706         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI);
 707         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI);
 708         seq_printf(s, "\n\n AUDIO Infoframe (Data Island slot N=%d):",
 709                    HDMI_IFRAME_SLOT_AUDIO);
 710         DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AUDIO);
 711         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AUDIO);
 712         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AUDIO);
 713         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AUDIO);
 714         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AUDIO);
 715         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AUDIO);
 716         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AUDIO);
 717         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AUDIO);
 718         seq_printf(s, "\n\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):",
 719                    HDMI_IFRAME_SLOT_VENDOR);
 720         DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_VENDOR);
 721         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_VENDOR);
 722         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_VENDOR);
 723         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_VENDOR);
 724         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_VENDOR);
 725         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_VENDOR);
 726         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_VENDOR);
 727         DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_VENDOR);
 728         seq_putc(s, '\n');
 729         return 0;
 730 }
 731
 732 static struct drm_info_list hdmi_debugfs_files[] = {
 733         { "hdmi", hdmi_dbg_show, 0, NULL },
 734 };
 735
 736 static void hdmi_debugfs_init(struct sti_hdmi *hdmi, struct drm_minor *minor)
 737 {
 738         unsigned int i;
 739
 740         for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_files); i++)
 741                 hdmi_debugfs_files[i].data = hdmi;
 742
 743         drm_debugfs_create_files(hdmi_debugfs_files,
 744                                  ARRAY_SIZE(hdmi_debugfs_files),
 745                                  minor->debugfs_root, minor);
 746 }
 747
 748 static void sti_hdmi_disable(struct drm_bridge *bridge)
 749 {
 750         struct sti_hdmi *hdmi = bridge->driver_private;
 751
 752         u32 val = hdmi_read(hdmi, HDMI_CFG);
 753
 754         if (!hdmi->enabled)
 755                 return;
 756
 757         DRM_DEBUG_DRIVER("\n");
 758
 759         /* Disable HDMI */
 760         val &= ~HDMI_CFG_DEVICE_EN;
 761         hdmi_write(hdmi, val, HDMI_CFG);
 762
 763         hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR);
 764
 765         /* Stop the phy */
 766         hdmi->phy_ops->stop(hdmi);
 767
 768         /* Reset info frame transmission */
 769         hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AVI);
 770         hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AUDIO);
 771         hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_VENDOR);
 772
 773         /* Set the default channel data to be a dark red */
 774         hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT);
 775         hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT);
 776         hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT);
 777
 778         /* Disable/unprepare hdmi clock */
 779         clk_disable_unprepare(hdmi->clk_phy);
 780         clk_disable_unprepare(hdmi->clk_tmds);
 781         clk_disable_unprepare(hdmi->clk_pix);
 782
 783         hdmi->enabled = false;
 784
 785         cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
 786 }
 787
 788 /**
 789  * sti_hdmi_audio_get_non_coherent_n() - get N parameter for non-coherent
 790  * clocks. None-coherent clocks means that audio and TMDS clocks have not the
 791  * same source (drifts between clocks). In this case assumption is that CTS is
 792  * automatically calculated by hardware.
 793  *
 794  * @audio_fs: audio frame clock frequency in Hz
 795  *
 796  * Values computed are based on table described in HDMI specification 1.4b
 797  *
 798  * Returns n value.
 799  */
 800 static int sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs)
 801 {
 802         unsigned int n;
 803
 804         switch (audio_fs) {
 805         case 32000:
 806                 n = 4096;
 807                 break;
 808         case 44100:
 809                 n = 6272;
 810                 break;
 811         case 48000:
 812                 n = 6144;
 813                 break;
 814         case 88200:
 815                 n = 6272 * 2;
 816                 break;
 817         case 96000:
 818                 n = 6144 * 2;
 819                 break;
 820         case 176400:
 821                 n = 6272 * 4;
 822                 break;
 823         case 192000:
 824                 n = 6144 * 4;
 825                 break;
 826         default:
 827                 /* Not pre-defined, recommended value: 128 * fs / 1000 */
 828                 n = (audio_fs * 128) / 1000;
 829         }
 830
 831         return n;
 832 }
 833
 834 static int hdmi_audio_configure(struct sti_hdmi *hdmi)
 835 {
 836         int audio_cfg, n;
 837         struct hdmi_audio_params *params = &hdmi->audio;
 838         struct hdmi_audio_infoframe *info = &params->cea;
 839
 840         DRM_DEBUG_DRIVER("\n");
 841
 842         if (!hdmi->enabled)
 843                 return 0;
 844
 845         /* update N parameter */
 846         n = sti_hdmi_audio_get_non_coherent_n(params->sample_rate);
 847
 848         DRM_DEBUG_DRIVER("Audio rate = %d Hz, TMDS clock = %d Hz, n = %d\n",
 849                          params->sample_rate, hdmi->mode.clock * 1000, n);
 850         hdmi_write(hdmi, n, HDMI_AUDN);
 851
 852         /* update HDMI registers according to configuration */
 853         audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
 854                     HDMI_AUD_CFG_ONE_BIT_INVALID;
 855
 856         switch (info->channels) {
 857         case 8:
 858                 audio_cfg |= HDMI_AUD_CFG_CH78_VALID;
 859                 fallthrough;
 860         case 6:
 861                 audio_cfg |= HDMI_AUD_CFG_CH56_VALID;
 862                 fallthrough;
 863         case 4:
 864                 audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH;
 865                 fallthrough;
 866         case 2:
 867                 audio_cfg |= HDMI_AUD_CFG_CH12_VALID;
 868                 break;
 869         default:
 870                 DRM_ERROR("ERROR: Unsupported number of channels (%d)!\n",
 871                           info->channels);
 872                 return -EINVAL;
 873         }
 874
 875         hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
 876
 877         return hdmi_audio_infoframe_config(hdmi);
 878 }
 879
 880 static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
 881 {
 882         struct sti_hdmi *hdmi = bridge->driver_private;
 883
 884         DRM_DEBUG_DRIVER("\n");
 885
 886         if (hdmi->enabled)
 887                 return;
 888
 889         /* Prepare/enable clocks */
 890         if (clk_prepare_enable(hdmi->clk_pix))
 891                 DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
 892         if (clk_prepare_enable(hdmi->clk_tmds))
 893                 DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
 894         if (clk_prepare_enable(hdmi->clk_phy))
 895                 DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n");
 896
 897         hdmi->enabled = true;
 898
 899         /* Program hdmi serializer and start phy */
 900         if (!hdmi->phy_ops->start(hdmi)) {
 901                 DRM_ERROR("Unable to start hdmi phy\n");
 902                 return;
 903         }
 904
 905         /* Program hdmi active area */
 906         hdmi_active_area(hdmi);
 907
 908         /* Enable working interrupts */
 909         hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN);
 910
 911         /* Program hdmi config */
 912         hdmi_config(hdmi);
 913
 914         /* Program AVI infoframe */
 915         if (hdmi_avi_infoframe_config(hdmi))
 916                 DRM_ERROR("Unable to configure AVI infoframe\n");
 917
 918         if (hdmi->audio.enabled) {
 919                 if (hdmi_audio_configure(hdmi))
 920                         DRM_ERROR("Unable to configure audio\n");
 921         } else {
 922                 hdmi_audio_infoframe_config(hdmi);
 923         }
 924
 925         /* Program VS infoframe */
 926         if (hdmi_vendor_infoframe_config(hdmi))
 927                 DRM_ERROR("Unable to configure VS infoframe\n");
 928
 929         /* Sw reset */
 930         hdmi_swreset(hdmi);
 931 }
 932
 933 static void sti_hdmi_set_mode(struct drm_bridge *bridge,
 934                               const struct drm_display_mode *mode,
 935                               const struct drm_display_mode *adjusted_mode)
 936 {
 937         struct sti_hdmi *hdmi = bridge->driver_private;
 938         int ret;
 939
 940         DRM_DEBUG_DRIVER("\n");
 941
 942         /* Copy the drm display mode in the connector local structure */
 943         memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode));
 944
 945         /* Update clock framerate according to the selected mode */
 946         ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000);
 947         if (ret < 0) {
 948                 DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
 949                           mode->clock * 1000);
 950                 return;
 951         }
 952         ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000);
 953         if (ret < 0) {
 954                 DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
 955                           mode->clock * 1000);
 956                 return;
 957         }
 958 }
 959
 960 static void sti_hdmi_bridge_nope(struct drm_bridge *bridge)
 961 {
 962         /* do nothing */
 963 }
 964
 965 static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = {
 966         .pre_enable = sti_hdmi_pre_enable,
 967         .enable = sti_hdmi_bridge_nope,
 968         .disable = sti_hdmi_disable,
 969         .post_disable = sti_hdmi_bridge_nope,
 970         .mode_set = sti_hdmi_set_mode,
 971 };
 972
 973 static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
 974 {
 975         struct sti_hdmi_connector *hdmi_connector
 976                 = to_sti_hdmi_connector(connector);
 977         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
 978         struct edid *edid;
 979         int count;
 980
 981         DRM_DEBUG_DRIVER("\n");
 982
 983         edid = drm_get_edid(connector, hdmi->ddc_adapt);
 984         if (!edid)
 985                 goto fail;
 986
 987         hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 988         DRM_DEBUG_KMS("%s : %dx%d cm\n",
 989                       (hdmi->hdmi_monitor ? "hdmi monitor" : "dvi monitor"),
 990                       edid->width_cm, edid->height_cm);
 991         cec_notifier_set_phys_addr_from_edid(hdmi->notifier, edid);
 992
 993         count = drm_add_edid_modes(connector, edid);
 994         drm_connector_update_edid_property(connector, edid);
 995
 996         kfree(edid);
 997         return count;
 998
 999 fail:
1000         DRM_ERROR("Can't read HDMI EDID\n");
1001         return 0;
1002 }
1003
1004 #define CLK_TOLERANCE_HZ 50
1005
1006 static int sti_hdmi_connector_mode_valid(struct drm_connector *connector,
1007                                         struct drm_display_mode *mode)
1008 {
1009         int target = mode->clock * 1000;
1010         int target_min = target - CLK_TOLERANCE_HZ;
1011         int target_max = target + CLK_TOLERANCE_HZ;
1012         int result;
1013         struct sti_hdmi_connector *hdmi_connector
1014                 = to_sti_hdmi_connector(connector);
1015         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1016
1017
1018         result = clk_round_rate(hdmi->clk_pix, target);
1019
1020         DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
1021                          target, result);
1022
1023         if ((result < target_min) || (result > target_max)) {
1024                 DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target);
1025                 return MODE_BAD;
1026         }
1027
1028         return MODE_OK;
1029 }
1030
1031 static const
1032 struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
1033         .get_modes = sti_hdmi_connector_get_modes,
1034         .mode_valid = sti_hdmi_connector_mode_valid,
1035 };
1036
1037 /* get detection status of display device */
1038 static enum drm_connector_status
1039 sti_hdmi_connector_detect(struct drm_connector *connector, bool force)
1040 {
1041         struct sti_hdmi_connector *hdmi_connector
1042                 = to_sti_hdmi_connector(connector);
1043         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1044
1045         DRM_DEBUG_DRIVER("\n");
1046
1047         if (hdmi->hpd) {
1048                 DRM_DEBUG_DRIVER("hdmi cable connected\n");
1049                 return connector_status_connected;
1050         }
1051
1052         DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
1053         cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
1054         return connector_status_disconnected;
1055 }
1056
1057 static void sti_hdmi_connector_init_property(struct drm_device *drm_dev,
1058                                              struct drm_connector *connector)
1059 {
1060         struct sti_hdmi_connector *hdmi_connector
1061                 = to_sti_hdmi_connector(connector);
1062         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1063         struct drm_property *prop;
1064
1065         /* colorspace property */
1066         hdmi->colorspace = DEFAULT_COLORSPACE_MODE;
1067         prop = drm_property_create_enum(drm_dev, 0, "colorspace",
1068                                         colorspace_mode_names,
1069                                         ARRAY_SIZE(colorspace_mode_names));
1070         if (!prop) {
1071                 DRM_ERROR("fails to create colorspace property\n");
1072                 return;
1073         }
1074         hdmi_connector->colorspace_property = prop;
1075         drm_object_attach_property(&connector->base, prop, hdmi->colorspace);
1076 }
1077
1078 static int
1079 sti_hdmi_connector_set_property(struct drm_connector *connector,
1080                                 struct drm_connector_state *state,
1081                                 struct drm_property *property,
1082                                 uint64_t val)
1083 {
1084         struct sti_hdmi_connector *hdmi_connector
1085                 = to_sti_hdmi_connector(connector);
1086         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1087
1088         if (property == hdmi_connector->colorspace_property) {
1089                 hdmi->colorspace = val;
1090                 return 0;
1091         }
1092
1093         DRM_ERROR("failed to set hdmi connector property\n");
1094         return -EINVAL;
1095 }
1096
1097 static int
1098 sti_hdmi_connector_get_property(struct drm_connector *connector,
1099                                 const struct drm_connector_state *state,
1100                                 struct drm_property *property,
1101                                 uint64_t *val)
1102 {
1103         struct sti_hdmi_connector *hdmi_connector
1104                 = to_sti_hdmi_connector(connector);
1105         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1106
1107         if (property == hdmi_connector->colorspace_property) {
1108                 *val = hdmi->colorspace;
1109                 return 0;
1110         }
1111
1112         DRM_ERROR("failed to get hdmi connector property\n");
1113         return -EINVAL;
1114 }
1115
1116 static int sti_hdmi_late_register(struct drm_connector *connector)
1117 {
1118         struct sti_hdmi_connector *hdmi_connector
1119                 = to_sti_hdmi_connector(connector);
1120         struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1121
1122         hdmi_debugfs_init(hdmi, hdmi->drm_dev->primary);
1123
1124         return 0;
1125 }
1126
1127 static const struct drm_connector_funcs sti_hdmi_connector_funcs = {
1128         .fill_modes = drm_helper_probe_single_connector_modes,
1129         .detect = sti_hdmi_connector_detect,
1130         .destroy = drm_connector_cleanup,
1131         .reset = drm_atomic_helper_connector_reset,
1132         .atomic_set_property = sti_hdmi_connector_set_property,
1133         .atomic_get_property = sti_hdmi_connector_get_property,
1134         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1135         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1136         .late_register = sti_hdmi_late_register,
1137 };
1138
1139 static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev)
1140 {
1141         struct drm_encoder *encoder;
1142
1143         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1144                 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1145                         return encoder;
1146         }
1147
1148         return NULL;
1149 }
1150
1151 static void hdmi_audio_shutdown(struct device *dev, void *data)
1152 {
1153         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1154         int audio_cfg;
1155
1156         DRM_DEBUG_DRIVER("\n");
1157
1158         /* disable audio */
1159         audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
1160                     HDMI_AUD_CFG_ONE_BIT_INVALID;
1161         hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
1162
1163         hdmi->audio.enabled = false;
1164         hdmi_audio_infoframe_config(hdmi);
1165 }
1166
1167 static int hdmi_audio_hw_params(struct device *dev,
1168                                 void *data,
1169                                 struct hdmi_codec_daifmt *daifmt,
1170                                 struct hdmi_codec_params *params)
1171 {
1172         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1173         int ret;
1174
1175         DRM_DEBUG_DRIVER("\n");
1176
1177         if ((daifmt->fmt != HDMI_I2S) || daifmt->bit_clk_inv ||
1178             daifmt->frame_clk_inv || daifmt->bit_clk_master ||
1179             daifmt->frame_clk_master) {
1180                 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1181                         daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1182                         daifmt->bit_clk_master,
1183                         daifmt->frame_clk_master);
1184                 return -EINVAL;
1185         }
1186
1187         hdmi->audio.sample_width = params->sample_width;
1188         hdmi->audio.sample_rate = params->sample_rate;
1189         hdmi->audio.cea = params->cea;
1190
1191         hdmi->audio.enabled = true;
1192
1193         ret = hdmi_audio_configure(hdmi);
1194         if (ret < 0)
1195                 return ret;
1196
1197         return 0;
1198 }
1199
1200 static int hdmi_audio_mute(struct device *dev, void *data,
1201                            bool enable, int direction)
1202 {
1203         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1204
1205         DRM_DEBUG_DRIVER("%s\n", enable ? "enable" : "disable");
1206
1207         if (enable)
1208                 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_ALL, HDMI_SAMPLE_FLAT_MASK);
1209         else
1210                 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_NO, HDMI_SAMPLE_FLAT_MASK);
1211
1212         return 0;
1213 }
1214
1215 static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1216 {
1217         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1218         struct drm_connector *connector = hdmi->drm_connector;
1219
1220         DRM_DEBUG_DRIVER("\n");
1221         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1222
1223         return 0;
1224 }
1225
1226 static const struct hdmi_codec_ops audio_codec_ops = {
1227         .hw_params = hdmi_audio_hw_params,
1228         .audio_shutdown = hdmi_audio_shutdown,
1229         .mute_stream = hdmi_audio_mute,
1230         .get_eld = hdmi_audio_get_eld,
1231         .no_capture_mute = 1,
1232 };
1233
1234 static int sti_hdmi_register_audio_driver(struct device *dev,
1235                                           struct sti_hdmi *hdmi)
1236 {
1237         struct hdmi_codec_pdata codec_data = {
1238                 .ops = &audio_codec_ops,
1239                 .max_i2s_channels = 8,
1240                 .i2s = 1,
1241         };
1242
1243         DRM_DEBUG_DRIVER("\n");
1244
1245         hdmi->audio.enabled = false;
1246
1247         hdmi->audio_pdev = platform_device_register_data(
1248                 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1249                 &codec_data, sizeof(codec_data));
1250
1251         if (IS_ERR(hdmi->audio_pdev))
1252                 return PTR_ERR(hdmi->audio_pdev);
1253
1254         DRM_INFO("%s Driver bound %s\n", HDMI_CODEC_DRV_NAME, dev_name(dev));
1255
1256         return 0;
1257 }
1258
1259 static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
1260 {
1261         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1262         struct drm_device *drm_dev = data;
1263         struct drm_encoder *encoder;
1264         struct sti_hdmi_connector *connector;
1265         struct cec_connector_info conn_info;
1266         struct drm_connector *drm_connector;
1267         struct drm_bridge *bridge;
1268         int err;
1269
1270         /* Set the drm device handle */
1271         hdmi->drm_dev = drm_dev;
1272
1273         encoder = sti_hdmi_find_encoder(drm_dev);
1274         if (!encoder)
1275                 return -EINVAL;
1276
1277         connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
1278         if (!connector)
1279                 return -EINVAL;
1280
1281         connector->hdmi = hdmi;
1282
1283         bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
1284         if (!bridge)
1285                 return -EINVAL;
1286
1287         bridge->driver_private = hdmi;
1288         bridge->funcs = &sti_hdmi_bridge_funcs;
1289         drm_bridge_attach(encoder, bridge, NULL, 0);
1290
1291         connector->encoder = encoder;
1292
1293         drm_connector = (struct drm_connector *)connector;
1294
1295         drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
1296
1297         drm_connector_init_with_ddc(drm_dev, drm_connector,
1298                                     &sti_hdmi_connector_funcs,
1299                                     DRM_MODE_CONNECTOR_HDMIA,
1300                                     hdmi->ddc_adapt);
1301         drm_connector_helper_add(drm_connector,
1302                         &sti_hdmi_connector_helper_funcs);
1303
1304         /* initialise property */
1305         sti_hdmi_connector_init_property(drm_dev, drm_connector);
1306
1307         hdmi->drm_connector = drm_connector;
1308
1309         err = drm_connector_attach_encoder(drm_connector, encoder);
1310         if (err) {
1311                 DRM_ERROR("Failed to attach a connector to a encoder\n");
1312                 goto err_sysfs;
1313         }
1314
1315         err = sti_hdmi_register_audio_driver(dev, hdmi);
1316         if (err) {
1317                 DRM_ERROR("Failed to attach an audio codec\n");
1318                 goto err_sysfs;
1319         }
1320
1321         /* Initialize audio infoframe */
1322         err = hdmi_audio_infoframe_init(&hdmi->audio.cea);
1323         if (err) {
1324                 DRM_ERROR("Failed to init audio infoframe\n");
1325                 goto err_sysfs;
1326         }
1327
1328         cec_fill_conn_info_from_drm(&conn_info, drm_connector);
1329         hdmi->notifier = cec_notifier_conn_register(&hdmi->dev, NULL,
1330                                                     &conn_info);
1331         if (!hdmi->notifier) {
1332                 hdmi->drm_connector = NULL;
1333                 return -ENOMEM;
1334         }
1335
1336         /* Enable default interrupts */
1337         hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN);
1338
1339         return 0;
1340
1341 err_sysfs:
1342         hdmi->drm_connector = NULL;
1343         return -EINVAL;
1344 }
1345
1346 static void sti_hdmi_unbind(struct device *dev,
1347                 struct device *master, void *data)
1348 {
1349         struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1350
1351         cec_notifier_conn_unregister(hdmi->notifier);
1352 }
1353
1354 static const struct component_ops sti_hdmi_ops = {
1355         .bind = sti_hdmi_bind,
1356         .unbind = sti_hdmi_unbind,
1357 };
1358
1359 static const struct of_device_id hdmi_of_match[] = {
1360         {
1361                 .compatible = "st,stih407-hdmi",
1362                 .data = &tx3g4c28phy_ops,
1363         }, {
1364                 /* end node */
1365         }
1366 };
1367 MODULE_DEVICE_TABLE(of, hdmi_of_match);
1368
1369 static int sti_hdmi_probe(struct platform_device *pdev)
1370 {
1371         struct device *dev = &pdev->dev;
1372         struct sti_hdmi *hdmi;
1373         struct device_node *np = dev->of_node;
1374         struct resource *res;
1375         struct device_node *ddc;
1376         int ret;
1377
1378         DRM_INFO("%s\n", __func__);
1379
1380         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1381         if (!hdmi)
1382                 return -ENOMEM;
1383
1384         ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0);
1385         if (ddc) {
1386                 hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc);
1387                 of_node_put(ddc);
1388                 if (!hdmi->ddc_adapt)
1389                         return -EPROBE_DEFER;
1390         }
1391
1392         hdmi->dev = pdev->dev;
1393
1394         /* Get resources */
1395         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg");
1396         if (!res) {
1397                 DRM_ERROR("Invalid hdmi resource\n");
1398                 ret = -ENOMEM;
1399                 goto release_adapter;
1400         }
1401         hdmi->regs = devm_ioremap(dev, res->start, resource_size(res));
1402         if (!hdmi->regs) {
1403                 ret = -ENOMEM;
1404                 goto release_adapter;
1405         }
1406
1407         hdmi->phy_ops = (struct hdmi_phy_ops *)
1408                 of_match_node(hdmi_of_match, np)->data;
1409
1410         /* Get clock resources */
1411         hdmi->clk_pix = devm_clk_get(dev, "pix");
1412         if (IS_ERR(hdmi->clk_pix)) {
1413                 DRM_ERROR("Cannot get hdmi_pix clock\n");
1414                 ret = PTR_ERR(hdmi->clk_pix);
1415                 goto release_adapter;
1416         }
1417
1418         hdmi->clk_tmds = devm_clk_get(dev, "tmds");
1419         if (IS_ERR(hdmi->clk_tmds)) {
1420                 DRM_ERROR("Cannot get hdmi_tmds clock\n");
1421                 ret = PTR_ERR(hdmi->clk_tmds);
1422                 goto release_adapter;
1423         }
1424
1425         hdmi->clk_phy = devm_clk_get(dev, "phy");
1426         if (IS_ERR(hdmi->clk_phy)) {
1427                 DRM_ERROR("Cannot get hdmi_phy clock\n");
1428                 ret = PTR_ERR(hdmi->clk_phy);
1429                 goto release_adapter;
1430         }
1431
1432         hdmi->clk_audio = devm_clk_get(dev, "audio");
1433         if (IS_ERR(hdmi->clk_audio)) {
1434                 DRM_ERROR("Cannot get hdmi_audio clock\n");
1435                 ret = PTR_ERR(hdmi->clk_audio);
1436                 goto release_adapter;
1437         }
1438
1439         hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
1440
1441         init_waitqueue_head(&hdmi->wait_event);
1442
1443         hdmi->irq = platform_get_irq_byname(pdev, "irq");
1444         if (hdmi->irq < 0) {
1445                 DRM_ERROR("Cannot get HDMI irq\n");
1446                 ret = hdmi->irq;
1447                 goto release_adapter;
1448         }
1449
1450         ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq,
1451                         hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi);
1452         if (ret) {
1453                 DRM_ERROR("Failed to register HDMI interrupt\n");
1454                 goto release_adapter;
1455         }
1456
1457         hdmi->reset = devm_reset_control_get(dev, "hdmi");
1458         /* Take hdmi out of reset */
1459         if (!IS_ERR(hdmi->reset))
1460                 reset_control_deassert(hdmi->reset);
1461
1462         platform_set_drvdata(pdev, hdmi);
1463
1464         return component_add(&pdev->dev, &sti_hdmi_ops);
1465
1466  release_adapter:
1467         i2c_put_adapter(hdmi->ddc_adapt);
1468
1469         return ret;
1470 }
1471
1472 static int sti_hdmi_remove(struct platform_device *pdev)
1473 {
1474         struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev);
1475
1476         i2c_put_adapter(hdmi->ddc_adapt);
1477         if (hdmi->audio_pdev)
1478                 platform_device_unregister(hdmi->audio_pdev);
1479         component_del(&pdev->dev, &sti_hdmi_ops);
1480
1481         return 0;
1482 }
1483
1484 struct platform_driver sti_hdmi_driver = {
1485         .driver = {
1486                 .name = "sti-hdmi",
1487                 .owner = THIS_MODULE,
1488                 .of_match_table = hdmi_of_match,
1489         },
1490         .probe = sti_hdmi_probe,
1491         .remove = sti_hdmi_remove,
1492 };
1493
1494 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1495 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1496 MODULE_LICENSE("GPL");