drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
   4  * Author: Andy Yan <andy.yan@rock-chips.com>
   5  */
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/delay.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/kernel.h>
  12 #include <linux/media-bus-format.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_graph.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <linux/swab.h>
  22
  23 #include <drm/drm.h>
  24 #include <drm/drm_atomic.h>
  25 #include <drm/drm_atomic_uapi.h>
  26 #include <drm/drm_blend.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_debugfs.h>
  29 #include <drm/drm_flip_work.h>
  30 #include <drm/drm_framebuffer.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/drm_vblank.h>
  33
  34 #include <uapi/linux/videodev2.h>
  35 #include <dt-bindings/soc/rockchip,vop2.h>
  36
  37 #include "rockchip_drm_drv.h"
  38 #include "rockchip_drm_gem.h"
  39 #include "rockchip_drm_fb.h"
  40 #include "rockchip_drm_vop2.h"
  41
  42 /*
  43  * VOP2 architecture
  44  *
  45  +----------+   +-------------+                                                        +-----------+
  46  |  Cluster |   | Sel 1 from 6|                                                        | 1 from 3  |
  47  |  window0 |   |    Layer0   |                                                        |    RGB    |
  48  +----------+   +-------------+              +---------------+    +-------------+      +-----------+
  49  +----------+   +-------------+              |N from 6 layers|    |             |
  50  |  Cluster |   | Sel 1 from 6|              |   Overlay0    +--->| Video Port0 |      +-----------+
  51  |  window1 |   |    Layer1   |              |               |    |             |      | 1 from 3  |
  52  +----------+   +-------------+              +---------------+    +-------------+      |   LVDS    |
  53  +----------+   +-------------+                                                        +-----------+
  54  |  Esmart  |   | Sel 1 from 6|
  55  |  window0 |   |   Layer2    |              +---------------+    +-------------+      +-----------+
  56  +----------+   +-------------+              |N from 6 Layers|    |             | +--> | 1 from 3  |
  57  +----------+   +-------------+   -------->  |   Overlay1    +--->| Video Port1 |      |   MIPI    |
  58  |  Esmart  |   | Sel 1 from 6|   -------->  |               |    |             |      +-----------+
  59  |  Window1 |   |   Layer3    |              +---------------+    +-------------+
  60  +----------+   +-------------+                                                        +-----------+
  61  +----------+   +-------------+                                                        | 1 from 3  |
  62  |  Smart   |   | Sel 1 from 6|              +---------------+    +-------------+      |   HDMI    |
  63  |  Window0 |   |    Layer4   |              |N from 6 Layers|    |             |      +-----------+
  64  +----------+   +-------------+              |   Overlay2    +--->| Video Port2 |
  65  +----------+   +-------------+              |               |    |             |      +-----------+
  66  |  Smart   |   | Sel 1 from 6|              +---------------+    +-------------+      |  1 from 3 |
  67  |  Window1 |   |    Layer5   |                                                        |    eDP    |
  68  +----------+   +-------------+                                                        +-----------+
  69  *
  70  */
  71
  72 enum vop2_data_format {
  73         VOP2_FMT_ARGB8888 = 0,
  74         VOP2_FMT_RGB888,
  75         VOP2_FMT_RGB565,
  76         VOP2_FMT_XRGB101010,
  77         VOP2_FMT_YUV420SP,
  78         VOP2_FMT_YUV422SP,
  79         VOP2_FMT_YUV444SP,
  80         VOP2_FMT_YUYV422 = 8,
  81         VOP2_FMT_YUYV420,
  82         VOP2_FMT_VYUY422,
  83         VOP2_FMT_VYUY420,
  84         VOP2_FMT_YUV420SP_TILE_8x4 = 0x10,
  85         VOP2_FMT_YUV420SP_TILE_16x2,
  86         VOP2_FMT_YUV422SP_TILE_8x4,
  87         VOP2_FMT_YUV422SP_TILE_16x2,
  88         VOP2_FMT_YUV420SP_10,
  89         VOP2_FMT_YUV422SP_10,
  90         VOP2_FMT_YUV444SP_10,
  91 };
  92
  93 enum vop2_afbc_format {
  94         VOP2_AFBC_FMT_RGB565,
  95         VOP2_AFBC_FMT_ARGB2101010 = 2,
  96         VOP2_AFBC_FMT_YUV420_10BIT,
  97         VOP2_AFBC_FMT_RGB888,
  98         VOP2_AFBC_FMT_ARGB8888,
  99         VOP2_AFBC_FMT_YUV420 = 9,
 100         VOP2_AFBC_FMT_YUV422 = 0xb,
 101         VOP2_AFBC_FMT_YUV422_10BIT = 0xe,
 102         VOP2_AFBC_FMT_INVALID = -1,
 103 };
 104
 105 union vop2_alpha_ctrl {
 106         u32 val;
 107         struct {
 108                 /* [0:1] */
 109                 u32 color_mode:1;
 110                 u32 alpha_mode:1;
 111                 /* [2:3] */
 112                 u32 blend_mode:2;
 113                 u32 alpha_cal_mode:1;
 114                 /* [5:7] */
 115                 u32 factor_mode:3;
 116                 /* [8:9] */
 117                 u32 alpha_en:1;
 118                 u32 src_dst_swap:1;
 119                 u32 reserved:6;
 120                 /* [16:23] */
 121                 u32 glb_alpha:8;
 122         } bits;
 123 };
 124
 125 struct vop2_alpha {
 126         union vop2_alpha_ctrl src_color_ctrl;
 127         union vop2_alpha_ctrl dst_color_ctrl;
 128         union vop2_alpha_ctrl src_alpha_ctrl;
 129         union vop2_alpha_ctrl dst_alpha_ctrl;
 130 };
 131
 132 struct vop2_alpha_config {
 133         bool src_premulti_en;
 134         bool dst_premulti_en;
 135         bool src_pixel_alpha_en;
 136         bool dst_pixel_alpha_en;
 137         u16 src_glb_alpha_value;
 138         u16 dst_glb_alpha_value;
 139 };
 140
 141 struct vop2_win {
 142         struct vop2 *vop2;
 143         struct drm_plane base;
 144         const struct vop2_win_data *data;
 145         struct regmap_field *reg[VOP2_WIN_MAX_REG];
 146
 147         /**
 148          * @win_id: graphic window id, a cluster may be split into two
 149          * graphics windows.
 150          */
 151         u8 win_id;
 152         u8 delay;
 153         u32 offset;
 154
 155         enum drm_plane_type type;
 156 };
 157
 158 struct vop2_video_port {
 159         struct drm_crtc crtc;
 160         struct vop2 *vop2;
 161         struct clk *dclk;
 162         unsigned int id;
 163         const struct vop2_video_port_regs *regs;
 164         const struct vop2_video_port_data *data;
 165
 166         struct completion dsp_hold_completion;
 167
 168         /**
 169          * @win_mask: Bitmask of windows attached to the video port;
 170          */
 171         u32 win_mask;
 172
 173         struct vop2_win *primary_plane;
 174         struct drm_pending_vblank_event *event;
 175
 176         unsigned int nlayers;
 177 };
 178
 179 struct vop2 {
 180         struct device *dev;
 181         struct drm_device *drm;
 182         struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
 183
 184         const struct vop2_data *data;
 185         /*
 186          * Number of windows that are registered as plane, may be less than the
 187          * total number of hardware windows.
 188          */
 189         u32 registered_num_wins;
 190
 191         void __iomem *regs;
 192         struct regmap *map;
 193
 194         struct regmap *grf;
 195
 196         /* physical map length of vop2 register */
 197         u32 len;
 198
 199         void __iomem *lut_regs;
 200
 201         /* protects crtc enable/disable */
 202         struct mutex vop2_lock;
 203
 204         int irq;
 205
 206         /*
 207          * Some global resources are shared between all video ports(crtcs), so
 208          * we need a ref counter here.
 209          */
 210         unsigned int enable_count;
 211         struct clk *hclk;
 212         struct clk *aclk;
 213
 214         /* must be put at the end of the struct */
 215         struct vop2_win win[];
 216 };
 217
 218 static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc)
 219 {
 220         return container_of(crtc, struct vop2_video_port, crtc);
 221 }
 222
 223 static struct vop2_win *to_vop2_win(struct drm_plane *p)
 224 {
 225         return container_of(p, struct vop2_win, base);
 226 }
 227
 228 static void vop2_lock(struct vop2 *vop2)
 229 {
 230         mutex_lock(&vop2->vop2_lock);
 231 }
 232
 233 static void vop2_unlock(struct vop2 *vop2)
 234 {
 235         mutex_unlock(&vop2->vop2_lock);
 236 }
 237
 238 static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
 239 {
 240         regmap_write(vop2->map, offset, v);
 241 }
 242
 243 static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v)
 244 {
 245         regmap_write(vp->vop2->map, vp->data->offset + offset, v);
 246 }
 247
 248 static u32 vop2_readl(struct vop2 *vop2, u32 offset)
 249 {
 250         u32 val;
 251
 252         regmap_read(vop2->map, offset, &val);
 253
 254         return val;
 255 }
 256
 257 static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v)
 258 {
 259         regmap_field_write(win->reg[reg], v);
 260 }
 261
 262 static bool vop2_cluster_window(const struct vop2_win *win)
 263 {
 264         return win->data->feature & WIN_FEATURE_CLUSTER;
 265 }
 266
 267 static void vop2_cfg_done(struct vop2_video_port *vp)
 268 {
 269         struct vop2 *vop2 = vp->vop2;
 270
 271         regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE,
 272                         BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
 273 }
 274
 275 static void vop2_win_disable(struct vop2_win *win)
 276 {
 277         vop2_win_write(win, VOP2_WIN_ENABLE, 0);
 278
 279         if (vop2_cluster_window(win))
 280                 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0);
 281 }
 282
 283 static enum vop2_data_format vop2_convert_format(u32 format)
 284 {
 285         switch (format) {
 286         case DRM_FORMAT_XRGB8888:
 287         case DRM_FORMAT_ARGB8888:
 288         case DRM_FORMAT_XBGR8888:
 289         case DRM_FORMAT_ABGR8888:
 290                 return VOP2_FMT_ARGB8888;
 291         case DRM_FORMAT_RGB888:
 292         case DRM_FORMAT_BGR888:
 293                 return VOP2_FMT_RGB888;
 294         case DRM_FORMAT_RGB565:
 295         case DRM_FORMAT_BGR565:
 296                 return VOP2_FMT_RGB565;
 297         case DRM_FORMAT_NV12:
 298                 return VOP2_FMT_YUV420SP;
 299         case DRM_FORMAT_NV16:
 300                 return VOP2_FMT_YUV422SP;
 301         case DRM_FORMAT_NV24:
 302                 return VOP2_FMT_YUV444SP;
 303         case DRM_FORMAT_YUYV:
 304         case DRM_FORMAT_YVYU:
 305                 return VOP2_FMT_VYUY422;
 306         case DRM_FORMAT_VYUY:
 307         case DRM_FORMAT_UYVY:
 308                 return VOP2_FMT_YUYV422;
 309         default:
 310                 DRM_ERROR("unsupported format[%08x]\n", format);
 311                 return -EINVAL;
 312         }
 313 }
 314
 315 static enum vop2_afbc_format vop2_convert_afbc_format(u32 format)
 316 {
 317         switch (format) {
 318         case DRM_FORMAT_XRGB8888:
 319         case DRM_FORMAT_ARGB8888:
 320         case DRM_FORMAT_XBGR8888:
 321         case DRM_FORMAT_ABGR8888:
 322                 return VOP2_AFBC_FMT_ARGB8888;
 323         case DRM_FORMAT_RGB888:
 324         case DRM_FORMAT_BGR888:
 325                 return VOP2_AFBC_FMT_RGB888;
 326         case DRM_FORMAT_RGB565:
 327         case DRM_FORMAT_BGR565:
 328                 return VOP2_AFBC_FMT_RGB565;
 329         case DRM_FORMAT_NV12:
 330                 return VOP2_AFBC_FMT_YUV420;
 331         case DRM_FORMAT_NV16:
 332                 return VOP2_AFBC_FMT_YUV422;
 333         default:
 334                 return VOP2_AFBC_FMT_INVALID;
 335         }
 336
 337         return VOP2_AFBC_FMT_INVALID;
 338 }
 339
 340 static bool vop2_win_rb_swap(u32 format)
 341 {
 342         switch (format) {
 343         case DRM_FORMAT_XBGR8888:
 344         case DRM_FORMAT_ABGR8888:
 345         case DRM_FORMAT_BGR888:
 346         case DRM_FORMAT_BGR565:
 347                 return true;
 348         default:
 349                 return false;
 350         }
 351 }
 352
 353 static bool vop2_afbc_rb_swap(u32 format)
 354 {
 355         switch (format) {
 356         case DRM_FORMAT_NV24:
 357                 return true;
 358         default:
 359                 return false;
 360         }
 361 }
 362
 363 static bool vop2_afbc_uv_swap(u32 format)
 364 {
 365         switch (format) {
 366         case DRM_FORMAT_NV12:
 367         case DRM_FORMAT_NV16:
 368                 return true;
 369         default:
 370                 return false;
 371         }
 372 }
 373
 374 static bool vop2_win_uv_swap(u32 format)
 375 {
 376         switch (format) {
 377         case DRM_FORMAT_NV12:
 378         case DRM_FORMAT_NV16:
 379         case DRM_FORMAT_NV24:
 380                 return true;
 381         default:
 382                 return false;
 383         }
 384 }
 385
 386 static bool vop2_win_dither_up(u32 format)
 387 {
 388         switch (format) {
 389         case DRM_FORMAT_BGR565:
 390         case DRM_FORMAT_RGB565:
 391                 return true;
 392         default:
 393                 return false;
 394         }
 395 }
 396
 397 static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode)
 398 {
 399         /*
 400          * FIXME:
 401          *
 402          * There is no media type for YUV444 output,
 403          * so when out_mode is AAAA or P888, assume output is YUV444 on
 404          * yuv format.
 405          *
 406          * From H/W testing, YUV444 mode need a rb swap.
 407          */
 408         if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 ||
 409             bus_format == MEDIA_BUS_FMT_VYUY8_1X16 ||
 410             bus_format == MEDIA_BUS_FMT_YVYU8_2X8 ||
 411             bus_format == MEDIA_BUS_FMT_VYUY8_2X8 ||
 412             ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
 413               bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
 414              (output_mode == ROCKCHIP_OUT_MODE_AAAA ||
 415               output_mode == ROCKCHIP_OUT_MODE_P888)))
 416                 return true;
 417         else
 418                 return false;
 419 }
 420
 421 static bool is_yuv_output(u32 bus_format)
 422 {
 423         switch (bus_format) {
 424         case MEDIA_BUS_FMT_YUV8_1X24:
 425         case MEDIA_BUS_FMT_YUV10_1X30:
 426         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 427         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 428         case MEDIA_BUS_FMT_YUYV8_2X8:
 429         case MEDIA_BUS_FMT_YVYU8_2X8:
 430         case MEDIA_BUS_FMT_UYVY8_2X8:
 431         case MEDIA_BUS_FMT_VYUY8_2X8:
 432         case MEDIA_BUS_FMT_YUYV8_1X16:
 433         case MEDIA_BUS_FMT_YVYU8_1X16:
 434         case MEDIA_BUS_FMT_UYVY8_1X16:
 435         case MEDIA_BUS_FMT_VYUY8_1X16:
 436                 return true;
 437         default:
 438                 return false;
 439         }
 440 }
 441
 442 static bool rockchip_afbc(struct drm_plane *plane, u64 modifier)
 443 {
 444         int i;
 445
 446         if (modifier == DRM_FORMAT_MOD_LINEAR)
 447                 return false;
 448
 449         for (i = 0 ; i < plane->modifier_count; i++)
 450                 if (plane->modifiers[i] == modifier)
 451                         return true;
 452
 453         return false;
 454 }
 455
 456 static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format,
 457                                         u64 modifier)
 458 {
 459         struct vop2_win *win = to_vop2_win(plane);
 460         struct vop2 *vop2 = win->vop2;
 461
 462         if (modifier == DRM_FORMAT_MOD_INVALID)
 463                 return false;
 464
 465         if (modifier == DRM_FORMAT_MOD_LINEAR)
 466                 return true;
 467
 468         if (!rockchip_afbc(plane, modifier)) {
 469                 drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n",
 470                         modifier);
 471
 472                 return false;
 473         }
 474
 475         return vop2_convert_afbc_format(format) >= 0;
 476 }
 477
 478 static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate,
 479                                       bool afbc_half_block_en)
 480 {
 481         struct drm_rect *src = &pstate->src;
 482         struct drm_framebuffer *fb = pstate->fb;
 483         u32 bpp = fb->format->cpp[0] * 8;
 484         u32 vir_width = (fb->pitches[0] << 3) / bpp;
 485         u32 width = drm_rect_width(src) >> 16;
 486         u32 height = drm_rect_height(src) >> 16;
 487         u32 act_xoffset = src->x1 >> 16;
 488         u32 act_yoffset = src->y1 >> 16;
 489         u32 align16_crop = 0;
 490         u32 align64_crop = 0;
 491         u32 height_tmp;
 492         u8 tx, ty;
 493         u8 bottom_crop_line_num = 0;
 494
 495         /* 16 pixel align */
 496         if (height & 0xf)
 497                 align16_crop = 16 - (height & 0xf);
 498
 499         height_tmp = height + align16_crop;
 500
 501         /* 64 pixel align */
 502         if (height_tmp & 0x3f)
 503                 align64_crop = 64 - (height_tmp & 0x3f);
 504
 505         bottom_crop_line_num = align16_crop + align64_crop;
 506
 507         switch (pstate->rotation &
 508                 (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y |
 509                  DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) {
 510         case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y:
 511                 tx = 16 - ((act_xoffset + width) & 0xf);
 512                 ty = bottom_crop_line_num - act_yoffset;
 513                 break;
 514         case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90:
 515                 tx = bottom_crop_line_num - act_yoffset;
 516                 ty = vir_width - width - act_xoffset;
 517                 break;
 518         case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270:
 519                 tx = act_yoffset;
 520                 ty = act_xoffset;
 521                 break;
 522         case DRM_MODE_REFLECT_X:
 523                 tx = 16 - ((act_xoffset + width) & 0xf);
 524                 ty = act_yoffset;
 525                 break;
 526         case DRM_MODE_REFLECT_Y:
 527                 tx = act_xoffset;
 528                 ty = bottom_crop_line_num - act_yoffset;
 529                 break;
 530         case DRM_MODE_ROTATE_90:
 531                 tx = bottom_crop_line_num - act_yoffset;
 532                 ty = act_xoffset;
 533                 break;
 534         case DRM_MODE_ROTATE_270:
 535                 tx = act_yoffset;
 536                 ty = vir_width - width - act_xoffset;
 537                 break;
 538         case 0:
 539                 tx = act_xoffset;
 540                 ty = act_yoffset;
 541                 break;
 542         }
 543
 544         if (afbc_half_block_en)
 545                 ty &= 0x7f;
 546
 547 #define TRANSFORM_XOFFSET GENMASK(7, 0)
 548 #define TRANSFORM_YOFFSET GENMASK(23, 16)
 549         return FIELD_PREP(TRANSFORM_XOFFSET, tx) |
 550                 FIELD_PREP(TRANSFORM_YOFFSET, ty);
 551 }
 552
 553 /*
 554  * A Cluster window has 2048 x 16 line buffer, which can
 555  * works at 2048 x 16(Full) or 4096 x 8 (Half) mode.
 556  * for Cluster_lb_mode register:
 557  * 0: half mode, for plane input width range 2048 ~ 4096
 558  * 1: half mode, for cluster work at 2 * 2048 plane mode
 559  * 2: half mode, for rotate_90/270 mode
 560  *
 561  */
 562 static int vop2_get_cluster_lb_mode(struct vop2_win *win,
 563                                     struct drm_plane_state *pstate)
 564 {
 565         if ((pstate->rotation & DRM_MODE_ROTATE_270) ||
 566             (pstate->rotation & DRM_MODE_ROTATE_90))
 567                 return 2;
 568         else
 569                 return 0;
 570 }
 571
 572 static u16 vop2_scale_factor(u32 src, u32 dst)
 573 {
 574         u32 fac;
 575         int shift;
 576
 577         if (src == dst)
 578                 return 0;
 579
 580         if (dst < 2)
 581                 return U16_MAX;
 582
 583         if (src < 2)
 584                 return 0;
 585
 586         if (src > dst)
 587                 shift = 12;
 588         else
 589                 shift = 16;
 590
 591         src--;
 592         dst--;
 593
 594         fac = DIV_ROUND_UP(src << shift, dst) - 1;
 595
 596         if (fac > U16_MAX)
 597                 return U16_MAX;
 598
 599         return fac;
 600 }
 601
 602 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
 603                              u32 src_w, u32 src_h, u32 dst_w,
 604                              u32 dst_h, u32 pixel_format)
 605 {
 606         const struct drm_format_info *info;
 607         u16 hor_scl_mode, ver_scl_mode;
 608         u16 hscl_filter_mode, vscl_filter_mode;
 609         u8 gt2 = 0;
 610         u8 gt4 = 0;
 611         u32 val;
 612
 613         info = drm_format_info(pixel_format);
 614
 615         if (src_h >= (4 * dst_h)) {
 616                 gt4 = 1;
 617                 src_h >>= 2;
 618         } else if (src_h >= (2 * dst_h)) {
 619                 gt2 = 1;
 620                 src_h >>= 1;
 621         }
 622
 623         hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 624         ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 625
 626         if (hor_scl_mode == SCALE_UP)
 627                 hscl_filter_mode = VOP2_SCALE_UP_BIC;
 628         else
 629                 hscl_filter_mode = VOP2_SCALE_DOWN_BIL;
 630
 631         if (ver_scl_mode == SCALE_UP)
 632                 vscl_filter_mode = VOP2_SCALE_UP_BIL;
 633         else
 634                 vscl_filter_mode = VOP2_SCALE_DOWN_BIL;
 635
 636         /*
 637          * RK3568 VOP Esmart/Smart dsp_w should be even pixel
 638          * at scale down mode
 639          */
 640         if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
 641                 if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) {
 642                         drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n",
 643                                 win->data->name, dst_w);
 644                         dst_w++;
 645                 }
 646         }
 647
 648         val = vop2_scale_factor(src_w, dst_w);
 649         vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val);
 650         val = vop2_scale_factor(src_h, dst_h);
 651         vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val);
 652
 653         vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4);
 654         vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2);
 655
 656         vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode);
 657         vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode);
 658
 659         if (vop2_cluster_window(win))
 660                 return;
 661
 662         vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode);
 663         vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode);
 664
 665         if (info->is_yuv) {
 666                 src_w /= info->hsub;
 667                 src_h /= info->vsub;
 668
 669                 gt4 = 0;
 670                 gt2 = 0;
 671
 672                 if (src_h >= (4 * dst_h)) {
 673                         gt4 = 1;
 674                         src_h >>= 2;
 675                 } else if (src_h >= (2 * dst_h)) {
 676                         gt2 = 1;
 677                         src_h >>= 1;
 678                 }
 679
 680                 hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 681                 ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 682
 683                 val = vop2_scale_factor(src_w, dst_w);
 684                 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val);
 685
 686                 val = vop2_scale_factor(src_h, dst_h);
 687                 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val);
 688
 689                 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4);
 690                 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2);
 691                 vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode);
 692                 vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode);
 693                 vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode);
 694                 vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode);
 695         }
 696 }
 697
 698 static int vop2_convert_csc_mode(int csc_mode)
 699 {
 700         switch (csc_mode) {
 701         case V4L2_COLORSPACE_SMPTE170M:
 702         case V4L2_COLORSPACE_470_SYSTEM_M:
 703         case V4L2_COLORSPACE_470_SYSTEM_BG:
 704                 return CSC_BT601L;
 705         case V4L2_COLORSPACE_REC709:
 706         case V4L2_COLORSPACE_SMPTE240M:
 707         case V4L2_COLORSPACE_DEFAULT:
 708                 return CSC_BT709L;
 709         case V4L2_COLORSPACE_JPEG:
 710                 return CSC_BT601F;
 711         case V4L2_COLORSPACE_BT2020:
 712                 return CSC_BT2020;
 713         default:
 714                 return CSC_BT709L;
 715         }
 716 }
 717
 718 /*
 719  * colorspace path:
 720  *      Input        Win csc                     Output
 721  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 722  *    RGB        --> R2Y                  __/
 723  *
 724  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 725  *    RGB        --> 709To2020->R2Y       __/
 726  *
 727  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 728  *    RGB        --> R2Y                  __/
 729  *
 730  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 731  *    RGB        --> 709To2020->R2Y       __/
 732  *
 733  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 734  *    RGB        --> R2Y                  __/
 735  *
 736  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 737  *    RGB        --> R2Y(601)             __/
 738  *
 739  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 740  *    RGB        --> bypass               __/
 741  *
 742  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 743  *
 744  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 745  *
 746  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 747  *
 748  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 749  */
 750
 751 static void vop2_setup_csc_mode(struct vop2_video_port *vp,
 752                                 struct vop2_win *win,
 753                                 struct drm_plane_state *pstate)
 754 {
 755         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
 756         int is_input_yuv = pstate->fb->format->is_yuv;
 757         int is_output_yuv = is_yuv_output(vcstate->bus_format);
 758         int input_csc = V4L2_COLORSPACE_DEFAULT;
 759         int output_csc = vcstate->color_space;
 760         bool r2y_en, y2r_en;
 761         int csc_mode;
 762
 763         if (is_input_yuv && !is_output_yuv) {
 764                 y2r_en = true;
 765                 r2y_en = false;
 766                 csc_mode = vop2_convert_csc_mode(input_csc);
 767         } else if (!is_input_yuv && is_output_yuv) {
 768                 y2r_en = false;
 769                 r2y_en = true;
 770                 csc_mode = vop2_convert_csc_mode(output_csc);
 771         } else {
 772                 y2r_en = false;
 773                 r2y_en = false;
 774                 csc_mode = false;
 775         }
 776
 777         vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en);
 778         vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en);
 779         vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode);
 780 }
 781
 782 static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq)
 783 {
 784         struct vop2 *vop2 = vp->vop2;
 785
 786         vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq);
 787         vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq);
 788 }
 789
 790 static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq)
 791 {
 792         struct vop2 *vop2 = vp->vop2;
 793
 794         vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16);
 795 }
 796
 797 static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
 798 {
 799         int ret;
 800
 801         ret = clk_prepare_enable(vop2->hclk);
 802         if (ret < 0) {
 803                 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret);
 804                 return ret;
 805         }
 806
 807         ret = clk_prepare_enable(vop2->aclk);
 808         if (ret < 0) {
 809                 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret);
 810                 goto err;
 811         }
 812
 813         return 0;
 814 err:
 815         clk_disable_unprepare(vop2->hclk);
 816
 817         return ret;
 818 }
 819
 820 static void vop2_enable(struct vop2 *vop2)
 821 {
 822         int ret;
 823
 824         ret = pm_runtime_resume_and_get(vop2->dev);
 825         if (ret < 0) {
 826                 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret);
 827                 return;
 828         }
 829
 830         ret = vop2_core_clks_prepare_enable(vop2);
 831         if (ret) {
 832                 pm_runtime_put_sync(vop2->dev);
 833                 return;
 834         }
 835
 836         ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev);
 837         if (ret) {
 838                 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret);
 839                 return;
 840         }
 841
 842         if (vop2->data->soc_id == 3566)
 843                 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
 844
 845         vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
 846
 847         /*
 848          * Disable auto gating, this is a workaround to
 849          * avoid display image shift when a window enabled.
 850          */
 851         regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL,
 852                           RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN);
 853
 854         vop2_writel(vop2, RK3568_SYS0_INT_CLR,
 855                     VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
 856         vop2_writel(vop2, RK3568_SYS0_INT_EN,
 857                     VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
 858         vop2_writel(vop2, RK3568_SYS1_INT_CLR,
 859                     VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
 860         vop2_writel(vop2, RK3568_SYS1_INT_EN,
 861                     VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
 862 }
 863
 864 static void vop2_disable(struct vop2 *vop2)
 865 {
 866         rockchip_drm_dma_detach_device(vop2->drm, vop2->dev);
 867
 868         pm_runtime_put_sync(vop2->dev);
 869
 870         clk_disable_unprepare(vop2->aclk);
 871         clk_disable_unprepare(vop2->hclk);
 872 }
 873
 874 static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
 875                                      struct drm_atomic_state *state)
 876 {
 877         struct vop2_video_port *vp = to_vop2_video_port(crtc);
 878         struct vop2 *vop2 = vp->vop2;
 879         struct drm_crtc_state *old_crtc_state;
 880         int ret;
 881
 882         vop2_lock(vop2);
 883
 884         old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
 885         drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
 886
 887         drm_crtc_vblank_off(crtc);
 888
 889         /*
 890          * Vop standby will take effect at end of current frame,
 891          * if dsp hold valid irq happen, it means standby complete.
 892          *
 893          * we must wait standby complete when we want to disable aclk,
 894          * if not, memory bus maybe dead.
 895          */
 896         reinit_completion(&vp->dsp_hold_completion);
 897
 898         vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID);
 899
 900         vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY);
 901
 902         ret = wait_for_completion_timeout(&vp->dsp_hold_completion,
 903                                           msecs_to_jiffies(50));
 904         if (!ret)
 905                 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id);
 906
 907         vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID);
 908
 909         clk_disable_unprepare(vp->dclk);
 910
 911         vop2->enable_count--;
 912
 913         if (!vop2->enable_count)
 914                 vop2_disable(vop2);
 915
 916         vop2_unlock(vop2);
 917
 918         if (crtc->state->event && !crtc->state->active) {
 919                 spin_lock_irq(&crtc->dev->event_lock);
 920                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 921                 spin_unlock_irq(&crtc->dev->event_lock);
 922
 923                 crtc->state->event = NULL;
 924         }
 925 }
 926
 927 static int vop2_plane_atomic_check(struct drm_plane *plane,
 928                                    struct drm_atomic_state *astate)
 929 {
 930         struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane);
 931         struct drm_framebuffer *fb = pstate->fb;
 932         struct drm_crtc *crtc = pstate->crtc;
 933         struct drm_crtc_state *cstate;
 934         struct vop2_video_port *vp;
 935         struct vop2 *vop2;
 936         const struct vop2_data *vop2_data;
 937         struct drm_rect *dest = &pstate->dst;
 938         struct drm_rect *src = &pstate->src;
 939         int min_scale = FRAC_16_16(1, 8);
 940         int max_scale = FRAC_16_16(8, 1);
 941         int format;
 942         int ret;
 943
 944         if (!crtc)
 945                 return 0;
 946
 947         vp = to_vop2_video_port(crtc);
 948         vop2 = vp->vop2;
 949         vop2_data = vop2->data;
 950
 951         cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc);
 952         if (WARN_ON(!cstate))
 953                 return -EINVAL;
 954
 955         ret = drm_atomic_helper_check_plane_state(pstate, cstate,
 956                                                   min_scale, max_scale,
 957                                                   true, true);
 958         if (ret)
 959                 return ret;
 960
 961         if (!pstate->visible)
 962                 return 0;
 963
 964         format = vop2_convert_format(fb->format->format);
 965         if (format < 0)
 966                 return format;
 967
 968         if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 ||
 969             drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) {
 970                 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n",
 971                         drm_rect_width(src) >> 16, drm_rect_height(src) >> 16,
 972                         drm_rect_width(dest), drm_rect_height(dest));
 973                 pstate->visible = false;
 974                 return 0;
 975         }
 976
 977         if (drm_rect_width(src) >> 16 > vop2_data->max_input.width ||
 978             drm_rect_height(src) >> 16 > vop2_data->max_input.height) {
 979                 drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n",
 980                         drm_rect_width(src) >> 16,
 981                         drm_rect_height(src) >> 16,
 982                         vop2_data->max_input.width,
 983                         vop2_data->max_input.height);
 984                 return -EINVAL;
 985         }
 986
 987         /*
 988          * Src.x1 can be odd when do clip, but yuv plane start point
 989          * need align with 2 pixel.
 990          */
 991         if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) {
 992                 drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n");
 993                 return -EINVAL;
 994         }
 995
 996         return 0;
 997 }
 998
 999 static void vop2_plane_atomic_disable(struct drm_plane *plane,
1000                                       struct drm_atomic_state *state)
1001 {
1002         struct drm_plane_state *old_pstate = NULL;
1003         struct vop2_win *win = to_vop2_win(plane);
1004         struct vop2 *vop2 = win->vop2;
1005
1006         drm_dbg(vop2->drm, "%s disable\n", win->data->name);
1007
1008         if (state)
1009                 old_pstate = drm_atomic_get_old_plane_state(state, plane);
1010         if (old_pstate && !old_pstate->crtc)
1011                 return;
1012
1013         vop2_win_disable(win);
1014         vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0);
1015 }
1016
1017 /*
1018  * The color key is 10 bit, so all format should
1019  * convert to 10 bit here.
1020  */
1021 static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key)
1022 {
1023         struct drm_plane_state *pstate = plane->state;
1024         struct drm_framebuffer *fb = pstate->fb;
1025         struct vop2_win *win = to_vop2_win(plane);
1026         u32 color_key_en = 0;
1027         u32 r = 0;
1028         u32 g = 0;
1029         u32 b = 0;
1030
1031         if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) {
1032                 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0);
1033                 return;
1034         }
1035
1036         switch (fb->format->format) {
1037         case DRM_FORMAT_RGB565:
1038         case DRM_FORMAT_BGR565:
1039                 r = (color_key & 0xf800) >> 11;
1040                 g = (color_key & 0x7e0) >> 5;
1041                 b = (color_key & 0x1f);
1042                 r <<= 5;
1043                 g <<= 4;
1044                 b <<= 5;
1045                 color_key_en = 1;
1046                 break;
1047         case DRM_FORMAT_XRGB8888:
1048         case DRM_FORMAT_ARGB8888:
1049         case DRM_FORMAT_XBGR8888:
1050         case DRM_FORMAT_ABGR8888:
1051         case DRM_FORMAT_RGB888:
1052         case DRM_FORMAT_BGR888:
1053                 r = (color_key & 0xff0000) >> 16;
1054                 g = (color_key & 0xff00) >> 8;
1055                 b = (color_key & 0xff);
1056                 r <<= 2;
1057                 g <<= 2;
1058                 b <<= 2;
1059                 color_key_en = 1;
1060                 break;
1061         }
1062
1063         vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en);
1064         vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b);
1065 }
1066
1067 static void vop2_plane_atomic_update(struct drm_plane *plane,
1068                                      struct drm_atomic_state *state)
1069 {
1070         struct drm_plane_state *pstate = plane->state;
1071         struct drm_crtc *crtc = pstate->crtc;
1072         struct vop2_win *win = to_vop2_win(plane);
1073         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1074         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1075         struct vop2 *vop2 = win->vop2;
1076         struct drm_framebuffer *fb = pstate->fb;
1077         u32 bpp = fb->format->cpp[0] * 8;
1078         u32 actual_w, actual_h, dsp_w, dsp_h;
1079         u32 act_info, dsp_info;
1080         u32 format;
1081         u32 afbc_format;
1082         u32 rb_swap;
1083         u32 uv_swap;
1084         struct drm_rect *src = &pstate->src;
1085         struct drm_rect *dest = &pstate->dst;
1086         u32 afbc_tile_num;
1087         u32 transform_offset;
1088         bool dither_up;
1089         bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false;
1090         bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false;
1091         bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270;
1092         bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90;
1093         struct rockchip_gem_object *rk_obj;
1094         unsigned long offset;
1095         bool afbc_en;
1096         dma_addr_t yrgb_mst;
1097         dma_addr_t uv_mst;
1098
1099         /*
1100          * can't update plane when vop2 is disabled.
1101          */
1102         if (WARN_ON(!crtc))
1103                 return;
1104
1105         if (!pstate->visible) {
1106                 vop2_plane_atomic_disable(plane, state);
1107                 return;
1108         }
1109
1110         afbc_en = rockchip_afbc(plane, fb->modifier);
1111
1112         offset = (src->x1 >> 16) * fb->format->cpp[0];
1113
1114         /*
1115          * AFBC HDR_PTR must set to the zero offset of the framebuffer.
1116          */
1117         if (afbc_en)
1118                 offset = 0;
1119         else if (pstate->rotation & DRM_MODE_REFLECT_Y)
1120                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1121         else
1122                 offset += (src->y1 >> 16) * fb->pitches[0];
1123
1124         rk_obj = to_rockchip_obj(fb->obj[0]);
1125
1126         yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
1127         if (fb->format->is_yuv) {
1128                 int hsub = fb->format->hsub;
1129                 int vsub = fb->format->vsub;
1130
1131                 offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub;
1132                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1133
1134                 if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en)
1135                         offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub;
1136
1137                 rk_obj = to_rockchip_obj(fb->obj[0]);
1138                 uv_mst = rk_obj->dma_addr + offset + fb->offsets[1];
1139         }
1140
1141         actual_w = drm_rect_width(src) >> 16;
1142         actual_h = drm_rect_height(src) >> 16;
1143         dsp_w = drm_rect_width(dest);
1144
1145         if (dest->x1 + dsp_w > adjusted_mode->hdisplay) {
1146                 drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
1147                         vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay);
1148                 dsp_w = adjusted_mode->hdisplay - dest->x1;
1149                 if (dsp_w < 4)
1150                         dsp_w = 4;
1151                 actual_w = dsp_w * actual_w / drm_rect_width(dest);
1152         }
1153
1154         dsp_h = drm_rect_height(dest);
1155
1156         if (dest->y1 + dsp_h > adjusted_mode->vdisplay) {
1157                 drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
1158                         vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay);
1159                 dsp_h = adjusted_mode->vdisplay - dest->y1;
1160                 if (dsp_h < 4)
1161                         dsp_h = 4;
1162                 actual_h = dsp_h * actual_h / drm_rect_height(dest);
1163         }
1164
1165         /*
1166          * This is workaround solution for IC design:
1167          * esmart can't support scale down when actual_w % 16 == 1.
1168          */
1169         if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
1170                 if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
1171                         drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n",
1172                                 vp->id, win->data->name, actual_w);
1173                         actual_w -= 1;
1174                 }
1175         }
1176
1177         if (afbc_en && actual_w % 4) {
1178                 drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n",
1179                         vp->id, win->data->name, actual_w);
1180                 actual_w = ALIGN_DOWN(actual_w, 4);
1181         }
1182
1183         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1184         dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff);
1185
1186         format = vop2_convert_format(fb->format->format);
1187
1188         drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n",
1189                 vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h,
1190                 dest->x1, dest->y1,
1191                 &fb->format->format,
1192                 afbc_en ? "AFBC" : "", &yrgb_mst);
1193
1194         if (afbc_en) {
1195                 u32 stride;
1196
1197                 /* the afbc superblock is 16 x 16 */
1198                 afbc_format = vop2_convert_afbc_format(fb->format->format);
1199
1200                 /* Enable color transform for YTR */
1201                 if (fb->modifier & AFBC_FORMAT_MOD_YTR)
1202                         afbc_format |= (1 << 4);
1203
1204                 afbc_tile_num = ALIGN(actual_w, 16) >> 4;
1205
1206                 /*
1207                  * AFBC pic_vir_width is count by pixel, this is different
1208                  * with WIN_VIR_STRIDE.
1209                  */
1210                 stride = (fb->pitches[0] << 3) / bpp;
1211                 if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270))
1212                         drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n",
1213                                 vp->id, win->data->name, stride);
1214
1215                 rb_swap = vop2_afbc_rb_swap(fb->format->format);
1216                 uv_swap = vop2_afbc_uv_swap(fb->format->format);
1217                 /*
1218                  * This is a workaround for crazy IC design, Cluster
1219                  * and Esmart/Smart use different format configuration map:
1220                  * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart.
1221                  *
1222                  * This is one thing we can make the convert simple:
1223                  * AFBCD decode all the YUV data to YUV444. So we just
1224                  * set all the yuv 10 bit to YUV444_10.
1225                  */
1226                 if (fb->format->is_yuv && bpp == 10)
1227                         format = VOP2_CLUSTER_YUV444_10;
1228
1229                 if (vop2_cluster_window(win))
1230                         vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1);
1231                 vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format);
1232                 vop2_win_write(win, VOP2_WIN_AFBC_RB_SWAP, rb_swap);
1233                 vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap);
1234                 vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0);
1235                 vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0);
1236                 if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) {
1237                         vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 0);
1238                         transform_offset = vop2_afbc_transform_offset(pstate, false);
1239                 } else {
1240                         vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 1);
1241                         transform_offset = vop2_afbc_transform_offset(pstate, true);
1242                 }
1243                 vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst);
1244                 vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info);
1245                 vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset);
1246                 vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1));
1247                 vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16)));
1248                 vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride);
1249                 vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num);
1250                 vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror);
1251                 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270);
1252                 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90);
1253         } else {
1254                 vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4));
1255         }
1256
1257         vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror);
1258
1259         if (rotate_90 || rotate_270) {
1260                 act_info = swahw32(act_info);
1261                 actual_w = drm_rect_height(src) >> 16;
1262                 actual_h = drm_rect_width(src) >> 16;
1263         }
1264
1265         vop2_win_write(win, VOP2_WIN_FORMAT, format);
1266         vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst);
1267
1268         rb_swap = vop2_win_rb_swap(fb->format->format);
1269         vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap);
1270         if (!vop2_cluster_window(win)) {
1271                 uv_swap = vop2_win_uv_swap(fb->format->format);
1272                 vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap);
1273         }
1274
1275         if (fb->format->is_yuv) {
1276                 vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4));
1277                 vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst);
1278         }
1279
1280         vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format);
1281         if (!vop2_cluster_window(win))
1282                 vop2_plane_setup_color_key(plane, 0);
1283         vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info);
1284         vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info);
1285         vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff));
1286
1287         vop2_setup_csc_mode(vp, win, pstate);
1288
1289         dither_up = vop2_win_dither_up(fb->format->format);
1290         vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up);
1291
1292         vop2_win_write(win, VOP2_WIN_ENABLE, 1);
1293
1294         if (vop2_cluster_window(win)) {
1295                 int lb_mode = vop2_get_cluster_lb_mode(win, pstate);
1296
1297                 vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode);
1298                 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1);
1299         }
1300 }
1301
1302 static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = {
1303         .atomic_check = vop2_plane_atomic_check,
1304         .atomic_update = vop2_plane_atomic_update,
1305         .atomic_disable = vop2_plane_atomic_disable,
1306 };
1307
1308 static const struct drm_plane_funcs vop2_plane_funcs = {
1309         .update_plane   = drm_atomic_helper_update_plane,
1310         .disable_plane  = drm_atomic_helper_disable_plane,
1311         .destroy = drm_plane_cleanup,
1312         .reset = drm_atomic_helper_plane_reset,
1313         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1314         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1315         .format_mod_supported = rockchip_vop2_mod_supported,
1316 };
1317
1318 static int vop2_crtc_enable_vblank(struct drm_crtc *crtc)
1319 {
1320         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1321
1322         vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD);
1323
1324         return 0;
1325 }
1326
1327 static void vop2_crtc_disable_vblank(struct drm_crtc *crtc)
1328 {
1329         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1330
1331         vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD);
1332 }
1333
1334 static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
1335                                  const struct drm_display_mode *mode,
1336                                  struct drm_display_mode *adj_mode)
1337 {
1338         drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V |
1339                                         CRTC_STEREO_DOUBLE);
1340
1341         return true;
1342 }
1343
1344 static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl)
1345 {
1346         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1347
1348         switch (vcstate->bus_format) {
1349         case MEDIA_BUS_FMT_RGB565_1X16:
1350                 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN;
1351                 break;
1352         case MEDIA_BUS_FMT_RGB666_1X18:
1353         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1354         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
1355                 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN;
1356                 *dsp_ctrl |= RGB888_TO_RGB666;
1357                 break;
1358         case MEDIA_BUS_FMT_YUV8_1X24:
1359         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1360                 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN;
1361                 break;
1362         default:
1363                 break;
1364         }
1365
1366         if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA)
1367                 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN;
1368
1369         *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL,
1370                                 DITHER_DOWN_ALLEGRO);
1371 }
1372
1373 static void vop2_post_config(struct drm_crtc *crtc)
1374 {
1375         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1376         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1377         u16 vtotal = mode->crtc_vtotal;
1378         u16 hdisplay = mode->crtc_hdisplay;
1379         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1380         u16 vdisplay = mode->crtc_vdisplay;
1381         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1382         u32 left_margin = 100, right_margin = 100;
1383         u32 top_margin = 100, bottom_margin = 100;
1384         u16 hsize = hdisplay * (left_margin + right_margin) / 200;
1385         u16 vsize = vdisplay * (top_margin + bottom_margin) / 200;
1386         u16 hact_end, vact_end;
1387         u32 val;
1388
1389         vsize = rounddown(vsize, 2);
1390         hsize = rounddown(hsize, 2);
1391         hact_st += hdisplay * (100 - left_margin) / 200;
1392         hact_end = hact_st + hsize;
1393         val = hact_st << 16;
1394         val |= hact_end;
1395         vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val);
1396         vact_st += vdisplay * (100 - top_margin) / 200;
1397         vact_end = vact_st + vsize;
1398         val = vact_st << 16;
1399         val |= vact_end;
1400         vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val);
1401         val = scl_cal_scale2(vdisplay, vsize) << 16;
1402         val |= scl_cal_scale2(hdisplay, hsize);
1403         vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val);
1404
1405         val = 0;
1406         if (hdisplay != hsize)
1407                 val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN;
1408         if (vdisplay != vsize)
1409                 val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN;
1410         vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val);
1411
1412         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1413                 u16 vact_st_f1 = vtotal + vact_st + 1;
1414                 u16 vact_end_f1 = vact_st_f1 + vsize;
1415
1416                 val = vact_st_f1 << 16 | vact_end_f1;
1417                 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val);
1418         }
1419
1420         vop2_vp_write(vp, RK3568_VP_DSP_BG, 0);
1421 }
1422
1423 static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id,
1424                                 u32 polflags)
1425 {
1426         struct vop2 *vop2 = vp->vop2;
1427         u32 die, dip;
1428
1429         die = vop2_readl(vop2, RK3568_DSP_IF_EN);
1430         dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
1431
1432         switch (id) {
1433         case ROCKCHIP_VOP2_EP_RGB0:
1434                 die &= ~RK3568_SYS_DSP_INFACE_EN_RGB_MUX;
1435                 die |= RK3568_SYS_DSP_INFACE_EN_RGB |
1436                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id);
1437                 if (polflags & POLFLAG_DCLK_INV)
1438                         regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3));
1439                 else
1440                         regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16));
1441                 break;
1442         case ROCKCHIP_VOP2_EP_HDMI0:
1443                 die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX;
1444                 die |= RK3568_SYS_DSP_INFACE_EN_HDMI |
1445                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id);
1446                 dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL;
1447                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags);
1448                 break;
1449         case ROCKCHIP_VOP2_EP_EDP0:
1450                 die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX;
1451                 die |= RK3568_SYS_DSP_INFACE_EN_EDP |
1452                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id);
1453                 dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL;
1454                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags);
1455                 break;
1456         case ROCKCHIP_VOP2_EP_MIPI0:
1457                 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX;
1458                 die |= RK3568_SYS_DSP_INFACE_EN_MIPI0 |
1459                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id);
1460                 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL;
1461                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags);
1462                 break;
1463         case ROCKCHIP_VOP2_EP_MIPI1:
1464                 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX;
1465                 die |= RK3568_SYS_DSP_INFACE_EN_MIPI1 |
1466                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id);
1467                 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL;
1468                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags);
1469                 break;
1470         case ROCKCHIP_VOP2_EP_LVDS0:
1471                 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX;
1472                 die |= RK3568_SYS_DSP_INFACE_EN_LVDS0 |
1473                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id);
1474                 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1475                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1476                 break;
1477         case ROCKCHIP_VOP2_EP_LVDS1:
1478                 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX;
1479                 die |= RK3568_SYS_DSP_INFACE_EN_LVDS1 |
1480                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id);
1481                 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1482                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1483                 break;
1484         default:
1485                 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1486                 return;
1487         }
1488
1489         dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD;
1490
1491         vop2_writel(vop2, RK3568_DSP_IF_EN, die);
1492         vop2_writel(vop2, RK3568_DSP_IF_POL, dip);
1493 }
1494
1495 static int us_to_vertical_line(struct drm_display_mode *mode, int us)
1496 {
1497         return us * mode->clock / mode->htotal / 1000;
1498 }
1499
1500 static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
1501                                     struct drm_atomic_state *state)
1502 {
1503         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1504         struct vop2 *vop2 = vp->vop2;
1505         const struct vop2_data *vop2_data = vop2->data;
1506         const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
1507         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1508         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1509         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1510         unsigned long clock = mode->crtc_clock * 1000;
1511         u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
1512         u16 hdisplay = mode->crtc_hdisplay;
1513         u16 htotal = mode->crtc_htotal;
1514         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1515         u16 hact_end = hact_st + hdisplay;
1516         u16 vdisplay = mode->crtc_vdisplay;
1517         u16 vtotal = mode->crtc_vtotal;
1518         u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
1519         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1520         u16 vact_end = vact_st + vdisplay;
1521         u8 out_mode;
1522         u32 dsp_ctrl = 0;
1523         int act_end;
1524         u32 val, polflags;
1525         int ret;
1526         struct drm_encoder *encoder;
1527
1528         drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
1529                 hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
1530                 drm_mode_vrefresh(mode), vcstate->output_type, vp->id);
1531
1532         vop2_lock(vop2);
1533
1534         ret = clk_prepare_enable(vp->dclk);
1535         if (ret < 0) {
1536                 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",
1537                         vp->id, ret);
1538                 vop2_unlock(vop2);
1539                 return;
1540         }
1541
1542         if (!vop2->enable_count)
1543                 vop2_enable(vop2);
1544
1545         vop2->enable_count++;
1546
1547         vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY);
1548
1549         polflags = 0;
1550         if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
1551                 polflags |= POLFLAG_DCLK_INV;
1552         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1553                 polflags |= BIT(HSYNC_POSITIVE);
1554         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1555                 polflags |= BIT(VSYNC_POSITIVE);
1556
1557         drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
1558                 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
1559
1560                 rk3568_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags);
1561         }
1562
1563         if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1564             !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1565                 out_mode = ROCKCHIP_OUT_MODE_P888;
1566         else
1567                 out_mode = vcstate->output_mode;
1568
1569         dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode);
1570
1571         if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))
1572                 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP;
1573
1574         if (is_yuv_output(vcstate->bus_format))
1575                 dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y;
1576
1577         vop2_dither_setup(crtc, &dsp_ctrl);
1578
1579         vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len);
1580         val = hact_st << 16;
1581         val |= hact_end;
1582         vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val);
1583
1584         val = vact_st << 16;
1585         val |= vact_end;
1586         vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val);
1587
1588         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1589                 u16 vact_st_f1 = vtotal + vact_st + 1;
1590                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1591
1592                 val = vact_st_f1 << 16 | vact_end_f1;
1593                 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val);
1594
1595                 val = vtotal << 16 | (vtotal + vsync_len);
1596                 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val);
1597                 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE;
1598                 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL;
1599                 dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN;
1600                 vtotal += vtotal + 1;
1601                 act_end = vact_end_f1;
1602         } else {
1603                 act_end = vact_end;
1604         }
1605
1606         vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id),
1607                     (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end);
1608
1609         vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len);
1610
1611         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1612                 dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV;
1613                 clock *= 2;
1614         }
1615
1616         vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
1617
1618         clk_set_rate(vp->dclk, clock);
1619
1620         vop2_post_config(crtc);
1621
1622         vop2_cfg_done(vp);
1623
1624         vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
1625
1626         drm_crtc_vblank_on(crtc);
1627
1628         vop2_unlock(vop2);
1629 }
1630
1631 static int vop2_crtc_atomic_check(struct drm_crtc *crtc,
1632                                   struct drm_atomic_state *state)
1633 {
1634         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1635         struct drm_plane *plane;
1636         int nplanes = 0;
1637         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1638
1639         drm_atomic_crtc_state_for_each_plane(plane, crtc_state)
1640                 nplanes++;
1641
1642         if (nplanes > vp->nlayers)
1643                 return -EINVAL;
1644
1645         return 0;
1646 }
1647
1648 static bool is_opaque(u16 alpha)
1649 {
1650         return (alpha >> 8) == 0xff;
1651 }
1652
1653 static void vop2_parse_alpha(struct vop2_alpha_config *alpha_config,
1654                              struct vop2_alpha *alpha)
1655 {
1656         int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1;
1657         int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1;
1658         int src_color_mode = alpha_config->src_premulti_en ?
1659                                 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL;
1660         int dst_color_mode = alpha_config->dst_premulti_en ?
1661                                 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL;
1662
1663         alpha->src_color_ctrl.val = 0;
1664         alpha->dst_color_ctrl.val = 0;
1665         alpha->src_alpha_ctrl.val = 0;
1666         alpha->dst_alpha_ctrl.val = 0;
1667
1668         if (!alpha_config->src_pixel_alpha_en)
1669                 alpha->src_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
1670         else if (alpha_config->src_pixel_alpha_en && !src_glb_alpha_en)
1671                 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX;
1672         else
1673                 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
1674
1675         alpha->src_color_ctrl.bits.alpha_en = 1;
1676
1677         if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_GLOBAL) {
1678                 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
1679                 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
1680         } else if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_PER_PIX) {
1681                 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
1682                 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_ONE;
1683         } else {
1684                 alpha->src_color_ctrl.bits.color_mode = ALPHA_SRC_PRE_MUL;
1685                 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
1686         }
1687         alpha->src_color_ctrl.bits.glb_alpha = alpha_config->src_glb_alpha_value >> 8;
1688         alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1689         alpha->src_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1690
1691         alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1692         alpha->dst_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1693         alpha->dst_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
1694         alpha->dst_color_ctrl.bits.glb_alpha = alpha_config->dst_glb_alpha_value >> 8;
1695         alpha->dst_color_ctrl.bits.color_mode = dst_color_mode;
1696         alpha->dst_color_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
1697
1698         alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1699         alpha->src_alpha_ctrl.bits.blend_mode = alpha->src_color_ctrl.bits.blend_mode;
1700         alpha->src_alpha_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1701         alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE;
1702
1703         alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1704         if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en)
1705                 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX;
1706         else
1707                 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
1708         alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION;
1709         alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
1710 }
1711
1712 static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id)
1713 {
1714         struct vop2_video_port *vp;
1715         int used_layer = 0;
1716         int i;
1717
1718         for (i = 0; i < port_id; i++) {
1719                 vp = &vop2->vps[i];
1720                 used_layer += hweight32(vp->win_mask);
1721         }
1722
1723         return used_layer;
1724 }
1725
1726 static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win)
1727 {
1728         u32 offset = (main_win->data->phys_id * 0x10);
1729         struct vop2_alpha_config alpha_config;
1730         struct vop2_alpha alpha;
1731         struct drm_plane_state *bottom_win_pstate;
1732         bool src_pixel_alpha_en = false;
1733         u16 src_glb_alpha_val, dst_glb_alpha_val;
1734         bool premulti_en = false;
1735         bool swap = false;
1736
1737         /* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */
1738         bottom_win_pstate = main_win->base.state;
1739         src_glb_alpha_val = 0;
1740         dst_glb_alpha_val = main_win->base.state->alpha;
1741
1742         if (!bottom_win_pstate->fb)
1743                 return;
1744
1745         alpha_config.src_premulti_en = premulti_en;
1746         alpha_config.dst_premulti_en = false;
1747         alpha_config.src_pixel_alpha_en = src_pixel_alpha_en;
1748         alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
1749         alpha_config.src_glb_alpha_value = src_glb_alpha_val;
1750         alpha_config.dst_glb_alpha_value = dst_glb_alpha_val;
1751         vop2_parse_alpha(&alpha_config, &alpha);
1752
1753         alpha.src_color_ctrl.bits.src_dst_swap = swap;
1754         vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset,
1755                     alpha.src_color_ctrl.val);
1756         vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset,
1757                     alpha.dst_color_ctrl.val);
1758         vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset,
1759                     alpha.src_alpha_ctrl.val);
1760         vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset,
1761                     alpha.dst_alpha_ctrl.val);
1762 }
1763
1764 static void vop2_setup_alpha(struct vop2_video_port *vp)
1765 {
1766         struct vop2 *vop2 = vp->vop2;
1767         struct drm_framebuffer *fb;
1768         struct vop2_alpha_config alpha_config;
1769         struct vop2_alpha alpha;
1770         struct drm_plane *plane;
1771         int pixel_alpha_en;
1772         int premulti_en, gpremulti_en = 0;
1773         int mixer_id;
1774         u32 offset;
1775         bool bottom_layer_alpha_en = false;
1776         u32 dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE;
1777
1778         mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
1779         alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
1780
1781         drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1782                 struct vop2_win *win = to_vop2_win(plane);
1783
1784                 if (plane->state->normalized_zpos == 0 &&
1785                     !is_opaque(plane->state->alpha) &&
1786                     !vop2_cluster_window(win)) {
1787                         /*
1788                          * If bottom layer have global alpha effect [except cluster layer,
1789                          * because cluster have deal with bottom layer global alpha value
1790                          * at cluster mix], bottom layer mix need deal with global alpha.
1791                          */
1792                         bottom_layer_alpha_en = true;
1793                         dst_global_alpha = plane->state->alpha;
1794                 }
1795         }
1796
1797         drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1798                 struct vop2_win *win = to_vop2_win(plane);
1799                 int zpos = plane->state->normalized_zpos;
1800
1801                 if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
1802                         premulti_en = 1;
1803                 else
1804                         premulti_en = 0;
1805
1806                 plane = &win->base;
1807                 fb = plane->state->fb;
1808
1809                 pixel_alpha_en = fb->format->has_alpha;
1810
1811                 alpha_config.src_premulti_en = premulti_en;
1812
1813                 if (bottom_layer_alpha_en && zpos == 1) {
1814                         gpremulti_en = premulti_en;
1815                         /* Cd = Cs + (1 - As) * Cd * Agd */
1816                         alpha_config.dst_premulti_en = false;
1817                         alpha_config.src_pixel_alpha_en = pixel_alpha_en;
1818                         alpha_config.src_glb_alpha_value = plane->state->alpha;
1819                         alpha_config.dst_glb_alpha_value = dst_global_alpha;
1820                 } else if (vop2_cluster_window(win)) {
1821                         /* Mix output data only have pixel alpha */
1822                         alpha_config.dst_premulti_en = true;
1823                         alpha_config.src_pixel_alpha_en = true;
1824                         alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1825                         alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1826                 } else {
1827                         /* Cd = Cs + (1 - As) * Cd */
1828                         alpha_config.dst_premulti_en = true;
1829                         alpha_config.src_pixel_alpha_en = pixel_alpha_en;
1830                         alpha_config.src_glb_alpha_value = plane->state->alpha;
1831                         alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1832                 }
1833
1834                 vop2_parse_alpha(&alpha_config, &alpha);
1835
1836                 offset = (mixer_id + zpos - 1) * 0x10;
1837                 vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset,
1838                             alpha.src_color_ctrl.val);
1839                 vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset,
1840                             alpha.dst_color_ctrl.val);
1841                 vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset,
1842                             alpha.src_alpha_ctrl.val);
1843                 vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset,
1844                             alpha.dst_alpha_ctrl.val);
1845         }
1846
1847         if (vp->id == 0) {
1848                 if (bottom_layer_alpha_en) {
1849                         /* Transfer pixel alpha to hdr mix */
1850                         alpha_config.src_premulti_en = gpremulti_en;
1851                         alpha_config.dst_premulti_en = true;
1852                         alpha_config.src_pixel_alpha_en = true;
1853                         alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1854                         alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1855                         vop2_parse_alpha(&alpha_config, &alpha);
1856
1857                         vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL,
1858                                     alpha.src_color_ctrl.val);
1859                         vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL,
1860                                     alpha.dst_color_ctrl.val);
1861                         vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL,
1862                                     alpha.src_alpha_ctrl.val);
1863                         vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL,
1864                                     alpha.dst_alpha_ctrl.val);
1865                 } else {
1866                         vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0);
1867                 }
1868         }
1869 }
1870
1871 static void vop2_setup_layer_mixer(struct vop2_video_port *vp)
1872 {
1873         struct vop2 *vop2 = vp->vop2;
1874         struct drm_plane *plane;
1875         u32 layer_sel = 0;
1876         u32 port_sel;
1877         unsigned int nlayer, ofs;
1878         struct drm_display_mode *adjusted_mode;
1879         u16 hsync_len;
1880         u16 hdisplay;
1881         u32 bg_dly;
1882         u32 pre_scan_dly;
1883         int i;
1884         struct vop2_video_port *vp0 = &vop2->vps[0];
1885         struct vop2_video_port *vp1 = &vop2->vps[1];
1886         struct vop2_video_port *vp2 = &vop2->vps[2];
1887
1888         adjusted_mode = &vp->crtc.state->adjusted_mode;
1889         hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1890         hdisplay = adjusted_mode->crtc_hdisplay;
1891
1892         bg_dly = vp->data->pre_scan_max_dly[3];
1893         vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
1894                     FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly));
1895
1896         pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
1897         vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);
1898
1899         vop2_writel(vop2, RK3568_OVL_CTRL, 0);
1900         port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL);
1901         port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT;
1902
1903         if (vp0->nlayers)
1904                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX,
1905                                      vp0->nlayers - 1);
1906         else
1907                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 8);
1908
1909         if (vp1->nlayers)
1910                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX,
1911                                      (vp0->nlayers + vp1->nlayers - 1));
1912         else
1913                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8);
1914
1915         if (vp2->nlayers)
1916                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX,
1917                         (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1));
1918         else
1919                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8);
1920
1921         layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
1922
1923         ofs = 0;
1924         for (i = 0; i < vp->id; i++)
1925                 ofs += vop2->vps[i].nlayers;
1926
1927         nlayer = 0;
1928         drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1929                 struct vop2_win *win = to_vop2_win(plane);
1930
1931                 switch (win->data->phys_id) {
1932                 case ROCKCHIP_VOP2_CLUSTER0:
1933                         port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0;
1934                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id);
1935                         break;
1936                 case ROCKCHIP_VOP2_CLUSTER1:
1937                         port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1;
1938                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id);
1939                         break;
1940                 case ROCKCHIP_VOP2_ESMART0:
1941                         port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0;
1942                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id);
1943                         break;
1944                 case ROCKCHIP_VOP2_ESMART1:
1945                         port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1;
1946                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id);
1947                         break;
1948                 case ROCKCHIP_VOP2_SMART0:
1949                         port_sel &= ~RK3568_OVL_PORT_SEL__SMART0;
1950                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id);
1951                         break;
1952                 case ROCKCHIP_VOP2_SMART1:
1953                         port_sel &= ~RK3568_OVL_PORT_SEL__SMART1;
1954                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id);
1955                         break;
1956                 }
1957
1958                 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs,
1959                                                           0x7);
1960                 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs,
1961                                                          win->data->layer_sel_id);
1962                 nlayer++;
1963         }
1964
1965         /* configure unused layers to 0x5 (reserved) */
1966         for (; nlayer < vp->nlayers; nlayer++) {
1967                 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 0x7);
1968                 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5);
1969         }
1970
1971         vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel);
1972         vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel);
1973         vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD);
1974 }
1975
1976 static void vop2_setup_dly_for_windows(struct vop2 *vop2)
1977 {
1978         struct vop2_win *win;
1979         int i = 0;
1980         u32 cdly = 0, sdly = 0;
1981
1982         for (i = 0; i < vop2->data->win_size; i++) {
1983                 u32 dly;
1984
1985                 win = &vop2->win[i];
1986                 dly = win->delay;
1987
1988                 switch (win->data->phys_id) {
1989                 case ROCKCHIP_VOP2_CLUSTER0:
1990                         cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_0, dly);
1991                         cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_1, dly);
1992                         break;
1993                 case ROCKCHIP_VOP2_CLUSTER1:
1994                         cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_0, dly);
1995                         cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_1, dly);
1996                         break;
1997                 case ROCKCHIP_VOP2_ESMART0:
1998                         sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART0, dly);
1999                         break;
2000                 case ROCKCHIP_VOP2_ESMART1:
2001                         sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly);
2002                         break;
2003                 case ROCKCHIP_VOP2_SMART0:
2004                         sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly);
2005                         break;
2006                 case ROCKCHIP_VOP2_SMART1:
2007                         sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly);
2008                         break;
2009                 }
2010         }
2011
2012         vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly);
2013         vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly);
2014 }
2015
2016 static void vop2_crtc_atomic_begin(struct drm_crtc *crtc,
2017                                    struct drm_atomic_state *state)
2018 {
2019         struct vop2_video_port *vp = to_vop2_video_port(crtc);
2020         struct vop2 *vop2 = vp->vop2;
2021         struct drm_plane *plane;
2022
2023         vp->win_mask = 0;
2024
2025         drm_atomic_crtc_for_each_plane(plane, crtc) {
2026                 struct vop2_win *win = to_vop2_win(plane);
2027
2028                 win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT];
2029
2030                 vp->win_mask |= BIT(win->data->phys_id);
2031
2032                 if (vop2_cluster_window(win))
2033                         vop2_setup_cluster_alpha(vop2, win);
2034         }
2035
2036         if (!vp->win_mask)
2037                 return;
2038
2039         vop2_setup_layer_mixer(vp);
2040         vop2_setup_alpha(vp);
2041         vop2_setup_dly_for_windows(vop2);
2042 }
2043
2044 static void vop2_crtc_atomic_flush(struct drm_crtc *crtc,
2045                                    struct drm_atomic_state *state)
2046 {
2047         struct vop2_video_port *vp = to_vop2_video_port(crtc);
2048
2049         vop2_post_config(crtc);
2050
2051         vop2_cfg_done(vp);
2052
2053         spin_lock_irq(&crtc->dev->event_lock);
2054
2055         if (crtc->state->event) {
2056                 WARN_ON(drm_crtc_vblank_get(crtc));
2057                 vp->event = crtc->state->event;
2058                 crtc->state->event = NULL;
2059         }
2060
2061         spin_unlock_irq(&crtc->dev->event_lock);
2062 }
2063
2064 static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = {
2065         .mode_fixup = vop2_crtc_mode_fixup,
2066         .atomic_check = vop2_crtc_atomic_check,
2067         .atomic_begin = vop2_crtc_atomic_begin,
2068         .atomic_flush = vop2_crtc_atomic_flush,
2069         .atomic_enable = vop2_crtc_atomic_enable,
2070         .atomic_disable = vop2_crtc_atomic_disable,
2071 };
2072
2073 static void vop2_crtc_reset(struct drm_crtc *crtc)
2074 {
2075         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
2076
2077         if (crtc->state) {
2078                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
2079                 kfree(vcstate);
2080         }
2081
2082         vcstate = kzalloc(sizeof(*vcstate), GFP_KERNEL);
2083         if (!vcstate)
2084                 return;
2085
2086         crtc->state = &vcstate->base;
2087         crtc->state->crtc = crtc;
2088 }
2089
2090 static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc)
2091 {
2092         struct rockchip_crtc_state *vcstate, *old_vcstate;
2093
2094         old_vcstate = to_rockchip_crtc_state(crtc->state);
2095
2096         vcstate = kmemdup(old_vcstate, sizeof(*old_vcstate), GFP_KERNEL);
2097         if (!vcstate)
2098                 return NULL;
2099
2100         __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base);
2101
2102         return &vcstate->base;
2103 }
2104
2105 static void vop2_crtc_destroy_state(struct drm_crtc *crtc,
2106                                     struct drm_crtc_state *state)
2107 {
2108         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
2109
2110         __drm_atomic_helper_crtc_destroy_state(&vcstate->base);
2111         kfree(vcstate);
2112 }
2113
2114 static const struct drm_crtc_funcs vop2_crtc_funcs = {
2115         .set_config = drm_atomic_helper_set_config,
2116         .page_flip = drm_atomic_helper_page_flip,
2117         .destroy = drm_crtc_cleanup,
2118         .reset = vop2_crtc_reset,
2119         .atomic_duplicate_state = vop2_crtc_duplicate_state,
2120         .atomic_destroy_state = vop2_crtc_destroy_state,
2121         .enable_vblank = vop2_crtc_enable_vblank,
2122         .disable_vblank = vop2_crtc_disable_vblank,
2123 };
2124
2125 static irqreturn_t vop2_isr(int irq, void *data)
2126 {
2127         struct vop2 *vop2 = data;
2128         const struct vop2_data *vop2_data = vop2->data;
2129         u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM];
2130         int ret = IRQ_NONE;
2131         int i;
2132
2133         /*
2134          * The irq is shared with the iommu. If the runtime-pm state of the
2135          * vop2-device is disabled the irq has to be targeted at the iommu.
2136          */
2137         if (!pm_runtime_get_if_in_use(vop2->dev))
2138                 return IRQ_NONE;
2139
2140         for (i = 0; i < vop2_data->nr_vps; i++) {
2141                 struct vop2_video_port *vp = &vop2->vps[i];
2142                 struct drm_crtc *crtc = &vp->crtc;
2143                 u32 irqs;
2144
2145                 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));
2146                 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs);
2147
2148                 if (irqs & VP_INT_DSP_HOLD_VALID) {
2149                         complete(&vp->dsp_hold_completion);
2150                         ret = IRQ_HANDLED;
2151                 }
2152
2153                 if (irqs & VP_INT_FS_FIELD) {
2154                         drm_crtc_handle_vblank(crtc);
2155                         spin_lock(&crtc->dev->event_lock);
2156                         if (vp->event) {
2157                                 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
2158
2159                                 if (!(val & BIT(vp->id))) {
2160                                         drm_crtc_send_vblank_event(crtc, vp->event);
2161                                         vp->event = NULL;
2162                                         drm_crtc_vblank_put(crtc);
2163                                 }
2164                         }
2165                         spin_unlock(&crtc->dev->event_lock);
2166
2167                         ret = IRQ_HANDLED;
2168                 }
2169
2170                 if (irqs & VP_INT_POST_BUF_EMPTY) {
2171                         drm_err_ratelimited(vop2->drm,
2172                                             "POST_BUF_EMPTY irq err at vp%d\n",
2173                                             vp->id);
2174                         ret = IRQ_HANDLED;
2175                 }
2176         }
2177
2178         axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS);
2179         vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]);
2180         axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS);
2181         vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]);
2182
2183         for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) {
2184                 if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) {
2185                         drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n");
2186                         ret = IRQ_HANDLED;
2187                 }
2188         }
2189
2190         pm_runtime_put(vop2->dev);
2191
2192         return ret;
2193 }
2194
2195 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win,
2196                            unsigned long possible_crtcs)
2197 {
2198         const struct vop2_win_data *win_data = win->data;
2199         unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2200                                   BIT(DRM_MODE_BLEND_PREMULTI) |
2201                                   BIT(DRM_MODE_BLEND_COVERAGE);
2202         int ret;
2203
2204         ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs,
2205                                        &vop2_plane_funcs, win_data->formats,
2206                                        win_data->nformats,
2207                                        win_data->format_modifiers,
2208                                        win->type, win_data->name);
2209         if (ret) {
2210                 drm_err(vop2->drm, "failed to initialize plane %d\n", ret);
2211                 return ret;
2212         }
2213
2214         drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs);
2215
2216         if (win->data->supported_rotations)
2217                 drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0,
2218                                                    DRM_MODE_ROTATE_0 |
2219                                                    win->data->supported_rotations);
2220         drm_plane_create_alpha_property(&win->base);
2221         drm_plane_create_blend_mode_property(&win->base, blend_caps);
2222         drm_plane_create_zpos_property(&win->base, win->win_id, 0,
2223                                        vop2->registered_num_wins - 1);
2224
2225         return 0;
2226 }
2227
2228 static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2)
2229 {
2230         int i;
2231
2232         for (i = 0; i < vop2->data->nr_vps; i++) {
2233                 struct vop2_video_port *vp = &vop2->vps[i];
2234
2235                 if (!vp->crtc.port)
2236                         continue;
2237                 if (vp->primary_plane)
2238                         continue;
2239
2240                 return vp;
2241         }
2242
2243         return NULL;
2244 }
2245
2246 #define NR_LAYERS 6
2247
2248 static int vop2_create_crtc(struct vop2 *vop2)
2249 {
2250         const struct vop2_data *vop2_data = vop2->data;
2251         struct drm_device *drm = vop2->drm;
2252         struct device *dev = vop2->dev;
2253         struct drm_plane *plane;
2254         struct device_node *port;
2255         struct vop2_video_port *vp;
2256         int i, nvp, nvps = 0;
2257         int ret;
2258
2259         for (i = 0; i < vop2_data->nr_vps; i++) {
2260                 const struct vop2_video_port_data *vp_data;
2261                 struct device_node *np;
2262                 char dclk_name[9];
2263
2264                 vp_data = &vop2_data->vp[i];
2265                 vp = &vop2->vps[i];
2266                 vp->vop2 = vop2;
2267                 vp->id = vp_data->id;
2268                 vp->regs = vp_data->regs;
2269                 vp->data = vp_data;
2270
2271                 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
2272                 vp->dclk = devm_clk_get(vop2->dev, dclk_name);
2273                 if (IS_ERR(vp->dclk)) {
2274                         drm_err(vop2->drm, "failed to get %s\n", dclk_name);
2275                         return PTR_ERR(vp->dclk);
2276                 }
2277
2278                 np = of_graph_get_remote_node(dev->of_node, i, -1);
2279                 if (!np) {
2280                         drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i);
2281                         continue;
2282                 }
2283                 of_node_put(np);
2284
2285                 port = of_graph_get_port_by_id(dev->of_node, i);
2286                 if (!port) {
2287                         drm_err(vop2->drm, "no port node found for video_port%d\n", i);
2288                         return -ENOENT;
2289                 }
2290
2291                 vp->crtc.port = port;
2292                 nvps++;
2293         }
2294
2295         nvp = 0;
2296         for (i = 0; i < vop2->registered_num_wins; i++) {
2297                 struct vop2_win *win = &vop2->win[i];
2298                 u32 possible_crtcs;
2299
2300                 if (vop2->data->soc_id == 3566) {
2301                         /*
2302                          * On RK3566 these windows don't have an independent
2303                          * framebuffer. They share the framebuffer with smart0,
2304                          * esmart0 and cluster0 respectively.
2305                          */
2306                         switch (win->data->phys_id) {
2307                         case ROCKCHIP_VOP2_SMART1:
2308                         case ROCKCHIP_VOP2_ESMART1:
2309                         case ROCKCHIP_VOP2_CLUSTER1:
2310                                 continue;
2311                         }
2312                 }
2313
2314                 if (win->type == DRM_PLANE_TYPE_PRIMARY) {
2315                         vp = find_vp_without_primary(vop2);
2316                         if (vp) {
2317                                 possible_crtcs = BIT(nvp);
2318                                 vp->primary_plane = win;
2319                                 nvp++;
2320                         } else {
2321                                 /* change the unused primary window to overlay window */
2322                                 win->type = DRM_PLANE_TYPE_OVERLAY;
2323                         }
2324                 } else if (win->type == DRM_PLANE_TYPE_OVERLAY) {
2325                         possible_crtcs = (1 << nvps) - 1;
2326                 } else {
2327                         possible_crtcs = 0;
2328                 }
2329
2330                 ret = vop2_plane_init(vop2, win, possible_crtcs);
2331                 if (ret) {
2332                         drm_err(vop2->drm, "failed to init plane %s: %d\n",
2333                                 win->data->name, ret);
2334                         return ret;
2335                 }
2336         }
2337
2338         for (i = 0; i < vop2_data->nr_vps; i++) {
2339                 vp = &vop2->vps[i];
2340
2341                 if (!vp->crtc.port)
2342                         continue;
2343
2344                 plane = &vp->primary_plane->base;
2345
2346                 ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL,
2347                                                 &vop2_crtc_funcs,
2348                                                 "video_port%d", vp->id);
2349                 if (ret) {
2350                         drm_err(vop2->drm, "crtc init for video_port%d failed\n", i);
2351                         return ret;
2352                 }
2353
2354                 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs);
2355
2356                 init_completion(&vp->dsp_hold_completion);
2357         }
2358
2359         /*
2360          * On the VOP2 it's very hard to change the number of layers on a VP
2361          * during runtime, so we distribute the layers equally over the used
2362          * VPs
2363          */
2364         for (i = 0; i < vop2->data->nr_vps; i++) {
2365                 struct vop2_video_port *vp = &vop2->vps[i];
2366
2367                 if (vp->crtc.port)
2368                         vp->nlayers = NR_LAYERS / nvps;
2369         }
2370
2371         return 0;
2372 }
2373
2374 static void vop2_destroy_crtc(struct drm_crtc *crtc)
2375 {
2376         of_node_put(crtc->port);
2377
2378         /*
2379          * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane()
2380          * references the CRTC.
2381          */
2382         drm_crtc_cleanup(crtc);
2383 }
2384
2385 static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = {
2386         [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0),
2387         [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5),
2388         [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14),
2389         [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18),
2390         [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31),
2391         [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31),
2392         [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31),
2393         [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31),
2394         [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31),
2395         [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19),
2396         [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15),
2397         [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31),
2398         [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8),
2399         [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9),
2400         [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11),
2401
2402         /* Scale */
2403         [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15),
2404         [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31),
2405         [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15),
2406         [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13),
2407         [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3),
2408         [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28),
2409         [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29),
2410
2411         /* cluster regs */
2412         [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1),
2413         [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0),
2414         [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7),
2415
2416         /* afbc regs */
2417         [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6),
2418         [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9),
2419         [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10),
2420         [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4),
2421         [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7),
2422         [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8),
2423         [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31),
2424         [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31),
2425         [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15),
2426         [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31),
2427         [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31),
2428         [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31),
2429         [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31),
2430         [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0),
2431         [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1),
2432         [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2),
2433         [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3),
2434         [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff },
2435         [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff },
2436         [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff },
2437         [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff },
2438         [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff },
2439         [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
2440         [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
2441         [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff },
2442         [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
2443         [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff },
2444         [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
2445         [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff },
2446         [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff },
2447 };
2448
2449 static int vop2_cluster_init(struct vop2_win *win)
2450 {
2451         struct vop2 *vop2 = win->vop2;
2452         struct reg_field *cluster_regs;
2453         int ret, i;
2454
2455         cluster_regs = kmemdup(vop2_cluster_regs, sizeof(vop2_cluster_regs),
2456                                GFP_KERNEL);
2457         if (!cluster_regs)
2458                 return -ENOMEM;
2459
2460         for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++)
2461                 if (cluster_regs[i].reg != 0xffffffff)
2462                         cluster_regs[i].reg += win->offset;
2463
2464         ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
2465                                            cluster_regs,
2466                                            ARRAY_SIZE(vop2_cluster_regs));
2467
2468         kfree(cluster_regs);
2469
2470         return ret;
2471 };
2472
2473 static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = {
2474         [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0),
2475         [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5),
2476         [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12),
2477         [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14),
2478         [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16),
2479         [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31),
2480         [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31),
2481         [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28),
2482         [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31),
2483         [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31),
2484         [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17),
2485         [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15),
2486         [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31),
2487         [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0),
2488         [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1),
2489         [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3),
2490         [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31),
2491         [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29),
2492         [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31),
2493
2494         /* Scale */
2495         [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15),
2496         [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31),
2497         [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15),
2498         [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31),
2499         [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1),
2500         [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3),
2501         [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5),
2502         [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7),
2503         [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9),
2504         [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11),
2505         [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13),
2506         [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15),
2507         [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17),
2508         [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8),
2509         [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9),
2510         [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10),
2511         [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11),
2512         [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff },
2513         [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff },
2514         [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff },
2515         [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff },
2516         [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff },
2517         [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff },
2518         [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff },
2519         [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff },
2520         [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff },
2521         [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff },
2522         [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff },
2523         [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff },
2524         [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff },
2525         [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff },
2526         [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff },
2527         [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff },
2528         [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff },
2529         [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff },
2530         [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff },
2531 };
2532
2533 static int vop2_esmart_init(struct vop2_win *win)
2534 {
2535         struct vop2 *vop2 = win->vop2;
2536         struct reg_field *esmart_regs;
2537         int ret, i;
2538
2539         esmart_regs = kmemdup(vop2_esmart_regs, sizeof(vop2_esmart_regs),
2540                               GFP_KERNEL);
2541         if (!esmart_regs)
2542                 return -ENOMEM;
2543
2544         for (i = 0; i < ARRAY_SIZE(vop2_esmart_regs); i++)
2545                 if (esmart_regs[i].reg != 0xffffffff)
2546                         esmart_regs[i].reg += win->offset;
2547
2548         ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
2549                                            esmart_regs,
2550                                            ARRAY_SIZE(vop2_esmart_regs));
2551
2552         kfree(esmart_regs);
2553
2554         return ret;
2555 };
2556
2557 static int vop2_win_init(struct vop2 *vop2)
2558 {
2559         const struct vop2_data *vop2_data = vop2->data;
2560         struct vop2_win *win;
2561         int i, ret;
2562
2563         for (i = 0; i < vop2_data->win_size; i++) {
2564                 const struct vop2_win_data *win_data = &vop2_data->win[i];
2565
2566                 win = &vop2->win[i];
2567                 win->data = win_data;
2568                 win->type = win_data->type;
2569                 win->offset = win_data->base;
2570                 win->win_id = i;
2571                 win->vop2 = vop2;
2572                 if (vop2_cluster_window(win))
2573                         ret = vop2_cluster_init(win);
2574                 else
2575                         ret = vop2_esmart_init(win);
2576                 if (ret)
2577                         return ret;
2578         }
2579
2580         vop2->registered_num_wins = vop2_data->win_size;
2581
2582         return 0;
2583 }
2584
2585 /*
2586  * The window registers are only updated when config done is written.
2587  * Until that they read back the old value. As we read-modify-write
2588  * these registers mark them as non-volatile. This makes sure we read
2589  * the new values from the regmap register cache.
2590  */
2591 static const struct regmap_range vop2_nonvolatile_range[] = {
2592         regmap_reg_range(0x1000, 0x23ff),
2593 };
2594
2595 static const struct regmap_access_table vop2_volatile_table = {
2596         .no_ranges = vop2_nonvolatile_range,
2597         .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range),
2598 };
2599
2600 static const struct regmap_config vop2_regmap_config = {
2601         .reg_bits       = 32,
2602         .val_bits       = 32,
2603         .reg_stride     = 4,
2604         .max_register   = 0x3000,
2605         .name           = "vop2",
2606         .volatile_table = &vop2_volatile_table,
2607         .cache_type     = REGCACHE_RBTREE,
2608 };
2609
2610 static int vop2_bind(struct device *dev, struct device *master, void *data)
2611 {
2612         struct platform_device *pdev = to_platform_device(dev);
2613         const struct vop2_data *vop2_data;
2614         struct drm_device *drm = data;
2615         struct vop2 *vop2;
2616         struct resource *res;
2617         size_t alloc_size;
2618         int ret;
2619
2620         vop2_data = of_device_get_match_data(dev);
2621         if (!vop2_data)
2622                 return -ENODEV;
2623
2624         /* Allocate vop2 struct and its vop2_win array */
2625         alloc_size = sizeof(*vop2) + sizeof(*vop2->win) * vop2_data->win_size;
2626         vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2627         if (!vop2)
2628                 return -ENOMEM;
2629
2630         vop2->dev = dev;
2631         vop2->data = vop2_data;
2632         vop2->drm = drm;
2633
2634         dev_set_drvdata(dev, vop2);
2635
2636         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vop");
2637         if (!res) {
2638                 drm_err(vop2->drm, "failed to get vop2 register byname\n");
2639                 return -EINVAL;
2640         }
2641
2642         vop2->regs = devm_ioremap_resource(dev, res);
2643         if (IS_ERR(vop2->regs))
2644                 return PTR_ERR(vop2->regs);
2645         vop2->len = resource_size(res);
2646
2647         vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config);
2648
2649         ret = vop2_win_init(vop2);
2650         if (ret)
2651                 return ret;
2652
2653         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma-lut");
2654         if (res) {
2655                 vop2->lut_regs = devm_ioremap_resource(dev, res);
2656                 if (IS_ERR(vop2->lut_regs))
2657                         return PTR_ERR(vop2->lut_regs);
2658         }
2659
2660         vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
2661
2662         vop2->hclk = devm_clk_get(vop2->dev, "hclk");
2663         if (IS_ERR(vop2->hclk)) {
2664                 drm_err(vop2->drm, "failed to get hclk source\n");
2665                 return PTR_ERR(vop2->hclk);
2666         }
2667
2668         vop2->aclk = devm_clk_get(vop2->dev, "aclk");
2669         if (IS_ERR(vop2->aclk)) {
2670                 drm_err(vop2->drm, "failed to get aclk source\n");
2671                 return PTR_ERR(vop2->aclk);
2672         }
2673
2674         vop2->irq = platform_get_irq(pdev, 0);
2675         if (vop2->irq < 0) {
2676                 drm_err(vop2->drm, "cannot find irq for vop2\n");
2677                 return vop2->irq;
2678         }
2679
2680         mutex_init(&vop2->vop2_lock);
2681
2682         ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2);
2683         if (ret)
2684                 return ret;
2685
2686         ret = vop2_create_crtc(vop2);
2687         if (ret)
2688                 return ret;
2689
2690         rockchip_drm_dma_init_device(vop2->drm, vop2->dev);
2691
2692         pm_runtime_enable(&pdev->dev);
2693
2694         return 0;
2695 }
2696
2697 static void vop2_unbind(struct device *dev, struct device *master, void *data)
2698 {
2699         struct vop2 *vop2 = dev_get_drvdata(dev);
2700         struct drm_device *drm = vop2->drm;
2701         struct list_head *plane_list = &drm->mode_config.plane_list;
2702         struct list_head *crtc_list = &drm->mode_config.crtc_list;
2703         struct drm_crtc *crtc, *tmpc;
2704         struct drm_plane *plane, *tmpp;
2705
2706         pm_runtime_disable(dev);
2707
2708         list_for_each_entry_safe(plane, tmpp, plane_list, head)
2709                 drm_plane_cleanup(plane);
2710
2711         list_for_each_entry_safe(crtc, tmpc, crtc_list, head)
2712                 vop2_destroy_crtc(crtc);
2713 }
2714
2715 const struct component_ops vop2_component_ops = {
2716         .bind = vop2_bind,
2717         .unbind = vop2_unbind,
2718 };
2719 EXPORT_SYMBOL_GPL(vop2_component_ops);