1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
7 #include <linux/mfd/syscon.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/phy/phy.h>
11 #include <linux/regmap.h>
13 #include <drm/drm_of.h>
15 #include <drm/drm_edid.h>
16 #include <drm/drm_probe_helper.h>
17 #include <drm/bridge/dw_hdmi.h>
19 #include "rockchip_drm_drv.h"
20 #include "rockchip_drm_vop.h"
22 #define RK3288_GRF_SOC_CON6 0x025C
23 #define RK3288_HDMI_LCDC_SEL BIT(4)
24 #define RK3328_GRF_SOC_CON2 0x0408
26 #define RK3328_HDMI_SDAIN_MSK BIT(11)
27 #define RK3328_HDMI_SCLIN_MSK BIT(10)
28 #define RK3328_HDMI_HPD_IOE BIT(2)
29 #define RK3328_GRF_SOC_CON3 0x040c
30 /* need to be unset if hdmi or i2c should control voltage */
31 #define RK3328_HDMI_SDA5V_GRF BIT(15)
32 #define RK3328_HDMI_SCL5V_GRF BIT(14)
33 #define RK3328_HDMI_HPD5V_GRF BIT(13)
34 #define RK3328_HDMI_CEC5V_GRF BIT(12)
35 #define RK3328_GRF_SOC_CON4 0x0410
36 #define RK3328_HDMI_HPD_SARADC BIT(13)
37 #define RK3328_HDMI_CEC_5V BIT(11)
38 #define RK3328_HDMI_SDA_5V BIT(10)
39 #define RK3328_HDMI_SCL_5V BIT(9)
40 #define RK3328_HDMI_HPD_5V BIT(8)
42 #define RK3399_GRF_SOC_CON20 0x6250
43 #define RK3399_HDMI_LCDC_SEL BIT(6)
45 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
48 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
49 * @lcdsel_grf_reg: grf register offset of lcdc select
50 * @lcdsel_big: reg value of selecting vop big for HDMI
51 * @lcdsel_lit: reg value of selecting vop little for HDMI
53 struct rockchip_hdmi_chip_data {
59 struct rockchip_hdmi {
61 struct regmap *regmap;
62 struct drm_encoder encoder;
63 const struct rockchip_hdmi_chip_data *chip_data;
70 #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
72 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
152 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
153 /* pixelclk bpp8 bpp10 bpp12 */
155 40000000, { 0x0018, 0x0018, 0x0018 },
157 65000000, { 0x0028, 0x0028, 0x0028 },
159 66000000, { 0x0038, 0x0038, 0x0038 },
161 74250000, { 0x0028, 0x0038, 0x0038 },
163 83500000, { 0x0028, 0x0038, 0x0038 },
165 146250000, { 0x0038, 0x0038, 0x0038 },
167 148500000, { 0x0000, 0x0038, 0x0038 },
169 ~0UL, { 0x0000, 0x0000, 0x0000},
173 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
174 /*pixelclk symbol term vlev*/
175 { 74250000, 0x8009, 0x0004, 0x0272},
176 { 148500000, 0x802b, 0x0004, 0x028d},
177 { 297000000, 0x8039, 0x0005, 0x028d},
178 { ~0UL, 0x0000, 0x0000, 0x0000}
181 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
183 struct device_node *np = hdmi->dev->of_node;
185 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
186 if (IS_ERR(hdmi->regmap)) {
187 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n");
188 return PTR_ERR(hdmi->regmap);
191 hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
192 if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
193 hdmi->vpll_clk = NULL;
194 } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
195 return -EPROBE_DEFER;
196 } else if (IS_ERR(hdmi->vpll_clk)) {
197 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
198 return PTR_ERR(hdmi->vpll_clk);
201 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
202 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
203 hdmi->grf_clk = NULL;
204 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
205 return -EPROBE_DEFER;
206 } else if (IS_ERR(hdmi->grf_clk)) {
207 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
208 return PTR_ERR(hdmi->grf_clk);
214 static enum drm_mode_status
215 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
216 const struct drm_display_mode *mode)
218 const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
219 int pclk = mode->clock * 1000;
223 for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
224 if (pclk == mpll_cfg[i].mpixelclock) {
230 return (valid) ? MODE_OK : MODE_BAD;
233 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
234 .destroy = drm_encoder_cleanup,
237 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
242 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
243 const struct drm_display_mode *mode,
244 struct drm_display_mode *adj_mode)
249 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
250 struct drm_display_mode *mode,
251 struct drm_display_mode *adj_mode)
253 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
255 clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
258 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
260 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
264 if (hdmi->chip_data->lcdsel_grf_reg < 0)
267 ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
269 val = hdmi->chip_data->lcdsel_lit;
271 val = hdmi->chip_data->lcdsel_big;
273 ret = clk_prepare_enable(hdmi->grf_clk);
275 DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret);
279 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
281 DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret);
283 clk_disable_unprepare(hdmi->grf_clk);
284 DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n",
285 ret ? "LIT" : "BIG");
289 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
290 struct drm_crtc_state *crtc_state,
291 struct drm_connector_state *conn_state)
293 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
295 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
296 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
301 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
302 .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
303 .mode_set = dw_hdmi_rockchip_encoder_mode_set,
304 .enable = dw_hdmi_rockchip_encoder_enable,
305 .disable = dw_hdmi_rockchip_encoder_disable,
306 .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
309 static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
310 struct drm_display_mode *mode)
312 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
314 return phy_power_on(hdmi->phy);
317 static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data)
319 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
321 phy_power_off(hdmi->phy);
324 static enum drm_connector_status
325 dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data)
327 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
328 enum drm_connector_status status;
330 status = dw_hdmi_phy_read_hpd(dw_hdmi, data);
332 if (status == connector_status_connected)
333 regmap_write(hdmi->regmap,
335 HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,
336 RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V));
338 regmap_write(hdmi->regmap,
340 HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |
341 RK3328_HDMI_SCL_5V));
345 static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
347 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
349 dw_hdmi_phy_setup_hpd(dw_hdmi, data);
351 /* Enable and map pins to 3V grf-controlled io-voltage */
352 regmap_write(hdmi->regmap,
354 HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |
355 RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |
356 RK3328_HDMI_HPD_5V));
357 regmap_write(hdmi->regmap,
359 HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |
360 RK3328_HDMI_HPD5V_GRF |
361 RK3328_HDMI_CEC5V_GRF));
362 regmap_write(hdmi->regmap,
364 HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,
365 RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |
366 RK3328_HDMI_HPD_IOE));
369 static struct rockchip_hdmi_chip_data rk3288_chip_data = {
370 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
371 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
372 .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
375 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
376 .mode_valid = dw_hdmi_rockchip_mode_valid,
377 .mpll_cfg = rockchip_mpll_cfg,
378 .cur_ctr = rockchip_cur_ctr,
379 .phy_config = rockchip_phy_config,
380 .phy_data = &rk3288_chip_data,
383 static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = {
384 .init = dw_hdmi_rockchip_genphy_init,
385 .disable = dw_hdmi_rockchip_genphy_disable,
386 .read_hpd = dw_hdmi_rk3328_read_hpd,
387 .update_hpd = dw_hdmi_phy_update_hpd,
388 .setup_hpd = dw_hdmi_rk3328_setup_hpd,
391 static struct rockchip_hdmi_chip_data rk3328_chip_data = {
392 .lcdsel_grf_reg = -1,
395 static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
396 .mode_valid = dw_hdmi_rockchip_mode_valid,
397 .mpll_cfg = rockchip_mpll_cfg,
398 .cur_ctr = rockchip_cur_ctr,
399 .phy_config = rockchip_phy_config,
400 .phy_data = &rk3328_chip_data,
401 .phy_ops = &rk3328_hdmi_phy_ops,
402 .phy_name = "inno_dw_hdmi_phy2",
403 .phy_force_vendor = true,
406 static struct rockchip_hdmi_chip_data rk3399_chip_data = {
407 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
408 .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
409 .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
412 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
413 .mode_valid = dw_hdmi_rockchip_mode_valid,
414 .mpll_cfg = rockchip_mpll_cfg,
415 .cur_ctr = rockchip_cur_ctr,
416 .phy_config = rockchip_phy_config,
417 .phy_data = &rk3399_chip_data,
420 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
421 { .compatible = "rockchip,rk3288-dw-hdmi",
422 .data = &rk3288_hdmi_drv_data
424 { .compatible = "rockchip,rk3328-dw-hdmi",
425 .data = &rk3328_hdmi_drv_data
427 { .compatible = "rockchip,rk3399-dw-hdmi",
428 .data = &rk3399_hdmi_drv_data
432 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
434 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
437 struct platform_device *pdev = to_platform_device(dev);
438 struct dw_hdmi_plat_data *plat_data;
439 const struct of_device_id *match;
440 struct drm_device *drm = data;
441 struct drm_encoder *encoder;
442 struct rockchip_hdmi *hdmi;
445 if (!pdev->dev.of_node)
448 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
452 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
453 plat_data = devm_kmemdup(&pdev->dev, match->data,
454 sizeof(*plat_data), GFP_KERNEL);
458 hdmi->dev = &pdev->dev;
459 hdmi->chip_data = plat_data->phy_data;
460 plat_data->phy_data = hdmi;
461 encoder = &hdmi->encoder;
463 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
465 * If we failed to find the CRTC(s) which this encoder is
466 * supposed to be connected to, it's because the CRTC has
467 * not been registered yet. Defer probing, and hope that
468 * the required CRTC is added later.
470 if (encoder->possible_crtcs == 0)
471 return -EPROBE_DEFER;
473 ret = rockchip_hdmi_parse_dt(hdmi);
475 DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n");
479 ret = clk_prepare_enable(hdmi->vpll_clk);
481 DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
486 hdmi->phy = devm_phy_optional_get(dev, "hdmi");
487 if (IS_ERR(hdmi->phy)) {
488 ret = PTR_ERR(hdmi->phy);
489 if (ret != -EPROBE_DEFER)
490 DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n");
494 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
495 drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
496 DRM_MODE_ENCODER_TMDS, NULL);
498 platform_set_drvdata(pdev, hdmi);
500 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
503 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
504 * which would have called the encoder cleanup. Do it manually.
506 if (IS_ERR(hdmi->hdmi)) {
507 ret = PTR_ERR(hdmi->hdmi);
508 drm_encoder_cleanup(encoder);
509 clk_disable_unprepare(hdmi->vpll_clk);
515 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
518 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
520 dw_hdmi_unbind(hdmi->hdmi);
521 clk_disable_unprepare(hdmi->vpll_clk);
524 static const struct component_ops dw_hdmi_rockchip_ops = {
525 .bind = dw_hdmi_rockchip_bind,
526 .unbind = dw_hdmi_rockchip_unbind,
529 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
531 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
534 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
536 component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
541 struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
542 .probe = dw_hdmi_rockchip_probe,
543 .remove = dw_hdmi_rockchip_remove,
545 .name = "dwhdmi-rockchip",
546 .of_match_table = dw_hdmi_rockchip_dt_ids,