drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   4  * Author:
   5  *      Chris Zhong <zyw@rock-chips.com>
   6  *      Nickey Yang <nickey.yang@rock-chips.com>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/math64.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18
  19 #include <video/mipi_display.h>
  20
  21 #include <drm/bridge/dw_mipi_dsi.h>
  22 #include <drm/drm_mipi_dsi.h>
  23 #include <drm/drm_of.h>
  24
  25 #include "rockchip_drm_drv.h"
  26 #include "rockchip_drm_vop.h"
  27
  28 #define DSI_PHY_RSTZ                    0xa0
  29 #define PHY_DISFORCEPLL                 0
  30 #define PHY_ENFORCEPLL                  BIT(3)
  31 #define PHY_DISABLECLK                  0
  32 #define PHY_ENABLECLK                   BIT(2)
  33 #define PHY_RSTZ                        0
  34 #define PHY_UNRSTZ                      BIT(1)
  35 #define PHY_SHUTDOWNZ                   0
  36 #define PHY_UNSHUTDOWNZ                 BIT(0)
  37
  38 #define DSI_PHY_IF_CFG                  0xa4
  39 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
  40 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
  41
  42 #define DSI_PHY_STATUS                  0xb0
  43 #define LOCK                            BIT(0)
  44 #define STOP_STATE_CLK_LANE             BIT(2)
  45
  46 #define DSI_PHY_TST_CTRL0               0xb4
  47 #define PHY_TESTCLK                     BIT(1)
  48 #define PHY_UNTESTCLK                   0
  49 #define PHY_TESTCLR                     BIT(0)
  50 #define PHY_UNTESTCLR                   0
  51
  52 #define DSI_PHY_TST_CTRL1               0xb8
  53 #define PHY_TESTEN                      BIT(16)
  54 #define PHY_UNTESTEN                    0
  55 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
  56 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
  57
  58 #define DSI_INT_ST0                     0xbc
  59 #define DSI_INT_ST1                     0xc0
  60 #define DSI_INT_MSK0                    0xc4
  61 #define DSI_INT_MSK1                    0xc8
  62
  63 #define PHY_STATUS_TIMEOUT_US           10000
  64 #define CMD_PKT_STATUS_TIMEOUT_US       20000
  65
  66 #define BYPASS_VCO_RANGE        BIT(7)
  67 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
  68 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
  69 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
  70 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
  71 #define REF_BIAS_CUR_SEL        BIT(0)
  72
  73 #define CP_CURRENT_3UA  0x1
  74 #define CP_CURRENT_4_5UA        0x2
  75 #define CP_CURRENT_7_5UA        0x6
  76 #define CP_CURRENT_6UA  0x9
  77 #define CP_CURRENT_12UA 0xb
  78 #define CP_CURRENT_SEL(val)     ((val) & 0xf)
  79 #define CP_PROGRAM_EN           BIT(7)
  80
  81 #define LPF_RESISTORS_15_5KOHM  0x1
  82 #define LPF_RESISTORS_13KOHM    0x2
  83 #define LPF_RESISTORS_11_5KOHM  0x4
  84 #define LPF_RESISTORS_10_5KOHM  0x8
  85 #define LPF_RESISTORS_8KOHM     0x10
  86 #define LPF_PROGRAM_EN          BIT(6)
  87 #define LPF_RESISTORS_SEL(val)  ((val) & 0x3f)
  88
  89 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
  90
  91 #define INPUT_DIVIDER(val)      (((val) - 1) & 0x7f)
  92 #define LOW_PROGRAM_EN          0
  93 #define HIGH_PROGRAM_EN         BIT(7)
  94 #define LOOP_DIV_LOW_SEL(val)   (((val) - 1) & 0x1f)
  95 #define LOOP_DIV_HIGH_SEL(val)  ((((val) - 1) >> 5) & 0xf)
  96 #define PLL_LOOP_DIV_EN         BIT(5)
  97 #define PLL_INPUT_DIV_EN        BIT(4)
  98
  99 #define POWER_CONTROL           BIT(6)
 100 #define INTERNAL_REG_CURRENT    BIT(3)
 101 #define BIAS_BLOCK_ON           BIT(2)
 102 #define BANDGAP_ON              BIT(0)
 103
 104 #define TER_RESISTOR_HIGH       BIT(7)
 105 #define TER_RESISTOR_LOW        0
 106 #define LEVEL_SHIFTERS_ON       BIT(6)
 107 #define TER_CAL_DONE            BIT(5)
 108 #define SETRD_MAX               (0x7 << 2)
 109 #define POWER_MANAGE            BIT(1)
 110 #define TER_RESISTORS_ON        BIT(0)
 111
 112 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 113 #define BANDGAP_SEL(val)        ((val) & 0x7)
 114 #define TLP_PROGRAM_EN          BIT(7)
 115 #define THS_PRE_PROGRAM_EN      BIT(7)
 116 #define THS_ZERO_PROGRAM_EN     BIT(6)
 117
 118 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL                0x10
 119 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS                  0x11
 120 #define PLL_LPF_AND_CP_CONTROL                          0x12
 121 #define PLL_INPUT_DIVIDER_RATIO                         0x17
 122 #define PLL_LOOP_DIVIDER_RATIO                          0x18
 123 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL       0x19
 124 #define BANDGAP_AND_BIAS_CONTROL                        0x20
 125 #define TERMINATION_RESISTER_CONTROL                    0x21
 126 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY         0x22
 127 #define HS_RX_CONTROL_OF_LANE_0                         0x44
 128 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL     0x60
 129 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL     0x61
 130 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL     0x62
 131 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL       0x63
 132 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL        0x64
 133 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL              0x65
 134 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL      0x70
 135 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL      0x71
 136 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL      0x72
 137 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL        0x73
 138 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL         0x74
 139
 140 #define DW_MIPI_NEEDS_PHY_CFG_CLK       BIT(0)
 141 #define DW_MIPI_NEEDS_GRF_CLK           BIT(1)
 142
 143 #define RK3288_GRF_SOC_CON6             0x025c
 144 #define RK3288_DSI0_LCDC_SEL            BIT(6)
 145 #define RK3288_DSI1_LCDC_SEL            BIT(9)
 146
 147 #define RK3399_GRF_SOC_CON20            0x6250
 148 #define RK3399_DSI0_LCDC_SEL            BIT(0)
 149 #define RK3399_DSI1_LCDC_SEL            BIT(4)
 150
 151 #define RK3399_GRF_SOC_CON22            0x6258
 152 #define RK3399_DSI0_TURNREQUEST         (0xf << 12)
 153 #define RK3399_DSI0_TURNDISABLE         (0xf << 8)
 154 #define RK3399_DSI0_FORCETXSTOPMODE     (0xf << 4)
 155 #define RK3399_DSI0_FORCERXMODE         (0xf << 0)
 156
 157 #define RK3399_GRF_SOC_CON23            0x625c
 158 #define RK3399_DSI1_TURNDISABLE         (0xf << 12)
 159 #define RK3399_DSI1_FORCETXSTOPMODE     (0xf << 8)
 160 #define RK3399_DSI1_FORCERXMODE         (0xf << 4)
 161 #define RK3399_DSI1_ENABLE              (0xf << 0)
 162
 163 #define RK3399_GRF_SOC_CON24            0x6260
 164 #define RK3399_TXRX_MASTERSLAVEZ        BIT(7)
 165 #define RK3399_TXRX_ENABLECLK           BIT(6)
 166 #define RK3399_TXRX_BASEDIR             BIT(5)
 167
 168 #define HIWORD_UPDATE(val, mask)        (val | (mask) << 16)
 169
 170 #define to_dsi(nm)      container_of(nm, struct dw_mipi_dsi_rockchip, nm)
 171
 172 enum {
 173         BANDGAP_97_07,
 174         BANDGAP_98_05,
 175         BANDGAP_99_02,
 176         BANDGAP_100_00,
 177         BANDGAP_93_17,
 178         BANDGAP_94_15,
 179         BANDGAP_95_12,
 180         BANDGAP_96_10,
 181 };
 182
 183 enum {
 184         BIASEXTR_87_1,
 185         BIASEXTR_91_5,
 186         BIASEXTR_95_9,
 187         BIASEXTR_100,
 188         BIASEXTR_105_94,
 189         BIASEXTR_111_88,
 190         BIASEXTR_118_8,
 191         BIASEXTR_127_7,
 192 };
 193
 194 struct rockchip_dw_dsi_chip_data {
 195         u32 reg;
 196
 197         u32 lcdsel_grf_reg;
 198         u32 lcdsel_big;
 199         u32 lcdsel_lit;
 200
 201         u32 enable_grf_reg;
 202         u32 enable;
 203
 204         u32 lanecfg1_grf_reg;
 205         u32 lanecfg1;
 206         u32 lanecfg2_grf_reg;
 207         u32 lanecfg2;
 208
 209         unsigned int flags;
 210         unsigned int max_data_lanes;
 211 };
 212
 213 struct dw_mipi_dsi_rockchip {
 214         struct device *dev;
 215         struct drm_encoder encoder;
 216         void __iomem *base;
 217
 218         struct regmap *grf_regmap;
 219         struct clk *pllref_clk;
 220         struct clk *grf_clk;
 221         struct clk *phy_cfg_clk;
 222
 223         /* dual-channel */
 224         bool is_slave;
 225         struct dw_mipi_dsi_rockchip *slave;
 226
 227         /* optional external dphy */
 228         struct phy *phy;
 229         union phy_configure_opts phy_opts;
 230
 231         unsigned int lane_mbps; /* per lane */
 232         u16 input_div;
 233         u16 feedback_div;
 234         u32 format;
 235
 236         struct dw_mipi_dsi *dmd;
 237         const struct rockchip_dw_dsi_chip_data *cdata;
 238         struct dw_mipi_dsi_plat_data pdata;
 239         int devcnt;
 240 };
 241
 242 struct dphy_pll_parameter_map {
 243         unsigned int max_mbps;
 244         u8 hsfreqrange;
 245         u8 icpctrl;
 246         u8 lpfctrl;
 247 };
 248
 249 /* The table is based on 27MHz DPHY pll reference clock. */
 250 static const struct dphy_pll_parameter_map dppa_map[] = {
 251         {  89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
 252         {  99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
 253         { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
 254         { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 255         { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 256         { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 257         { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
 258         { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
 259         { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
 260         { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
 261         { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
 262         { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
 263         { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
 264         { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
 265         { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 266         { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 267         { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 268         { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 269         { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 270         { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
 271         { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
 272         { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 273         { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 274         { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 275         { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 276         { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 277         { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 278         { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 279         { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 280         {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 281         {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 282         {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 283         {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 284         {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 285         {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 286         {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 287         {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 288         {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 289         {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
 290 };
 291
 292 static int max_mbps_to_parameter(unsigned int max_mbps)
 293 {
 294         int i;
 295
 296         for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
 297                 if (dppa_map[i].max_mbps >= max_mbps)
 298                         return i;
 299
 300         return -EINVAL;
 301 }
 302
 303 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
 304 {
 305         writel(val, dsi->base + reg);
 306 }
 307
 308 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
 309 {
 310         return readl(dsi->base + reg);
 311 }
 312
 313 static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask)
 314 {
 315         dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
 316 }
 317
 318 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,
 319                                    u32 mask, u32 val)
 320 {
 321         dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
 322 }
 323
 324 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
 325                                   u8 test_code,
 326                                   u8 test_data)
 327 {
 328         /*
 329          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 330          * is latched internally as the current test code. Test data is
 331          * programmed internally by rising edge on TESTCLK.
 332          */
 333         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 334
 335         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 336                                           PHY_TESTDIN(test_code));
 337
 338         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 339
 340         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 341                                           PHY_TESTDIN(test_data));
 342
 343         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 344 }
 345
 346 /**
 347  * ns2bc - Nanoseconds to byte clock cycles
 348  */
 349 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
 350 {
 351         return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
 352 }
 353
 354 /**
 355  * ns2ui - Nanoseconds to UI time periods
 356  */
 357 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
 358 {
 359         return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
 360 }
 361
 362 static int dw_mipi_dsi_phy_init(void *priv_data)
 363 {
 364         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 365         int ret, i, vco;
 366
 367         if (dsi->phy)
 368                 return 0;
 369
 370         /*
 371          * Get vco from frequency(lane_mbps)
 372          * vco  frequency table
 373          * 000 - between   80 and  200 MHz
 374          * 001 - between  200 and  300 MHz
 375          * 010 - between  300 and  500 MHz
 376          * 011 - between  500 and  700 MHz
 377          * 100 - between  700 and  900 MHz
 378          * 101 - between  900 and 1100 MHz
 379          * 110 - between 1100 and 1300 MHz
 380          * 111 - between 1300 and 1500 MHz
 381          */
 382         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 383
 384         i = max_mbps_to_parameter(dsi->lane_mbps);
 385         if (i < 0) {
 386                 DRM_DEV_ERROR(dsi->dev,
 387                               "failed to get parameter for %dmbps clock\n",
 388                               dsi->lane_mbps);
 389                 return i;
 390         }
 391
 392         ret = clk_prepare_enable(dsi->phy_cfg_clk);
 393         if (ret) {
 394                 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
 395                 return ret;
 396         }
 397
 398         dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
 399                               BYPASS_VCO_RANGE |
 400                               VCO_RANGE_CON_SEL(vco) |
 401                               VCO_IN_CAP_CON_LOW |
 402                               REF_BIAS_CUR_SEL);
 403
 404         dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
 405                               CP_CURRENT_SEL(dppa_map[i].icpctrl));
 406         dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
 407                               CP_PROGRAM_EN | LPF_PROGRAM_EN |
 408                               LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
 409
 410         dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
 411                               HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
 412
 413         dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
 414                               INPUT_DIVIDER(dsi->input_div));
 415         dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
 416                               LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 417                               LOW_PROGRAM_EN);
 418         /*
 419          * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately
 420          * to make the configured LSB effective according to IP simulation
 421          * and lab test results.
 422          * Only in this way can we get correct mipi phy pll frequency.
 423          */
 424         dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
 425                               PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 426         dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
 427                               LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 428                               HIGH_PROGRAM_EN);
 429         dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
 430                               PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 431
 432         dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
 433                               LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
 434         dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
 435                               HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
 436
 437         dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
 438                               POWER_CONTROL | INTERNAL_REG_CURRENT |
 439                               BIAS_BLOCK_ON | BANDGAP_ON);
 440
 441         dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
 442                               TER_RESISTOR_LOW | TER_CAL_DONE |
 443                               SETRD_MAX | TER_RESISTORS_ON);
 444         dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
 445                               TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 446                               SETRD_MAX | POWER_MANAGE |
 447                               TER_RESISTORS_ON);
 448
 449         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
 450                               TLP_PROGRAM_EN | ns2bc(dsi, 500));
 451         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
 452                               THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
 453         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
 454                               THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
 455         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
 456                               THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
 457         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
 458                               BIT(5) | ns2bc(dsi, 100));
 459         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
 460                               BIT(5) | (ns2bc(dsi, 60) + 7));
 461
 462         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
 463                               TLP_PROGRAM_EN | ns2bc(dsi, 500));
 464         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
 465                               THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
 466         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
 467                               THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
 468         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
 469                               THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
 470         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
 471                               BIT(5) | ns2bc(dsi, 100));
 472
 473         clk_disable_unprepare(dsi->phy_cfg_clk);
 474
 475         return ret;
 476 }
 477
 478 static void dw_mipi_dsi_phy_power_on(void *priv_data)
 479 {
 480         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 481         int ret;
 482
 483         ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
 484         if (ret) {
 485                 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
 486                 return;
 487         }
 488
 489         phy_configure(dsi->phy, &dsi->phy_opts);
 490         phy_power_on(dsi->phy);
 491 }
 492
 493 static void dw_mipi_dsi_phy_power_off(void *priv_data)
 494 {
 495         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 496
 497         phy_power_off(dsi->phy);
 498 }
 499
 500 static int
 501 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
 502                           unsigned long mode_flags, u32 lanes, u32 format,
 503                           unsigned int *lane_mbps)
 504 {
 505         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 506         int bpp;
 507         unsigned long mpclk, tmp;
 508         unsigned int target_mbps = 1000;
 509         unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
 510         unsigned long best_freq = 0;
 511         unsigned long fvco_min, fvco_max, fin, fout;
 512         unsigned int min_prediv, max_prediv;
 513         unsigned int _prediv, uninitialized_var(best_prediv);
 514         unsigned long _fbdiv, uninitialized_var(best_fbdiv);
 515         unsigned long min_delta = ULONG_MAX;
 516
 517         dsi->format = format;
 518         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 519         if (bpp < 0) {
 520                 DRM_DEV_ERROR(dsi->dev,
 521                               "failed to get bpp for pixel format %d\n",
 522                               dsi->format);
 523                 return bpp;
 524         }
 525
 526         mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
 527         if (mpclk) {
 528                 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
 529                 tmp = mpclk * (bpp / lanes) * 10 / 8;
 530                 if (tmp < max_mbps)
 531                         target_mbps = tmp;
 532                 else
 533                         DRM_DEV_ERROR(dsi->dev,
 534                                       "DPHY clock frequency is out of range\n");
 535         }
 536
 537         /* for external phy only a the mipi_dphy_config is necessary */
 538         if (dsi->phy) {
 539                 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8,
 540                                                  bpp, lanes,
 541                                                  &dsi->phy_opts.mipi_dphy);
 542                 dsi->lane_mbps = target_mbps;
 543                 *lane_mbps = dsi->lane_mbps;
 544
 545                 return 0;
 546         }
 547
 548         fin = clk_get_rate(dsi->pllref_clk);
 549         fout = target_mbps * USEC_PER_SEC;
 550
 551         /* constraint: 5Mhz <= Fref / N <= 40MHz */
 552         min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
 553         max_prediv = fin / (5 * USEC_PER_SEC);
 554
 555         /* constraint: 80MHz <= Fvco <= 1500Mhz */
 556         fvco_min = 80 * USEC_PER_SEC;
 557         fvco_max = 1500 * USEC_PER_SEC;
 558
 559         for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
 560                 u64 tmp;
 561                 u32 delta;
 562                 /* Fvco = Fref * M / N */
 563                 tmp = (u64)fout * _prediv;
 564                 do_div(tmp, fin);
 565                 _fbdiv = tmp;
 566                 /*
 567                  * Due to the use of a "by 2 pre-scaler," the range of the
 568                  * feedback multiplication value M is limited to even division
 569                  * numbers, and m must be greater than 6, not bigger than 512.
 570                  */
 571                 if (_fbdiv < 6 || _fbdiv > 512)
 572                         continue;
 573
 574                 _fbdiv += _fbdiv % 2;
 575
 576                 tmp = (u64)_fbdiv * fin;
 577                 do_div(tmp, _prediv);
 578                 if (tmp < fvco_min || tmp > fvco_max)
 579                         continue;
 580
 581                 delta = abs(fout - tmp);
 582                 if (delta < min_delta) {
 583                         best_prediv = _prediv;
 584                         best_fbdiv = _fbdiv;
 585                         min_delta = delta;
 586                         best_freq = tmp;
 587                 }
 588         }
 589
 590         if (best_freq) {
 591                 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
 592                 *lane_mbps = dsi->lane_mbps;
 593                 dsi->input_div = best_prediv;
 594                 dsi->feedback_div = best_fbdiv;
 595         } else {
 596                 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
 597                 return -EINVAL;
 598         }
 599
 600         return 0;
 601 }
 602
 603 struct hstt {
 604         unsigned int maxfreq;
 605         struct dw_mipi_dsi_dphy_timing timing;
 606 };
 607
 608 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp)  \
 609 {                                       \
 610         .maxfreq = _maxfreq,            \
 611         .timing = {                     \
 612                 .clk_lp2hs = _c_lp2hs,  \
 613                 .clk_hs2lp = _c_hs2lp,  \
 614                 .data_lp2hs = _d_lp2hs, \
 615                 .data_hs2lp = _d_hs2lp, \
 616         }                               \
 617 }
 618
 619 /* Table A-3 High-Speed Transition Times */
 620 struct hstt hstt_table[] = {
 621         HSTT(  90,  32, 20,  26, 13),
 622         HSTT( 100,  35, 23,  28, 14),
 623         HSTT( 110,  32, 22,  26, 13),
 624         HSTT( 130,  31, 20,  27, 13),
 625         HSTT( 140,  33, 22,  26, 14),
 626         HSTT( 150,  33, 21,  26, 14),
 627         HSTT( 170,  32, 20,  27, 13),
 628         HSTT( 180,  36, 23,  30, 15),
 629         HSTT( 200,  40, 22,  33, 15),
 630         HSTT( 220,  40, 22,  33, 15),
 631         HSTT( 240,  44, 24,  36, 16),
 632         HSTT( 250,  48, 24,  38, 17),
 633         HSTT( 270,  48, 24,  38, 17),
 634         HSTT( 300,  50, 27,  41, 18),
 635         HSTT( 330,  56, 28,  45, 18),
 636         HSTT( 360,  59, 28,  48, 19),
 637         HSTT( 400,  61, 30,  50, 20),
 638         HSTT( 450,  67, 31,  55, 21),
 639         HSTT( 500,  73, 31,  59, 22),
 640         HSTT( 550,  79, 36,  63, 24),
 641         HSTT( 600,  83, 37,  68, 25),
 642         HSTT( 650,  90, 38,  73, 27),
 643         HSTT( 700,  95, 40,  77, 28),
 644         HSTT( 750, 102, 40,  84, 28),
 645         HSTT( 800, 106, 42,  87, 30),
 646         HSTT( 850, 113, 44,  93, 31),
 647         HSTT( 900, 118, 47,  98, 32),
 648         HSTT( 950, 124, 47, 102, 34),
 649         HSTT(1000, 130, 49, 107, 35),
 650         HSTT(1050, 135, 51, 111, 37),
 651         HSTT(1100, 139, 51, 114, 38),
 652         HSTT(1150, 146, 54, 120, 40),
 653         HSTT(1200, 153, 57, 125, 41),
 654         HSTT(1250, 158, 58, 130, 42),
 655         HSTT(1300, 163, 58, 135, 44),
 656         HSTT(1350, 168, 60, 140, 45),
 657         HSTT(1400, 172, 64, 144, 47),
 658         HSTT(1450, 176, 65, 148, 48),
 659         HSTT(1500, 181, 66, 153, 50)
 660 };
 661
 662 static int
 663 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
 664                            struct dw_mipi_dsi_dphy_timing *timing)
 665 {
 666         int i;
 667
 668         for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
 669                 if (lane_mbps < hstt_table[i].maxfreq)
 670                         break;
 671
 672         if (i == ARRAY_SIZE(hstt_table))
 673                 i--;
 674
 675         *timing = hstt_table[i].timing;
 676
 677         return 0;
 678 }
 679
 680 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
 681         .init = dw_mipi_dsi_phy_init,
 682         .power_on = dw_mipi_dsi_phy_power_on,
 683         .power_off = dw_mipi_dsi_phy_power_off,
 684         .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
 685         .get_timing = dw_mipi_dsi_phy_get_timing,
 686 };
 687
 688 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi,
 689                                         int mux)
 690 {
 691         if (dsi->cdata->lcdsel_grf_reg)
 692                 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
 693                         mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
 694
 695         if (dsi->cdata->lanecfg1_grf_reg)
 696                 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
 697                                               dsi->cdata->lanecfg1);
 698
 699         if (dsi->cdata->lanecfg2_grf_reg)
 700                 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
 701                                               dsi->cdata->lanecfg2);
 702
 703         if (dsi->cdata->enable_grf_reg)
 704                 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
 705                                               dsi->cdata->enable);
 706 }
 707
 708 static int
 709 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
 710                                  struct drm_crtc_state *crtc_state,
 711                                  struct drm_connector_state *conn_state)
 712 {
 713         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 714         struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
 715
 716         switch (dsi->format) {
 717         case MIPI_DSI_FMT_RGB888:
 718                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 719                 break;
 720         case MIPI_DSI_FMT_RGB666:
 721                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
 722                 break;
 723         case MIPI_DSI_FMT_RGB565:
 724                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
 725                 break;
 726         default:
 727                 WARN_ON(1);
 728                 return -EINVAL;
 729         }
 730
 731         s->output_type = DRM_MODE_CONNECTOR_DSI;
 732         if (dsi->slave)
 733                 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL;
 734
 735         return 0;
 736 }
 737
 738 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 739 {
 740         struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
 741         int ret, mux;
 742
 743         mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
 744                                                 &dsi->encoder);
 745         if (mux < 0)
 746                 return;
 747
 748         pm_runtime_get_sync(dsi->dev);
 749         if (dsi->slave)
 750                 pm_runtime_get_sync(dsi->slave->dev);
 751
 752         /*
 753          * For the RK3399, the clk of grf must be enabled before writing grf
 754          * register. And for RK3288 or other soc, this grf_clk must be NULL,
 755          * the clk_prepare_enable return true directly.
 756          */
 757         ret = clk_prepare_enable(dsi->grf_clk);
 758         if (ret) {
 759                 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
 760                 return;
 761         }
 762
 763         dw_mipi_dsi_rockchip_config(dsi, mux);
 764         if (dsi->slave)
 765                 dw_mipi_dsi_rockchip_config(dsi->slave, mux);
 766
 767         clk_disable_unprepare(dsi->grf_clk);
 768 }
 769
 770 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 771 {
 772         struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
 773
 774         if (dsi->slave)
 775                 pm_runtime_put(dsi->slave->dev);
 776         pm_runtime_put(dsi->dev);
 777 }
 778
 779 static const struct drm_encoder_helper_funcs
 780 dw_mipi_dsi_encoder_helper_funcs = {
 781         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
 782         .enable = dw_mipi_dsi_encoder_enable,
 783         .disable = dw_mipi_dsi_encoder_disable,
 784 };
 785
 786 static const struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
 787         .destroy = drm_encoder_cleanup,
 788 };
 789
 790 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
 791                                            struct drm_device *drm_dev)
 792 {
 793         struct drm_encoder *encoder = &dsi->encoder;
 794         int ret;
 795
 796         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
 797                                                              dsi->dev->of_node);
 798
 799         ret = drm_encoder_init(drm_dev, encoder, &dw_mipi_dsi_encoder_funcs,
 800                                DRM_MODE_ENCODER_DSI, NULL);
 801         if (ret) {
 802                 DRM_ERROR("Failed to initialize encoder with drm\n");
 803                 return ret;
 804         }
 805
 806         drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
 807
 808         return 0;
 809 }
 810
 811 static struct device
 812 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
 813 {
 814         const struct of_device_id *match;
 815         struct device_node *node = NULL, *local;
 816
 817         match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);
 818
 819         local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
 820         if (!local)
 821                 return NULL;
 822
 823         while ((node = of_find_compatible_node(node, NULL,
 824                                                match->compatible))) {
 825                 struct device_node *remote;
 826
 827                 /* found ourself */
 828                 if (node == dsi->dev->of_node)
 829                         continue;
 830
 831                 remote = of_graph_get_remote_node(node, 1, 0);
 832                 if (!remote)
 833                         continue;
 834
 835                 /* same display device in port1-ep0 for both */
 836                 if (remote == local) {
 837                         struct dw_mipi_dsi_rockchip *dsi2;
 838                         struct platform_device *pdev;
 839
 840                         pdev = of_find_device_by_node(node);
 841
 842                         /*
 843                          * we have found the second, so will either return it
 844                          * or return with an error. In any case won't need the
 845                          * nodes anymore nor continue the loop.
 846                          */
 847                         of_node_put(remote);
 848                         of_node_put(node);
 849                         of_node_put(local);
 850
 851                         if (!pdev)
 852                                 return ERR_PTR(-EPROBE_DEFER);
 853
 854                         dsi2 = platform_get_drvdata(pdev);
 855                         if (!dsi2) {
 856                                 platform_device_put(pdev);
 857                                 return ERR_PTR(-EPROBE_DEFER);
 858                         }
 859
 860                         return &pdev->dev;
 861                 }
 862
 863                 of_node_put(remote);
 864         }
 865
 866         of_node_put(local);
 867
 868         return NULL;
 869 }
 870
 871 static int dw_mipi_dsi_rockchip_bind(struct device *dev,
 872                                      struct device *master,
 873                                      void *data)
 874 {
 875         struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
 876         struct drm_device *drm_dev = data;
 877         struct device *second;
 878         bool master1, master2;
 879         int ret;
 880
 881         second = dw_mipi_dsi_rockchip_find_second(dsi);
 882         if (IS_ERR(second))
 883                 return PTR_ERR(second);
 884
 885         if (second) {
 886                 master1 = of_property_read_bool(dsi->dev->of_node,
 887                                                 "clock-master");
 888                 master2 = of_property_read_bool(second->of_node,
 889                                                 "clock-master");
 890
 891                 if (master1 && master2) {
 892                         DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");
 893                         return -EINVAL;
 894                 }
 895
 896                 if (!master1 && !master2) {
 897                         DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");
 898                         return -EINVAL;
 899                 }
 900
 901                 /* we are the slave in dual-DSI */
 902                 if (!master1) {
 903                         dsi->is_slave = true;
 904                         return 0;
 905                 }
 906
 907                 dsi->slave = dev_get_drvdata(second);
 908                 if (!dsi->slave) {
 909                         DRM_DEV_ERROR(dev, "could not get slaves data\n");
 910                         return -ENODEV;
 911                 }
 912
 913                 dsi->slave->is_slave = true;
 914                 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
 915                 put_device(second);
 916         }
 917
 918         ret = clk_prepare_enable(dsi->pllref_clk);
 919         if (ret) {
 920                 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
 921                 return ret;
 922         }
 923
 924         ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
 925         if (ret) {
 926                 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
 927                 return ret;
 928         }
 929
 930         ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
 931         if (ret) {
 932                 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
 933                 return ret;
 934         }
 935
 936         return 0;
 937 }
 938
 939 static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
 940                                         struct device *master,
 941                                         void *data)
 942 {
 943         struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
 944
 945         if (dsi->is_slave)
 946                 return;
 947
 948         dw_mipi_dsi_unbind(dsi->dmd);
 949
 950         clk_disable_unprepare(dsi->pllref_clk);
 951 }
 952
 953 static const struct component_ops dw_mipi_dsi_rockchip_ops = {
 954         .bind   = dw_mipi_dsi_rockchip_bind,
 955         .unbind = dw_mipi_dsi_rockchip_unbind,
 956 };
 957
 958 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
 959                                             struct mipi_dsi_device *device)
 960 {
 961         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 962         struct device *second;
 963         int ret;
 964
 965         ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
 966         if (ret) {
 967                 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
 968                                         ret);
 969                 return ret;
 970         }
 971
 972         second = dw_mipi_dsi_rockchip_find_second(dsi);
 973         if (IS_ERR(second))
 974                 return PTR_ERR(second);
 975         if (second) {
 976                 ret = component_add(second, &dw_mipi_dsi_rockchip_ops);
 977                 if (ret) {
 978                         DRM_DEV_ERROR(second,
 979                                       "Failed to register component: %d\n",
 980                                       ret);
 981                         return ret;
 982                 }
 983         }
 984
 985         return 0;
 986 }
 987
 988 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
 989                                             struct mipi_dsi_device *device)
 990 {
 991         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 992         struct device *second;
 993
 994         second = dw_mipi_dsi_rockchip_find_second(dsi);
 995         if (second && !IS_ERR(second))
 996                 component_del(second, &dw_mipi_dsi_rockchip_ops);
 997
 998         component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
 999
1000         return 0;
1001 }
1002
1003 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
1004         .attach = dw_mipi_dsi_rockchip_host_attach,
1005         .detach = dw_mipi_dsi_rockchip_host_detach,
1006 };
1007
1008 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
1009 {
1010         struct device *dev = &pdev->dev;
1011         struct device_node *np = dev->of_node;
1012         struct dw_mipi_dsi_rockchip *dsi;
1013         struct resource *res;
1014         const struct rockchip_dw_dsi_chip_data *cdata =
1015                                 of_device_get_match_data(dev);
1016         int ret, i;
1017
1018         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1019         if (!dsi)
1020                 return -ENOMEM;
1021
1022         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1023         dsi->base = devm_ioremap_resource(dev, res);
1024         if (IS_ERR(dsi->base)) {
1025                 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
1026                 return PTR_ERR(dsi->base);
1027         }
1028
1029         i = 0;
1030         while (cdata[i].reg) {
1031                 if (cdata[i].reg == res->start) {
1032                         dsi->cdata = &cdata[i];
1033                         break;
1034                 }
1035
1036                 i++;
1037         }
1038
1039         if (!dsi->cdata) {
1040                 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
1041                 return -EINVAL;
1042         }
1043
1044         /* try to get a possible external dphy */
1045         dsi->phy = devm_phy_optional_get(dev, "dphy");
1046         if (IS_ERR(dsi->phy)) {
1047                 ret = PTR_ERR(dsi->phy);
1048                 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
1049                 return ret;
1050         }
1051
1052         dsi->pllref_clk = devm_clk_get(dev, "ref");
1053         if (IS_ERR(dsi->pllref_clk)) {
1054                 if (dsi->phy) {
1055                         /*
1056                          * if external phy is present, pll will be
1057                          * generated there.
1058                          */
1059                         dsi->pllref_clk = NULL;
1060                 } else {
1061                         ret = PTR_ERR(dsi->pllref_clk);
1062                         DRM_DEV_ERROR(dev,
1063                                       "Unable to get pll reference clock: %d\n",
1064                                       ret);
1065                         return ret;
1066                 }
1067         }
1068
1069         if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
1070                 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1071                 if (IS_ERR(dsi->phy_cfg_clk)) {
1072                         ret = PTR_ERR(dsi->phy_cfg_clk);
1073                         DRM_DEV_ERROR(dev,
1074                                       "Unable to get phy_cfg_clk: %d\n", ret);
1075                         return ret;
1076                 }
1077         }
1078
1079         if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
1080                 dsi->grf_clk = devm_clk_get(dev, "grf");
1081                 if (IS_ERR(dsi->grf_clk)) {
1082                         ret = PTR_ERR(dsi->grf_clk);
1083                         DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
1084                         return ret;
1085                 }
1086         }
1087
1088         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1089         if (IS_ERR(dsi->grf_regmap)) {
1090                 DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");
1091                 return PTR_ERR(dsi->grf_regmap);
1092         }
1093
1094         dsi->dev = dev;
1095         dsi->pdata.base = dsi->base;
1096         dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
1097         dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
1098         dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
1099         dsi->pdata.priv_data = dsi;
1100         platform_set_drvdata(pdev, dsi);
1101
1102         dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
1103         if (IS_ERR(dsi->dmd)) {
1104                 ret = PTR_ERR(dsi->dmd);
1105                 if (ret != -EPROBE_DEFER)
1106                         DRM_DEV_ERROR(dev,
1107                                       "Failed to probe dw_mipi_dsi: %d\n", ret);
1108                 goto err_clkdisable;
1109         }
1110
1111         return 0;
1112
1113 err_clkdisable:
1114         clk_disable_unprepare(dsi->pllref_clk);
1115         return ret;
1116 }
1117
1118 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
1119 {
1120         struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
1121
1122         if (dsi->devcnt == 0)
1123                 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1124
1125         dw_mipi_dsi_remove(dsi->dmd);
1126
1127         return 0;
1128 }
1129
1130 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
1131         {
1132                 .reg = 0xff960000,
1133                 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1134                 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1135                 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1136
1137                 .max_data_lanes = 4,
1138         },
1139         {
1140                 .reg = 0xff964000,
1141                 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1142                 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1143                 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1144
1145                 .max_data_lanes = 4,
1146         },
1147         { /* sentinel */ }
1148 };
1149
1150 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
1151         {
1152                 .reg = 0xff960000,
1153                 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1154                 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1155                 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1156                                             RK3399_DSI0_LCDC_SEL),
1157
1158                 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
1159                 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1160                                              RK3399_DSI0_TURNDISABLE |
1161                                              RK3399_DSI0_FORCETXSTOPMODE |
1162                                              RK3399_DSI0_FORCERXMODE),
1163
1164                 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1165                 .max_data_lanes = 4,
1166         },
1167         {
1168                 .reg = 0xff968000,
1169                 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1170                 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1171                 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1172                                             RK3399_DSI1_LCDC_SEL),
1173
1174                 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
1175                 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1176                                              RK3399_DSI1_FORCETXSTOPMODE |
1177                                              RK3399_DSI1_FORCERXMODE |
1178                                              RK3399_DSI1_ENABLE),
1179
1180                 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
1181                 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1182                                           RK3399_TXRX_ENABLECLK,
1183                                           RK3399_TXRX_MASTERSLAVEZ |
1184                                           RK3399_TXRX_ENABLECLK |
1185                                           RK3399_TXRX_BASEDIR),
1186
1187                 .enable_grf_reg = RK3399_GRF_SOC_CON23,
1188                 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1189
1190                 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1191                 .max_data_lanes = 4,
1192         },
1193         { /* sentinel */ }
1194 };
1195
1196 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
1197         {
1198          .compatible = "rockchip,rk3288-mipi-dsi",
1199          .data = &rk3288_chip_data,
1200         }, {
1201          .compatible = "rockchip,rk3399-mipi-dsi",
1202          .data = &rk3399_chip_data,
1203         },
1204         { /* sentinel */ }
1205 };
1206 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
1207
1208 struct platform_driver dw_mipi_dsi_rockchip_driver = {
1209         .probe          = dw_mipi_dsi_rockchip_probe,
1210         .remove         = dw_mipi_dsi_rockchip_remove,
1211         .driver         = {
1212                 .of_match_table = dw_mipi_dsi_rockchip_dt_ids,
1213                 .name   = "dw-mipi-dsi-rockchip",
1214         },
1215 };