1 // SPDX-License-Identifier: GPL-2.0
3 * RZ/G2L MIPI DSI Encoder Driver
5 * Copyright (C) 2022 Renesas Electronics Corporation
8 #include <linux/delay.h>
10 #include <linux/iopoll.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/reset.h>
18 #include <linux/slab.h>
20 #include <drm/drm_atomic.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_bridge.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_panel.h>
26 #include <drm/drm_probe_helper.h>
28 #include "rzg2l_mipi_dsi_regs.h"
30 struct rzg2l_mipi_dsi {
34 struct reset_control *rstc;
35 struct reset_control *arstc;
36 struct reset_control *prstc;
38 struct mipi_dsi_host host;
39 struct drm_bridge bridge;
40 struct drm_bridge *next_bridge;
44 enum mipi_dsi_pixel_format format;
45 unsigned int num_data_lanes;
47 unsigned long mode_flags;
50 static inline struct rzg2l_mipi_dsi *
51 bridge_to_rzg2l_mipi_dsi(struct drm_bridge *bridge)
53 return container_of(bridge, struct rzg2l_mipi_dsi, bridge);
56 static inline struct rzg2l_mipi_dsi *
57 host_to_rzg2l_mipi_dsi(struct mipi_dsi_host *host)
59 return container_of(host, struct rzg2l_mipi_dsi, host);
62 struct rzg2l_mipi_dsi_timings {
63 unsigned long hsfreq_max;
77 static const struct rzg2l_mipi_dsi_timings rzg2l_mipi_dsi_global_timings[] = {
107 .hsfreq_max = 250000,
121 .hsfreq_max = 360000,
135 .hsfreq_max = 720000,
149 .hsfreq_max = 1500000,
164 static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data)
166 iowrite32(data, dsi->mmio + reg);
169 static void rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data)
171 iowrite32(data, dsi->mmio + LINK_REG_OFFSET + reg);
174 static u32 rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
176 return ioread32(dsi->mmio + reg);
179 static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
181 return ioread32(dsi->mmio + LINK_REG_OFFSET + reg);
184 /* -----------------------------------------------------------------------------
188 static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
189 unsigned long hsfreq)
191 const struct rzg2l_mipi_dsi_timings *dphy_timings;
200 /* All DSI global operation timings are set with recommended setting */
201 for (i = 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) {
202 dphy_timings = &rzg2l_mipi_dsi_global_timings[i];
203 if (hsfreq <= dphy_timings->hsfreq_max)
207 /* Initializing DPHY before accessing LINK */
208 dphyctrl0 = DSIDPHYCTRL0_CAL_EN_HSRX_OFS | DSIDPHYCTRL0_CMN_MASTER_EN |
209 DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | DSIDPHYCTRL0_EN_BGR;
211 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
212 usleep_range(20, 30);
214 dphyctrl0 |= DSIDPHYCTRL0_EN_LDO1200;
215 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
216 usleep_range(10, 20);
218 dphytim0 = DSIDPHYTIM0_TCLK_MISS(0) |
219 DSIDPHYTIM0_T_INIT(dphy_timings->t_init);
220 dphytim1 = DSIDPHYTIM1_THS_PREPARE(dphy_timings->ths_prepare) |
221 DSIDPHYTIM1_TCLK_PREPARE(dphy_timings->tclk_prepare) |
222 DSIDPHYTIM1_THS_SETTLE(0) |
223 DSIDPHYTIM1_TCLK_SETTLE(0);
224 dphytim2 = DSIDPHYTIM2_TCLK_TRAIL(dphy_timings->tclk_trail) |
225 DSIDPHYTIM2_TCLK_POST(dphy_timings->tclk_post) |
226 DSIDPHYTIM2_TCLK_PRE(dphy_timings->tclk_pre) |
227 DSIDPHYTIM2_TCLK_ZERO(dphy_timings->tclk_zero);
228 dphytim3 = DSIDPHYTIM3_TLPX(dphy_timings->tlpx) |
229 DSIDPHYTIM3_THS_EXIT(dphy_timings->ths_exit) |
230 DSIDPHYTIM3_THS_TRAIL(dphy_timings->ths_trail) |
231 DSIDPHYTIM3_THS_ZERO(dphy_timings->ths_zero);
233 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM0, dphytim0);
234 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM1, dphytim1);
235 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM2, dphytim2);
236 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM3, dphytim3);
238 ret = reset_control_deassert(dsi->rstc);
247 static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi)
251 dphyctrl0 = rzg2l_mipi_dsi_phy_read(dsi, DSIDPHYCTRL0);
253 dphyctrl0 &= ~(DSIDPHYCTRL0_EN_LDO1200 | DSIDPHYCTRL0_EN_BGR);
254 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
256 reset_control_assert(dsi->rstc);
259 static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
260 const struct drm_display_mode *mode)
262 unsigned long hsfreq;
274 * Relationship between hsclk and vclk must follow
275 * vclk * bpp = hsclk * 8 * lanes
276 * where vclk: video clock (Hz)
277 * bpp: video pixel bit depth
278 * hsclk: DSI HS Byte clock frequency (Hz)
279 * lanes: number of data lanes
281 * hsclk(bit) = hsclk(byte) * 8
283 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
284 hsfreq = (mode->clock * bpp * 8) / (8 * dsi->lanes);
286 ret = pm_runtime_resume_and_get(dsi->dev);
290 clk_set_rate(dsi->vclk, mode->clock * 1000);
292 ret = rzg2l_mipi_dsi_dphy_init(dsi, hsfreq);
296 /* Enable Data lanes and Clock lanes */
297 txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN;
298 rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr);
301 * Global timings characteristic depends on high speed Clock Frequency
302 * Currently MIPI DSI-IF just supports maximum FHD@60 with:
303 * - videoclock = 148.5 (MHz)
304 * - bpp: maximum 24bpp
305 * - data lanes: maximum 4 lanes
306 * Therefore maximum hsclk will be 891 Mbps.
308 if (hsfreq > 445500) {
313 } else if (hsfreq > 250000) {
325 clstptsetr = CLSTPTSETR_CLKKPT(clkkpt) | CLSTPTSETR_CLKBFHT(clkbfht) |
326 CLSTPTSETR_CLKSTPT(clkstpt);
327 rzg2l_mipi_dsi_link_write(dsi, CLSTPTSETR, clstptsetr);
329 lptrnstsetr = LPTRNSTSETR_GOLPBKT(golpbkt);
330 rzg2l_mipi_dsi_link_write(dsi, LPTRNSTSETR, lptrnstsetr);
335 rzg2l_mipi_dsi_dphy_exit(dsi);
336 pm_runtime_put(dsi->dev);
341 static void rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi *dsi)
343 rzg2l_mipi_dsi_dphy_exit(dsi);
344 pm_runtime_put(dsi->dev);
347 static void rzg2l_mipi_dsi_set_display_timing(struct rzg2l_mipi_dsi *dsi,
348 const struct drm_display_mode *mode)
359 /* Configuration for Pixel Packet */
360 dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format);
361 switch (dsi_format) {
363 vich1ppsetr = VICH1PPSETR_DT_RGB24;
366 vich1ppsetr = VICH1PPSETR_DT_RGB18;
370 if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) &&
371 !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST))
372 vich1ppsetr |= VICH1PPSETR_TXESYNC_PULSE;
374 rzg2l_mipi_dsi_link_write(dsi, VICH1PPSETR, vich1ppsetr);
376 /* Configuration for Video Parameters */
377 vich1vssetr = VICH1VSSETR_VACTIVE(mode->vdisplay) |
378 VICH1VSSETR_VSA(mode->vsync_end - mode->vsync_start);
379 vich1vssetr |= (mode->flags & DRM_MODE_FLAG_PVSYNC) ?
380 VICH1VSSETR_VSPOL_HIGH : VICH1VSSETR_VSPOL_LOW;
382 vich1vpsetr = VICH1VPSETR_VFP(mode->vsync_start - mode->vdisplay) |
383 VICH1VPSETR_VBP(mode->vtotal - mode->vsync_end);
385 vich1hssetr = VICH1HSSETR_HACTIVE(mode->hdisplay) |
386 VICH1HSSETR_HSA(mode->hsync_end - mode->hsync_start);
387 vich1hssetr |= (mode->flags & DRM_MODE_FLAG_PHSYNC) ?
388 VICH1HSSETR_HSPOL_HIGH : VICH1HSSETR_HSPOL_LOW;
390 vich1hpsetr = VICH1HPSETR_HFP(mode->hsync_start - mode->hdisplay) |
391 VICH1HPSETR_HBP(mode->htotal - mode->hsync_end);
393 rzg2l_mipi_dsi_link_write(dsi, VICH1VSSETR, vich1vssetr);
394 rzg2l_mipi_dsi_link_write(dsi, VICH1VPSETR, vich1vpsetr);
395 rzg2l_mipi_dsi_link_write(dsi, VICH1HSSETR, vich1hssetr);
396 rzg2l_mipi_dsi_link_write(dsi, VICH1HPSETR, vich1hpsetr);
399 * Configuration for Delay Value
400 * Delay value based on 2 ranges of video clock.
401 * 74.25MHz is videoclock of HD@60p or FHD@30p
403 if (mode->clock > 74250) {
411 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
416 rzg2l_mipi_dsi_link_write(dsi, VICH1SET1R,
417 VICH1SET1R_DLY(delay[index]));
420 static int rzg2l_mipi_dsi_start_hs_clock(struct rzg2l_mipi_dsi *dsi)
427 is_clk_cont = !(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS);
430 hsclksetr = HSCLKSETR_HSCLKRUN_HS | (is_clk_cont ?
431 HSCLKSETR_HSCLKMODE_CONT :
432 HSCLKSETR_HSCLKMODE_NON_CONT);
433 rzg2l_mipi_dsi_link_write(dsi, HSCLKSETR, hsclksetr);
436 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
437 status & PLSR_CLLP2HS,
438 2000, 20000, false, dsi, PLSR);
440 dev_err(dsi->dev, "failed to start HS clock\n");
445 dev_dbg(dsi->dev, "Start High Speed Clock with %s clock mode",
446 is_clk_cont ? "continuous" : "non-continuous");
451 static int rzg2l_mipi_dsi_stop_hs_clock(struct rzg2l_mipi_dsi *dsi)
457 is_clk_cont = !(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS);
460 rzg2l_mipi_dsi_link_write(dsi, HSCLKSETR,
461 is_clk_cont ? HSCLKSETR_HSCLKMODE_CONT :
462 HSCLKSETR_HSCLKMODE_NON_CONT);
465 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
466 status & PLSR_CLHS2LP,
467 2000, 20000, false, dsi, PLSR);
469 dev_err(dsi->dev, "failed to stop HS clock\n");
477 static int rzg2l_mipi_dsi_start_video(struct rzg2l_mipi_dsi *dsi)
483 /* Configuration for Blanking sequence and start video input*/
484 vich1set0r = VICH1SET0R_HFPNOLP | VICH1SET0R_HBPNOLP |
485 VICH1SET0R_HSANOLP | VICH1SET0R_VSTART;
486 rzg2l_mipi_dsi_link_write(dsi, VICH1SET0R, vich1set0r);
488 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
489 status & VICH1SR_VIRDY,
490 2000, 20000, false, dsi, VICH1SR);
492 dev_err(dsi->dev, "Failed to start video signal input\n");
497 static int rzg2l_mipi_dsi_stop_video(struct rzg2l_mipi_dsi *dsi)
502 rzg2l_mipi_dsi_link_write(dsi, VICH1SET0R, VICH1SET0R_VSTPAFT);
503 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
504 (status & VICH1SR_STOP) && (!(status & VICH1SR_RUNNING)),
505 2000, 20000, false, dsi, VICH1SR);
509 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
510 !(status & LINKSR_HSBUSY),
511 2000, 20000, false, dsi, LINKSR);
518 dev_err(dsi->dev, "Failed to stop video signal input\n");
522 /* -----------------------------------------------------------------------------
526 static int rzg2l_mipi_dsi_attach(struct drm_bridge *bridge,
527 enum drm_bridge_attach_flags flags)
529 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
531 return drm_bridge_attach(bridge->encoder, dsi->next_bridge, bridge,
535 static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
536 struct drm_bridge_state *old_bridge_state)
538 struct drm_atomic_state *state = old_bridge_state->base.state;
539 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
540 const struct drm_display_mode *mode;
541 struct drm_connector *connector;
542 struct drm_crtc *crtc;
545 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
546 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
547 mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode;
549 ret = rzg2l_mipi_dsi_startup(dsi, mode);
553 rzg2l_mipi_dsi_set_display_timing(dsi, mode);
555 ret = rzg2l_mipi_dsi_start_hs_clock(dsi);
559 ret = rzg2l_mipi_dsi_start_video(dsi);
566 rzg2l_mipi_dsi_stop_hs_clock(dsi);
568 rzg2l_mipi_dsi_stop(dsi);
571 static void rzg2l_mipi_dsi_atomic_disable(struct drm_bridge *bridge,
572 struct drm_bridge_state *old_bridge_state)
574 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
576 rzg2l_mipi_dsi_stop_video(dsi);
577 rzg2l_mipi_dsi_stop_hs_clock(dsi);
578 rzg2l_mipi_dsi_stop(dsi);
581 static enum drm_mode_status
582 rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
583 const struct drm_display_info *info,
584 const struct drm_display_mode *mode)
586 if (mode->clock > 148500)
587 return MODE_CLOCK_HIGH;
592 static const struct drm_bridge_funcs rzg2l_mipi_dsi_bridge_ops = {
593 .attach = rzg2l_mipi_dsi_attach,
594 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
595 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
596 .atomic_reset = drm_atomic_helper_bridge_reset,
597 .atomic_enable = rzg2l_mipi_dsi_atomic_enable,
598 .atomic_disable = rzg2l_mipi_dsi_atomic_disable,
599 .mode_valid = rzg2l_mipi_dsi_bridge_mode_valid,
602 /* -----------------------------------------------------------------------------
606 static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host,
607 struct mipi_dsi_device *device)
609 struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
612 if (device->lanes > dsi->num_data_lanes) {
614 "Number of lines of device (%u) exceeds host (%u)\n",
615 device->lanes, dsi->num_data_lanes);
619 switch (mipi_dsi_pixel_format_to_bpp(device->format)) {
624 dev_err(dsi->dev, "Unsupported format 0x%04x\n", device->format);
628 dsi->lanes = device->lanes;
629 dsi->format = device->format;
630 dsi->mode_flags = device->mode_flags;
632 dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
634 if (IS_ERR(dsi->next_bridge)) {
635 ret = PTR_ERR(dsi->next_bridge);
636 dev_err(dsi->dev, "failed to get next bridge: %d\n", ret);
640 drm_bridge_add(&dsi->bridge);
645 static int rzg2l_mipi_dsi_host_detach(struct mipi_dsi_host *host,
646 struct mipi_dsi_device *device)
648 struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
650 drm_bridge_remove(&dsi->bridge);
655 static const struct mipi_dsi_host_ops rzg2l_mipi_dsi_host_ops = {
656 .attach = rzg2l_mipi_dsi_host_attach,
657 .detach = rzg2l_mipi_dsi_host_detach,
660 /* -----------------------------------------------------------------------------
664 static int __maybe_unused rzg2l_mipi_pm_runtime_suspend(struct device *dev)
666 struct rzg2l_mipi_dsi *dsi = dev_get_drvdata(dev);
668 reset_control_assert(dsi->prstc);
669 reset_control_assert(dsi->arstc);
674 static int __maybe_unused rzg2l_mipi_pm_runtime_resume(struct device *dev)
676 struct rzg2l_mipi_dsi *dsi = dev_get_drvdata(dev);
679 ret = reset_control_deassert(dsi->arstc);
683 ret = reset_control_deassert(dsi->prstc);
685 reset_control_assert(dsi->arstc);
690 static const struct dev_pm_ops rzg2l_mipi_pm_ops = {
691 SET_RUNTIME_PM_OPS(rzg2l_mipi_pm_runtime_suspend, rzg2l_mipi_pm_runtime_resume, NULL)
694 /* -----------------------------------------------------------------------------
698 static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
700 unsigned int num_data_lanes;
701 struct rzg2l_mipi_dsi *dsi;
705 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
709 platform_set_drvdata(pdev, dsi);
710 dsi->dev = &pdev->dev;
712 ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
714 return dev_err_probe(dsi->dev, ret,
715 "missing or invalid data-lanes property\n");
717 num_data_lanes = ret;
719 dsi->mmio = devm_platform_ioremap_resource(pdev, 0);
720 if (IS_ERR(dsi->mmio))
721 return PTR_ERR(dsi->mmio);
723 dsi->vclk = devm_clk_get(dsi->dev, "vclk");
724 if (IS_ERR(dsi->vclk))
725 return PTR_ERR(dsi->vclk);
727 dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst");
728 if (IS_ERR(dsi->rstc))
729 return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
730 "failed to get rst\n");
732 dsi->arstc = devm_reset_control_get_exclusive(dsi->dev, "arst");
733 if (IS_ERR(dsi->arstc))
734 return dev_err_probe(&pdev->dev, PTR_ERR(dsi->arstc),
735 "failed to get arst\n");
737 dsi->prstc = devm_reset_control_get_exclusive(dsi->dev, "prst");
738 if (IS_ERR(dsi->prstc))
739 return dev_err_probe(dsi->dev, PTR_ERR(dsi->prstc),
740 "failed to get prst\n");
742 platform_set_drvdata(pdev, dsi);
744 pm_runtime_enable(dsi->dev);
746 ret = pm_runtime_resume_and_get(dsi->dev);
751 * TXSETR register can be read only after DPHY init. But during probe
752 * mode->clock and format are not available. So initialize DPHY with
753 * timing parameters for 80Mbps.
755 ret = rzg2l_mipi_dsi_dphy_init(dsi, 80000);
759 txsetr = rzg2l_mipi_dsi_link_read(dsi, TXSETR);
760 dsi->num_data_lanes = min(((txsetr >> 16) & 3) + 1, num_data_lanes);
761 rzg2l_mipi_dsi_dphy_exit(dsi);
762 pm_runtime_put(dsi->dev);
764 /* Initialize the DRM bridge. */
765 dsi->bridge.funcs = &rzg2l_mipi_dsi_bridge_ops;
766 dsi->bridge.of_node = dsi->dev->of_node;
768 /* Init host device */
769 dsi->host.dev = dsi->dev;
770 dsi->host.ops = &rzg2l_mipi_dsi_host_ops;
771 ret = mipi_dsi_host_register(&dsi->host);
778 rzg2l_mipi_dsi_dphy_exit(dsi);
779 pm_runtime_put(dsi->dev);
781 pm_runtime_disable(dsi->dev);
785 static int rzg2l_mipi_dsi_remove(struct platform_device *pdev)
787 struct rzg2l_mipi_dsi *dsi = platform_get_drvdata(pdev);
789 mipi_dsi_host_unregister(&dsi->host);
790 pm_runtime_disable(&pdev->dev);
795 static const struct of_device_id rzg2l_mipi_dsi_of_table[] = {
796 { .compatible = "renesas,rzg2l-mipi-dsi" },
800 MODULE_DEVICE_TABLE(of, rzg2l_mipi_dsi_of_table);
802 static struct platform_driver rzg2l_mipi_dsi_platform_driver = {
803 .probe = rzg2l_mipi_dsi_probe,
804 .remove = rzg2l_mipi_dsi_remove,
806 .name = "rzg2l-mipi-dsi",
807 .pm = &rzg2l_mipi_pm_ops,
808 .of_match_table = rzg2l_mipi_dsi_of_table,
812 module_platform_driver(rzg2l_mipi_dsi_platform_driver);
814 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
815 MODULE_DESCRIPTION("Renesas RZ/G2L MIPI DSI Encoder Driver");
816 MODULE_LICENSE("GPL");