1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R-Car MIPI DSI Interface Registers Definitions
5 * Copyright (C) 2020 Renesas Electronics Corporation
8 #ifndef __RCAR_MIPI_DSI_REGS_H__
9 #define __RCAR_MIPI_DSI_REGS_H__
12 #define LINKSR_LPBUSY (1 << 1)
13 #define LINKSR_HSBUSY (1 << 0)
18 #define TXVMSETR 0x180
19 #define TXVMSETR_SYNSEQ_PULSES (0 << 16)
20 #define TXVMSETR_SYNSEQ_EVENTS (1 << 16)
21 #define TXVMSETR_VSTPM (1 << 15)
22 #define TXVMSETR_PIXWDTH (1 << 8)
23 #define TXVMSETR_VSEN_EN (1 << 4)
24 #define TXVMSETR_VSEN_DIS (0 << 4)
25 #define TXVMSETR_HFPBPEN_EN (1 << 2)
26 #define TXVMSETR_HFPBPEN_DIS (0 << 2)
27 #define TXVMSETR_HBPBPEN_EN (1 << 1)
28 #define TXVMSETR_HBPBPEN_DIS (0 << 1)
29 #define TXVMSETR_HSABPEN_EN (1 << 0)
30 #define TXVMSETR_HSABPEN_DIS (0 << 0)
33 #define TXVMCR_VFCLR (1 << 12)
34 #define TXVMCR_EN_VIDEO (1 << 0)
37 #define TXVMSR_STR (1 << 16)
38 #define TXVMSR_VFRDY (1 << 12)
39 #define TXVMSR_ACT (1 << 8)
40 #define TXVMSR_RDY (1 << 0)
43 #define TXVMSCR_STR (1 << 16)
45 #define TXVMPSPHSETR 0x1c0
46 #define TXVMPSPHSETR_DT_RGB16 (0x0e << 16)
47 #define TXVMPSPHSETR_DT_RGB18 (0x1e << 16)
48 #define TXVMPSPHSETR_DT_RGB18_LS (0x2e << 16)
49 #define TXVMPSPHSETR_DT_RGB24 (0x3e << 16)
50 #define TXVMPSPHSETR_DT_YCBCR16 (0x2c << 16)
52 #define TXVMVPRMSET0R 0x1d0
53 #define TXVMVPRMSET0R_HSPOL_HIG (0 << 17)
54 #define TXVMVPRMSET0R_HSPOL_LOW (1 << 17)
55 #define TXVMVPRMSET0R_VSPOL_HIG (0 << 16)
56 #define TXVMVPRMSET0R_VSPOL_LOW (1 << 16)
57 #define TXVMVPRMSET0R_CSPC_RGB (0 << 4)
58 #define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4)
59 #define TXVMVPRMSET0R_BPP_16 (0 << 0)
60 #define TXVMVPRMSET0R_BPP_18 (1 << 0)
61 #define TXVMVPRMSET0R_BPP_24 (2 << 0)
63 #define TXVMVPRMSET1R 0x1d4
64 #define TXVMVPRMSET1R_VACTIVE(x) (((x) & 0x7fff) << 16)
65 #define TXVMVPRMSET1R_VSA(x) (((x) & 0xfff) << 0)
67 #define TXVMVPRMSET2R 0x1d8
68 #define TXVMVPRMSET2R_VFP(x) (((x) & 0x1fff) << 16)
69 #define TXVMVPRMSET2R_VBP(x) (((x) & 0x1fff) << 0)
71 #define TXVMVPRMSET3R 0x1dc
72 #define TXVMVPRMSET3R_HACTIVE(x) (((x) & 0x7fff) << 16)
73 #define TXVMVPRMSET3R_HSA(x) (((x) & 0xfff) << 0)
75 #define TXVMVPRMSET4R 0x1e0
76 #define TXVMVPRMSET4R_HFP(x) (((x) & 0x1fff) << 16)
77 #define TXVMVPRMSET4R_HBP(x) (((x) & 0x1fff) << 0)
80 * PHY-Protocol Interface (PPI) Registers
83 #define PPISETR_DLEN_0 (0x1 << 0)
84 #define PPISETR_DLEN_1 (0x3 << 0)
85 #define PPISETR_DLEN_2 (0x7 << 0)
86 #define PPISETR_DLEN_3 (0xf << 0)
87 #define PPISETR_CLEN (1 << 8)
90 #define PPICLCR_TXREQHS (1 << 8)
91 #define PPICLCR_TXULPSEXT (1 << 1)
92 #define PPICLCR_TXULPSCLK (1 << 0)
95 #define PPICLSR_HSTOLP (1 << 27)
96 #define PPICLSR_TOHS (1 << 26)
97 #define PPICLSR_STPST (1 << 0)
99 #define PPICLSCR 0x724
100 #define PPICLSCR_HSTOLP (1 << 27)
101 #define PPICLSCR_TOHS (1 << 26)
103 #define PPIDLSR 0x760
104 #define PPIDLSR_STPST (0xf << 0)
109 #define LPCLKSET 0x1000
110 #define LPCLKSET_CKEN (1 << 8)
111 #define LPCLKSET_LPCLKDIV(x) (((x) & 0x3f) << 0)
113 #define CFGCLKSET 0x1004
114 #define CFGCLKSET_CKEN (1 << 8)
115 #define CFGCLKSET_CFGCLKDIV(x) (((x) & 0x3f) << 0)
117 #define DOTCLKDIV 0x1008
118 #define DOTCLKDIV_CKEN (1 << 8)
119 #define DOTCLKDIV_DOTCLKDIV(x) (((x) & 0x3f) << 0)
121 #define VCLKSET 0x100c
122 #define VCLKSET_CKEN (1 << 16)
123 #define VCLKSET_COLOR_RGB (0 << 8)
124 #define VCLKSET_COLOR_YCC (1 << 8)
125 #define VCLKSET_DIV_V3U(x) (((x) & 0x3) << 4)
126 #define VCLKSET_DIV_V4H(x) (((x) & 0x7) << 4)
127 #define VCLKSET_BPP_16 (0 << 2)
128 #define VCLKSET_BPP_18 (1 << 2)
129 #define VCLKSET_BPP_18L (2 << 2)
130 #define VCLKSET_BPP_24 (3 << 2)
131 #define VCLKSET_LANE(x) (((x) & 0x3) << 0)
133 #define VCLKEN 0x1010
134 #define VCLKEN_CKEN (1 << 0)
136 #define PHYSETUP 0x1014
137 #define PHYSETUP_HSFREQRANGE(x) (((x) & 0x7f) << 16)
138 #define PHYSETUP_HSFREQRANGE_MASK (0x7f << 16)
139 #define PHYSETUP_CFGCLKFREQRANGE(x) (((x) & 0x3f) << 8)
140 #define PHYSETUP_SHUTDOWNZ (1 << 1)
141 #define PHYSETUP_RSTZ (1 << 0)
143 #define CLOCKSET1 0x101c
144 #define CLOCKSET1_LOCK_PHY (1 << 17)
145 #define CLOCKSET1_LOCK (1 << 16)
146 #define CLOCKSET1_CLKSEL (1 << 8)
147 #define CLOCKSET1_CLKINSEL_EXTAL (0 << 2)
148 #define CLOCKSET1_CLKINSEL_DIG (1 << 2)
149 #define CLOCKSET1_CLKINSEL_DU (1 << 3)
150 #define CLOCKSET1_SHADOW_CLEAR (1 << 1)
151 #define CLOCKSET1_UPDATEPLL (1 << 0)
153 #define CLOCKSET2 0x1020
154 #define CLOCKSET2_M(x) (((x) & 0xfff) << 16)
155 #define CLOCKSET2_VCO_CNTRL(x) (((x) & 0x3f) << 8)
156 #define CLOCKSET2_N(x) (((x) & 0xf) << 0)
158 #define CLOCKSET3 0x1024
159 #define CLOCKSET3_PROP_CNTRL(x) (((x) & 0x3f) << 24)
160 #define CLOCKSET3_INT_CNTRL(x) (((x) & 0x3f) << 16)
161 #define CLOCKSET3_CPBIAS_CNTRL(x) (((x) & 0x7f) << 8)
162 #define CLOCKSET3_GMP_CNTRL(x) (((x) & 0x3) << 0)
165 #define PHTW_DWEN (1 << 24)
166 #define PHTW_TESTDIN_DATA(x) (((x) & 0xff) << 16)
167 #define PHTW_CWEN (1 << 8)
168 #define PHTW_TESTDIN_CODE(x) (((x) & 0xff) << 0)
171 #define PHTR_TEST (1 << 16)
174 #define PHTC_TESTCLR (1 << 0)
176 #endif /* __RCAR_MIPI_DSI_REGS_H__ */