drivers/gpu/drm/rcar-du/rcar_mipi_dsi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R-Car MIPI DSI Encoder
   4  *
   5  * Copyright (C) 2020 Renesas Electronics Corporation
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_graph.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/reset.h>
  19 #include <linux/slab.h>
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_bridge.h>
  24 #include <drm/drm_mipi_dsi.h>
  25 #include <drm/drm_of.h>
  26 #include <drm/drm_panel.h>
  27 #include <drm/drm_probe_helper.h>
  28
  29 #include "rcar_mipi_dsi.h"
  30 #include "rcar_mipi_dsi_regs.h"
  31
  32 #define MHZ(v) ((u32)((v) * 1000000U))
  33
  34 enum rcar_mipi_dsi_hw_model {
  35         RCAR_DSI_V3U,
  36         RCAR_DSI_V4H,
  37 };
  38
  39 struct rcar_mipi_dsi_device_info {
  40         enum rcar_mipi_dsi_hw_model model;
  41
  42         const struct dsi_clk_config *clk_cfg;
  43
  44         u8 clockset2_m_offset;
  45
  46         u8 n_min;
  47         u8 n_max;
  48         u8 n_mul;
  49         unsigned long fpfd_min;
  50         unsigned long fpfd_max;
  51         u16 m_min;
  52         u16 m_max;
  53         unsigned long fout_min;
  54         unsigned long fout_max;
  55 };
  56
  57 struct rcar_mipi_dsi {
  58         struct device *dev;
  59         const struct rcar_mipi_dsi_device_info *info;
  60         struct reset_control *rstc;
  61
  62         struct mipi_dsi_host host;
  63         struct drm_bridge bridge;
  64         struct drm_bridge *next_bridge;
  65         struct drm_connector connector;
  66
  67         void __iomem *mmio;
  68         struct {
  69                 struct clk *mod;
  70                 struct clk *pll;
  71                 struct clk *dsi;
  72         } clocks;
  73
  74         enum mipi_dsi_pixel_format format;
  75         unsigned int num_data_lanes;
  76         unsigned int lanes;
  77 };
  78
  79 struct dsi_setup_info {
  80         unsigned long hsfreq;
  81         u16 hsfreqrange;
  82
  83         unsigned long fout;
  84         u16 m;
  85         u16 n;
  86         u16 vclk_divider;
  87         const struct dsi_clk_config *clkset;
  88 };
  89
  90 static inline struct rcar_mipi_dsi *
  91 bridge_to_rcar_mipi_dsi(struct drm_bridge *bridge)
  92 {
  93         return container_of(bridge, struct rcar_mipi_dsi, bridge);
  94 }
  95
  96 static inline struct rcar_mipi_dsi *
  97 host_to_rcar_mipi_dsi(struct mipi_dsi_host *host)
  98 {
  99         return container_of(host, struct rcar_mipi_dsi, host);
 100 }
 101
 102 static const u32 hsfreqrange_table[][2] = {
 103         {   MHZ(80), 0x00 }, {   MHZ(90), 0x10 }, {  MHZ(100), 0x20 },
 104         {  MHZ(110), 0x30 }, {  MHZ(120), 0x01 }, {  MHZ(130), 0x11 },
 105         {  MHZ(140), 0x21 }, {  MHZ(150), 0x31 }, {  MHZ(160), 0x02 },
 106         {  MHZ(170), 0x12 }, {  MHZ(180), 0x22 }, {  MHZ(190), 0x32 },
 107         {  MHZ(205), 0x03 }, {  MHZ(220), 0x13 }, {  MHZ(235), 0x23 },
 108         {  MHZ(250), 0x33 }, {  MHZ(275), 0x04 }, {  MHZ(300), 0x14 },
 109         {  MHZ(325), 0x25 }, {  MHZ(350), 0x35 }, {  MHZ(400), 0x05 },
 110         {  MHZ(450), 0x16 }, {  MHZ(500), 0x26 }, {  MHZ(550), 0x37 },
 111         {  MHZ(600), 0x07 }, {  MHZ(650), 0x18 }, {  MHZ(700), 0x28 },
 112         {  MHZ(750), 0x39 }, {  MHZ(800), 0x09 }, {  MHZ(850), 0x19 },
 113         {  MHZ(900), 0x29 }, {  MHZ(950), 0x3a }, { MHZ(1000), 0x0a },
 114         { MHZ(1050), 0x1a }, { MHZ(1100), 0x2a }, { MHZ(1150), 0x3b },
 115         { MHZ(1200), 0x0b }, { MHZ(1250), 0x1b }, { MHZ(1300), 0x2b },
 116         { MHZ(1350), 0x3c }, { MHZ(1400), 0x0c }, { MHZ(1450), 0x1c },
 117         { MHZ(1500), 0x2c }, { MHZ(1550), 0x3d }, { MHZ(1600), 0x0d },
 118         { MHZ(1650), 0x1d }, { MHZ(1700), 0x2e }, { MHZ(1750), 0x3e },
 119         { MHZ(1800), 0x0e }, { MHZ(1850), 0x1e }, { MHZ(1900), 0x2f },
 120         { MHZ(1950), 0x3f }, { MHZ(2000), 0x0f }, { MHZ(2050), 0x40 },
 121         { MHZ(2100), 0x41 }, { MHZ(2150), 0x42 }, { MHZ(2200), 0x43 },
 122         { MHZ(2250), 0x44 }, { MHZ(2300), 0x45 }, { MHZ(2350), 0x46 },
 123         { MHZ(2400), 0x47 }, { MHZ(2450), 0x48 }, { MHZ(2500), 0x49 },
 124         { /* sentinel */ },
 125 };
 126
 127 struct dsi_clk_config {
 128         u32 min_freq;
 129         u32 max_freq;
 130         u8 vco_cntrl;
 131         u8 cpbias_cntrl;
 132         u8 gmp_cntrl;
 133         u8 int_cntrl;
 134         u8 prop_cntrl;
 135 };
 136
 137 static const struct dsi_clk_config dsi_clk_cfg_v3u[] = {
 138         {   MHZ(40),    MHZ(55), 0x3f, 0x10, 0x01, 0x00, 0x0b },
 139         {   MHZ(52.5),  MHZ(80), 0x39, 0x10, 0x01, 0x00, 0x0b },
 140         {   MHZ(80),   MHZ(110), 0x2f, 0x10, 0x01, 0x00, 0x0b },
 141         {  MHZ(105),   MHZ(160), 0x29, 0x10, 0x01, 0x00, 0x0b },
 142         {  MHZ(160),   MHZ(220), 0x1f, 0x10, 0x01, 0x00, 0x0b },
 143         {  MHZ(210),   MHZ(320), 0x19, 0x10, 0x01, 0x00, 0x0b },
 144         {  MHZ(320),   MHZ(440), 0x0f, 0x10, 0x01, 0x00, 0x0b },
 145         {  MHZ(420),   MHZ(660), 0x09, 0x10, 0x01, 0x00, 0x0b },
 146         {  MHZ(630),  MHZ(1149), 0x03, 0x10, 0x01, 0x00, 0x0b },
 147         { MHZ(1100),  MHZ(1152), 0x01, 0x10, 0x01, 0x00, 0x0b },
 148         { MHZ(1150),  MHZ(1250), 0x01, 0x10, 0x01, 0x00, 0x0c },
 149         { /* sentinel */ },
 150 };
 151
 152 static const struct dsi_clk_config dsi_clk_cfg_v4h[] = {
 153         {   MHZ(40),    MHZ(45.31),  0x2b, 0x00, 0x00, 0x08, 0x0a },
 154         {   MHZ(45.31), MHZ(54.66),  0x28, 0x00, 0x00, 0x08, 0x0a },
 155         {   MHZ(54.66), MHZ(62.5),   0x28, 0x00, 0x00, 0x08, 0x0a },
 156         {   MHZ(62.5),  MHZ(75),     0x27, 0x00, 0x00, 0x08, 0x0a },
 157         {   MHZ(75),    MHZ(90.63),  0x23, 0x00, 0x00, 0x08, 0x0a },
 158         {   MHZ(90.63), MHZ(109.37), 0x20, 0x00, 0x00, 0x08, 0x0a },
 159         {  MHZ(109.37), MHZ(125),    0x20, 0x00, 0x00, 0x08, 0x0a },
 160         {  MHZ(125),    MHZ(150),    0x1f, 0x00, 0x00, 0x08, 0x0a },
 161         {  MHZ(150),    MHZ(181.25), 0x1b, 0x00, 0x00, 0x08, 0x0a },
 162         {  MHZ(181.25), MHZ(218.75), 0x18, 0x00, 0x00, 0x08, 0x0a },
 163         {  MHZ(218.75), MHZ(250),    0x18, 0x00, 0x00, 0x08, 0x0a },
 164         {  MHZ(250),    MHZ(300),    0x17, 0x00, 0x00, 0x08, 0x0a },
 165         {  MHZ(300),    MHZ(362.5),  0x13, 0x00, 0x00, 0x08, 0x0a },
 166         {  MHZ(362.5),  MHZ(455.48), 0x10, 0x00, 0x00, 0x08, 0x0a },
 167         {  MHZ(455.48), MHZ(500),    0x10, 0x00, 0x00, 0x08, 0x0a },
 168         {  MHZ(500),    MHZ(600),    0x0f, 0x00, 0x00, 0x08, 0x0a },
 169         {  MHZ(600),    MHZ(725),    0x0b, 0x00, 0x00, 0x08, 0x0a },
 170         {  MHZ(725),    MHZ(875),    0x08, 0x00, 0x00, 0x08, 0x0a },
 171         {  MHZ(875),   MHZ(1000),    0x08, 0x00, 0x00, 0x08, 0x0a },
 172         { MHZ(1000),   MHZ(1200),    0x07, 0x00, 0x00, 0x08, 0x0a },
 173         { MHZ(1200),   MHZ(1250),    0x03, 0x00, 0x00, 0x08, 0x0a },
 174         { /* sentinel */ },
 175 };
 176
 177 static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *dsi, u32 reg, u32 data)
 178 {
 179         iowrite32(data, dsi->mmio + reg);
 180 }
 181
 182 static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *dsi, u32 reg)
 183 {
 184         return ioread32(dsi->mmio + reg);
 185 }
 186
 187 static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *dsi, u32 reg, u32 clr)
 188 {
 189         rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr);
 190 }
 191
 192 static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *dsi, u32 reg, u32 set)
 193 {
 194         rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) | set);
 195 }
 196
 197 static int rcar_mipi_dsi_write_phtw(struct rcar_mipi_dsi *dsi, u32 phtw)
 198 {
 199         u32 status;
 200         int ret;
 201
 202         rcar_mipi_dsi_write(dsi, PHTW, phtw);
 203
 204         ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 205                                 !(status & (PHTW_DWEN | PHTW_CWEN)),
 206                                 2000, 10000, false, dsi, PHTW);
 207         if (ret < 0) {
 208                 dev_err(dsi->dev, "PHY test interface write timeout (0x%08x)\n",
 209                         phtw);
 210                 return ret;
 211         }
 212
 213         return ret;
 214 }
 215
 216 static int rcar_mipi_dsi_write_phtw_arr(struct rcar_mipi_dsi *dsi,
 217                                         const u32 *phtw, unsigned int size)
 218 {
 219         for (unsigned int i = 0; i < size; i++) {
 220                 int ret = rcar_mipi_dsi_write_phtw(dsi, phtw[i]);
 221
 222                 if (ret < 0)
 223                         return ret;
 224         }
 225
 226         return 0;
 227 }
 228
 229 #define WRITE_PHTW(...)                                               \
 230         ({                                                            \
 231                 static const u32 phtw[] = { __VA_ARGS__ };            \
 232                 int ret;                                              \
 233                 ret = rcar_mipi_dsi_write_phtw_arr(dsi, phtw,         \
 234                                                    ARRAY_SIZE(phtw)); \
 235                 ret;                                                  \
 236         })
 237
 238 static int rcar_mipi_dsi_init_phtw_v3u(struct rcar_mipi_dsi *dsi)
 239 {
 240         return WRITE_PHTW(0x01020114, 0x01600115, 0x01030116, 0x0102011d,
 241                           0x011101a4, 0x018601a4, 0x014201a0, 0x010001a3,
 242                           0x0101011f);
 243 }
 244
 245 static int rcar_mipi_dsi_post_init_phtw_v3u(struct rcar_mipi_dsi *dsi)
 246 {
 247         return WRITE_PHTW(0x010c0130, 0x010c0140, 0x010c0150, 0x010c0180,
 248                           0x010c0190, 0x010a0160, 0x010a0170, 0x01800164,
 249                           0x01800174);
 250 }
 251
 252 static int rcar_mipi_dsi_init_phtw_v4h(struct rcar_mipi_dsi *dsi,
 253                                        const struct dsi_setup_info *setup_info)
 254 {
 255         int ret;
 256
 257         if (setup_info->hsfreq < MHZ(450)) {
 258                 ret = WRITE_PHTW(0x01010100, 0x011b01ac);
 259                 if (ret)
 260                         return ret;
 261         }
 262
 263         ret = WRITE_PHTW(0x01010100, 0x01030173, 0x01000174, 0x01500175,
 264                          0x01030176, 0x01040166, 0x010201ad);
 265         if (ret)
 266                 return ret;
 267
 268         if (setup_info->hsfreq <= MHZ(1000))
 269                 ret = WRITE_PHTW(0x01020100, 0x01910170, 0x01020171,
 270                                  0x01110172);
 271         else if (setup_info->hsfreq <= MHZ(1500))
 272                 ret = WRITE_PHTW(0x01020100, 0x01980170, 0x01030171,
 273                                  0x01100172);
 274         else if (setup_info->hsfreq <= MHZ(2500))
 275                 ret = WRITE_PHTW(0x01020100, 0x0144016b, 0x01000172);
 276         else
 277                 return -EINVAL;
 278
 279         if (ret)
 280                 return ret;
 281
 282         if (dsi->lanes <= 1) {
 283                 ret = WRITE_PHTW(0x01070100, 0x010e010b);
 284                 if (ret)
 285                         return ret;
 286         }
 287
 288         if (dsi->lanes <= 2) {
 289                 ret = WRITE_PHTW(0x01090100, 0x010e010b);
 290                 if (ret)
 291                         return ret;
 292         }
 293
 294         if (dsi->lanes <= 3) {
 295                 ret = WRITE_PHTW(0x010b0100, 0x010e010b);
 296                 if (ret)
 297                         return ret;
 298         }
 299
 300         if (setup_info->hsfreq <= MHZ(1500)) {
 301                 ret = WRITE_PHTW(0x01010100, 0x01c0016e);
 302                 if (ret)
 303                         return ret;
 304         }
 305
 306         return 0;
 307 }
 308
 309 static int
 310 rcar_mipi_dsi_post_init_phtw_v4h(struct rcar_mipi_dsi *dsi,
 311                                  const struct dsi_setup_info *setup_info)
 312 {
 313         u32 status;
 314         int ret;
 315
 316         if (setup_info->hsfreq <= MHZ(1500)) {
 317                 WRITE_PHTW(0x01020100, 0x00000180);
 318
 319                 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 320                                         status & PHTR_TEST, 2000, 10000, false,
 321                                         dsi, PHTR);
 322                 if (ret < 0) {
 323                         dev_err(dsi->dev, "failed to test PHTR\n");
 324                         return ret;
 325                 }
 326
 327                 WRITE_PHTW(0x01010100, 0x0100016e);
 328         }
 329
 330         return 0;
 331 }
 332
 333 /* -----------------------------------------------------------------------------
 334  * Hardware Setup
 335  */
 336
 337 static void rcar_mipi_dsi_pll_calc(struct rcar_mipi_dsi *dsi,
 338                                    unsigned long fin_rate,
 339                                    unsigned long fout_target,
 340                                    struct dsi_setup_info *setup_info)
 341 {
 342         unsigned int best_err = -1;
 343         const struct rcar_mipi_dsi_device_info *info = dsi->info;
 344
 345         for (unsigned int n = info->n_min; n <= info->n_max; n++) {
 346                 unsigned long fpfd;
 347
 348                 fpfd = fin_rate / n;
 349
 350                 if (fpfd < info->fpfd_min || fpfd > info->fpfd_max)
 351                         continue;
 352
 353                 for (unsigned int m = info->m_min; m <= info->m_max; m++) {
 354                         unsigned int err;
 355                         u64 fout;
 356
 357                         fout = div64_u64((u64)fpfd * m, dsi->info->n_mul);
 358
 359                         if (fout < info->fout_min || fout > info->fout_max)
 360                                 continue;
 361
 362                         fout = div64_u64(fout, setup_info->vclk_divider);
 363
 364                         if (fout < setup_info->clkset->min_freq ||
 365                             fout > setup_info->clkset->max_freq)
 366                                 continue;
 367
 368                         err = abs((long)(fout - fout_target) * 10000 /
 369                                   (long)fout_target);
 370                         if (err < best_err) {
 371                                 setup_info->m = m;
 372                                 setup_info->n = n;
 373                                 setup_info->fout = (unsigned long)fout;
 374                                 best_err = err;
 375
 376                                 if (err == 0)
 377                                         return;
 378                         }
 379                 }
 380         }
 381 }
 382
 383 static void rcar_mipi_dsi_parameters_calc(struct rcar_mipi_dsi *dsi,
 384                                           struct clk *clk, unsigned long target,
 385                                           struct dsi_setup_info *setup_info)
 386 {
 387
 388         const struct dsi_clk_config *clk_cfg;
 389         unsigned long fout_target;
 390         unsigned long fin_rate;
 391         unsigned int i;
 392         unsigned int err;
 393
 394         /*
 395          * Calculate Fout = dot clock * ColorDepth / (2 * Lane Count)
 396          * The range out Fout is [40 - 1250] Mhz
 397          */
 398         fout_target = target * mipi_dsi_pixel_format_to_bpp(dsi->format)
 399                     / (2 * dsi->lanes);
 400         if (fout_target < MHZ(40) || fout_target > MHZ(1250))
 401                 return;
 402
 403         /* Find PLL settings */
 404         for (clk_cfg = dsi->info->clk_cfg; clk_cfg->min_freq != 0; clk_cfg++) {
 405                 if (fout_target > clk_cfg->min_freq &&
 406                     fout_target <= clk_cfg->max_freq) {
 407                         setup_info->clkset = clk_cfg;
 408                         break;
 409                 }
 410         }
 411
 412         fin_rate = clk_get_rate(clk);
 413
 414         switch (dsi->info->model) {
 415         case RCAR_DSI_V3U:
 416         default:
 417                 setup_info->vclk_divider = 1 << ((clk_cfg->vco_cntrl >> 4) & 0x3);
 418                 break;
 419
 420         case RCAR_DSI_V4H:
 421                 setup_info->vclk_divider = 1 << (((clk_cfg->vco_cntrl >> 3) & 0x7) + 1);
 422                 break;
 423         }
 424
 425         rcar_mipi_dsi_pll_calc(dsi, fin_rate, fout_target, setup_info);
 426
 427         /* Find hsfreqrange */
 428         setup_info->hsfreq = setup_info->fout * 2;
 429         for (i = 0; i < ARRAY_SIZE(hsfreqrange_table); i++) {
 430                 if (hsfreqrange_table[i][0] >= setup_info->hsfreq) {
 431                         setup_info->hsfreqrange = hsfreqrange_table[i][1];
 432                         break;
 433                 }
 434         }
 435
 436         err = abs((long)(setup_info->fout - fout_target) * 10000 / (long)fout_target);
 437
 438         dev_dbg(dsi->dev,
 439                 "Fout = %u * %lu / (%u * %u * %u) = %lu (target %lu Hz, error %d.%02u%%)\n",
 440                 setup_info->m, fin_rate, dsi->info->n_mul, setup_info->n,
 441                 setup_info->vclk_divider, setup_info->fout, fout_target,
 442                 err / 100, err % 100);
 443
 444         dev_dbg(dsi->dev,
 445                 "vco_cntrl = 0x%x\tprop_cntrl = 0x%x\thsfreqrange = 0x%x\n",
 446                 clk_cfg->vco_cntrl, clk_cfg->prop_cntrl,
 447                 setup_info->hsfreqrange);
 448 }
 449
 450 static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi,
 451                                              const struct drm_display_mode *mode)
 452 {
 453         u32 setr;
 454         u32 vprmset0r;
 455         u32 vprmset1r;
 456         u32 vprmset2r;
 457         u32 vprmset3r;
 458         u32 vprmset4r;
 459
 460         /* Configuration for Pixel Stream and Packet Header */
 461         if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 24)
 462                 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB24);
 463         else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 18)
 464                 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB18);
 465         else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 16)
 466                 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB16);
 467         else {
 468                 dev_warn(dsi->dev, "unsupported format");
 469                 return;
 470         }
 471
 472         /* Configuration for Blanking sequence and Input Pixel */
 473         setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN
 474              | TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES
 475              | TXVMSETR_PIXWDTH | TXVMSETR_VSTPM;
 476         rcar_mipi_dsi_write(dsi, TXVMSETR, setr);
 477
 478         /* Configuration for Video Parameters */
 479         vprmset0r = (mode->flags & DRM_MODE_FLAG_PVSYNC ?
 480                      TXVMVPRMSET0R_VSPOL_HIG : TXVMVPRMSET0R_VSPOL_LOW)
 481                   | (mode->flags & DRM_MODE_FLAG_PHSYNC ?
 482                      TXVMVPRMSET0R_HSPOL_HIG : TXVMVPRMSET0R_HSPOL_LOW)
 483                   | TXVMVPRMSET0R_CSPC_RGB | TXVMVPRMSET0R_BPP_24;
 484
 485         vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay)
 486                   | TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start);
 487
 488         vprmset2r = TXVMVPRMSET2R_VFP(mode->vsync_start - mode->vdisplay)
 489                   | TXVMVPRMSET2R_VBP(mode->vtotal - mode->vsync_end);
 490
 491         vprmset3r = TXVMVPRMSET3R_HACTIVE(mode->hdisplay)
 492                   | TXVMVPRMSET3R_HSA(mode->hsync_end - mode->hsync_start);
 493
 494         vprmset4r = TXVMVPRMSET4R_HFP(mode->hsync_start - mode->hdisplay)
 495                   | TXVMVPRMSET4R_HBP(mode->htotal - mode->hsync_end);
 496
 497         rcar_mipi_dsi_write(dsi, TXVMVPRMSET0R, vprmset0r);
 498         rcar_mipi_dsi_write(dsi, TXVMVPRMSET1R, vprmset1r);
 499         rcar_mipi_dsi_write(dsi, TXVMVPRMSET2R, vprmset2r);
 500         rcar_mipi_dsi_write(dsi, TXVMVPRMSET3R, vprmset3r);
 501         rcar_mipi_dsi_write(dsi, TXVMVPRMSET4R, vprmset4r);
 502 }
 503
 504 static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi,
 505                                  const struct drm_display_mode *mode)
 506 {
 507         struct dsi_setup_info setup_info = {};
 508         unsigned int timeout;
 509         int ret;
 510         int dsi_format;
 511         u32 phy_setup;
 512         u32 clockset2, clockset3;
 513         u32 ppisetr;
 514         u32 vclkset;
 515
 516         /* Checking valid format */
 517         dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format);
 518         if (dsi_format < 0) {
 519                 dev_warn(dsi->dev, "invalid format");
 520                 return -EINVAL;
 521         }
 522
 523         /* Parameters Calculation */
 524         rcar_mipi_dsi_parameters_calc(dsi, dsi->clocks.pll,
 525                                       mode->clock * 1000, &setup_info);
 526
 527         /* LPCLK enable */
 528         rcar_mipi_dsi_set(dsi, LPCLKSET, LPCLKSET_CKEN);
 529
 530         /* CFGCLK enabled */
 531         rcar_mipi_dsi_set(dsi, CFGCLKSET, CFGCLKSET_CKEN);
 532
 533         rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
 534         rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
 535
 536         rcar_mipi_dsi_set(dsi, PHTC, PHTC_TESTCLR);
 537         rcar_mipi_dsi_clr(dsi, PHTC, PHTC_TESTCLR);
 538
 539         /* PHY setting */
 540         phy_setup = rcar_mipi_dsi_read(dsi, PHYSETUP);
 541         phy_setup &= ~PHYSETUP_HSFREQRANGE_MASK;
 542         phy_setup |= PHYSETUP_HSFREQRANGE(setup_info.hsfreqrange);
 543         rcar_mipi_dsi_write(dsi, PHYSETUP, phy_setup);
 544
 545         switch (dsi->info->model) {
 546         case RCAR_DSI_V3U:
 547         default:
 548                 ret = rcar_mipi_dsi_init_phtw_v3u(dsi);
 549                 if (ret < 0)
 550                         return ret;
 551                 break;
 552
 553         case RCAR_DSI_V4H:
 554                 ret = rcar_mipi_dsi_init_phtw_v4h(dsi, &setup_info);
 555                 if (ret < 0)
 556                         return ret;
 557                 break;
 558         }
 559
 560         /* PLL Clock Setting */
 561         rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
 562         rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
 563         rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
 564
 565         clockset2 = CLOCKSET2_M(setup_info.m - dsi->info->clockset2_m_offset)
 566                   | CLOCKSET2_N(setup_info.n - 1)
 567                   | CLOCKSET2_VCO_CNTRL(setup_info.clkset->vco_cntrl);
 568         clockset3 = CLOCKSET3_PROP_CNTRL(setup_info.clkset->prop_cntrl)
 569                   | CLOCKSET3_INT_CNTRL(setup_info.clkset->int_cntrl)
 570                   | CLOCKSET3_CPBIAS_CNTRL(setup_info.clkset->cpbias_cntrl)
 571                   | CLOCKSET3_GMP_CNTRL(setup_info.clkset->gmp_cntrl);
 572         rcar_mipi_dsi_write(dsi, CLOCKSET2, clockset2);
 573         rcar_mipi_dsi_write(dsi, CLOCKSET3, clockset3);
 574
 575         rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
 576         rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
 577         udelay(10);
 578         rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
 579
 580         ppisetr = PPISETR_DLEN_3 | PPISETR_CLEN;
 581         rcar_mipi_dsi_write(dsi, PPISETR, ppisetr);
 582
 583         rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
 584         rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_RSTZ);
 585         usleep_range(400, 500);
 586
 587         /* Checking PPI clock status register */
 588         for (timeout = 10; timeout > 0; --timeout) {
 589                 if ((rcar_mipi_dsi_read(dsi, PPICLSR) & PPICLSR_STPST) &&
 590                     (rcar_mipi_dsi_read(dsi, PPIDLSR) & PPIDLSR_STPST) &&
 591                     (rcar_mipi_dsi_read(dsi, CLOCKSET1) & CLOCKSET1_LOCK))
 592                         break;
 593
 594                 usleep_range(1000, 2000);
 595         }
 596
 597         if (!timeout) {
 598                 dev_err(dsi->dev, "failed to enable PPI clock\n");
 599                 return -ETIMEDOUT;
 600         }
 601
 602         switch (dsi->info->model) {
 603         case RCAR_DSI_V3U:
 604         default:
 605                 ret = rcar_mipi_dsi_post_init_phtw_v3u(dsi);
 606                 if (ret < 0)
 607                         return ret;
 608                 break;
 609
 610         case RCAR_DSI_V4H:
 611                 ret = rcar_mipi_dsi_post_init_phtw_v4h(dsi, &setup_info);
 612                 if (ret < 0)
 613                         return ret;
 614                 break;
 615         }
 616
 617         /* Enable DOT clock */
 618         vclkset = VCLKSET_CKEN;
 619         rcar_mipi_dsi_write(dsi, VCLKSET, vclkset);
 620
 621         if (dsi_format == 24)
 622                 vclkset |= VCLKSET_BPP_24;
 623         else if (dsi_format == 18)
 624                 vclkset |= VCLKSET_BPP_18;
 625         else if (dsi_format == 16)
 626                 vclkset |= VCLKSET_BPP_16;
 627         else {
 628                 dev_warn(dsi->dev, "unsupported format");
 629                 return -EINVAL;
 630         }
 631
 632         vclkset |= VCLKSET_COLOR_RGB | VCLKSET_LANE(dsi->lanes - 1);
 633
 634         switch (dsi->info->model) {
 635         case RCAR_DSI_V3U:
 636         default:
 637                 vclkset |= VCLKSET_DIV_V3U(__ffs(setup_info.vclk_divider));
 638                 break;
 639
 640         case RCAR_DSI_V4H:
 641                 vclkset |= VCLKSET_DIV_V4H(__ffs(setup_info.vclk_divider) - 1);
 642                 break;
 643         }
 644
 645         rcar_mipi_dsi_write(dsi, VCLKSET, vclkset);
 646
 647         /* After setting VCLKSET register, enable VCLKEN */
 648         rcar_mipi_dsi_set(dsi, VCLKEN, VCLKEN_CKEN);
 649
 650         dev_dbg(dsi->dev, "DSI device is started\n");
 651
 652         return 0;
 653 }
 654
 655 static void rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi *dsi)
 656 {
 657         /* Disable VCLKEN */
 658         rcar_mipi_dsi_write(dsi, VCLKSET, 0);
 659
 660         /* Disable DOT clock */
 661         rcar_mipi_dsi_write(dsi, VCLKSET, 0);
 662
 663         rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
 664         rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
 665
 666         /* CFGCLK disable */
 667         rcar_mipi_dsi_clr(dsi, CFGCLKSET, CFGCLKSET_CKEN);
 668
 669         /* LPCLK disable */
 670         rcar_mipi_dsi_clr(dsi, LPCLKSET, LPCLKSET_CKEN);
 671
 672         dev_dbg(dsi->dev, "DSI device is shutdown\n");
 673 }
 674
 675 static int rcar_mipi_dsi_clk_enable(struct rcar_mipi_dsi *dsi)
 676 {
 677         int ret;
 678
 679         reset_control_deassert(dsi->rstc);
 680
 681         ret = clk_prepare_enable(dsi->clocks.mod);
 682         if (ret < 0)
 683                 goto err_reset;
 684
 685         ret = clk_prepare_enable(dsi->clocks.dsi);
 686         if (ret < 0)
 687                 goto err_clock;
 688
 689         return 0;
 690
 691 err_clock:
 692         clk_disable_unprepare(dsi->clocks.mod);
 693 err_reset:
 694         reset_control_assert(dsi->rstc);
 695         return ret;
 696 }
 697
 698 static void rcar_mipi_dsi_clk_disable(struct rcar_mipi_dsi *dsi)
 699 {
 700         clk_disable_unprepare(dsi->clocks.dsi);
 701         clk_disable_unprepare(dsi->clocks.mod);
 702
 703         reset_control_assert(dsi->rstc);
 704 }
 705
 706 static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *dsi)
 707 {
 708         /*
 709          * In HW manual, we need to check TxDDRClkHS-Q Stable? but it dont
 710          * write how to check. So we skip this check in this patch
 711          */
 712         u32 status;
 713         int ret;
 714
 715         /* Start HS clock. */
 716         rcar_mipi_dsi_set(dsi, PPICLCR, PPICLCR_TXREQHS);
 717
 718         ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 719                                 status & PPICLSR_TOHS,
 720                                 2000, 10000, false, dsi, PPICLSR);
 721         if (ret < 0) {
 722                 dev_err(dsi->dev, "failed to enable HS clock\n");
 723                 return ret;
 724         }
 725
 726         rcar_mipi_dsi_set(dsi, PPICLSCR, PPICLSCR_TOHS);
 727
 728         return 0;
 729 }
 730
 731 static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *dsi)
 732 {
 733         u32 status;
 734         int ret;
 735
 736         /* Wait for the link to be ready. */
 737         ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 738                                 !(status & (LINKSR_LPBUSY | LINKSR_HSBUSY)),
 739                                 2000, 10000, false, dsi, LINKSR);
 740         if (ret < 0) {
 741                 dev_err(dsi->dev, "Link failed to become ready\n");
 742                 return ret;
 743         }
 744
 745         /* De-assert video FIFO clear. */
 746         rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_VFCLR);
 747
 748         ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 749                                 status & TXVMSR_VFRDY,
 750                                 2000, 10000, false, dsi, TXVMSR);
 751         if (ret < 0) {
 752                 dev_err(dsi->dev, "Failed to de-assert video FIFO clear\n");
 753                 return ret;
 754         }
 755
 756         /* Enable transmission in video mode. */
 757         rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_EN_VIDEO);
 758
 759         ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 760                                 status & TXVMSR_RDY,
 761                                 2000, 10000, false, dsi, TXVMSR);
 762         if (ret < 0) {
 763                 dev_err(dsi->dev, "Failed to enable video transmission\n");
 764                 return ret;
 765         }
 766
 767         return 0;
 768 }
 769
 770 static void rcar_mipi_dsi_stop_video(struct rcar_mipi_dsi *dsi)
 771 {
 772         u32 status;
 773         int ret;
 774
 775         /* Disable transmission in video mode. */
 776         rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_EN_VIDEO);
 777
 778         ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 779                                 !(status & TXVMSR_ACT),
 780                                 2000, 100000, false, dsi, TXVMSR);
 781         if (ret < 0) {
 782                 dev_err(dsi->dev, "Failed to disable video transmission\n");
 783                 return;
 784         }
 785
 786         /* Assert video FIFO clear. */
 787         rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_VFCLR);
 788
 789         ret = read_poll_timeout(rcar_mipi_dsi_read, status,
 790                                 !(status & TXVMSR_VFRDY),
 791                                 2000, 100000, false, dsi, TXVMSR);
 792         if (ret < 0) {
 793                 dev_err(dsi->dev, "Failed to assert video FIFO clear\n");
 794                 return;
 795         }
 796 }
 797
 798 /* -----------------------------------------------------------------------------
 799  * Bridge
 800  */
 801
 802 static int rcar_mipi_dsi_attach(struct drm_bridge *bridge,
 803                                 enum drm_bridge_attach_flags flags)
 804 {
 805         struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
 806
 807         return drm_bridge_attach(bridge->encoder, dsi->next_bridge, bridge,
 808                                  flags);
 809 }
 810
 811 static void rcar_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
 812                                         struct drm_bridge_state *old_bridge_state)
 813 {
 814         struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
 815
 816         rcar_mipi_dsi_start_video(dsi);
 817 }
 818
 819 static void rcar_mipi_dsi_atomic_disable(struct drm_bridge *bridge,
 820                                          struct drm_bridge_state *old_bridge_state)
 821 {
 822         struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
 823
 824         rcar_mipi_dsi_stop_video(dsi);
 825 }
 826
 827 void rcar_mipi_dsi_pclk_enable(struct drm_bridge *bridge,
 828                                struct drm_atomic_state *state)
 829 {
 830         struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
 831         const struct drm_display_mode *mode;
 832         struct drm_connector *connector;
 833         struct drm_crtc *crtc;
 834         int ret;
 835
 836         connector = drm_atomic_get_new_connector_for_encoder(state,
 837                                                              bridge->encoder);
 838         crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
 839         mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode;
 840
 841         ret = rcar_mipi_dsi_clk_enable(dsi);
 842         if (ret < 0) {
 843                 dev_err(dsi->dev, "failed to enable DSI clocks\n");
 844                 return;
 845         }
 846
 847         ret = rcar_mipi_dsi_startup(dsi, mode);
 848         if (ret < 0)
 849                 goto err_dsi_startup;
 850
 851         rcar_mipi_dsi_set_display_timing(dsi, mode);
 852
 853         ret = rcar_mipi_dsi_start_hs_clock(dsi);
 854         if (ret < 0)
 855                 goto err_dsi_start_hs;
 856
 857         return;
 858
 859 err_dsi_start_hs:
 860         rcar_mipi_dsi_shutdown(dsi);
 861 err_dsi_startup:
 862         rcar_mipi_dsi_clk_disable(dsi);
 863 }
 864 EXPORT_SYMBOL_GPL(rcar_mipi_dsi_pclk_enable);
 865
 866 void rcar_mipi_dsi_pclk_disable(struct drm_bridge *bridge)
 867 {
 868         struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
 869
 870         rcar_mipi_dsi_shutdown(dsi);
 871         rcar_mipi_dsi_clk_disable(dsi);
 872 }
 873 EXPORT_SYMBOL_GPL(rcar_mipi_dsi_pclk_disable);
 874
 875 static enum drm_mode_status
 876 rcar_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
 877                                 const struct drm_display_info *info,
 878                                 const struct drm_display_mode *mode)
 879 {
 880         if (mode->clock > 297000)
 881                 return MODE_CLOCK_HIGH;
 882
 883         return MODE_OK;
 884 }
 885
 886 static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = {
 887         .attach = rcar_mipi_dsi_attach,
 888         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 889         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
 890         .atomic_reset = drm_atomic_helper_bridge_reset,
 891         .atomic_enable = rcar_mipi_dsi_atomic_enable,
 892         .atomic_disable = rcar_mipi_dsi_atomic_disable,
 893         .mode_valid = rcar_mipi_dsi_bridge_mode_valid,
 894 };
 895
 896 /* -----------------------------------------------------------------------------
 897  * Host setting
 898  */
 899
 900 static int rcar_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 901                                      struct mipi_dsi_device *device)
 902 {
 903         struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
 904         int ret;
 905
 906         if (device->lanes > dsi->num_data_lanes)
 907                 return -EINVAL;
 908
 909         dsi->lanes = device->lanes;
 910         dsi->format = device->format;
 911
 912         dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
 913                                                   1, 0);
 914         if (IS_ERR(dsi->next_bridge)) {
 915                 ret = PTR_ERR(dsi->next_bridge);
 916                 dev_err(dsi->dev, "failed to get next bridge: %d\n", ret);
 917                 return ret;
 918         }
 919
 920         /* Initialize the DRM bridge. */
 921         dsi->bridge.funcs = &rcar_mipi_dsi_bridge_ops;
 922         dsi->bridge.of_node = dsi->dev->of_node;
 923         drm_bridge_add(&dsi->bridge);
 924
 925         return 0;
 926 }
 927
 928 static int rcar_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 929                                         struct mipi_dsi_device *device)
 930 {
 931         struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
 932
 933         drm_bridge_remove(&dsi->bridge);
 934
 935         return 0;
 936 }
 937
 938 static const struct mipi_dsi_host_ops rcar_mipi_dsi_host_ops = {
 939         .attach = rcar_mipi_dsi_host_attach,
 940         .detach = rcar_mipi_dsi_host_detach,
 941 };
 942
 943 /* -----------------------------------------------------------------------------
 944  * Probe & Remove
 945  */
 946
 947 static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *dsi)
 948 {
 949         int ret;
 950
 951         ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
 952         if (ret < 0) {
 953                 dev_err(dsi->dev, "missing or invalid data-lanes property\n");
 954                 return ret;
 955         }
 956
 957         dsi->num_data_lanes = ret;
 958         return 0;
 959 }
 960
 961 static struct clk *rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi *dsi,
 962                                            const char *name,
 963                                            bool optional)
 964 {
 965         struct clk *clk;
 966
 967         clk = devm_clk_get(dsi->dev, name);
 968         if (!IS_ERR(clk))
 969                 return clk;
 970
 971         if (PTR_ERR(clk) == -ENOENT && optional)
 972                 return NULL;
 973
 974         dev_err_probe(dsi->dev, PTR_ERR(clk), "failed to get %s clock\n",
 975                       name ? name : "module");
 976
 977         return clk;
 978 }
 979
 980 static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *dsi)
 981 {
 982         dsi->clocks.mod = rcar_mipi_dsi_get_clock(dsi, NULL, false);
 983         if (IS_ERR(dsi->clocks.mod))
 984                 return PTR_ERR(dsi->clocks.mod);
 985
 986         dsi->clocks.pll = rcar_mipi_dsi_get_clock(dsi, "pll", true);
 987         if (IS_ERR(dsi->clocks.pll))
 988                 return PTR_ERR(dsi->clocks.pll);
 989
 990         dsi->clocks.dsi = rcar_mipi_dsi_get_clock(dsi, "dsi", true);
 991         if (IS_ERR(dsi->clocks.dsi))
 992                 return PTR_ERR(dsi->clocks.dsi);
 993
 994         if (!dsi->clocks.pll && !dsi->clocks.dsi) {
 995                 dev_err(dsi->dev, "no input clock (pll, dsi)\n");
 996                 return -EINVAL;
 997         }
 998
 999         return 0;
1000 }
1001
1002 static int rcar_mipi_dsi_probe(struct platform_device *pdev)
1003 {
1004         struct rcar_mipi_dsi *dsi;
1005         struct resource *mem;
1006         int ret;
1007
1008         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1009         if (dsi == NULL)
1010                 return -ENOMEM;
1011
1012         platform_set_drvdata(pdev, dsi);
1013
1014         dsi->dev = &pdev->dev;
1015         dsi->info = of_device_get_match_data(&pdev->dev);
1016
1017         ret = rcar_mipi_dsi_parse_dt(dsi);
1018         if (ret < 0)
1019                 return ret;
1020
1021         /* Acquire resources. */
1022         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1023         dsi->mmio = devm_ioremap_resource(dsi->dev, mem);
1024         if (IS_ERR(dsi->mmio))
1025                 return PTR_ERR(dsi->mmio);
1026
1027         ret = rcar_mipi_dsi_get_clocks(dsi);
1028         if (ret < 0)
1029                 return ret;
1030
1031         dsi->rstc = devm_reset_control_get(dsi->dev, NULL);
1032         if (IS_ERR(dsi->rstc)) {
1033                 dev_err(dsi->dev, "failed to get cpg reset\n");
1034                 return PTR_ERR(dsi->rstc);
1035         }
1036
1037         /* Initialize the DSI host. */
1038         dsi->host.dev = dsi->dev;
1039         dsi->host.ops = &rcar_mipi_dsi_host_ops;
1040         ret = mipi_dsi_host_register(&dsi->host);
1041         if (ret < 0)
1042                 return ret;
1043
1044         return 0;
1045 }
1046
1047 static int rcar_mipi_dsi_remove(struct platform_device *pdev)
1048 {
1049         struct rcar_mipi_dsi *dsi = platform_get_drvdata(pdev);
1050
1051         mipi_dsi_host_unregister(&dsi->host);
1052
1053         return 0;
1054 }
1055
1056 static const struct rcar_mipi_dsi_device_info v3u_data = {
1057         .model = RCAR_DSI_V3U,
1058         .clk_cfg = dsi_clk_cfg_v3u,
1059         .clockset2_m_offset = 2,
1060         .n_min = 3,
1061         .n_max = 8,
1062         .n_mul = 1,
1063         .fpfd_min = MHZ(2),
1064         .fpfd_max = MHZ(8),
1065         .m_min = 64,
1066         .m_max = 625,
1067         .fout_min = MHZ(320),
1068         .fout_max = MHZ(1250),
1069 };
1070
1071 static const struct rcar_mipi_dsi_device_info v4h_data = {
1072         .model = RCAR_DSI_V4H,
1073         .clk_cfg = dsi_clk_cfg_v4h,
1074         .clockset2_m_offset = 0,
1075         .n_min = 1,
1076         .n_max = 8,
1077         .n_mul = 2,
1078         .fpfd_min = MHZ(8),
1079         .fpfd_max = MHZ(24),
1080         .m_min = 167,
1081         .m_max = 1000,
1082         .fout_min = MHZ(2000),
1083         .fout_max = MHZ(4000),
1084 };
1085
1086 static const struct of_device_id rcar_mipi_dsi_of_table[] = {
1087         { .compatible = "renesas,r8a779a0-dsi-csi2-tx", .data = &v3u_data },
1088         { .compatible = "renesas,r8a779g0-dsi-csi2-tx", .data = &v4h_data },
1089         { }
1090 };
1091
1092 MODULE_DEVICE_TABLE(of, rcar_mipi_dsi_of_table);
1093
1094 static struct platform_driver rcar_mipi_dsi_platform_driver = {
1095         .probe          = rcar_mipi_dsi_probe,
1096         .remove         = rcar_mipi_dsi_remove,
1097         .driver         = {
1098                 .name   = "rcar-mipi-dsi",
1099                 .of_match_table = rcar_mipi_dsi_of_table,
1100         },
1101 };
1102
1103 module_platform_driver(rcar_mipi_dsi_platform_driver);
1104
1105 MODULE_DESCRIPTION("Renesas R-Car MIPI DSI Encoder Driver");
1106 MODULE_LICENSE("GPL");