1 // SPDX-License-Identifier: GPL-2.0
3 * rcar_lvds.c -- R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
10 #include <linux/clk.h>
11 #include <linux/delay.h>
13 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/of_graph.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
20 #include <drm/drm_atomic.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_bridge.h>
23 #include <drm/drm_panel.h>
24 #include <drm/drm_probe_helper.h>
26 #include "rcar_lvds.h"
27 #include "rcar_lvds_regs.h"
31 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
33 RCAR_LVDS_MODE_JEIDA = 0,
34 RCAR_LVDS_MODE_MIRROR = 1,
35 RCAR_LVDS_MODE_VESA = 4,
38 #define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */
39 #define RCAR_LVDS_QUIRK_GEN3_LVEN BIT(1) /* LVEN bit needs to be set on R8A77970/R8A7799x */
40 #define RCAR_LVDS_QUIRK_PWD BIT(2) /* PWD bit available (all of Gen3 but E3) */
41 #define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
42 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
44 struct rcar_lvds_device_info {
47 void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
52 const struct rcar_lvds_device_info *info;
54 struct drm_bridge bridge;
56 struct drm_bridge *next_bridge;
57 struct drm_connector connector;
58 struct drm_panel *panel;
62 struct clk *mod; /* CPG module clock */
63 struct clk *extal; /* External clock */
64 struct clk *dotclkin[2]; /* External DU clocks */
67 struct drm_display_mode display_mode;
68 enum rcar_lvds_mode mode;
70 struct drm_bridge *companion;
74 #define bridge_to_rcar_lvds(bridge) \
75 container_of(bridge, struct rcar_lvds, bridge)
77 #define connector_to_rcar_lvds(connector) \
78 container_of(connector, struct rcar_lvds, connector)
80 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
82 iowrite32(data, lvds->mmio + reg);
85 /* -----------------------------------------------------------------------------
89 static int rcar_lvds_connector_get_modes(struct drm_connector *connector)
91 struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
93 return drm_panel_get_modes(lvds->panel);
96 static int rcar_lvds_connector_atomic_check(struct drm_connector *connector,
97 struct drm_atomic_state *state)
99 struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
100 const struct drm_display_mode *panel_mode;
101 struct drm_connector_state *conn_state;
102 struct drm_crtc_state *crtc_state;
104 conn_state = drm_atomic_get_new_connector_state(state, connector);
105 if (!conn_state->crtc)
108 if (list_empty(&connector->modes)) {
109 dev_dbg(lvds->dev, "connector: empty modes list\n");
113 panel_mode = list_first_entry(&connector->modes,
114 struct drm_display_mode, head);
116 /* We're not allowed to modify the resolution. */
117 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
118 if (IS_ERR(crtc_state))
119 return PTR_ERR(crtc_state);
121 if (crtc_state->mode.hdisplay != panel_mode->hdisplay ||
122 crtc_state->mode.vdisplay != panel_mode->vdisplay)
125 /* The flat panel mode is fixed, just copy it to the adjusted mode. */
126 drm_mode_copy(&crtc_state->adjusted_mode, panel_mode);
131 static const struct drm_connector_helper_funcs rcar_lvds_conn_helper_funcs = {
132 .get_modes = rcar_lvds_connector_get_modes,
133 .atomic_check = rcar_lvds_connector_atomic_check,
136 static const struct drm_connector_funcs rcar_lvds_conn_funcs = {
137 .reset = drm_atomic_helper_connector_reset,
138 .fill_modes = drm_helper_probe_single_connector_modes,
139 .destroy = drm_connector_cleanup,
140 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
141 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
144 /* -----------------------------------------------------------------------------
148 static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
153 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
154 else if (freq < 61000000)
155 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
156 else if (freq < 121000000)
157 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
159 val = LVDPLLCR_PLLDLYCNT_150M;
161 rcar_lvds_write(lvds, LVDPLLCR, val);
164 static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
169 val = LVDPLLCR_PLLDIVCNT_42M;
170 else if (freq < 85000000)
171 val = LVDPLLCR_PLLDIVCNT_85M;
172 else if (freq < 128000000)
173 val = LVDPLLCR_PLLDIVCNT_128M;
175 val = LVDPLLCR_PLLDIVCNT_148M;
177 rcar_lvds_write(lvds, LVDPLLCR, val);
189 static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
190 unsigned long target, struct pll_info *pll,
191 u32 clksel, bool dot_clock_only)
193 unsigned int div7 = dot_clock_only ? 1 : 7;
194 unsigned long output;
205 * The LVDS PLL is made of a pre-divider and a multiplier (strangely
206 * enough called M and N respectively), followed by a post-divider E.
208 * ,-----. ,-----. ,-----. ,-----.
209 * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
210 * `-----' ,-> | | `-----' | `-----'
213 * `-------- | 1/N | <-------'
216 * The clock output by the PLL is then further divided by a programmable
217 * divider DIV to achieve the desired target frequency. Finally, an
218 * optional fixed /7 divider is used to convert the bit clock to a pixel
219 * clock (as LVDS transmits 7 bits per lane per clock sample).
221 * ,-------. ,-----. |\
222 * Fout --> | 1/DIV | --> | 1/7 | --> | |
223 * `-------' | `-----' | | --> dot clock
227 * The /7 divider is optional, it is enabled when the LVDS PLL is used
228 * to drive the LVDS encoder, and disabled when used to generate a dot
229 * clock for the DU RGB output, without using the LVDS encoder.
231 * The PLL allowed input frequency range is 12 MHz to 192 MHz.
234 fin = clk_get_rate(clk);
235 if (fin < 12000000 || fin > 192000000)
239 * The comparison frequency range is 12 MHz to 24 MHz, which limits the
240 * allowed values for the pre-divider M (normal range 1-8).
244 m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
245 m_max = min_t(unsigned int, 8, fin / 12000000);
247 for (m = m_min; m <= m_max; ++m) {
254 * The VCO operating range is 900 Mhz to 1800 MHz, which limits
255 * the allowed values for the multiplier N (normal range
261 n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
262 n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
264 for (n = n_min; n < n_max; ++n) {
270 * The output frequency is limited to 1039.5 MHz,
271 * limiting again the allowed values for the
272 * post-divider E (normal value 1, 2 or 4).
277 e_min = fvco > 1039500000 ? 1 : 0;
279 for (e = e_min; e < 3; ++e) {
285 * Finally we have a programable divider after
286 * the PLL, followed by a an optional fixed /7
289 fout = fvco / (1 << e) / div7;
290 div = max(1UL, DIV_ROUND_CLOSEST(fout, target));
291 diff = abs(fout / div - target);
293 if (diff < pll->diff) {
299 pll->clksel = clksel;
309 output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
311 error = (long)(output - target) * 10000 / (long)target;
314 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
315 clk, fin, output, target, error / 100,
316 error < 0 ? -error % 100 : error % 100,
317 pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
320 static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds,
321 unsigned int freq, bool dot_clock_only)
323 struct pll_info pll = { .diff = (unsigned long)-1 };
326 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
327 LVDPLLCR_CKSEL_DU_DOTCLKIN(0), dot_clock_only);
328 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
329 LVDPLLCR_CKSEL_DU_DOTCLKIN(1), dot_clock_only);
330 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
331 LVDPLLCR_CKSEL_EXTAL, dot_clock_only);
333 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
334 | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
337 lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
338 | LVDPLLCR_PLLE(pll.pll_e - 1);
341 lvdpllcr |= LVDPLLCR_OCKSEL;
343 rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
347 * The DIVRESET bit is a misnomer, setting it to 1 deasserts the
350 rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
351 LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
353 rcar_lvds_write(lvds, LVDDIV, 0);
356 static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
358 __rcar_lvds_pll_setup_d3_e3(lvds, freq, false);
361 /* -----------------------------------------------------------------------------
365 int rcar_lvds_clk_enable(struct drm_bridge *bridge, unsigned long freq)
367 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
370 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
373 dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq);
375 ret = clk_prepare_enable(lvds->clocks.mod);
379 __rcar_lvds_pll_setup_d3_e3(lvds, freq, true);
383 EXPORT_SYMBOL_GPL(rcar_lvds_clk_enable);
385 void rcar_lvds_clk_disable(struct drm_bridge *bridge)
387 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
389 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
392 dev_dbg(lvds->dev, "disabling LVDS PLL\n");
394 rcar_lvds_write(lvds, LVDPLLCR, 0);
396 clk_disable_unprepare(lvds->clocks.mod);
398 EXPORT_SYMBOL_GPL(rcar_lvds_clk_disable);
400 /* -----------------------------------------------------------------------------
404 static void rcar_lvds_enable(struct drm_bridge *bridge)
406 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
407 const struct drm_display_mode *mode = &lvds->display_mode;
412 ret = clk_prepare_enable(lvds->clocks.mod);
416 /* Enable the companion LVDS encoder in dual-link mode. */
417 if (lvds->dual_link && lvds->companion)
418 lvds->companion->funcs->enable(lvds->companion);
421 * Hardcode the channels and control signals routing for now.
428 rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
429 LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
430 LVDCTRCR_CTR0SEL_HSYNC);
432 if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
433 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
434 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
436 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
437 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
439 rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
441 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
443 * Configure vertical stripe based on the mode of operation of
444 * the connected device.
446 rcar_lvds_write(lvds, LVDSTRIPE,
447 lvds->dual_link ? LVDSTRIPE_ST_ON : 0);
451 * PLL clock configuration on all instances but the companion in
454 if (!lvds->dual_link || lvds->companion)
455 lvds->info->pll_setup(lvds, mode->clock * 1000);
457 /* Set the LVDS mode and select the input. */
458 lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
460 if (lvds->bridge.encoder) {
462 * FIXME: We should really retrieve the CRTC through the state,
463 * but how do we get a state pointer?
465 if (drm_crtc_index(lvds->bridge.encoder->crtc) == 2)
466 lvdcr0 |= LVDCR0_DUSEL;
469 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
471 /* Turn all the channels on. */
472 rcar_lvds_write(lvds, LVDCR1,
473 LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
474 LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
476 if (lvds->info->gen < 3) {
477 /* Enable LVDS operation and turn the bias circuitry on. */
478 lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
479 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
482 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
484 * Turn the PLL on (simple PLL only, extended PLL is fully
485 * controlled through LVDPLLCR).
487 lvdcr0 |= LVDCR0_PLLON;
488 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
491 if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
492 /* Set LVDS normal mode. */
493 lvdcr0 |= LVDCR0_PWD;
494 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
497 if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
499 * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be
500 * set at the same time, so don't write the register yet.
502 lvdcr0 |= LVDCR0_LVEN;
503 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD))
504 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
507 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
508 /* Wait for the PLL startup delay (simple PLL only). */
509 usleep_range(100, 150);
512 /* Turn the output on. */
513 lvdcr0 |= LVDCR0_LVRES;
514 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
517 drm_panel_prepare(lvds->panel);
518 drm_panel_enable(lvds->panel);
522 static void rcar_lvds_disable(struct drm_bridge *bridge)
524 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
527 drm_panel_disable(lvds->panel);
528 drm_panel_unprepare(lvds->panel);
531 rcar_lvds_write(lvds, LVDCR0, 0);
532 rcar_lvds_write(lvds, LVDCR1, 0);
533 rcar_lvds_write(lvds, LVDPLLCR, 0);
535 /* Disable the companion LVDS encoder in dual-link mode. */
536 if (lvds->dual_link && lvds->companion)
537 lvds->companion->funcs->disable(lvds->companion);
539 clk_disable_unprepare(lvds->clocks.mod);
542 static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
543 const struct drm_display_mode *mode,
544 struct drm_display_mode *adjusted_mode)
546 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
550 * The internal LVDS encoder has a restricted clock frequency operating
551 * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to
552 * 148.5MHz on all other platforms. Clamp the clock accordingly.
554 min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
555 adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
560 static void rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds)
562 struct drm_display_info *info = &lvds->connector.display_info;
563 enum rcar_lvds_mode mode;
566 * There is no API yet to retrieve LVDS mode from a bridge, only panels
572 if (!info->num_bus_formats || !info->bus_formats) {
573 dev_err(lvds->dev, "no LVDS bus format reported\n");
577 switch (info->bus_formats[0]) {
578 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
579 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
580 mode = RCAR_LVDS_MODE_JEIDA;
582 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
583 mode = RCAR_LVDS_MODE_VESA;
586 dev_err(lvds->dev, "unsupported LVDS bus format 0x%04x\n",
587 info->bus_formats[0]);
591 if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
592 mode |= RCAR_LVDS_MODE_MIRROR;
597 static void rcar_lvds_mode_set(struct drm_bridge *bridge,
598 const struct drm_display_mode *mode,
599 const struct drm_display_mode *adjusted_mode)
601 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
603 lvds->display_mode = *adjusted_mode;
605 rcar_lvds_get_lvds_mode(lvds);
608 static int rcar_lvds_attach(struct drm_bridge *bridge)
610 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
611 struct drm_connector *connector = &lvds->connector;
612 struct drm_encoder *encoder = bridge->encoder;
615 /* If we have a next bridge just attach it. */
616 if (lvds->next_bridge)
617 return drm_bridge_attach(bridge->encoder, lvds->next_bridge,
620 /* Otherwise if we have a panel, create a connector. */
624 ret = drm_connector_init(bridge->dev, connector, &rcar_lvds_conn_funcs,
625 DRM_MODE_CONNECTOR_LVDS);
629 drm_connector_helper_add(connector, &rcar_lvds_conn_helper_funcs);
631 ret = drm_connector_attach_encoder(connector, encoder);
635 return drm_panel_attach(lvds->panel, connector);
638 static void rcar_lvds_detach(struct drm_bridge *bridge)
640 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
643 drm_panel_detach(lvds->panel);
646 static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
647 .attach = rcar_lvds_attach,
648 .detach = rcar_lvds_detach,
649 .enable = rcar_lvds_enable,
650 .disable = rcar_lvds_disable,
651 .mode_fixup = rcar_lvds_mode_fixup,
652 .mode_set = rcar_lvds_mode_set,
655 bool rcar_lvds_dual_link(struct drm_bridge *bridge)
657 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
659 return lvds->dual_link;
661 EXPORT_SYMBOL_GPL(rcar_lvds_dual_link);
663 /* -----------------------------------------------------------------------------
667 static int rcar_lvds_parse_dt_companion(struct rcar_lvds *lvds)
669 const struct of_device_id *match;
670 struct device_node *companion;
671 struct device *dev = lvds->dev;
674 /* Locate the companion LVDS encoder for dual-link operation, if any. */
675 companion = of_parse_phandle(dev->of_node, "renesas,companion", 0);
680 * Sanity check: the companion encoder must have the same compatible
683 match = of_match_device(dev->driver->of_match_table, dev);
684 if (!of_device_is_compatible(companion, match->compatible)) {
685 dev_err(dev, "Companion LVDS encoder is invalid\n");
690 lvds->companion = of_drm_find_bridge(companion);
691 if (!lvds->companion) {
696 dev_dbg(dev, "Found companion encoder %pOF\n", companion);
699 of_node_put(companion);
704 static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
706 struct device_node *local_output = NULL;
707 struct device_node *remote_input = NULL;
708 struct device_node *remote = NULL;
709 struct device_node *node;
710 bool is_bridge = false;
713 local_output = of_graph_get_endpoint_by_regs(lvds->dev->of_node, 1, 0);
715 dev_dbg(lvds->dev, "unconnected port@1\n");
721 * Locate the connected entity and infer its type from the number of
724 remote = of_graph_get_remote_port_parent(local_output);
726 dev_dbg(lvds->dev, "unconnected endpoint %pOF\n", local_output);
731 if (!of_device_is_available(remote)) {
732 dev_dbg(lvds->dev, "connected entity %pOF is disabled\n",
738 remote_input = of_graph_get_remote_endpoint(local_output);
740 for_each_endpoint_of_node(remote, node) {
741 if (node != remote_input) {
743 * We've found one endpoint other than the input, this
753 lvds->next_bridge = of_drm_find_bridge(remote);
754 if (!lvds->next_bridge) {
759 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK)
760 lvds->dual_link = lvds->next_bridge->timings
761 ? lvds->next_bridge->timings->dual_link
764 lvds->panel = of_drm_find_panel(remote);
765 if (IS_ERR(lvds->panel)) {
766 ret = PTR_ERR(lvds->panel);
772 ret = rcar_lvds_parse_dt_companion(lvds);
775 of_node_put(local_output);
776 of_node_put(remote_input);
780 * On D3/E3 the LVDS encoder provides a clock to the DU, which can be
781 * used for the DPAD output even when the LVDS output is not connected.
782 * Don't fail probe in that case as the DU will need the bridge to
785 if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
786 return ret == -ENODEV ? 0 : ret;
791 static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
796 clk = devm_clk_get(lvds->dev, name);
800 if (PTR_ERR(clk) == -ENOENT && optional)
803 if (PTR_ERR(clk) != -EPROBE_DEFER)
804 dev_err(lvds->dev, "failed to get %s clock\n",
805 name ? name : "module");
810 static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
812 lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
813 if (IS_ERR(lvds->clocks.mod))
814 return PTR_ERR(lvds->clocks.mod);
817 * LVDS encoders without an extended PLL have no external clock inputs.
819 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
822 lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
823 if (IS_ERR(lvds->clocks.extal))
824 return PTR_ERR(lvds->clocks.extal);
826 lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
827 if (IS_ERR(lvds->clocks.dotclkin[0]))
828 return PTR_ERR(lvds->clocks.dotclkin[0]);
830 lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
831 if (IS_ERR(lvds->clocks.dotclkin[1]))
832 return PTR_ERR(lvds->clocks.dotclkin[1]);
834 /* At least one input to the PLL must be available. */
835 if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
836 !lvds->clocks.dotclkin[1]) {
838 "no input clock (extal, dclkin.0 or dclkin.1)\n");
845 static int rcar_lvds_probe(struct platform_device *pdev)
847 struct rcar_lvds *lvds;
848 struct resource *mem;
851 lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
855 platform_set_drvdata(pdev, lvds);
857 lvds->dev = &pdev->dev;
858 lvds->info = of_device_get_match_data(&pdev->dev);
860 ret = rcar_lvds_parse_dt(lvds);
864 lvds->bridge.driver_private = lvds;
865 lvds->bridge.funcs = &rcar_lvds_bridge_ops;
866 lvds->bridge.of_node = pdev->dev.of_node;
868 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
869 lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
870 if (IS_ERR(lvds->mmio))
871 return PTR_ERR(lvds->mmio);
873 ret = rcar_lvds_get_clocks(lvds);
877 drm_bridge_add(&lvds->bridge);
882 static int rcar_lvds_remove(struct platform_device *pdev)
884 struct rcar_lvds *lvds = platform_get_drvdata(pdev);
886 drm_bridge_remove(&lvds->bridge);
891 static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
893 .pll_setup = rcar_lvds_pll_setup_gen2,
896 static const struct rcar_lvds_device_info rcar_lvds_r8a7790_info = {
898 .quirks = RCAR_LVDS_QUIRK_LANES,
899 .pll_setup = rcar_lvds_pll_setup_gen2,
902 static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
904 .quirks = RCAR_LVDS_QUIRK_PWD,
905 .pll_setup = rcar_lvds_pll_setup_gen3,
908 static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
910 .quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
911 .pll_setup = rcar_lvds_pll_setup_gen2,
914 static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
916 .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
917 | RCAR_LVDS_QUIRK_DUAL_LINK,
918 .pll_setup = rcar_lvds_pll_setup_d3_e3,
921 static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
923 .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
924 | RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
925 .pll_setup = rcar_lvds_pll_setup_d3_e3,
928 static const struct of_device_id rcar_lvds_of_table[] = {
929 { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
930 { .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info },
931 { .compatible = "renesas,r8a774a1-lvds", .data = &rcar_lvds_gen3_info },
932 { .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
933 { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info },
934 { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
935 { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
936 { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
937 { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
938 { .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
939 { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
940 { .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
941 { .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
942 { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
946 MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
948 static struct platform_driver rcar_lvds_platform_driver = {
949 .probe = rcar_lvds_probe,
950 .remove = rcar_lvds_remove,
953 .of_match_table = rcar_lvds_of_table,
957 module_platform_driver(rcar_lvds_platform_driver);
959 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
960 MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
961 MODULE_LICENSE("GPL");