drivers/gpu/drm/rcar-du/rcar_du_drv.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * R-Car Display Unit DRM driver
   4  *
   5  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/io.h>
  13 #include <linux/mm.h>
  14 #include <linux/module.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm.h>
  18 #include <linux/slab.h>
  19 #include <linux/sys_soc.h>
  20 #include <linux/wait.h>
  21
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_drv.h>
  24 #include <drm/drm_fbdev_generic.h>
  25 #include <drm/drm_gem_dma_helper.h>
  26 #include <drm/drm_managed.h>
  27 #include <drm/drm_probe_helper.h>
  28
  29 #include "rcar_du_drv.h"
  30 #include "rcar_du_kms.h"
  31
  32 /* -----------------------------------------------------------------------------
  33  * Device Information
  34  */
  35
  36 static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
  37         .gen = 2,
  38         .features = RCAR_DU_FEATURE_CRTC_IRQ
  39                   | RCAR_DU_FEATURE_CRTC_CLOCK
  40                   | RCAR_DU_FEATURE_INTERLACED
  41                   | RCAR_DU_FEATURE_TVM_SYNC,
  42         .channels_mask = BIT(1) | BIT(0),
  43         .routes = {
  44                 /*
  45                  * R8A774[34] has one RGB output and one LVDS output
  46                  */
  47                 [RCAR_DU_OUTPUT_DPAD0] = {
  48                         .possible_crtcs = BIT(1) | BIT(0),
  49                         .port = 0,
  50                 },
  51                 [RCAR_DU_OUTPUT_LVDS0] = {
  52                         .possible_crtcs = BIT(0),
  53                         .port = 1,
  54                 },
  55         },
  56         .num_lvds = 1,
  57         .num_rpf = 4,
  58 };
  59
  60 static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
  61         .gen = 2,
  62         .features = RCAR_DU_FEATURE_CRTC_IRQ
  63                   | RCAR_DU_FEATURE_CRTC_CLOCK
  64                   | RCAR_DU_FEATURE_INTERLACED
  65                   | RCAR_DU_FEATURE_TVM_SYNC,
  66         .channels_mask = BIT(1) | BIT(0),
  67         .routes = {
  68                 /*
  69                  * R8A7745 has two RGB outputs
  70                  */
  71                 [RCAR_DU_OUTPUT_DPAD0] = {
  72                         .possible_crtcs = BIT(0),
  73                         .port = 0,
  74                 },
  75                 [RCAR_DU_OUTPUT_DPAD1] = {
  76                         .possible_crtcs = BIT(1),
  77                         .port = 1,
  78                 },
  79         },
  80         .num_rpf = 4,
  81 };
  82
  83 static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
  84         .gen = 2,
  85         .features = RCAR_DU_FEATURE_CRTC_IRQ
  86                   | RCAR_DU_FEATURE_CRTC_CLOCK
  87                   | RCAR_DU_FEATURE_INTERLACED
  88                   | RCAR_DU_FEATURE_TVM_SYNC,
  89         .channels_mask = BIT(1) | BIT(0),
  90         .routes = {
  91                 /*
  92                  * R8A77470 has two RGB outputs, one LVDS output, and
  93                  * one (currently unsupported) analog video output
  94                  */
  95                 [RCAR_DU_OUTPUT_DPAD0] = {
  96                         .possible_crtcs = BIT(0),
  97                         .port = 0,
  98                 },
  99                 [RCAR_DU_OUTPUT_DPAD1] = {
 100                         .possible_crtcs = BIT(1),
 101                         .port = 1,
 102                 },
 103                 [RCAR_DU_OUTPUT_LVDS0] = {
 104                         .possible_crtcs = BIT(0) | BIT(1),
 105                         .port = 2,
 106                 },
 107         },
 108         .num_rpf = 4,
 109 };
 110
 111 static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
 112         .gen = 3,
 113         .features = RCAR_DU_FEATURE_CRTC_IRQ
 114                   | RCAR_DU_FEATURE_CRTC_CLOCK
 115                   | RCAR_DU_FEATURE_VSP1_SOURCE
 116                   | RCAR_DU_FEATURE_INTERLACED
 117                   | RCAR_DU_FEATURE_TVM_SYNC,
 118         .channels_mask = BIT(2) | BIT(1) | BIT(0),
 119         .routes = {
 120                 /*
 121                  * R8A774A1 has one RGB output, one LVDS output and one HDMI
 122                  * output.
 123                  */
 124                 [RCAR_DU_OUTPUT_DPAD0] = {
 125                         .possible_crtcs = BIT(2),
 126                         .port = 0,
 127                 },
 128                 [RCAR_DU_OUTPUT_HDMI0] = {
 129                         .possible_crtcs = BIT(1),
 130                         .port = 1,
 131                 },
 132                 [RCAR_DU_OUTPUT_LVDS0] = {
 133                         .possible_crtcs = BIT(0),
 134                         .port = 2,
 135                 },
 136         },
 137         .num_lvds = 1,
 138         .num_rpf = 5,
 139         .dpll_mask =  BIT(1),
 140 };
 141
 142 static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
 143         .gen = 3,
 144         .features = RCAR_DU_FEATURE_CRTC_IRQ
 145                   | RCAR_DU_FEATURE_CRTC_CLOCK
 146                   | RCAR_DU_FEATURE_VSP1_SOURCE
 147                   | RCAR_DU_FEATURE_INTERLACED
 148                   | RCAR_DU_FEATURE_TVM_SYNC,
 149         .channels_mask = BIT(3) | BIT(1) | BIT(0),
 150         .routes = {
 151                 /*
 152                  * R8A774B1 has one RGB output, one LVDS output and one HDMI
 153                  * output.
 154                  */
 155                 [RCAR_DU_OUTPUT_DPAD0] = {
 156                         .possible_crtcs = BIT(2),
 157                         .port = 0,
 158                 },
 159                 [RCAR_DU_OUTPUT_HDMI0] = {
 160                         .possible_crtcs = BIT(1),
 161                         .port = 1,
 162                 },
 163                 [RCAR_DU_OUTPUT_LVDS0] = {
 164                         .possible_crtcs = BIT(0),
 165                         .port = 2,
 166                 },
 167         },
 168         .num_lvds = 1,
 169         .num_rpf = 5,
 170         .dpll_mask =  BIT(1),
 171 };
 172
 173 static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
 174         .gen = 3,
 175         .features = RCAR_DU_FEATURE_CRTC_IRQ
 176                   | RCAR_DU_FEATURE_CRTC_CLOCK
 177                   | RCAR_DU_FEATURE_VSP1_SOURCE,
 178         .channels_mask = BIT(1) | BIT(0),
 179         .routes = {
 180                 /*
 181                  * R8A774C0 has one RGB output and two LVDS outputs
 182                  */
 183                 [RCAR_DU_OUTPUT_DPAD0] = {
 184                         .possible_crtcs = BIT(0) | BIT(1),
 185                         .port = 0,
 186                 },
 187                 [RCAR_DU_OUTPUT_LVDS0] = {
 188                         .possible_crtcs = BIT(0),
 189                         .port = 1,
 190                 },
 191                 [RCAR_DU_OUTPUT_LVDS1] = {
 192                         .possible_crtcs = BIT(1),
 193                         .port = 2,
 194                 },
 195         },
 196         .num_lvds = 2,
 197         .num_rpf = 4,
 198         .lvds_clk_mask =  BIT(1) | BIT(0),
 199 };
 200
 201 static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
 202         .gen = 3,
 203         .features = RCAR_DU_FEATURE_CRTC_IRQ
 204                   | RCAR_DU_FEATURE_CRTC_CLOCK
 205                   | RCAR_DU_FEATURE_VSP1_SOURCE
 206                   | RCAR_DU_FEATURE_INTERLACED
 207                   | RCAR_DU_FEATURE_TVM_SYNC,
 208         .channels_mask = BIT(3) | BIT(1) | BIT(0),
 209         .routes = {
 210                 /*
 211                  * R8A774E1 has one RGB output, one LVDS output and one HDMI
 212                  * output.
 213                  */
 214                 [RCAR_DU_OUTPUT_DPAD0] = {
 215                         .possible_crtcs = BIT(2),
 216                         .port = 0,
 217                 },
 218                 [RCAR_DU_OUTPUT_HDMI0] = {
 219                         .possible_crtcs = BIT(1),
 220                         .port = 1,
 221                 },
 222                 [RCAR_DU_OUTPUT_LVDS0] = {
 223                         .possible_crtcs = BIT(0),
 224                         .port = 2,
 225                 },
 226         },
 227         .num_lvds = 1,
 228         .num_rpf = 5,
 229         .dpll_mask =  BIT(1),
 230 };
 231
 232 static const struct rcar_du_device_info rcar_du_r8a7779_info = {
 233         .gen = 1,
 234         .features = RCAR_DU_FEATURE_INTERLACED
 235                   | RCAR_DU_FEATURE_TVM_SYNC,
 236         .channels_mask = BIT(1) | BIT(0),
 237         .routes = {
 238                 /*
 239                  * R8A7779 has two RGB outputs and one (currently unsupported)
 240                  * TCON output.
 241                  */
 242                 [RCAR_DU_OUTPUT_DPAD0] = {
 243                         .possible_crtcs = BIT(0),
 244                         .port = 0,
 245                 },
 246                 [RCAR_DU_OUTPUT_DPAD1] = {
 247                         .possible_crtcs = BIT(1) | BIT(0),
 248                         .port = 1,
 249                 },
 250         },
 251 };
 252
 253 static const struct rcar_du_device_info rcar_du_r8a7790_info = {
 254         .gen = 2,
 255         .features = RCAR_DU_FEATURE_CRTC_IRQ
 256                   | RCAR_DU_FEATURE_CRTC_CLOCK
 257                   | RCAR_DU_FEATURE_INTERLACED
 258                   | RCAR_DU_FEATURE_TVM_SYNC,
 259         .quirks = RCAR_DU_QUIRK_ALIGN_128B,
 260         .channels_mask = BIT(2) | BIT(1) | BIT(0),
 261         .routes = {
 262                 /*
 263                  * R8A7742 and R8A7790 each have one RGB output and two LVDS
 264                  * outputs. Additionally R8A7790 supports one TCON output
 265                  * (currently unsupported by the driver).
 266                  */
 267                 [RCAR_DU_OUTPUT_DPAD0] = {
 268                         .possible_crtcs = BIT(2) | BIT(1) | BIT(0),
 269                         .port = 0,
 270                 },
 271                 [RCAR_DU_OUTPUT_LVDS0] = {
 272                         .possible_crtcs = BIT(0),
 273                         .port = 1,
 274                 },
 275                 [RCAR_DU_OUTPUT_LVDS1] = {
 276                         .possible_crtcs = BIT(2) | BIT(1),
 277                         .port = 2,
 278                 },
 279         },
 280         .num_lvds = 2,
 281         .num_rpf = 4,
 282 };
 283
 284 /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
 285 static const struct rcar_du_device_info rcar_du_r8a7791_info = {
 286         .gen = 2,
 287         .features = RCAR_DU_FEATURE_CRTC_IRQ
 288                   | RCAR_DU_FEATURE_CRTC_CLOCK
 289                   | RCAR_DU_FEATURE_INTERLACED
 290                   | RCAR_DU_FEATURE_TVM_SYNC,
 291         .channels_mask = BIT(1) | BIT(0),
 292         .routes = {
 293                 /*
 294                  * R8A779[13] has one RGB output, one LVDS output and one
 295                  * (currently unsupported) TCON output.
 296                  */
 297                 [RCAR_DU_OUTPUT_DPAD0] = {
 298                         .possible_crtcs = BIT(1) | BIT(0),
 299                         .port = 0,
 300                 },
 301                 [RCAR_DU_OUTPUT_LVDS0] = {
 302                         .possible_crtcs = BIT(0),
 303                         .port = 1,
 304                 },
 305         },
 306         .num_lvds = 1,
 307         .num_rpf = 4,
 308 };
 309
 310 static const struct rcar_du_device_info rcar_du_r8a7792_info = {
 311         .gen = 2,
 312         .features = RCAR_DU_FEATURE_CRTC_IRQ
 313                   | RCAR_DU_FEATURE_CRTC_CLOCK
 314                   | RCAR_DU_FEATURE_INTERLACED
 315                   | RCAR_DU_FEATURE_TVM_SYNC,
 316         .channels_mask = BIT(1) | BIT(0),
 317         .routes = {
 318                 /* R8A7792 has two RGB outputs. */
 319                 [RCAR_DU_OUTPUT_DPAD0] = {
 320                         .possible_crtcs = BIT(0),
 321                         .port = 0,
 322                 },
 323                 [RCAR_DU_OUTPUT_DPAD1] = {
 324                         .possible_crtcs = BIT(1),
 325                         .port = 1,
 326                 },
 327         },
 328         .num_rpf = 4,
 329 };
 330
 331 static const struct rcar_du_device_info rcar_du_r8a7794_info = {
 332         .gen = 2,
 333         .features = RCAR_DU_FEATURE_CRTC_IRQ
 334                   | RCAR_DU_FEATURE_CRTC_CLOCK
 335                   | RCAR_DU_FEATURE_INTERLACED
 336                   | RCAR_DU_FEATURE_TVM_SYNC,
 337         .channels_mask = BIT(1) | BIT(0),
 338         .routes = {
 339                 /*
 340                  * R8A7794 has two RGB outputs and one (currently unsupported)
 341                  * TCON output.
 342                  */
 343                 [RCAR_DU_OUTPUT_DPAD0] = {
 344                         .possible_crtcs = BIT(0),
 345                         .port = 0,
 346                 },
 347                 [RCAR_DU_OUTPUT_DPAD1] = {
 348                         .possible_crtcs = BIT(1),
 349                         .port = 1,
 350                 },
 351         },
 352         .num_rpf = 4,
 353 };
 354
 355 static const struct rcar_du_device_info rcar_du_r8a7795_info = {
 356         .gen = 3,
 357         .features = RCAR_DU_FEATURE_CRTC_IRQ
 358                   | RCAR_DU_FEATURE_CRTC_CLOCK
 359                   | RCAR_DU_FEATURE_VSP1_SOURCE
 360                   | RCAR_DU_FEATURE_INTERLACED
 361                   | RCAR_DU_FEATURE_TVM_SYNC,
 362         .channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
 363         .routes = {
 364                 /*
 365                  * R8A7795 has one RGB output, two HDMI outputs and one
 366                  * LVDS output.
 367                  */
 368                 [RCAR_DU_OUTPUT_DPAD0] = {
 369                         .possible_crtcs = BIT(3),
 370                         .port = 0,
 371                 },
 372                 [RCAR_DU_OUTPUT_HDMI0] = {
 373                         .possible_crtcs = BIT(1),
 374                         .port = 1,
 375                 },
 376                 [RCAR_DU_OUTPUT_HDMI1] = {
 377                         .possible_crtcs = BIT(2),
 378                         .port = 2,
 379                 },
 380                 [RCAR_DU_OUTPUT_LVDS0] = {
 381                         .possible_crtcs = BIT(0),
 382                         .port = 3,
 383                 },
 384         },
 385         .num_lvds = 1,
 386         .num_rpf = 5,
 387         .dpll_mask =  BIT(2) | BIT(1),
 388 };
 389
 390 static const struct rcar_du_device_info rcar_du_r8a7795_es1_info = {
 391         .gen = 3,
 392         .features = RCAR_DU_FEATURE_CRTC_IRQ
 393                   | RCAR_DU_FEATURE_CRTC_CLOCK
 394                   | RCAR_DU_FEATURE_VSP1_SOURCE
 395                   | RCAR_DU_FEATURE_INTERLACED
 396                   | RCAR_DU_FEATURE_TVM_SYNC,
 397         .quirks = RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY
 398                 | RCAR_DU_QUIRK_H3_ES1_PLL,
 399         .channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
 400         .routes = {
 401                 /*
 402                  * R8A7795 has one RGB output, two HDMI outputs and one
 403                  * LVDS output.
 404                  */
 405                 [RCAR_DU_OUTPUT_DPAD0] = {
 406                         .possible_crtcs = BIT(3),
 407                         .port = 0,
 408                 },
 409                 [RCAR_DU_OUTPUT_HDMI0] = {
 410                         .possible_crtcs = BIT(1),
 411                         .port = 1,
 412                 },
 413                 [RCAR_DU_OUTPUT_HDMI1] = {
 414                         .possible_crtcs = BIT(2),
 415                         .port = 2,
 416                 },
 417                 [RCAR_DU_OUTPUT_LVDS0] = {
 418                         .possible_crtcs = BIT(0),
 419                         .port = 3,
 420                 },
 421         },
 422         .num_lvds = 1,
 423         .num_rpf = 5,
 424         .dpll_mask =  BIT(2) | BIT(1),
 425 };
 426
 427 static const struct rcar_du_device_info rcar_du_r8a7796_info = {
 428         .gen = 3,
 429         .features = RCAR_DU_FEATURE_CRTC_IRQ
 430                   | RCAR_DU_FEATURE_CRTC_CLOCK
 431                   | RCAR_DU_FEATURE_VSP1_SOURCE
 432                   | RCAR_DU_FEATURE_INTERLACED
 433                   | RCAR_DU_FEATURE_TVM_SYNC,
 434         .channels_mask = BIT(2) | BIT(1) | BIT(0),
 435         .routes = {
 436                 /*
 437                  * R8A7796 has one RGB output, one LVDS output and one HDMI
 438                  * output.
 439                  */
 440                 [RCAR_DU_OUTPUT_DPAD0] = {
 441                         .possible_crtcs = BIT(2),
 442                         .port = 0,
 443                 },
 444                 [RCAR_DU_OUTPUT_HDMI0] = {
 445                         .possible_crtcs = BIT(1),
 446                         .port = 1,
 447                 },
 448                 [RCAR_DU_OUTPUT_LVDS0] = {
 449                         .possible_crtcs = BIT(0),
 450                         .port = 2,
 451                 },
 452         },
 453         .num_lvds = 1,
 454         .num_rpf = 5,
 455         .dpll_mask =  BIT(1),
 456 };
 457
 458 static const struct rcar_du_device_info rcar_du_r8a77965_info = {
 459         .gen = 3,
 460         .features = RCAR_DU_FEATURE_CRTC_IRQ
 461                   | RCAR_DU_FEATURE_CRTC_CLOCK
 462                   | RCAR_DU_FEATURE_VSP1_SOURCE
 463                   | RCAR_DU_FEATURE_INTERLACED
 464                   | RCAR_DU_FEATURE_TVM_SYNC,
 465         .channels_mask = BIT(3) | BIT(1) | BIT(0),
 466         .routes = {
 467                 /*
 468                  * R8A77965 has one RGB output, one LVDS output and one HDMI
 469                  * output.
 470                  */
 471                 [RCAR_DU_OUTPUT_DPAD0] = {
 472                         .possible_crtcs = BIT(2),
 473                         .port = 0,
 474                 },
 475                 [RCAR_DU_OUTPUT_HDMI0] = {
 476                         .possible_crtcs = BIT(1),
 477                         .port = 1,
 478                 },
 479                 [RCAR_DU_OUTPUT_LVDS0] = {
 480                         .possible_crtcs = BIT(0),
 481                         .port = 2,
 482                 },
 483         },
 484         .num_lvds = 1,
 485         .num_rpf = 5,
 486         .dpll_mask =  BIT(1),
 487 };
 488
 489 static const struct rcar_du_device_info rcar_du_r8a77970_info = {
 490         .gen = 3,
 491         .features = RCAR_DU_FEATURE_CRTC_IRQ
 492                   | RCAR_DU_FEATURE_CRTC_CLOCK
 493                   | RCAR_DU_FEATURE_VSP1_SOURCE
 494                   | RCAR_DU_FEATURE_INTERLACED
 495                   | RCAR_DU_FEATURE_TVM_SYNC,
 496         .channels_mask = BIT(0),
 497         .routes = {
 498                 /*
 499                  * R8A77970 and R8A77980 have one RGB output and one LVDS
 500                  * output.
 501                  */
 502                 [RCAR_DU_OUTPUT_DPAD0] = {
 503                         .possible_crtcs = BIT(0),
 504                         .port = 0,
 505                 },
 506                 [RCAR_DU_OUTPUT_LVDS0] = {
 507                         .possible_crtcs = BIT(0),
 508                         .port = 1,
 509                 },
 510         },
 511         .num_lvds = 1,
 512         .num_rpf = 5,
 513 };
 514
 515 static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
 516         .gen = 3,
 517         .features = RCAR_DU_FEATURE_CRTC_IRQ
 518                   | RCAR_DU_FEATURE_CRTC_CLOCK
 519                   | RCAR_DU_FEATURE_VSP1_SOURCE,
 520         .channels_mask = BIT(1) | BIT(0),
 521         .routes = {
 522                 /*
 523                  * R8A77990 and R8A77995 have one RGB output and two LVDS
 524                  * outputs.
 525                  */
 526                 [RCAR_DU_OUTPUT_DPAD0] = {
 527                         .possible_crtcs = BIT(0) | BIT(1),
 528                         .port = 0,
 529                 },
 530                 [RCAR_DU_OUTPUT_LVDS0] = {
 531                         .possible_crtcs = BIT(0),
 532                         .port = 1,
 533                 },
 534                 [RCAR_DU_OUTPUT_LVDS1] = {
 535                         .possible_crtcs = BIT(1),
 536                         .port = 2,
 537                 },
 538         },
 539         .num_lvds = 2,
 540         .num_rpf = 5,
 541         .lvds_clk_mask =  BIT(1) | BIT(0),
 542 };
 543
 544 static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
 545         .gen = 4,
 546         .features = RCAR_DU_FEATURE_CRTC_IRQ
 547                   | RCAR_DU_FEATURE_VSP1_SOURCE
 548                   | RCAR_DU_FEATURE_NO_BLENDING,
 549         .channels_mask = BIT(1) | BIT(0),
 550         .routes = {
 551                 /* R8A779A0 has two MIPI DSI outputs. */
 552                 [RCAR_DU_OUTPUT_DSI0] = {
 553                         .possible_crtcs = BIT(0),
 554                         .port = 0,
 555                 },
 556                 [RCAR_DU_OUTPUT_DSI1] = {
 557                         .possible_crtcs = BIT(1),
 558                         .port = 1,
 559                 },
 560         },
 561         .num_rpf = 5,
 562         .dsi_clk_mask =  BIT(1) | BIT(0),
 563 };
 564
 565 static const struct rcar_du_device_info rcar_du_r8a779g0_info = {
 566         .gen = 4,
 567         .features = RCAR_DU_FEATURE_CRTC_IRQ
 568                   | RCAR_DU_FEATURE_VSP1_SOURCE
 569                   | RCAR_DU_FEATURE_NO_BLENDING,
 570         .channels_mask = BIT(1) | BIT(0),
 571         .routes = {
 572                 /* R8A779G0 has two MIPI DSI outputs. */
 573                 [RCAR_DU_OUTPUT_DSI0] = {
 574                         .possible_crtcs = BIT(0),
 575                         .port = 0,
 576                 },
 577                 [RCAR_DU_OUTPUT_DSI1] = {
 578                         .possible_crtcs = BIT(1),
 579                         .port = 1,
 580                 },
 581         },
 582         .num_rpf = 5,
 583         .dsi_clk_mask =  BIT(1) | BIT(0),
 584 };
 585
 586 static const struct of_device_id rcar_du_of_table[] = {
 587         { .compatible = "renesas,du-r8a7742", .data = &rcar_du_r8a7790_info },
 588         { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
 589         { .compatible = "renesas,du-r8a7744", .data = &rzg1_du_r8a7743_info },
 590         { .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info },
 591         { .compatible = "renesas,du-r8a77470", .data = &rzg1_du_r8a77470_info },
 592         { .compatible = "renesas,du-r8a774a1", .data = &rcar_du_r8a774a1_info },
 593         { .compatible = "renesas,du-r8a774b1", .data = &rcar_du_r8a774b1_info },
 594         { .compatible = "renesas,du-r8a774c0", .data = &rcar_du_r8a774c0_info },
 595         { .compatible = "renesas,du-r8a774e1", .data = &rcar_du_r8a774e1_info },
 596         { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
 597         { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
 598         { .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
 599         { .compatible = "renesas,du-r8a7792", .data = &rcar_du_r8a7792_info },
 600         { .compatible = "renesas,du-r8a7793", .data = &rcar_du_r8a7791_info },
 601         { .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info },
 602         { .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info },
 603         { .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info },
 604         { .compatible = "renesas,du-r8a77961", .data = &rcar_du_r8a7796_info },
 605         { .compatible = "renesas,du-r8a77965", .data = &rcar_du_r8a77965_info },
 606         { .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info },
 607         { .compatible = "renesas,du-r8a77980", .data = &rcar_du_r8a77970_info },
 608         { .compatible = "renesas,du-r8a77990", .data = &rcar_du_r8a7799x_info },
 609         { .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a7799x_info },
 610         { .compatible = "renesas,du-r8a779a0", .data = &rcar_du_r8a779a0_info },
 611         { .compatible = "renesas,du-r8a779g0", .data = &rcar_du_r8a779g0_info },
 612         { }
 613 };
 614
 615 MODULE_DEVICE_TABLE(of, rcar_du_of_table);
 616
 617 static const struct soc_device_attribute rcar_du_soc_table[] = {
 618         { .soc_id = "r8a7795", .revision = "ES1.*", .data = &rcar_du_r8a7795_es1_info },
 619         { /* sentinel */ }
 620 };
 621
 622 const char *rcar_du_output_name(enum rcar_du_output output)
 623 {
 624         static const char * const names[] = {
 625                 [RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
 626                 [RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
 627                 [RCAR_DU_OUTPUT_DSI0] = "DSI0",
 628                 [RCAR_DU_OUTPUT_DSI1] = "DSI1",
 629                 [RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
 630                 [RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
 631                 [RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
 632                 [RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
 633                 [RCAR_DU_OUTPUT_TCON] = "TCON",
 634         };
 635
 636         if (output >= ARRAY_SIZE(names) || !names[output])
 637                 return "UNKNOWN";
 638
 639         return names[output];
 640 }
 641
 642 /* -----------------------------------------------------------------------------
 643  * DRM operations
 644  */
 645
 646 DEFINE_DRM_GEM_DMA_FOPS(rcar_du_fops);
 647
 648 static const struct drm_driver rcar_du_driver = {
 649         .driver_features        = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
 650         .dumb_create            = rcar_du_dumb_create,
 651         .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
 652         .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
 653         .gem_prime_import_sg_table = rcar_du_gem_prime_import_sg_table,
 654         .gem_prime_mmap         = drm_gem_prime_mmap,
 655         .fops                   = &rcar_du_fops,
 656         .name                   = "rcar-du",
 657         .desc                   = "Renesas R-Car Display Unit",
 658         .date                   = "20130110",
 659         .major                  = 1,
 660         .minor                  = 0,
 661 };
 662
 663 /* -----------------------------------------------------------------------------
 664  * Power management
 665  */
 666
 667 static int rcar_du_pm_suspend(struct device *dev)
 668 {
 669         struct rcar_du_device *rcdu = dev_get_drvdata(dev);
 670
 671         return drm_mode_config_helper_suspend(&rcdu->ddev);
 672 }
 673
 674 static int rcar_du_pm_resume(struct device *dev)
 675 {
 676         struct rcar_du_device *rcdu = dev_get_drvdata(dev);
 677
 678         return drm_mode_config_helper_resume(&rcdu->ddev);
 679 }
 680
 681 static DEFINE_SIMPLE_DEV_PM_OPS(rcar_du_pm_ops,
 682                                 rcar_du_pm_suspend, rcar_du_pm_resume);
 683
 684 /* -----------------------------------------------------------------------------
 685  * Platform driver
 686  */
 687
 688 static int rcar_du_remove(struct platform_device *pdev)
 689 {
 690         struct rcar_du_device *rcdu = platform_get_drvdata(pdev);
 691         struct drm_device *ddev = &rcdu->ddev;
 692
 693         drm_dev_unregister(ddev);
 694         drm_atomic_helper_shutdown(ddev);
 695
 696         drm_kms_helper_poll_fini(ddev);
 697
 698         return 0;
 699 }
 700
 701 static void rcar_du_shutdown(struct platform_device *pdev)
 702 {
 703         struct rcar_du_device *rcdu = platform_get_drvdata(pdev);
 704
 705         drm_atomic_helper_shutdown(&rcdu->ddev);
 706 }
 707
 708 static int rcar_du_probe(struct platform_device *pdev)
 709 {
 710         const struct soc_device_attribute *soc_attr;
 711         struct rcar_du_device *rcdu;
 712         unsigned int mask;
 713         int ret;
 714
 715         if (drm_firmware_drivers_only())
 716                 return -ENODEV;
 717
 718         /* Allocate and initialize the R-Car device structure. */
 719         rcdu = devm_drm_dev_alloc(&pdev->dev, &rcar_du_driver,
 720                                   struct rcar_du_device, ddev);
 721         if (IS_ERR(rcdu))
 722                 return PTR_ERR(rcdu);
 723
 724         rcdu->dev = &pdev->dev;
 725
 726         rcdu->info = of_device_get_match_data(rcdu->dev);
 727
 728         soc_attr = soc_device_match(rcar_du_soc_table);
 729         if (soc_attr)
 730                 rcdu->info = soc_attr->data;
 731
 732         platform_set_drvdata(pdev, rcdu);
 733
 734         /* I/O resources */
 735         rcdu->mmio = devm_platform_ioremap_resource(pdev, 0);
 736         if (IS_ERR(rcdu->mmio))
 737                 return PTR_ERR(rcdu->mmio);
 738
 739         /*
 740          * Set the DMA coherent mask to reflect the DU 32-bit DMA address space
 741          * limitations. When sourcing frames from a VSP the DU doesn't perform
 742          * any memory access so set the mask to 40 bits to accept all buffers.
 743          */
 744         mask = rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE) ? 40 : 32;
 745         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(mask));
 746         if (ret)
 747                 return ret;
 748
 749         /* DRM/KMS objects */
 750         ret = rcar_du_modeset_init(rcdu);
 751         if (ret < 0) {
 752                 if (ret != -EPROBE_DEFER)
 753                         dev_err(&pdev->dev,
 754                                 "failed to initialize DRM/KMS (%d)\n", ret);
 755                 goto error;
 756         }
 757
 758         /*
 759          * Register the DRM device with the core and the connectors with
 760          * sysfs.
 761          */
 762         ret = drm_dev_register(&rcdu->ddev, 0);
 763         if (ret)
 764                 goto error;
 765
 766         DRM_INFO("Device %s probed\n", dev_name(&pdev->dev));
 767
 768         drm_fbdev_generic_setup(&rcdu->ddev, 32);
 769
 770         return 0;
 771
 772 error:
 773         drm_kms_helper_poll_fini(&rcdu->ddev);
 774         return ret;
 775 }
 776
 777 static struct platform_driver rcar_du_platform_driver = {
 778         .probe          = rcar_du_probe,
 779         .remove         = rcar_du_remove,
 780         .shutdown       = rcar_du_shutdown,
 781         .driver         = {
 782                 .name   = "rcar-du",
 783                 .pm     = pm_sleep_ptr(&rcar_du_pm_ops),
 784                 .of_match_table = rcar_du_of_table,
 785         },
 786 };
 787
 788 module_platform_driver(rcar_du_platform_driver);
 789
 790 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
 791 MODULE_DESCRIPTION("Renesas R-Car Display Unit DRM Driver");
 792 MODULE_LICENSE("GPL");