drivers/gpu/drm/radeon/sislands_smc.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef PP_SISLANDS_SMC_H
  24 #define PP_SISLANDS_SMC_H
  25
  26 #include "ppsmc.h"
  27
  28 #pragma pack(push, 1)
  29
  30 #define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
  31
  32 struct PP_SIslands_Dpm2PerfLevel
  33 {
  34     uint8_t MaxPS;
  35     uint8_t TgtAct;
  36     uint8_t MaxPS_StepInc;
  37     uint8_t MaxPS_StepDec;
  38     uint8_t PSSamplingTime;
  39     uint8_t NearTDPDec;
  40     uint8_t AboveSafeInc;
  41     uint8_t BelowSafeInc;
  42     uint8_t PSDeltaLimit;
  43     uint8_t PSDeltaWin;
  44     uint16_t PwrEfficiencyRatio;
  45     uint8_t Reserved[4];
  46 };
  47
  48 typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel;
  49
  50 struct PP_SIslands_DPM2Status
  51 {
  52     uint32_t    dpm2Flags;
  53     uint8_t     CurrPSkip;
  54     uint8_t     CurrPSkipPowerShift;
  55     uint8_t     CurrPSkipTDP;
  56     uint8_t     CurrPSkipOCP;
  57     uint8_t     MaxSPLLIndex;
  58     uint8_t     MinSPLLIndex;
  59     uint8_t     CurrSPLLIndex;
  60     uint8_t     InfSweepMode;
  61     uint8_t     InfSweepDir;
  62     uint8_t     TDPexceeded;
  63     uint8_t     reserved;
  64     uint8_t     SwitchDownThreshold;
  65     uint32_t    SwitchDownCounter;
  66     uint32_t    SysScalingFactor;
  67 };
  68
  69 typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status;
  70
  71 struct PP_SIslands_DPM2Parameters
  72 {
  73     uint32_t    TDPLimit;
  74     uint32_t    NearTDPLimit;
  75     uint32_t    SafePowerLimit;
  76     uint32_t    PowerBoostLimit;
  77     uint32_t    MinLimitDelta;
  78 };
  79 typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters;
  80
  81 struct PP_SIslands_PAPMStatus
  82 {
  83     uint32_t    EstimatedDGPU_T;
  84     uint32_t    EstimatedDGPU_P;
  85     uint32_t    EstimatedAPU_T;
  86     uint32_t    EstimatedAPU_P;
  87     uint8_t     dGPU_T_Limit_Exceeded;
  88     uint8_t     reserved[3];
  89 };
  90 typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus;
  91
  92 struct PP_SIslands_PAPMParameters {
  93     uint32_t    NearTDPLimitTherm;
  94     uint32_t    NearTDPLimitPAPM;
  95     uint32_t    PlatformPowerLimit;
  96     uint32_t    dGPU_T_Limit;
  97     uint32_t    dGPU_T_Warning;
  98     uint32_t    dGPU_T_Hysteresis;
  99 };
 100 typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters;
 101
 102 struct SISLANDS_SMC_SCLK_VALUE {
 103     uint32_t    vCG_SPLL_FUNC_CNTL;
 104     uint32_t    vCG_SPLL_FUNC_CNTL_2;
 105     uint32_t    vCG_SPLL_FUNC_CNTL_3;
 106     uint32_t    vCG_SPLL_FUNC_CNTL_4;
 107     uint32_t    vCG_SPLL_SPREAD_SPECTRUM;
 108     uint32_t    vCG_SPLL_SPREAD_SPECTRUM_2;
 109     uint32_t    sclk_value;
 110 };
 111
 112 typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE;
 113
 114 struct SISLANDS_SMC_MCLK_VALUE {
 115     uint32_t    vMPLL_FUNC_CNTL;
 116     uint32_t    vMPLL_FUNC_CNTL_1;
 117     uint32_t    vMPLL_FUNC_CNTL_2;
 118     uint32_t    vMPLL_AD_FUNC_CNTL;
 119     uint32_t    vMPLL_DQ_FUNC_CNTL;
 120     uint32_t    vMCLK_PWRMGT_CNTL;
 121     uint32_t    vDLL_CNTL;
 122     uint32_t    vMPLL_SS;
 123     uint32_t    vMPLL_SS2;
 124     uint32_t    mclk_value;
 125 };
 126
 127 typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE;
 128
 129 struct SISLANDS_SMC_VOLTAGE_VALUE {
 130     uint16_t    value;
 131     uint8_t     index;
 132     uint8_t     phase_settings;
 133 };
 134
 135 typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE;
 136
 137 struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL {
 138     uint8_t                     ACIndex;
 139     uint8_t                     displayWatermark;
 140     uint8_t                     gen2PCIE;
 141     uint8_t                     UVDWatermark;
 142     uint8_t                     VCEWatermark;
 143     uint8_t                     strobeMode;
 144     uint8_t                     mcFlags;
 145     uint8_t                     padding;
 146     uint32_t                    aT;
 147     uint32_t                    bSP;
 148     SISLANDS_SMC_SCLK_VALUE     sclk;
 149     SISLANDS_SMC_MCLK_VALUE     mclk;
 150     SISLANDS_SMC_VOLTAGE_VALUE  vddc;
 151     SISLANDS_SMC_VOLTAGE_VALUE  mvdd;
 152     SISLANDS_SMC_VOLTAGE_VALUE  vddci;
 153     SISLANDS_SMC_VOLTAGE_VALUE  std_vddc;
 154     uint8_t                     hysteresisUp;
 155     uint8_t                     hysteresisDown;
 156     uint8_t                     stateFlags;
 157     uint8_t                     arbRefreshState;
 158     uint32_t                    SQPowerThrottle;
 159     uint32_t                    SQPowerThrottle_2;
 160     uint32_t                    MaxPoweredUpCU;
 161     SISLANDS_SMC_VOLTAGE_VALUE  high_temp_vddc;
 162     SISLANDS_SMC_VOLTAGE_VALUE  low_temp_vddc;
 163     uint32_t                    reserved[2];
 164     PP_SIslands_Dpm2PerfLevel   dpm2;
 165 };
 166
 167 #define SISLANDS_SMC_STROBE_RATIO    0x0F
 168 #define SISLANDS_SMC_STROBE_ENABLE   0x10
 169
 170 #define SISLANDS_SMC_MC_EDC_RD_FLAG  0x01
 171 #define SISLANDS_SMC_MC_EDC_WR_FLAG  0x02
 172 #define SISLANDS_SMC_MC_RTT_ENABLE   0x04
 173 #define SISLANDS_SMC_MC_STUTTER_EN   0x08
 174 #define SISLANDS_SMC_MC_PG_EN        0x10
 175
 176 typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL;
 177
 178 struct SISLANDS_SMC_SWSTATE {
 179         uint8_t                             flags;
 180         uint8_t                             levelCount;
 181         uint8_t                             padding2;
 182         uint8_t                             padding3;
 183         SISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[];
 184 };
 185
 186 typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
 187
 188 struct SISLANDS_SMC_SWSTATE_SINGLE {
 189         uint8_t                             flags;
 190         uint8_t                             levelCount;
 191         uint8_t                             padding2;
 192         uint8_t                             padding3;
 193         SISLANDS_SMC_HW_PERFORMANCE_LEVEL   level;
 194 };
 195
 196 #define SISLANDS_SMC_VOLTAGEMASK_VDDC  0
 197 #define SISLANDS_SMC_VOLTAGEMASK_MVDD  1
 198 #define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2
 199 #define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3
 200 #define SISLANDS_SMC_VOLTAGEMASK_MAX   4
 201
 202 struct SISLANDS_SMC_VOLTAGEMASKTABLE {
 203     uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];
 204 };
 205
 206 typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE;
 207
 208 #define SISLANDS_MAX_NO_VREG_STEPS 32
 209
 210 struct SISLANDS_SMC_STATETABLE {
 211         uint8_t                                 thermalProtectType;
 212         uint8_t                                 systemFlags;
 213         uint8_t                                 maxVDDCIndexInPPTable;
 214         uint8_t                                 extraFlags;
 215         uint32_t                                lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
 216         SISLANDS_SMC_VOLTAGEMASKTABLE           voltageMaskTable;
 217         SISLANDS_SMC_VOLTAGEMASKTABLE           phaseMaskTable;
 218         PP_SIslands_DPM2Parameters              dpm2Params;
 219         struct SISLANDS_SMC_SWSTATE_SINGLE      initialState;
 220         struct SISLANDS_SMC_SWSTATE_SINGLE      ACPIState;
 221         struct SISLANDS_SMC_SWSTATE_SINGLE      ULVState;
 222         SISLANDS_SMC_SWSTATE                    driverState;
 223         SISLANDS_SMC_HW_PERFORMANCE_LEVEL       dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
 224 };
 225
 226 typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE;
 227
 228 #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout         0x0
 229 #define SI_SMC_SOFT_REGISTER_delay_vreg               0xC
 230 #define SI_SMC_SOFT_REGISTER_delay_acpi               0x28
 231 #define SI_SMC_SOFT_REGISTER_seq_index                0x5C
 232 #define SI_SMC_SOFT_REGISTER_mvdd_chg_time            0x60
 233 #define SI_SMC_SOFT_REGISTER_mclk_switch_lim          0x70
 234 #define SI_SMC_SOFT_REGISTER_watermark_threshold      0x78
 235 #define SI_SMC_SOFT_REGISTER_phase_shedding_delay     0x88
 236 #define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay    0x8C
 237 #define SI_SMC_SOFT_REGISTER_mc_block_delay           0x98
 238 #define SI_SMC_SOFT_REGISTER_ticks_per_us             0xA8
 239 #define SI_SMC_SOFT_REGISTER_crtc_index               0xC4
 240 #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8
 241 #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC
 242 #define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width  0xF4
 243 #define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen   0xFC
 244 #define SI_SMC_SOFT_REGISTER_vr_hot_gpio              0x100
 245 #define SI_SMC_SOFT_REGISTER_svi_rework_plat_type     0x118
 246 #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd   0x11c
 247 #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc   0x120
 248
 249 struct PP_SIslands_FanTable {
 250         uint8_t  fdo_mode;
 251         uint8_t  padding;
 252         int16_t  temp_min;
 253         int16_t  temp_med;
 254         int16_t  temp_max;
 255         int16_t  slope1;
 256         int16_t  slope2;
 257         int16_t  fdo_min;
 258         int16_t  hys_up;
 259         int16_t  hys_down;
 260         int16_t  hys_slope;
 261         int16_t  temp_resp_lim;
 262         int16_t  temp_curr;
 263         int16_t  slope_curr;
 264         int16_t  pwm_curr;
 265         uint32_t refresh_period;
 266         int16_t  fdo_max;
 267         uint8_t  temp_src;
 268         int8_t  padding2;
 269 };
 270
 271 typedef struct PP_SIslands_FanTable PP_SIslands_FanTable;
 272
 273 #define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
 274 #define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32
 275
 276 #define SMC_SISLANDS_SCALE_I  7
 277 #define SMC_SISLANDS_SCALE_R 12
 278
 279 struct PP_SIslands_CacConfig {
 280     uint16_t   cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
 281     uint32_t   lkge_lut_V0;
 282     uint32_t   lkge_lut_Vstep;
 283     uint32_t   WinTime;
 284     uint32_t   R_LL;
 285     uint32_t   calculation_repeats;
 286     uint32_t   l2numWin_TDP;
 287     uint32_t   dc_cac;
 288     uint8_t    lts_truncate_n;
 289     uint8_t    SHIFT_N;
 290     uint8_t    log2_PG_LKG_SCALE;
 291     uint8_t    cac_temp;
 292     uint32_t   lkge_lut_T0;
 293     uint32_t   lkge_lut_Tstep;
 294 };
 295
 296 typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig;
 297
 298 #define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16
 299 #define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
 300
 301 struct SMC_SIslands_MCRegisterAddress {
 302     uint16_t s0;
 303     uint16_t s1;
 304 };
 305
 306 typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress;
 307
 308 struct SMC_SIslands_MCRegisterSet {
 309     uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
 310 };
 311
 312 typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet;
 313
 314 struct SMC_SIslands_MCRegisters {
 315     uint8_t                             last;
 316     uint8_t                             reserved[3];
 317     SMC_SIslands_MCRegisterAddress      address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
 318     SMC_SIslands_MCRegisterSet          data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
 319 };
 320
 321 typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters;
 322
 323 struct SMC_SIslands_MCArbDramTimingRegisterSet {
 324     uint32_t mc_arb_dram_timing;
 325     uint32_t mc_arb_dram_timing2;
 326     uint8_t  mc_arb_rfsh_rate;
 327     uint8_t  mc_arb_burst_time;
 328     uint8_t  padding[2];
 329 };
 330
 331 typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet;
 332
 333 struct SMC_SIslands_MCArbDramTimingRegisters {
 334     uint8_t                                     arb_current;
 335     uint8_t                                     reserved[3];
 336     SMC_SIslands_MCArbDramTimingRegisterSet     data[16];
 337 };
 338
 339 typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters;
 340
 341 struct SMC_SISLANDS_SPLL_DIV_TABLE {
 342     uint32_t    freq[256];
 343     uint32_t    ss[256];
 344 };
 345
 346 #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK  0x01ffffff
 347 #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
 348 #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK   0xfe000000
 349 #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT  25
 350 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK   0x000fffff
 351 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT  0
 352 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK   0xfff00000
 353 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT  20
 354
 355 typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE;
 356
 357 #define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5
 358
 359 #define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16
 360
 361 struct Smc_SIslands_DTE_Configuration {
 362     uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
 363     uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
 364     uint32_t K;
 365     uint32_t T0;
 366     uint32_t MaxT;
 367     uint8_t  WindowSize;
 368     uint8_t  Tdep_count;
 369     uint8_t  temp_select;
 370     uint8_t  DTE_mode;
 371     uint8_t  T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
 372     uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
 373     uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
 374     uint32_t Tthreshold;
 375 };
 376
 377 typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration;
 378
 379 #define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1
 380
 381 #define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000
 382
 383 #define SISLANDS_SMC_FIRMWARE_HEADER_version                   0x0
 384 #define SISLANDS_SMC_FIRMWARE_HEADER_flags                     0x4
 385 #define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters             0xC
 386 #define SISLANDS_SMC_FIRMWARE_HEADER_stateTable                0x10
 387 #define SISLANDS_SMC_FIRMWARE_HEADER_fanTable                  0x14
 388 #define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable            0x18
 389 #define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable           0x24
 390 #define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30
 391 #define SISLANDS_SMC_FIRMWARE_HEADER_spllTable                 0x38
 392 #define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration          0x40
 393 #define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters            0x48
 394
 395 #pragma pack(pop)
 396
 397 int si_copy_bytes_to_smc(struct radeon_device *rdev,
 398                          u32 smc_start_address,
 399                          const u8 *src, u32 byte_count, u32 limit);
 400 void si_start_smc(struct radeon_device *rdev);
 401 void si_reset_smc(struct radeon_device *rdev);
 402 int si_program_jump_on_start(struct radeon_device *rdev);
 403 void si_stop_smc_clock(struct radeon_device *rdev);
 404 void si_start_smc_clock(struct radeon_device *rdev);
 405 bool si_is_smc_running(struct radeon_device *rdev);
 406 PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
 407 PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev);
 408 int si_load_smc_ucode(struct radeon_device *rdev, u32 limit);
 409 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
 410                            u32 *value, u32 limit);
 411 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
 412                             u32 value, u32 limit);
 413
 414 #endif
 415