2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
32 #include <drm/drm_device.h>
33 #include <drm/drm_file.h>
37 #include "radeon_asic.h"
38 #include "rv515_reg_safe.h"
41 /* This files gather functions specifics to: rv515 */
42 static void rv515_gpu_init(struct radeon_device *rdev);
43 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
45 static const u32 crtc_offsets[2] =
48 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
51 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
55 r = radeon_ring_lock(rdev, ring, 64);
59 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
60 radeon_ring_write(ring,
64 ISYNC_CPSCRATCH_IDLEGUI);
65 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
66 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
67 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
68 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
69 radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
70 radeon_ring_write(ring, 0);
71 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
72 radeon_ring_write(ring, 0);
73 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
74 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
75 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
76 radeon_ring_write(ring, 0);
77 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
78 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
79 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
80 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
81 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
82 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
83 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
84 radeon_ring_write(ring, 0);
85 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
86 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
87 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
88 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
89 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
90 radeon_ring_write(ring,
97 (6 << MSBD0_Y_SHIFT) |
98 (6 << MSBD0_X_SHIFT)));
99 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
100 radeon_ring_write(ring,
101 ((6 << MS_X3_SHIFT) |
107 (6 << MSBD1_SHIFT)));
108 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
109 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
110 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
111 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
112 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
113 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
114 radeon_ring_write(ring, PACKET0(0x20C8, 0));
115 radeon_ring_write(ring, 0);
116 radeon_ring_unlock_commit(rdev, ring, false);
119 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
124 for (i = 0; i < rdev->usec_timeout; i++) {
126 tmp = RREG32_MC(MC_STATUS);
127 if (tmp & MC_STATUS_IDLE) {
135 void rv515_vga_render_disable(struct radeon_device *rdev)
137 WREG32(R_000300_VGA_RENDER_CONTROL,
138 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
141 static void rv515_gpu_init(struct radeon_device *rdev)
143 unsigned pipe_select_current, gb_pipe_select, tmp;
145 if (r100_gui_wait_for_idle(rdev)) {
146 pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n");
148 rv515_vga_render_disable(rdev);
149 r420_pipes_init(rdev);
150 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
151 tmp = RREG32(R300_DST_PIPE_CONFIG);
152 pipe_select_current = (tmp >> 2) & 3;
153 tmp = (1 << pipe_select_current) |
154 (((gb_pipe_select >> 8) & 0xF) << 4);
155 WREG32_PLL(0x000D, tmp);
156 if (r100_gui_wait_for_idle(rdev)) {
157 pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n");
159 if (rv515_mc_wait_for_idle(rdev)) {
160 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
164 static void rv515_vram_get_type(struct radeon_device *rdev)
168 rdev->mc.vram_width = 128;
169 rdev->mc.vram_is_ddr = true;
170 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
173 rdev->mc.vram_width = 64;
176 rdev->mc.vram_width = 128;
179 rdev->mc.vram_width = 128;
184 static void rv515_mc_init(struct radeon_device *rdev)
187 rv515_vram_get_type(rdev);
188 r100_vram_init_sizes(rdev);
189 radeon_vram_location(rdev, &rdev->mc, 0);
190 rdev->mc.gtt_base_align = 0;
191 if (!(rdev->flags & RADEON_IS_AGP))
192 radeon_gtt_location(rdev, &rdev->mc);
193 radeon_update_bandwidth_info(rdev);
196 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
201 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
202 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
203 r = RREG32(MC_IND_DATA);
204 WREG32(MC_IND_INDEX, 0);
205 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
210 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
214 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
215 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
216 WREG32(MC_IND_DATA, (v));
217 WREG32(MC_IND_INDEX, 0);
218 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
221 #if defined(CONFIG_DEBUG_FS)
222 static int rv515_debugfs_pipes_info_show(struct seq_file *m, void *unused)
224 struct radeon_device *rdev = (struct radeon_device *)m->private;
227 tmp = RREG32(GB_PIPE_SELECT);
228 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
229 tmp = RREG32(SU_REG_DEST);
230 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
231 tmp = RREG32(GB_TILE_CONFIG);
232 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
233 tmp = RREG32(DST_PIPE_CONFIG);
234 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
238 static int rv515_debugfs_ga_info_show(struct seq_file *m, void *unused)
240 struct radeon_device *rdev = (struct radeon_device *)m->private;
243 tmp = RREG32(0x2140);
244 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
245 radeon_asic_reset(rdev);
246 tmp = RREG32(0x425C);
247 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
251 DEFINE_SHOW_ATTRIBUTE(rv515_debugfs_pipes_info);
252 DEFINE_SHOW_ATTRIBUTE(rv515_debugfs_ga_info);
255 void rv515_debugfs(struct radeon_device *rdev)
257 #if defined(CONFIG_DEBUG_FS)
258 struct dentry *root = rdev->ddev->primary->debugfs_root;
260 debugfs_create_file("rv515_pipes_info", 0444, root, rdev,
261 &rv515_debugfs_pipes_info_fops);
262 debugfs_create_file("rv515_ga_info", 0444, root, rdev,
263 &rv515_debugfs_ga_info_fops);
265 r100_debugfs_rbbm_init(rdev);
268 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
270 u32 crtc_enabled, tmp, frame_count, blackout;
273 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
274 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
276 /* disable VGA render */
277 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
278 /* blank the display controllers */
279 for (i = 0; i < rdev->num_crtc; i++) {
280 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
282 save->crtc_enabled[i] = true;
283 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
284 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
285 radeon_wait_for_vblank(rdev, i);
286 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
287 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
288 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
289 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
291 /* wait for the next frame */
292 frame_count = radeon_get_vblank_counter(rdev, i);
293 for (j = 0; j < rdev->usec_timeout; j++) {
294 if (radeon_get_vblank_counter(rdev, i) != frame_count)
299 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
300 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
301 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
302 tmp &= ~AVIVO_CRTC_EN;
303 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
304 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
305 save->crtc_enabled[i] = false;
308 save->crtc_enabled[i] = false;
312 radeon_mc_wait_for_idle(rdev);
314 if (rdev->family >= CHIP_R600) {
315 if (rdev->family >= CHIP_RV770)
316 blackout = RREG32(R700_MC_CITF_CNTL);
318 blackout = RREG32(R600_CITF_CNTL);
319 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
320 /* Block CPU access */
321 WREG32(R600_BIF_FB_EN, 0);
322 /* blackout the MC */
323 blackout |= R600_BLACKOUT_MASK;
324 if (rdev->family >= CHIP_RV770)
325 WREG32(R700_MC_CITF_CNTL, blackout);
327 WREG32(R600_CITF_CNTL, blackout);
330 /* wait for the MC to settle */
333 /* lock double buffered regs */
334 for (i = 0; i < rdev->num_crtc; i++) {
335 if (save->crtc_enabled[i]) {
336 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
337 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
338 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
339 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
341 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
344 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
350 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
352 u32 tmp, frame_count;
355 /* update crtc base addresses */
356 for (i = 0; i < rdev->num_crtc; i++) {
357 if (rdev->family >= CHIP_RV770) {
359 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
360 upper_32_bits(rdev->mc.vram_start));
361 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
362 upper_32_bits(rdev->mc.vram_start));
364 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
365 upper_32_bits(rdev->mc.vram_start));
366 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
367 upper_32_bits(rdev->mc.vram_start));
370 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
371 (u32)rdev->mc.vram_start);
372 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
373 (u32)rdev->mc.vram_start);
375 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
377 /* unlock regs and wait for update */
378 for (i = 0; i < rdev->num_crtc; i++) {
379 if (save->crtc_enabled[i]) {
380 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
381 if ((tmp & 0x7) != 3) {
384 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
386 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
387 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
388 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
389 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
391 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
394 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
396 for (j = 0; j < rdev->usec_timeout; j++) {
397 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
398 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
405 if (rdev->family >= CHIP_R600) {
406 /* unblackout the MC */
407 if (rdev->family >= CHIP_RV770)
408 tmp = RREG32(R700_MC_CITF_CNTL);
410 tmp = RREG32(R600_CITF_CNTL);
411 tmp &= ~R600_BLACKOUT_MASK;
412 if (rdev->family >= CHIP_RV770)
413 WREG32(R700_MC_CITF_CNTL, tmp);
415 WREG32(R600_CITF_CNTL, tmp);
416 /* allow CPU access */
417 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
420 for (i = 0; i < rdev->num_crtc; i++) {
421 if (save->crtc_enabled[i]) {
422 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
423 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
424 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
425 /* wait for the next frame */
426 frame_count = radeon_get_vblank_counter(rdev, i);
427 for (j = 0; j < rdev->usec_timeout; j++) {
428 if (radeon_get_vblank_counter(rdev, i) != frame_count)
434 /* Unlock vga access */
435 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
437 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
440 static void rv515_mc_program(struct radeon_device *rdev)
442 struct rv515_mc_save save;
444 /* Stops all mc clients */
445 rv515_mc_stop(rdev, &save);
447 /* Wait for mc idle */
448 if (rv515_mc_wait_for_idle(rdev))
449 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
450 /* Write VRAM size in case we are limiting it */
451 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
452 /* Program MC, should be a 32bits limited address space */
453 WREG32_MC(R_000001_MC_FB_LOCATION,
454 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
455 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
456 WREG32(R_000134_HDP_FB_LOCATION,
457 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
458 if (rdev->flags & RADEON_IS_AGP) {
459 WREG32_MC(R_000002_MC_AGP_LOCATION,
460 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
461 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
462 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
463 WREG32_MC(R_000004_MC_AGP_BASE_2,
464 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
466 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
467 WREG32_MC(R_000003_MC_AGP_BASE, 0);
468 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
471 rv515_mc_resume(rdev, &save);
474 void rv515_clock_startup(struct radeon_device *rdev)
476 if (radeon_dynclks != -1 && radeon_dynclks)
477 radeon_atom_set_clock_gating(rdev, 1);
478 /* We need to force on some of the block */
479 WREG32_PLL(R_00000F_CP_DYN_CNTL,
480 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
481 WREG32_PLL(R_000011_E2_DYN_CNTL,
482 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
483 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
484 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
487 static int rv515_startup(struct radeon_device *rdev)
491 rv515_mc_program(rdev);
493 rv515_clock_startup(rdev);
494 /* Initialize GPU configuration (# pipes, ...) */
495 rv515_gpu_init(rdev);
496 /* Initialize GART (initialize after TTM so we can allocate
497 * memory through TTM but finalize after TTM) */
498 if (rdev->flags & RADEON_IS_PCIE) {
499 r = rv370_pcie_gart_enable(rdev);
504 /* allocate wb buffer */
505 r = radeon_wb_init(rdev);
509 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
511 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
516 if (!rdev->irq.installed) {
517 r = radeon_irq_kms_init(rdev);
523 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
525 r = r100_cp_init(rdev, 1024 * 1024);
527 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
531 r = radeon_ib_pool_init(rdev);
533 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
540 int rv515_resume(struct radeon_device *rdev)
544 /* Make sur GART are not working */
545 if (rdev->flags & RADEON_IS_PCIE)
546 rv370_pcie_gart_disable(rdev);
547 /* Resume clock before doing reset */
548 rv515_clock_startup(rdev);
549 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
550 if (radeon_asic_reset(rdev)) {
551 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
552 RREG32(R_000E40_RBBM_STATUS),
553 RREG32(R_0007C0_CP_STAT));
556 atom_asic_init(rdev->mode_info.atom_context);
557 /* Resume clock after posting */
558 rv515_clock_startup(rdev);
559 /* Initialize surface registers */
560 radeon_surface_init(rdev);
562 rdev->accel_working = true;
563 r = rv515_startup(rdev);
565 rdev->accel_working = false;
570 int rv515_suspend(struct radeon_device *rdev)
572 radeon_pm_suspend(rdev);
573 r100_cp_disable(rdev);
574 radeon_wb_disable(rdev);
575 rs600_irq_disable(rdev);
576 if (rdev->flags & RADEON_IS_PCIE)
577 rv370_pcie_gart_disable(rdev);
581 void rv515_set_safe_registers(struct radeon_device *rdev)
583 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
584 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
587 void rv515_fini(struct radeon_device *rdev)
589 radeon_pm_fini(rdev);
591 radeon_wb_fini(rdev);
592 radeon_ib_pool_fini(rdev);
593 radeon_gem_fini(rdev);
594 rv370_pcie_gart_fini(rdev);
595 radeon_agp_fini(rdev);
596 radeon_irq_kms_fini(rdev);
597 radeon_fence_driver_fini(rdev);
598 radeon_bo_fini(rdev);
599 radeon_atombios_fini(rdev);
604 int rv515_init(struct radeon_device *rdev)
608 /* Initialize scratch registers */
609 radeon_scratch_init(rdev);
610 /* Initialize surface registers */
611 radeon_surface_init(rdev);
612 /* TODO: disable VGA need to use VGA request */
613 /* restore some register to sane defaults */
614 r100_restore_sanity(rdev);
616 if (!radeon_get_bios(rdev)) {
617 if (ASIC_IS_AVIVO(rdev))
620 if (rdev->is_atom_bios) {
621 r = radeon_atombios_init(rdev);
625 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
628 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
629 if (radeon_asic_reset(rdev)) {
631 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
632 RREG32(R_000E40_RBBM_STATUS),
633 RREG32(R_0007C0_CP_STAT));
635 /* check if cards are posted or not */
636 if (radeon_boot_test_post_card(rdev) == false)
638 /* Initialize clocks */
639 radeon_get_clock_info(rdev->ddev);
641 if (rdev->flags & RADEON_IS_AGP) {
642 r = radeon_agp_init(rdev);
644 radeon_agp_disable(rdev);
647 /* initialize memory controller */
651 r = radeon_fence_driver_init(rdev);
655 r = radeon_bo_init(rdev);
658 r = rv370_pcie_gart_init(rdev);
661 rv515_set_safe_registers(rdev);
663 /* Initialize power management */
664 radeon_pm_init(rdev);
666 rdev->accel_working = true;
667 r = rv515_startup(rdev);
669 /* Somethings want wront with the accel init stop accel */
670 dev_err(rdev->dev, "Disabling GPU acceleration\n");
672 radeon_wb_fini(rdev);
673 radeon_ib_pool_fini(rdev);
674 radeon_irq_kms_fini(rdev);
675 rv370_pcie_gart_fini(rdev);
676 radeon_agp_fini(rdev);
677 rdev->accel_working = false;
682 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
684 int index_reg = 0x6578 + crtc->crtc_offset;
685 int data_reg = 0x657c + crtc->crtc_offset;
687 WREG32(0x659C + crtc->crtc_offset, 0x0);
688 WREG32(0x6594 + crtc->crtc_offset, 0x705);
689 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
690 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
691 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
692 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
693 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
694 WREG32(index_reg, 0x0);
695 WREG32(data_reg, 0x841880A8);
696 WREG32(index_reg, 0x1);
697 WREG32(data_reg, 0x84208680);
698 WREG32(index_reg, 0x2);
699 WREG32(data_reg, 0xBFF880B0);
700 WREG32(index_reg, 0x100);
701 WREG32(data_reg, 0x83D88088);
702 WREG32(index_reg, 0x101);
703 WREG32(data_reg, 0x84608680);
704 WREG32(index_reg, 0x102);
705 WREG32(data_reg, 0xBFF080D0);
706 WREG32(index_reg, 0x200);
707 WREG32(data_reg, 0x83988068);
708 WREG32(index_reg, 0x201);
709 WREG32(data_reg, 0x84A08680);
710 WREG32(index_reg, 0x202);
711 WREG32(data_reg, 0xBFF080F8);
712 WREG32(index_reg, 0x300);
713 WREG32(data_reg, 0x83588058);
714 WREG32(index_reg, 0x301);
715 WREG32(data_reg, 0x84E08660);
716 WREG32(index_reg, 0x302);
717 WREG32(data_reg, 0xBFF88120);
718 WREG32(index_reg, 0x400);
719 WREG32(data_reg, 0x83188040);
720 WREG32(index_reg, 0x401);
721 WREG32(data_reg, 0x85008660);
722 WREG32(index_reg, 0x402);
723 WREG32(data_reg, 0xBFF88150);
724 WREG32(index_reg, 0x500);
725 WREG32(data_reg, 0x82D88030);
726 WREG32(index_reg, 0x501);
727 WREG32(data_reg, 0x85408640);
728 WREG32(index_reg, 0x502);
729 WREG32(data_reg, 0xBFF88180);
730 WREG32(index_reg, 0x600);
731 WREG32(data_reg, 0x82A08018);
732 WREG32(index_reg, 0x601);
733 WREG32(data_reg, 0x85808620);
734 WREG32(index_reg, 0x602);
735 WREG32(data_reg, 0xBFF081B8);
736 WREG32(index_reg, 0x700);
737 WREG32(data_reg, 0x82608010);
738 WREG32(index_reg, 0x701);
739 WREG32(data_reg, 0x85A08600);
740 WREG32(index_reg, 0x702);
741 WREG32(data_reg, 0x800081F0);
742 WREG32(index_reg, 0x800);
743 WREG32(data_reg, 0x8228BFF8);
744 WREG32(index_reg, 0x801);
745 WREG32(data_reg, 0x85E085E0);
746 WREG32(index_reg, 0x802);
747 WREG32(data_reg, 0xBFF88228);
748 WREG32(index_reg, 0x10000);
749 WREG32(data_reg, 0x82A8BF00);
750 WREG32(index_reg, 0x10001);
751 WREG32(data_reg, 0x82A08CC0);
752 WREG32(index_reg, 0x10002);
753 WREG32(data_reg, 0x8008BEF8);
754 WREG32(index_reg, 0x10100);
755 WREG32(data_reg, 0x81F0BF28);
756 WREG32(index_reg, 0x10101);
757 WREG32(data_reg, 0x83608CA0);
758 WREG32(index_reg, 0x10102);
759 WREG32(data_reg, 0x8018BED0);
760 WREG32(index_reg, 0x10200);
761 WREG32(data_reg, 0x8148BF38);
762 WREG32(index_reg, 0x10201);
763 WREG32(data_reg, 0x84408C80);
764 WREG32(index_reg, 0x10202);
765 WREG32(data_reg, 0x8008BEB8);
766 WREG32(index_reg, 0x10300);
767 WREG32(data_reg, 0x80B0BF78);
768 WREG32(index_reg, 0x10301);
769 WREG32(data_reg, 0x85008C20);
770 WREG32(index_reg, 0x10302);
771 WREG32(data_reg, 0x8020BEA0);
772 WREG32(index_reg, 0x10400);
773 WREG32(data_reg, 0x8028BF90);
774 WREG32(index_reg, 0x10401);
775 WREG32(data_reg, 0x85E08BC0);
776 WREG32(index_reg, 0x10402);
777 WREG32(data_reg, 0x8018BE90);
778 WREG32(index_reg, 0x10500);
779 WREG32(data_reg, 0xBFB8BFB0);
780 WREG32(index_reg, 0x10501);
781 WREG32(data_reg, 0x86C08B40);
782 WREG32(index_reg, 0x10502);
783 WREG32(data_reg, 0x8010BE90);
784 WREG32(index_reg, 0x10600);
785 WREG32(data_reg, 0xBF58BFC8);
786 WREG32(index_reg, 0x10601);
787 WREG32(data_reg, 0x87A08AA0);
788 WREG32(index_reg, 0x10602);
789 WREG32(data_reg, 0x8010BE98);
790 WREG32(index_reg, 0x10700);
791 WREG32(data_reg, 0xBF10BFF0);
792 WREG32(index_reg, 0x10701);
793 WREG32(data_reg, 0x886089E0);
794 WREG32(index_reg, 0x10702);
795 WREG32(data_reg, 0x8018BEB0);
796 WREG32(index_reg, 0x10800);
797 WREG32(data_reg, 0xBED8BFE8);
798 WREG32(index_reg, 0x10801);
799 WREG32(data_reg, 0x89408940);
800 WREG32(index_reg, 0x10802);
801 WREG32(data_reg, 0xBFE8BED8);
802 WREG32(index_reg, 0x20000);
803 WREG32(data_reg, 0x80008000);
804 WREG32(index_reg, 0x20001);
805 WREG32(data_reg, 0x90008000);
806 WREG32(index_reg, 0x20002);
807 WREG32(data_reg, 0x80008000);
808 WREG32(index_reg, 0x20003);
809 WREG32(data_reg, 0x80008000);
810 WREG32(index_reg, 0x20100);
811 WREG32(data_reg, 0x80108000);
812 WREG32(index_reg, 0x20101);
813 WREG32(data_reg, 0x8FE0BF70);
814 WREG32(index_reg, 0x20102);
815 WREG32(data_reg, 0xBFE880C0);
816 WREG32(index_reg, 0x20103);
817 WREG32(data_reg, 0x80008000);
818 WREG32(index_reg, 0x20200);
819 WREG32(data_reg, 0x8018BFF8);
820 WREG32(index_reg, 0x20201);
821 WREG32(data_reg, 0x8F80BF08);
822 WREG32(index_reg, 0x20202);
823 WREG32(data_reg, 0xBFD081A0);
824 WREG32(index_reg, 0x20203);
825 WREG32(data_reg, 0xBFF88000);
826 WREG32(index_reg, 0x20300);
827 WREG32(data_reg, 0x80188000);
828 WREG32(index_reg, 0x20301);
829 WREG32(data_reg, 0x8EE0BEC0);
830 WREG32(index_reg, 0x20302);
831 WREG32(data_reg, 0xBFB082A0);
832 WREG32(index_reg, 0x20303);
833 WREG32(data_reg, 0x80008000);
834 WREG32(index_reg, 0x20400);
835 WREG32(data_reg, 0x80188000);
836 WREG32(index_reg, 0x20401);
837 WREG32(data_reg, 0x8E00BEA0);
838 WREG32(index_reg, 0x20402);
839 WREG32(data_reg, 0xBF8883C0);
840 WREG32(index_reg, 0x20403);
841 WREG32(data_reg, 0x80008000);
842 WREG32(index_reg, 0x20500);
843 WREG32(data_reg, 0x80188000);
844 WREG32(index_reg, 0x20501);
845 WREG32(data_reg, 0x8D00BE90);
846 WREG32(index_reg, 0x20502);
847 WREG32(data_reg, 0xBF588500);
848 WREG32(index_reg, 0x20503);
849 WREG32(data_reg, 0x80008008);
850 WREG32(index_reg, 0x20600);
851 WREG32(data_reg, 0x80188000);
852 WREG32(index_reg, 0x20601);
853 WREG32(data_reg, 0x8BC0BE98);
854 WREG32(index_reg, 0x20602);
855 WREG32(data_reg, 0xBF308660);
856 WREG32(index_reg, 0x20603);
857 WREG32(data_reg, 0x80008008);
858 WREG32(index_reg, 0x20700);
859 WREG32(data_reg, 0x80108000);
860 WREG32(index_reg, 0x20701);
861 WREG32(data_reg, 0x8A80BEB0);
862 WREG32(index_reg, 0x20702);
863 WREG32(data_reg, 0xBF0087C0);
864 WREG32(index_reg, 0x20703);
865 WREG32(data_reg, 0x80008008);
866 WREG32(index_reg, 0x20800);
867 WREG32(data_reg, 0x80108000);
868 WREG32(index_reg, 0x20801);
869 WREG32(data_reg, 0x8920BED0);
870 WREG32(index_reg, 0x20802);
871 WREG32(data_reg, 0xBED08920);
872 WREG32(index_reg, 0x20803);
873 WREG32(data_reg, 0x80008010);
874 WREG32(index_reg, 0x30000);
875 WREG32(data_reg, 0x90008000);
876 WREG32(index_reg, 0x30001);
877 WREG32(data_reg, 0x80008000);
878 WREG32(index_reg, 0x30100);
879 WREG32(data_reg, 0x8FE0BF90);
880 WREG32(index_reg, 0x30101);
881 WREG32(data_reg, 0xBFF880A0);
882 WREG32(index_reg, 0x30200);
883 WREG32(data_reg, 0x8F60BF40);
884 WREG32(index_reg, 0x30201);
885 WREG32(data_reg, 0xBFE88180);
886 WREG32(index_reg, 0x30300);
887 WREG32(data_reg, 0x8EC0BF00);
888 WREG32(index_reg, 0x30301);
889 WREG32(data_reg, 0xBFC88280);
890 WREG32(index_reg, 0x30400);
891 WREG32(data_reg, 0x8DE0BEE0);
892 WREG32(index_reg, 0x30401);
893 WREG32(data_reg, 0xBFA083A0);
894 WREG32(index_reg, 0x30500);
895 WREG32(data_reg, 0x8CE0BED0);
896 WREG32(index_reg, 0x30501);
897 WREG32(data_reg, 0xBF7884E0);
898 WREG32(index_reg, 0x30600);
899 WREG32(data_reg, 0x8BA0BED8);
900 WREG32(index_reg, 0x30601);
901 WREG32(data_reg, 0xBF508640);
902 WREG32(index_reg, 0x30700);
903 WREG32(data_reg, 0x8A60BEE8);
904 WREG32(index_reg, 0x30701);
905 WREG32(data_reg, 0xBF2087A0);
906 WREG32(index_reg, 0x30800);
907 WREG32(data_reg, 0x8900BF00);
908 WREG32(index_reg, 0x30801);
909 WREG32(data_reg, 0xBF008900);
912 struct rv515_watermark {
913 u32 lb_request_fifo_depth;
914 fixed20_12 num_line_pair;
915 fixed20_12 estimated_width;
916 fixed20_12 worst_case_latency;
917 fixed20_12 consumption_rate;
918 fixed20_12 active_time;
920 fixed20_12 priority_mark_max;
921 fixed20_12 priority_mark;
925 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
926 struct radeon_crtc *crtc,
927 struct rv515_watermark *wm,
930 struct drm_display_mode *mode = &crtc->base.mode;
932 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
933 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
937 if (!crtc->base.enabled) {
938 /* FIXME: wouldn't it better to set priority mark to maximum */
939 wm->lb_request_fifo_depth = 4;
944 if ((rdev->family >= CHIP_RV610) &&
945 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
946 selected_sclk = radeon_dpm_get_sclk(rdev, low);
948 selected_sclk = rdev->pm.current_sclk;
951 a.full = dfixed_const(100);
952 sclk.full = dfixed_const(selected_sclk);
953 sclk.full = dfixed_div(sclk, a);
955 if (crtc->vsc.full > dfixed_const(2))
956 wm->num_line_pair.full = dfixed_const(2);
958 wm->num_line_pair.full = dfixed_const(1);
960 b.full = dfixed_const(mode->crtc_hdisplay);
961 c.full = dfixed_const(256);
962 a.full = dfixed_div(b, c);
963 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
964 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
965 if (a.full < dfixed_const(4)) {
966 wm->lb_request_fifo_depth = 4;
968 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
971 /* Determine consumption rate
972 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
973 * vtaps = number of vertical taps,
974 * vsc = vertical scaling ratio, defined as source/destination
975 * hsc = horizontal scaling ration, defined as source/destination
977 a.full = dfixed_const(mode->clock);
978 b.full = dfixed_const(1000);
979 a.full = dfixed_div(a, b);
980 pclk.full = dfixed_div(b, a);
981 if (crtc->rmx_type != RMX_OFF) {
982 b.full = dfixed_const(2);
983 if (crtc->vsc.full > b.full)
984 b.full = crtc->vsc.full;
985 b.full = dfixed_mul(b, crtc->hsc);
986 c.full = dfixed_const(2);
987 b.full = dfixed_div(b, c);
988 consumption_time.full = dfixed_div(pclk, b);
990 consumption_time.full = pclk.full;
992 a.full = dfixed_const(1);
993 wm->consumption_rate.full = dfixed_div(a, consumption_time);
996 /* Determine line time
997 * LineTime = total time for one line of displayhtotal
998 * LineTime = total number of horizontal pixels
999 * pclk = pixel clock period(ns)
1001 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1002 line_time.full = dfixed_mul(a, pclk);
1004 /* Determine active time
1005 * ActiveTime = time of active region of display within one line,
1006 * hactive = total number of horizontal active pixels
1007 * htotal = total number of horizontal pixels
1009 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1010 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1011 wm->active_time.full = dfixed_mul(line_time, b);
1012 wm->active_time.full = dfixed_div(wm->active_time, a);
1014 /* Determine chunk time
1015 * ChunkTime = the time it takes the DCP to send one chunk of data
1016 * to the LB which consists of pipeline delay and inter chunk gap
1017 * sclk = system clock(Mhz)
1019 a.full = dfixed_const(600 * 1000);
1020 chunk_time.full = dfixed_div(a, sclk);
1021 read_delay_latency.full = dfixed_const(1000);
1023 /* Determine the worst case latency
1024 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
1025 * WorstCaseLatency = worst case time from urgent to when the MC starts
1027 * READ_DELAY_IDLE_MAX = constant of 1us
1028 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
1029 * which consists of pipeline delay and inter chunk gap
1031 if (dfixed_trunc(wm->num_line_pair) > 1) {
1032 a.full = dfixed_const(3);
1033 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
1034 wm->worst_case_latency.full += read_delay_latency.full;
1036 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
1039 /* Determine the tolerable latency
1040 * TolerableLatency = Any given request has only 1 line time
1041 * for the data to be returned
1042 * LBRequestFifoDepth = Number of chunk requests the LB can
1043 * put into the request FIFO for a display
1044 * LineTime = total time for one line of display
1045 * ChunkTime = the time it takes the DCP to send one chunk
1046 * of data to the LB which consists of
1047 * pipeline delay and inter chunk gap
1049 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
1050 tolerable_latency.full = line_time.full;
1052 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
1053 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
1054 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
1055 tolerable_latency.full = line_time.full - tolerable_latency.full;
1057 /* We assume worst case 32bits (4 bytes) */
1058 wm->dbpp.full = dfixed_const(2 * 16);
1060 /* Determine the maximum priority mark
1061 * width = viewport width in pixels
1063 a.full = dfixed_const(16);
1064 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1065 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
1066 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
1068 /* Determine estimated width */
1069 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1070 estimated_width.full = dfixed_div(estimated_width, consumption_time);
1071 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1072 wm->priority_mark.full = wm->priority_mark_max.full;
1074 a.full = dfixed_const(16);
1075 wm->priority_mark.full = dfixed_div(estimated_width, a);
1076 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
1077 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1081 static void rv515_compute_mode_priority(struct radeon_device *rdev,
1082 struct rv515_watermark *wm0,
1083 struct rv515_watermark *wm1,
1084 struct drm_display_mode *mode0,
1085 struct drm_display_mode *mode1,
1086 u32 *d1mode_priority_a_cnt,
1087 u32 *d2mode_priority_a_cnt)
1089 fixed20_12 priority_mark02, priority_mark12, fill_rate;
1092 *d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
1093 *d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
1095 if (mode0 && mode1) {
1096 if (dfixed_trunc(wm0->dbpp) > 64)
1097 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1099 a.full = wm0->num_line_pair.full;
1100 if (dfixed_trunc(wm1->dbpp) > 64)
1101 b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1103 b.full = wm1->num_line_pair.full;
1105 fill_rate.full = dfixed_div(wm0->sclk, a);
1106 if (wm0->consumption_rate.full > fill_rate.full) {
1107 b.full = wm0->consumption_rate.full - fill_rate.full;
1108 b.full = dfixed_mul(b, wm0->active_time);
1109 a.full = dfixed_const(16);
1110 b.full = dfixed_div(b, a);
1111 a.full = dfixed_mul(wm0->worst_case_latency,
1112 wm0->consumption_rate);
1113 priority_mark02.full = a.full + b.full;
1115 a.full = dfixed_mul(wm0->worst_case_latency,
1116 wm0->consumption_rate);
1117 b.full = dfixed_const(16 * 1000);
1118 priority_mark02.full = dfixed_div(a, b);
1120 if (wm1->consumption_rate.full > fill_rate.full) {
1121 b.full = wm1->consumption_rate.full - fill_rate.full;
1122 b.full = dfixed_mul(b, wm1->active_time);
1123 a.full = dfixed_const(16);
1124 b.full = dfixed_div(b, a);
1125 a.full = dfixed_mul(wm1->worst_case_latency,
1126 wm1->consumption_rate);
1127 priority_mark12.full = a.full + b.full;
1129 a.full = dfixed_mul(wm1->worst_case_latency,
1130 wm1->consumption_rate);
1131 b.full = dfixed_const(16 * 1000);
1132 priority_mark12.full = dfixed_div(a, b);
1134 if (wm0->priority_mark.full > priority_mark02.full)
1135 priority_mark02.full = wm0->priority_mark.full;
1136 if (wm0->priority_mark_max.full > priority_mark02.full)
1137 priority_mark02.full = wm0->priority_mark_max.full;
1138 if (wm1->priority_mark.full > priority_mark12.full)
1139 priority_mark12.full = wm1->priority_mark.full;
1140 if (wm1->priority_mark_max.full > priority_mark12.full)
1141 priority_mark12.full = wm1->priority_mark_max.full;
1142 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1143 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1144 if (rdev->disp_priority == 2) {
1145 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1146 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1149 if (dfixed_trunc(wm0->dbpp) > 64)
1150 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1152 a.full = wm0->num_line_pair.full;
1153 fill_rate.full = dfixed_div(wm0->sclk, a);
1154 if (wm0->consumption_rate.full > fill_rate.full) {
1155 b.full = wm0->consumption_rate.full - fill_rate.full;
1156 b.full = dfixed_mul(b, wm0->active_time);
1157 a.full = dfixed_const(16);
1158 b.full = dfixed_div(b, a);
1159 a.full = dfixed_mul(wm0->worst_case_latency,
1160 wm0->consumption_rate);
1161 priority_mark02.full = a.full + b.full;
1163 a.full = dfixed_mul(wm0->worst_case_latency,
1164 wm0->consumption_rate);
1165 b.full = dfixed_const(16);
1166 priority_mark02.full = dfixed_div(a, b);
1168 if (wm0->priority_mark.full > priority_mark02.full)
1169 priority_mark02.full = wm0->priority_mark.full;
1170 if (wm0->priority_mark_max.full > priority_mark02.full)
1171 priority_mark02.full = wm0->priority_mark_max.full;
1172 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1173 if (rdev->disp_priority == 2)
1174 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1176 if (dfixed_trunc(wm1->dbpp) > 64)
1177 a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1179 a.full = wm1->num_line_pair.full;
1180 fill_rate.full = dfixed_div(wm1->sclk, a);
1181 if (wm1->consumption_rate.full > fill_rate.full) {
1182 b.full = wm1->consumption_rate.full - fill_rate.full;
1183 b.full = dfixed_mul(b, wm1->active_time);
1184 a.full = dfixed_const(16);
1185 b.full = dfixed_div(b, a);
1186 a.full = dfixed_mul(wm1->worst_case_latency,
1187 wm1->consumption_rate);
1188 priority_mark12.full = a.full + b.full;
1190 a.full = dfixed_mul(wm1->worst_case_latency,
1191 wm1->consumption_rate);
1192 b.full = dfixed_const(16 * 1000);
1193 priority_mark12.full = dfixed_div(a, b);
1195 if (wm1->priority_mark.full > priority_mark12.full)
1196 priority_mark12.full = wm1->priority_mark.full;
1197 if (wm1->priority_mark_max.full > priority_mark12.full)
1198 priority_mark12.full = wm1->priority_mark_max.full;
1199 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1200 if (rdev->disp_priority == 2)
1201 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1205 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1207 struct drm_display_mode *mode0 = NULL;
1208 struct drm_display_mode *mode1 = NULL;
1209 struct rv515_watermark wm0_high, wm0_low;
1210 struct rv515_watermark wm1_high, wm1_low;
1212 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
1213 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
1215 if (rdev->mode_info.crtcs[0]->base.enabled)
1216 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1217 if (rdev->mode_info.crtcs[1]->base.enabled)
1218 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1219 rs690_line_buffer_adjust(rdev, mode0, mode1);
1221 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
1222 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
1224 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
1225 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
1227 tmp = wm0_high.lb_request_fifo_depth;
1228 tmp |= wm1_high.lb_request_fifo_depth << 16;
1229 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1231 rv515_compute_mode_priority(rdev,
1232 &wm0_high, &wm1_high,
1234 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
1235 rv515_compute_mode_priority(rdev,
1238 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
1240 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1241 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
1242 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1243 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
1246 void rv515_bandwidth_update(struct radeon_device *rdev)
1249 struct drm_display_mode *mode0 = NULL;
1250 struct drm_display_mode *mode1 = NULL;
1252 if (!rdev->mode_info.mode_config_initialized)
1255 radeon_update_display_priority(rdev);
1257 if (rdev->mode_info.crtcs[0]->base.enabled)
1258 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1259 if (rdev->mode_info.crtcs[1]->base.enabled)
1260 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1262 * Set display0/1 priority up in the memory controller for
1263 * modes if the user specifies HIGH for displaypriority
1266 if ((rdev->disp_priority == 2) &&
1267 (rdev->family == CHIP_RV515)) {
1268 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1269 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1270 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1272 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1274 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1275 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1277 rv515_bandwidth_avivo_update(rdev);