drivers/gpu/drm/radeon/rs600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 /* RS600 / Radeon X1250/X1270 integrated GPU
  29  *
  30  * This file gather function specific to RS600 which is the IGP of
  31  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33  * the avivo one, bios is an atombios, 3D block are the one of the
  34  * R4XX family. The GART is different from the RS400 one and is very
  35  * close to the one of the R600 family (R600 likely being an evolution
  36  * of the RS600 GART block).
  37  */
  38 #include <drm/drmP.h>
  39 #include "radeon.h"
  40 #include "radeon_asic.h"
  41 #include "radeon_audio.h"
  42 #include "atom.h"
  43 #include "rs600d.h"
  44
  45 #include "rs600_reg_safe.h"
  46
  47 static void rs600_gpu_init(struct radeon_device *rdev);
  48 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  49
  50 static const u32 crtc_offsets[2] =
  51 {
  52         0,
  53         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  54 };
  55
  56 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
  57 {
  58         if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
  59                 return true;
  60         else
  61                 return false;
  62 }
  63
  64 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
  65 {
  66         u32 pos1, pos2;
  67
  68         pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
  69         pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
  70
  71         if (pos1 != pos2)
  72                 return true;
  73         else
  74                 return false;
  75 }
  76
  77 /**
  78  * avivo_wait_for_vblank - vblank wait asic callback.
  79  *
  80  * @rdev: radeon_device pointer
  81  * @crtc: crtc to wait for vblank on
  82  *
  83  * Wait for vblank on the requested crtc (r5xx-r7xx).
  84  */
  85 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
  86 {
  87         unsigned i = 0;
  88
  89         if (crtc >= rdev->num_crtc)
  90                 return;
  91
  92         if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
  93                 return;
  94
  95         /* depending on when we hit vblank, we may be close to active; if so,
  96          * wait for another frame.
  97          */
  98         while (avivo_is_in_vblank(rdev, crtc)) {
  99                 if (i++ % 100 == 0) {
 100                         if (!avivo_is_counter_moving(rdev, crtc))
 101                                 break;
 102                 }
 103         }
 104
 105         while (!avivo_is_in_vblank(rdev, crtc)) {
 106                 if (i++ % 100 == 0) {
 107                         if (!avivo_is_counter_moving(rdev, crtc))
 108                                 break;
 109                 }
 110         }
 111 }
 112
 113 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 114 {
 115         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 116         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
 117         int i;
 118
 119         /* Lock the graphics update lock */
 120         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
 121         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 122
 123         /* update the scanout addresses */
 124         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 125                (u32)crtc_base);
 126         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 127                (u32)crtc_base);
 128
 129         /* Wait for update_pending to go high. */
 130         for (i = 0; i < rdev->usec_timeout; i++) {
 131                 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
 132                         break;
 133                 udelay(1);
 134         }
 135         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 136
 137         /* Unlock the lock, so double-buffering can take place inside vblank */
 138         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
 139         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 140 }
 141
 142 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)
 143 {
 144         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 145
 146         /* Return current update_pending status: */
 147         return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
 148                 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);
 149 }
 150
 151 void avivo_program_fmt(struct drm_encoder *encoder)
 152 {
 153         struct drm_device *dev = encoder->dev;
 154         struct radeon_device *rdev = dev->dev_private;
 155         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 156         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 157         int bpc = 0;
 158         u32 tmp = 0;
 159         enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
 160
 161         if (connector) {
 162                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 163                 bpc = radeon_get_monitor_bpc(connector);
 164                 dither = radeon_connector->dither;
 165         }
 166
 167         /* LVDS FMT is set up by atom */
 168         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 169                 return;
 170
 171         if (bpc == 0)
 172                 return;
 173
 174         switch (bpc) {
 175         case 6:
 176                 if (dither == RADEON_FMT_DITHER_ENABLE)
 177                         /* XXX sort out optimal dither settings */
 178                         tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
 179                 else
 180                         tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
 181                 break;
 182         case 8:
 183                 if (dither == RADEON_FMT_DITHER_ENABLE)
 184                         /* XXX sort out optimal dither settings */
 185                         tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
 186                                 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
 187                 else
 188                         tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
 189                                 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
 190                 break;
 191         case 10:
 192         default:
 193                 /* not needed */
 194                 break;
 195         }
 196
 197         switch (radeon_encoder->encoder_id) {
 198         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 199                 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
 200                 break;
 201         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 202                 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
 203                 break;
 204         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 205                 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
 206                 break;
 207         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 208                 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
 209                 break;
 210         default:
 211                 break;
 212         }
 213 }
 214
 215 void rs600_pm_misc(struct radeon_device *rdev)
 216 {
 217         int requested_index = rdev->pm.requested_power_state_index;
 218         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 219         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 220         u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
 221         u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
 222
 223         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 224                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 225                         tmp = RREG32(voltage->gpio.reg);
 226                         if (voltage->active_high)
 227                                 tmp |= voltage->gpio.mask;
 228                         else
 229                                 tmp &= ~(voltage->gpio.mask);
 230                         WREG32(voltage->gpio.reg, tmp);
 231                         if (voltage->delay)
 232                                 udelay(voltage->delay);
 233                 } else {
 234                         tmp = RREG32(voltage->gpio.reg);
 235                         if (voltage->active_high)
 236                                 tmp &= ~voltage->gpio.mask;
 237                         else
 238                                 tmp |= voltage->gpio.mask;
 239                         WREG32(voltage->gpio.reg, tmp);
 240                         if (voltage->delay)
 241                                 udelay(voltage->delay);
 242                 }
 243         } else if (voltage->type == VOLTAGE_VDDC)
 244                 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
 245
 246         dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
 247         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
 248         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
 249         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 250                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
 251                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
 252                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
 253                 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
 254                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
 255                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
 256                 }
 257         } else {
 258                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
 259                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
 260         }
 261         WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
 262
 263         dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
 264         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 265                 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
 266                 if (voltage->delay) {
 267                         dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
 268                         dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
 269                 } else
 270                         dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
 271         } else
 272                 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
 273         WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
 274
 275         hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
 276         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 277                 hdp_dyn_cntl &= ~HDP_FORCEON;
 278         else
 279                 hdp_dyn_cntl |= HDP_FORCEON;
 280         WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
 281 #if 0
 282         /* mc_host_dyn seems to cause hangs from time to time */
 283         mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
 284         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
 285                 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
 286         else
 287                 mc_host_dyn_cntl |= MC_HOST_FORCEON;
 288         WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
 289 #endif
 290         dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
 291         if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
 292                 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
 293         else
 294                 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
 295         WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
 296
 297         /* set pcie lanes */
 298         if ((rdev->flags & RADEON_IS_PCIE) &&
 299             !(rdev->flags & RADEON_IS_IGP) &&
 300             rdev->asic->pm.set_pcie_lanes &&
 301             (ps->pcie_lanes !=
 302              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 303                 radeon_set_pcie_lanes(rdev,
 304                                       ps->pcie_lanes);
 305                 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
 306         }
 307 }
 308
 309 void rs600_pm_prepare(struct radeon_device *rdev)
 310 {
 311         struct drm_device *ddev = rdev->ddev;
 312         struct drm_crtc *crtc;
 313         struct radeon_crtc *radeon_crtc;
 314         u32 tmp;
 315
 316         /* disable any active CRTCs */
 317         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 318                 radeon_crtc = to_radeon_crtc(crtc);
 319                 if (radeon_crtc->enabled) {
 320                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
 321                         tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 322                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 323                 }
 324         }
 325 }
 326
 327 void rs600_pm_finish(struct radeon_device *rdev)
 328 {
 329         struct drm_device *ddev = rdev->ddev;
 330         struct drm_crtc *crtc;
 331         struct radeon_crtc *radeon_crtc;
 332         u32 tmp;
 333
 334         /* enable any active CRTCs */
 335         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 336                 radeon_crtc = to_radeon_crtc(crtc);
 337                 if (radeon_crtc->enabled) {
 338                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
 339                         tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 340                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 341                 }
 342         }
 343 }
 344
 345 /* hpd for digital panel detect/disconnect */
 346 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 347 {
 348         u32 tmp;
 349         bool connected = false;
 350
 351         switch (hpd) {
 352         case RADEON_HPD_1:
 353                 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
 354                 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
 355                         connected = true;
 356                 break;
 357         case RADEON_HPD_2:
 358                 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
 359                 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
 360                         connected = true;
 361                 break;
 362         default:
 363                 break;
 364         }
 365         return connected;
 366 }
 367
 368 void rs600_hpd_set_polarity(struct radeon_device *rdev,
 369                             enum radeon_hpd_id hpd)
 370 {
 371         u32 tmp;
 372         bool connected = rs600_hpd_sense(rdev, hpd);
 373
 374         switch (hpd) {
 375         case RADEON_HPD_1:
 376                 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 377                 if (connected)
 378                         tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 379                 else
 380                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 381                 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 382                 break;
 383         case RADEON_HPD_2:
 384                 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 385                 if (connected)
 386                         tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 387                 else
 388                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 389                 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 390                 break;
 391         default:
 392                 break;
 393         }
 394 }
 395
 396 void rs600_hpd_init(struct radeon_device *rdev)
 397 {
 398         struct drm_device *dev = rdev->ddev;
 399         struct drm_connector *connector;
 400         unsigned enable = 0;
 401
 402         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 403                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 404                 switch (radeon_connector->hpd.hpd) {
 405                 case RADEON_HPD_1:
 406                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 407                                S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
 408                         break;
 409                 case RADEON_HPD_2:
 410                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 411                                S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
 412                         break;
 413                 default:
 414                         break;
 415                 }
 416                 enable |= 1 << radeon_connector->hpd.hpd;
 417                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 418         }
 419         radeon_irq_kms_enable_hpd(rdev, enable);
 420 }
 421
 422 void rs600_hpd_fini(struct radeon_device *rdev)
 423 {
 424         struct drm_device *dev = rdev->ddev;
 425         struct drm_connector *connector;
 426         unsigned disable = 0;
 427
 428         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 429                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 430                 switch (radeon_connector->hpd.hpd) {
 431                 case RADEON_HPD_1:
 432                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 433                                S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
 434                         break;
 435                 case RADEON_HPD_2:
 436                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 437                                S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
 438                         break;
 439                 default:
 440                         break;
 441                 }
 442                 disable |= 1 << radeon_connector->hpd.hpd;
 443         }
 444         radeon_irq_kms_disable_hpd(rdev, disable);
 445 }
 446
 447 int rs600_asic_reset(struct radeon_device *rdev)
 448 {
 449         struct rv515_mc_save save;
 450         u32 status, tmp;
 451         int ret = 0;
 452
 453         status = RREG32(R_000E40_RBBM_STATUS);
 454         if (!G_000E40_GUI_ACTIVE(status)) {
 455                 return 0;
 456         }
 457         /* Stops all mc clients */
 458         rv515_mc_stop(rdev, &save);
 459         status = RREG32(R_000E40_RBBM_STATUS);
 460         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 461         /* stop CP */
 462         WREG32(RADEON_CP_CSQ_CNTL, 0);
 463         tmp = RREG32(RADEON_CP_RB_CNTL);
 464         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 465         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 466         WREG32(RADEON_CP_RB_WPTR, 0);
 467         WREG32(RADEON_CP_RB_CNTL, tmp);
 468         pci_save_state(rdev->pdev);
 469         /* disable bus mastering */
 470         pci_clear_master(rdev->pdev);
 471         mdelay(1);
 472         /* reset GA+VAP */
 473         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
 474                                         S_0000F0_SOFT_RESET_GA(1));
 475         RREG32(R_0000F0_RBBM_SOFT_RESET);
 476         mdelay(500);
 477         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 478         mdelay(1);
 479         status = RREG32(R_000E40_RBBM_STATUS);
 480         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 481         /* reset CP */
 482         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
 483         RREG32(R_0000F0_RBBM_SOFT_RESET);
 484         mdelay(500);
 485         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 486         mdelay(1);
 487         status = RREG32(R_000E40_RBBM_STATUS);
 488         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 489         /* reset MC */
 490         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
 491         RREG32(R_0000F0_RBBM_SOFT_RESET);
 492         mdelay(500);
 493         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 494         mdelay(1);
 495         status = RREG32(R_000E40_RBBM_STATUS);
 496         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 497         /* restore PCI & busmastering */
 498         pci_restore_state(rdev->pdev);
 499         /* Check if GPU is idle */
 500         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
 501                 dev_err(rdev->dev, "failed to reset GPU\n");
 502                 ret = -1;
 503         } else
 504                 dev_info(rdev->dev, "GPU reset succeed\n");
 505         rv515_mc_resume(rdev, &save);
 506         return ret;
 507 }
 508
 509 /*
 510  * GART.
 511  */
 512 void rs600_gart_tlb_flush(struct radeon_device *rdev)
 513 {
 514         uint32_t tmp;
 515
 516         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 517         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 518         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 519
 520         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 521         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
 522         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 523
 524         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 525         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 526         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 527         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 528 }
 529
 530 static int rs600_gart_init(struct radeon_device *rdev)
 531 {
 532         int r;
 533
 534         if (rdev->gart.robj) {
 535                 WARN(1, "RS600 GART already initialized\n");
 536                 return 0;
 537         }
 538         /* Initialize common gart structure */
 539         r = radeon_gart_init(rdev);
 540         if (r) {
 541                 return r;
 542         }
 543         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 544         return radeon_gart_table_vram_alloc(rdev);
 545 }
 546
 547 static int rs600_gart_enable(struct radeon_device *rdev)
 548 {
 549         u32 tmp;
 550         int r, i;
 551
 552         if (rdev->gart.robj == NULL) {
 553                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 554                 return -EINVAL;
 555         }
 556         r = radeon_gart_table_vram_pin(rdev);
 557         if (r)
 558                 return r;
 559         /* Enable bus master */
 560         tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 561         WREG32(RADEON_BUS_CNTL, tmp);
 562         /* FIXME: setup default page */
 563         WREG32_MC(R_000100_MC_PT0_CNTL,
 564                   (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
 565                    S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
 566
 567         for (i = 0; i < 19; i++) {
 568                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
 569                           S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
 570                           S_00016C_SYSTEM_ACCESS_MODE_MASK(
 571                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
 572                           S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
 573                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
 574                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
 575                           S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
 576                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
 577         }
 578         /* enable first context */
 579         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
 580                   S_000102_ENABLE_PAGE_TABLE(1) |
 581                   S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
 582
 583         /* disable all other contexts */
 584         for (i = 1; i < 8; i++)
 585                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
 586
 587         /* setup the page table */
 588         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 589                   rdev->gart.table_addr);
 590         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
 591         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
 592         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 593
 594         /* System context maps to VRAM space */
 595         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
 596         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
 597
 598         /* enable page tables */
 599         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 600         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
 601         tmp = RREG32_MC(R_000009_MC_CNTL1);
 602         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
 603         rs600_gart_tlb_flush(rdev);
 604         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 605                  (unsigned)(rdev->mc.gtt_size >> 20),
 606                  (unsigned long long)rdev->gart.table_addr);
 607         rdev->gart.ready = true;
 608         return 0;
 609 }
 610
 611 static void rs600_gart_disable(struct radeon_device *rdev)
 612 {
 613         u32 tmp;
 614
 615         /* FIXME: disable out of gart access */
 616         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
 617         tmp = RREG32_MC(R_000009_MC_CNTL1);
 618         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
 619         radeon_gart_table_vram_unpin(rdev);
 620 }
 621
 622 static void rs600_gart_fini(struct radeon_device *rdev)
 623 {
 624         radeon_gart_fini(rdev);
 625         rs600_gart_disable(rdev);
 626         radeon_gart_table_vram_free(rdev);
 627 }
 628
 629 uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags)
 630 {
 631         addr = addr & 0xFFFFFFFFFFFFF000ULL;
 632         addr |= R600_PTE_SYSTEM;
 633         if (flags & RADEON_GART_PAGE_VALID)
 634                 addr |= R600_PTE_VALID;
 635         if (flags & RADEON_GART_PAGE_READ)
 636                 addr |= R600_PTE_READABLE;
 637         if (flags & RADEON_GART_PAGE_WRITE)
 638                 addr |= R600_PTE_WRITEABLE;
 639         if (flags & RADEON_GART_PAGE_SNOOP)
 640                 addr |= R600_PTE_SNOOPED;
 641         return addr;
 642 }
 643
 644 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
 645                          uint64_t entry)
 646 {
 647         void __iomem *ptr = (void *)rdev->gart.ptr;
 648         writeq(entry, ptr + (i * 8));
 649 }
 650
 651 int rs600_irq_set(struct radeon_device *rdev)
 652 {
 653         uint32_t tmp = 0;
 654         uint32_t mode_int = 0;
 655         u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
 656                 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 657         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
 658                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 659         u32 hdmi0;
 660         if (ASIC_IS_DCE2(rdev))
 661                 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
 662                         ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 663         else
 664                 hdmi0 = 0;
 665
 666         if (!rdev->irq.installed) {
 667                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 668                 WREG32(R_000040_GEN_INT_CNTL, 0);
 669                 return -EINVAL;
 670         }
 671         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 672                 tmp |= S_000040_SW_INT_EN(1);
 673         }
 674         if (rdev->irq.crtc_vblank_int[0] ||
 675             atomic_read(&rdev->irq.pflip[0])) {
 676                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
 677         }
 678         if (rdev->irq.crtc_vblank_int[1] ||
 679             atomic_read(&rdev->irq.pflip[1])) {
 680                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
 681         }
 682         if (rdev->irq.hpd[0]) {
 683                 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 684         }
 685         if (rdev->irq.hpd[1]) {
 686                 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 687         }
 688         if (rdev->irq.afmt[0]) {
 689                 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 690         }
 691         WREG32(R_000040_GEN_INT_CNTL, tmp);
 692         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
 693         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
 694         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
 695         if (ASIC_IS_DCE2(rdev))
 696                 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
 697         return 0;
 698 }
 699
 700 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
 701 {
 702         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
 703         uint32_t irq_mask = S_000044_SW_INT(1);
 704         u32 tmp;
 705
 706         if (G_000044_DISPLAY_INT_STAT(irqs)) {
 707                 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
 708                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 709                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
 710                                 S_006534_D1MODE_VBLANK_ACK(1));
 711                 }
 712                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 713                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
 714                                 S_006D34_D2MODE_VBLANK_ACK(1));
 715                 }
 716                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 717                         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 718                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
 719                         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 720                 }
 721                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 722                         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 723                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
 724                         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 725                 }
 726         } else {
 727                 rdev->irq.stat_regs.r500.disp_int = 0;
 728         }
 729
 730         if (ASIC_IS_DCE2(rdev)) {
 731                 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
 732                         S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
 733                 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
 734                         tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
 735                         tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
 736                         WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
 737                 }
 738         } else
 739                 rdev->irq.stat_regs.r500.hdmi0_status = 0;
 740
 741         if (irqs) {
 742                 WREG32(R_000044_GEN_INT_STATUS, irqs);
 743         }
 744         return irqs & irq_mask;
 745 }
 746
 747 void rs600_irq_disable(struct radeon_device *rdev)
 748 {
 749         u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
 750                 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 751         WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
 752         WREG32(R_000040_GEN_INT_CNTL, 0);
 753         WREG32(R_006540_DxMODE_INT_MASK, 0);
 754         /* Wait and acknowledge irq */
 755         mdelay(1);
 756         rs600_irq_ack(rdev);
 757 }
 758
 759 int rs600_irq_process(struct radeon_device *rdev)
 760 {
 761         u32 status, msi_rearm;
 762         bool queue_hotplug = false;
 763         bool queue_hdmi = false;
 764
 765         status = rs600_irq_ack(rdev);
 766         if (!status &&
 767             !rdev->irq.stat_regs.r500.disp_int &&
 768             !rdev->irq.stat_regs.r500.hdmi0_status) {
 769                 return IRQ_NONE;
 770         }
 771         while (status ||
 772                rdev->irq.stat_regs.r500.disp_int ||
 773                rdev->irq.stat_regs.r500.hdmi0_status) {
 774                 /* SW interrupt */
 775                 if (G_000044_SW_INT(status)) {
 776                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 777                 }
 778                 /* Vertical blank interrupts */
 779                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 780                         if (rdev->irq.crtc_vblank_int[0]) {
 781                                 drm_handle_vblank(rdev->ddev, 0);
 782                                 rdev->pm.vblank_sync = true;
 783                                 wake_up(&rdev->irq.vblank_queue);
 784                         }
 785                         if (atomic_read(&rdev->irq.pflip[0]))
 786                                 radeon_crtc_handle_vblank(rdev, 0);
 787                 }
 788                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 789                         if (rdev->irq.crtc_vblank_int[1]) {
 790                                 drm_handle_vblank(rdev->ddev, 1);
 791                                 rdev->pm.vblank_sync = true;
 792                                 wake_up(&rdev->irq.vblank_queue);
 793                         }
 794                         if (atomic_read(&rdev->irq.pflip[1]))
 795                                 radeon_crtc_handle_vblank(rdev, 1);
 796                 }
 797                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 798                         queue_hotplug = true;
 799                         DRM_DEBUG("HPD1\n");
 800                 }
 801                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 802                         queue_hotplug = true;
 803                         DRM_DEBUG("HPD2\n");
 804                 }
 805                 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
 806                         queue_hdmi = true;
 807                         DRM_DEBUG("HDMI0\n");
 808                 }
 809                 status = rs600_irq_ack(rdev);
 810         }
 811         if (queue_hotplug)
 812                 schedule_work(&rdev->hotplug_work);
 813         if (queue_hdmi)
 814                 schedule_work(&rdev->audio_work);
 815         if (rdev->msi_enabled) {
 816                 switch (rdev->family) {
 817                 case CHIP_RS600:
 818                 case CHIP_RS690:
 819                 case CHIP_RS740:
 820                         msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
 821                         WREG32(RADEON_BUS_CNTL, msi_rearm);
 822                         WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
 823                         break;
 824                 default:
 825                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 826                         break;
 827                 }
 828         }
 829         return IRQ_HANDLED;
 830 }
 831
 832 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
 833 {
 834         if (crtc == 0)
 835                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
 836         else
 837                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
 838 }
 839
 840 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
 841 {
 842         unsigned i;
 843
 844         for (i = 0; i < rdev->usec_timeout; i++) {
 845                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
 846                         return 0;
 847                 udelay(1);
 848         }
 849         return -1;
 850 }
 851
 852 static void rs600_gpu_init(struct radeon_device *rdev)
 853 {
 854         r420_pipes_init(rdev);
 855         /* Wait for mc idle */
 856         if (rs600_mc_wait_for_idle(rdev))
 857                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 858 }
 859
 860 static void rs600_mc_init(struct radeon_device *rdev)
 861 {
 862         u64 base;
 863
 864         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
 865         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
 866         rdev->mc.vram_is_ddr = true;
 867         rdev->mc.vram_width = 128;
 868         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 869         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 870         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 871         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 872         base = RREG32_MC(R_000004_MC_FB_LOCATION);
 873         base = G_000004_MC_FB_START(base) << 16;
 874         radeon_vram_location(rdev, &rdev->mc, base);
 875         rdev->mc.gtt_base_align = 0;
 876         radeon_gtt_location(rdev, &rdev->mc);
 877         radeon_update_bandwidth_info(rdev);
 878 }
 879
 880 void rs600_bandwidth_update(struct radeon_device *rdev)
 881 {
 882         struct drm_display_mode *mode0 = NULL;
 883         struct drm_display_mode *mode1 = NULL;
 884         u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
 885         /* FIXME: implement full support */
 886
 887         if (!rdev->mode_info.mode_config_initialized)
 888                 return;
 889
 890         radeon_update_display_priority(rdev);
 891
 892         if (rdev->mode_info.crtcs[0]->base.enabled)
 893                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 894         if (rdev->mode_info.crtcs[1]->base.enabled)
 895                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 896
 897         rs690_line_buffer_adjust(rdev, mode0, mode1);
 898
 899         if (rdev->disp_priority == 2) {
 900                 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
 901                 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
 902                 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 903                 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 904                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
 905                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
 906                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
 907                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 908         }
 909 }
 910
 911 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 912 {
 913         unsigned long flags;
 914         u32 r;
 915
 916         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 917         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 918                 S_000070_MC_IND_CITF_ARB0(1));
 919         r = RREG32(R_000074_MC_IND_DATA);
 920         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 921         return r;
 922 }
 923
 924 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 925 {
 926         unsigned long flags;
 927
 928         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 929         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 930                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
 931         WREG32(R_000074_MC_IND_DATA, v);
 932         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 933 }
 934
 935 static void rs600_debugfs(struct radeon_device *rdev)
 936 {
 937         if (r100_debugfs_rbbm_init(rdev))
 938                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 939 }
 940
 941 void rs600_set_safe_registers(struct radeon_device *rdev)
 942 {
 943         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
 944         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
 945 }
 946
 947 static void rs600_mc_program(struct radeon_device *rdev)
 948 {
 949         struct rv515_mc_save save;
 950
 951         /* Stops all mc clients */
 952         rv515_mc_stop(rdev, &save);
 953
 954         /* Wait for mc idle */
 955         if (rs600_mc_wait_for_idle(rdev))
 956                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 957
 958         /* FIXME: What does AGP means for such chipset ? */
 959         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
 960         WREG32_MC(R_000006_AGP_BASE, 0);
 961         WREG32_MC(R_000007_AGP_BASE_2, 0);
 962         /* Program MC */
 963         WREG32_MC(R_000004_MC_FB_LOCATION,
 964                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
 965                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
 966         WREG32(R_000134_HDP_FB_LOCATION,
 967                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 968
 969         rv515_mc_resume(rdev, &save);
 970 }
 971
 972 static int rs600_startup(struct radeon_device *rdev)
 973 {
 974         int r;
 975
 976         rs600_mc_program(rdev);
 977         /* Resume clock */
 978         rv515_clock_startup(rdev);
 979         /* Initialize GPU configuration (# pipes, ...) */
 980         rs600_gpu_init(rdev);
 981         /* Initialize GART (initialize after TTM so we can allocate
 982          * memory through TTM but finalize after TTM) */
 983         r = rs600_gart_enable(rdev);
 984         if (r)
 985                 return r;
 986
 987         /* allocate wb buffer */
 988         r = radeon_wb_init(rdev);
 989         if (r)
 990                 return r;
 991
 992         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 993         if (r) {
 994                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 995                 return r;
 996         }
 997
 998         /* Enable IRQ */
 999         if (!rdev->irq.installed) {
1000                 r = radeon_irq_kms_init(rdev);
1001                 if (r)
1002                         return r;
1003         }
1004
1005         rs600_irq_set(rdev);
1006         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1007         /* 1M ring buffer */
1008         r = r100_cp_init(rdev, 1024 * 1024);
1009         if (r) {
1010                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1011                 return r;
1012         }
1013
1014         r = radeon_ib_pool_init(rdev);
1015         if (r) {
1016                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1017                 return r;
1018         }
1019
1020         r = radeon_audio_init(rdev);
1021         if (r) {
1022                 dev_err(rdev->dev, "failed initializing audio\n");
1023                 return r;
1024         }
1025
1026         return 0;
1027 }
1028
1029 int rs600_resume(struct radeon_device *rdev)
1030 {
1031         int r;
1032
1033         /* Make sur GART are not working */
1034         rs600_gart_disable(rdev);
1035         /* Resume clock before doing reset */
1036         rv515_clock_startup(rdev);
1037         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1038         if (radeon_asic_reset(rdev)) {
1039                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1040                         RREG32(R_000E40_RBBM_STATUS),
1041                         RREG32(R_0007C0_CP_STAT));
1042         }
1043         /* post */
1044         atom_asic_init(rdev->mode_info.atom_context);
1045         /* Resume clock after posting */
1046         rv515_clock_startup(rdev);
1047         /* Initialize surface registers */
1048         radeon_surface_init(rdev);
1049
1050         rdev->accel_working = true;
1051         r = rs600_startup(rdev);
1052         if (r) {
1053                 rdev->accel_working = false;
1054         }
1055         return r;
1056 }
1057
1058 int rs600_suspend(struct radeon_device *rdev)
1059 {
1060         radeon_pm_suspend(rdev);
1061         radeon_audio_fini(rdev);
1062         r100_cp_disable(rdev);
1063         radeon_wb_disable(rdev);
1064         rs600_irq_disable(rdev);
1065         rs600_gart_disable(rdev);
1066         return 0;
1067 }
1068
1069 void rs600_fini(struct radeon_device *rdev)
1070 {
1071         radeon_pm_fini(rdev);
1072         radeon_audio_fini(rdev);
1073         r100_cp_fini(rdev);
1074         radeon_wb_fini(rdev);
1075         radeon_ib_pool_fini(rdev);
1076         radeon_gem_fini(rdev);
1077         rs600_gart_fini(rdev);
1078         radeon_irq_kms_fini(rdev);
1079         radeon_fence_driver_fini(rdev);
1080         radeon_bo_fini(rdev);
1081         radeon_atombios_fini(rdev);
1082         kfree(rdev->bios);
1083         rdev->bios = NULL;
1084 }
1085
1086 int rs600_init(struct radeon_device *rdev)
1087 {
1088         int r;
1089
1090         /* Disable VGA */
1091         rv515_vga_render_disable(rdev);
1092         /* Initialize scratch registers */
1093         radeon_scratch_init(rdev);
1094         /* Initialize surface registers */
1095         radeon_surface_init(rdev);
1096         /* restore some register to sane defaults */
1097         r100_restore_sanity(rdev);
1098         /* BIOS */
1099         if (!radeon_get_bios(rdev)) {
1100                 if (ASIC_IS_AVIVO(rdev))
1101                         return -EINVAL;
1102         }
1103         if (rdev->is_atom_bios) {
1104                 r = radeon_atombios_init(rdev);
1105                 if (r)
1106                         return r;
1107         } else {
1108                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1109                 return -EINVAL;
1110         }
1111         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1112         if (radeon_asic_reset(rdev)) {
1113                 dev_warn(rdev->dev,
1114                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1115                         RREG32(R_000E40_RBBM_STATUS),
1116                         RREG32(R_0007C0_CP_STAT));
1117         }
1118         /* check if cards are posted or not */
1119         if (radeon_boot_test_post_card(rdev) == false)
1120                 return -EINVAL;
1121
1122         /* Initialize clocks */
1123         radeon_get_clock_info(rdev->ddev);
1124         /* initialize memory controller */
1125         rs600_mc_init(rdev);
1126         rs600_debugfs(rdev);
1127         /* Fence driver */
1128         r = radeon_fence_driver_init(rdev);
1129         if (r)
1130                 return r;
1131         /* Memory manager */
1132         r = radeon_bo_init(rdev);
1133         if (r)
1134                 return r;
1135         r = rs600_gart_init(rdev);
1136         if (r)
1137                 return r;
1138         rs600_set_safe_registers(rdev);
1139
1140         /* Initialize power management */
1141         radeon_pm_init(rdev);
1142
1143         rdev->accel_working = true;
1144         r = rs600_startup(rdev);
1145         if (r) {
1146                 /* Somethings want wront with the accel init stop accel */
1147                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1148                 r100_cp_fini(rdev);
1149                 radeon_wb_fini(rdev);
1150                 radeon_ib_pool_fini(rdev);
1151                 rs600_gart_fini(rdev);
1152                 radeon_irq_kms_fini(rdev);
1153                 rdev->accel_working = false;
1154         }
1155         return 0;
1156 }