drivers/gpu/drm/radeon/rs600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 /* RS600 / Radeon X1250/X1270 integrated GPU
  29  *
  30  * This file gather function specific to RS600 which is the IGP of
  31  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33  * the avivo one, bios is an atombios, 3D block are the one of the
  34  * R4XX family. The GART is different from the RS400 one and is very
  35  * close to the one of the R600 family (R600 likely being an evolution
  36  * of the RS600 GART block).
  37  */
  38
  39 #include <linux/io-64-nonatomic-lo-hi.h>
  40 #include <linux/pci.h>
  41
  42 #include <drm/drm_device.h>
  43 #include <drm/drm_vblank.h>
  44
  45 #include "atom.h"
  46 #include "radeon.h"
  47 #include "radeon_asic.h"
  48 #include "radeon_audio.h"
  49 #include "rs600_reg_safe.h"
  50 #include "rs600d.h"
  51
  52 static void rs600_gpu_init(struct radeon_device *rdev);
  53 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  54
  55 static const u32 crtc_offsets[2] =
  56 {
  57         0,
  58         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  59 };
  60
  61 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
  62 {
  63         if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
  64                 return true;
  65         else
  66                 return false;
  67 }
  68
  69 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
  70 {
  71         u32 pos1, pos2;
  72
  73         pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
  74         pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
  75
  76         if (pos1 != pos2)
  77                 return true;
  78         else
  79                 return false;
  80 }
  81
  82 /**
  83  * avivo_wait_for_vblank - vblank wait asic callback.
  84  *
  85  * @rdev: radeon_device pointer
  86  * @crtc: crtc to wait for vblank on
  87  *
  88  * Wait for vblank on the requested crtc (r5xx-r7xx).
  89  */
  90 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
  91 {
  92         unsigned i = 0;
  93
  94         if (crtc >= rdev->num_crtc)
  95                 return;
  96
  97         if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
  98                 return;
  99
 100         /* depending on when we hit vblank, we may be close to active; if so,
 101          * wait for another frame.
 102          */
 103         while (avivo_is_in_vblank(rdev, crtc)) {
 104                 if (i++ % 100 == 0) {
 105                         if (!avivo_is_counter_moving(rdev, crtc))
 106                                 break;
 107                 }
 108         }
 109
 110         while (!avivo_is_in_vblank(rdev, crtc)) {
 111                 if (i++ % 100 == 0) {
 112                         if (!avivo_is_counter_moving(rdev, crtc))
 113                                 break;
 114                 }
 115         }
 116 }
 117
 118 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
 119 {
 120         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 121         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
 122         int i;
 123
 124         /* Lock the graphics update lock */
 125         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
 126         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 127
 128         /* update the scanout addresses */
 129         WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
 130                async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);
 131         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 132                (u32)crtc_base);
 133         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 134                (u32)crtc_base);
 135
 136         /* Wait for update_pending to go high. */
 137         for (i = 0; i < rdev->usec_timeout; i++) {
 138                 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
 139                         break;
 140                 udelay(1);
 141         }
 142         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 143
 144         /* Unlock the lock, so double-buffering can take place inside vblank */
 145         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
 146         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 147 }
 148
 149 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)
 150 {
 151         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 152
 153         /* Return current update_pending status: */
 154         return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
 155                 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);
 156 }
 157
 158 void avivo_program_fmt(struct drm_encoder *encoder)
 159 {
 160         struct drm_device *dev = encoder->dev;
 161         struct radeon_device *rdev = dev->dev_private;
 162         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 163         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 164         int bpc = 0;
 165         u32 tmp = 0;
 166         enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
 167
 168         if (connector) {
 169                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 170                 bpc = radeon_get_monitor_bpc(connector);
 171                 dither = radeon_connector->dither;
 172         }
 173
 174         /* LVDS FMT is set up by atom */
 175         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 176                 return;
 177
 178         if (bpc == 0)
 179                 return;
 180
 181         switch (bpc) {
 182         case 6:
 183                 if (dither == RADEON_FMT_DITHER_ENABLE)
 184                         /* XXX sort out optimal dither settings */
 185                         tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
 186                 else
 187                         tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
 188                 break;
 189         case 8:
 190                 if (dither == RADEON_FMT_DITHER_ENABLE)
 191                         /* XXX sort out optimal dither settings */
 192                         tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
 193                                 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
 194                 else
 195                         tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
 196                                 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
 197                 break;
 198         case 10:
 199         default:
 200                 /* not needed */
 201                 break;
 202         }
 203
 204         switch (radeon_encoder->encoder_id) {
 205         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 206                 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
 207                 break;
 208         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 209                 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
 210                 break;
 211         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 212                 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
 213                 break;
 214         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 215                 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
 216                 break;
 217         default:
 218                 break;
 219         }
 220 }
 221
 222 void rs600_pm_misc(struct radeon_device *rdev)
 223 {
 224         int requested_index = rdev->pm.requested_power_state_index;
 225         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 226         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 227         u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
 228         u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
 229
 230         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 231                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 232                         tmp = RREG32(voltage->gpio.reg);
 233                         if (voltage->active_high)
 234                                 tmp |= voltage->gpio.mask;
 235                         else
 236                                 tmp &= ~(voltage->gpio.mask);
 237                         WREG32(voltage->gpio.reg, tmp);
 238                         if (voltage->delay)
 239                                 udelay(voltage->delay);
 240                 } else {
 241                         tmp = RREG32(voltage->gpio.reg);
 242                         if (voltage->active_high)
 243                                 tmp &= ~voltage->gpio.mask;
 244                         else
 245                                 tmp |= voltage->gpio.mask;
 246                         WREG32(voltage->gpio.reg, tmp);
 247                         if (voltage->delay)
 248                                 udelay(voltage->delay);
 249                 }
 250         } else if (voltage->type == VOLTAGE_VDDC)
 251                 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
 252
 253         dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
 254         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
 255         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
 256         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 257                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
 258                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
 259                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
 260                 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
 261                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
 262                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
 263                 }
 264         } else {
 265                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
 266                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
 267         }
 268         WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
 269
 270         dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
 271         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 272                 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
 273                 if (voltage->delay) {
 274                         dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
 275                         dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
 276                 } else
 277                         dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
 278         } else
 279                 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
 280         WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
 281
 282         hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
 283         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 284                 hdp_dyn_cntl &= ~HDP_FORCEON;
 285         else
 286                 hdp_dyn_cntl |= HDP_FORCEON;
 287         WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
 288 #if 0
 289         /* mc_host_dyn seems to cause hangs from time to time */
 290         mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
 291         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
 292                 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
 293         else
 294                 mc_host_dyn_cntl |= MC_HOST_FORCEON;
 295         WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
 296 #endif
 297         dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
 298         if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
 299                 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
 300         else
 301                 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
 302         WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
 303
 304         /* set pcie lanes */
 305         if ((rdev->flags & RADEON_IS_PCIE) &&
 306             !(rdev->flags & RADEON_IS_IGP) &&
 307             rdev->asic->pm.set_pcie_lanes &&
 308             (ps->pcie_lanes !=
 309              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 310                 radeon_set_pcie_lanes(rdev,
 311                                       ps->pcie_lanes);
 312                 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
 313         }
 314 }
 315
 316 void rs600_pm_prepare(struct radeon_device *rdev)
 317 {
 318         struct drm_device *ddev = rdev->ddev;
 319         struct drm_crtc *crtc;
 320         struct radeon_crtc *radeon_crtc;
 321         u32 tmp;
 322
 323         /* disable any active CRTCs */
 324         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 325                 radeon_crtc = to_radeon_crtc(crtc);
 326                 if (radeon_crtc->enabled) {
 327                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
 328                         tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 329                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 330                 }
 331         }
 332 }
 333
 334 void rs600_pm_finish(struct radeon_device *rdev)
 335 {
 336         struct drm_device *ddev = rdev->ddev;
 337         struct drm_crtc *crtc;
 338         struct radeon_crtc *radeon_crtc;
 339         u32 tmp;
 340
 341         /* enable any active CRTCs */
 342         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 343                 radeon_crtc = to_radeon_crtc(crtc);
 344                 if (radeon_crtc->enabled) {
 345                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
 346                         tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 347                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 348                 }
 349         }
 350 }
 351
 352 /* hpd for digital panel detect/disconnect */
 353 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 354 {
 355         u32 tmp;
 356         bool connected = false;
 357
 358         switch (hpd) {
 359         case RADEON_HPD_1:
 360                 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
 361                 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
 362                         connected = true;
 363                 break;
 364         case RADEON_HPD_2:
 365                 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
 366                 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
 367                         connected = true;
 368                 break;
 369         default:
 370                 break;
 371         }
 372         return connected;
 373 }
 374
 375 void rs600_hpd_set_polarity(struct radeon_device *rdev,
 376                             enum radeon_hpd_id hpd)
 377 {
 378         u32 tmp;
 379         bool connected = rs600_hpd_sense(rdev, hpd);
 380
 381         switch (hpd) {
 382         case RADEON_HPD_1:
 383                 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 384                 if (connected)
 385                         tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 386                 else
 387                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 388                 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 389                 break;
 390         case RADEON_HPD_2:
 391                 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 392                 if (connected)
 393                         tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 394                 else
 395                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 396                 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 397                 break;
 398         default:
 399                 break;
 400         }
 401 }
 402
 403 void rs600_hpd_init(struct radeon_device *rdev)
 404 {
 405         struct drm_device *dev = rdev->ddev;
 406         struct drm_connector *connector;
 407         unsigned enable = 0;
 408
 409         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 410                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 411                 switch (radeon_connector->hpd.hpd) {
 412                 case RADEON_HPD_1:
 413                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 414                                S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
 415                         break;
 416                 case RADEON_HPD_2:
 417                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 418                                S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
 419                         break;
 420                 default:
 421                         break;
 422                 }
 423                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 424                         enable |= 1 << radeon_connector->hpd.hpd;
 425                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 426         }
 427         radeon_irq_kms_enable_hpd(rdev, enable);
 428 }
 429
 430 void rs600_hpd_fini(struct radeon_device *rdev)
 431 {
 432         struct drm_device *dev = rdev->ddev;
 433         struct drm_connector *connector;
 434         unsigned disable = 0;
 435
 436         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 437                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 438                 switch (radeon_connector->hpd.hpd) {
 439                 case RADEON_HPD_1:
 440                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 441                                S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
 442                         break;
 443                 case RADEON_HPD_2:
 444                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 445                                S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
 446                         break;
 447                 default:
 448                         break;
 449                 }
 450                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 451                         disable |= 1 << radeon_connector->hpd.hpd;
 452         }
 453         radeon_irq_kms_disable_hpd(rdev, disable);
 454 }
 455
 456 int rs600_asic_reset(struct radeon_device *rdev, bool hard)
 457 {
 458         struct rv515_mc_save save;
 459         u32 status, tmp;
 460         int ret = 0;
 461
 462         status = RREG32(R_000E40_RBBM_STATUS);
 463         if (!G_000E40_GUI_ACTIVE(status)) {
 464                 return 0;
 465         }
 466         /* Stops all mc clients */
 467         rv515_mc_stop(rdev, &save);
 468         status = RREG32(R_000E40_RBBM_STATUS);
 469         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 470         /* stop CP */
 471         WREG32(RADEON_CP_CSQ_CNTL, 0);
 472         tmp = RREG32(RADEON_CP_RB_CNTL);
 473         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 474         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 475         WREG32(RADEON_CP_RB_WPTR, 0);
 476         WREG32(RADEON_CP_RB_CNTL, tmp);
 477         pci_save_state(rdev->pdev);
 478         /* disable bus mastering */
 479         pci_clear_master(rdev->pdev);
 480         mdelay(1);
 481         /* reset GA+VAP */
 482         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
 483                                         S_0000F0_SOFT_RESET_GA(1));
 484         RREG32(R_0000F0_RBBM_SOFT_RESET);
 485         mdelay(500);
 486         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 487         mdelay(1);
 488         status = RREG32(R_000E40_RBBM_STATUS);
 489         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 490         /* reset CP */
 491         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
 492         RREG32(R_0000F0_RBBM_SOFT_RESET);
 493         mdelay(500);
 494         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 495         mdelay(1);
 496         status = RREG32(R_000E40_RBBM_STATUS);
 497         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 498         /* reset MC */
 499         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
 500         RREG32(R_0000F0_RBBM_SOFT_RESET);
 501         mdelay(500);
 502         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 503         mdelay(1);
 504         status = RREG32(R_000E40_RBBM_STATUS);
 505         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 506         /* restore PCI & busmastering */
 507         pci_restore_state(rdev->pdev);
 508         /* Check if GPU is idle */
 509         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
 510                 dev_err(rdev->dev, "failed to reset GPU\n");
 511                 ret = -1;
 512         } else
 513                 dev_info(rdev->dev, "GPU reset succeed\n");
 514         rv515_mc_resume(rdev, &save);
 515         return ret;
 516 }
 517
 518 /*
 519  * GART.
 520  */
 521 void rs600_gart_tlb_flush(struct radeon_device *rdev)
 522 {
 523         uint32_t tmp;
 524
 525         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 526         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 527         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 528
 529         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 530         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
 531         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 532
 533         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 534         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 535         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 536         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 537 }
 538
 539 static int rs600_gart_init(struct radeon_device *rdev)
 540 {
 541         int r;
 542
 543         if (rdev->gart.robj) {
 544                 WARN(1, "RS600 GART already initialized\n");
 545                 return 0;
 546         }
 547         /* Initialize common gart structure */
 548         r = radeon_gart_init(rdev);
 549         if (r) {
 550                 return r;
 551         }
 552         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 553         return radeon_gart_table_vram_alloc(rdev);
 554 }
 555
 556 static int rs600_gart_enable(struct radeon_device *rdev)
 557 {
 558         u32 tmp;
 559         int r, i;
 560
 561         if (rdev->gart.robj == NULL) {
 562                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 563                 return -EINVAL;
 564         }
 565         r = radeon_gart_table_vram_pin(rdev);
 566         if (r)
 567                 return r;
 568         /* Enable bus master */
 569         tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 570         WREG32(RADEON_BUS_CNTL, tmp);
 571         /* FIXME: setup default page */
 572         WREG32_MC(R_000100_MC_PT0_CNTL,
 573                   (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
 574                    S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
 575
 576         for (i = 0; i < 19; i++) {
 577                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
 578                           S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
 579                           S_00016C_SYSTEM_ACCESS_MODE_MASK(
 580                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
 581                           S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
 582                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
 583                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
 584                           S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
 585                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
 586         }
 587         /* enable first context */
 588         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
 589                   S_000102_ENABLE_PAGE_TABLE(1) |
 590                   S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
 591
 592         /* disable all other contexts */
 593         for (i = 1; i < 8; i++)
 594                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
 595
 596         /* setup the page table */
 597         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 598                   rdev->gart.table_addr);
 599         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
 600         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
 601         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 602
 603         /* System context maps to VRAM space */
 604         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
 605         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
 606
 607         /* enable page tables */
 608         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 609         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
 610         tmp = RREG32_MC(R_000009_MC_CNTL1);
 611         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
 612         rs600_gart_tlb_flush(rdev);
 613         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 614                  (unsigned)(rdev->mc.gtt_size >> 20),
 615                  (unsigned long long)rdev->gart.table_addr);
 616         rdev->gart.ready = true;
 617         return 0;
 618 }
 619
 620 static void rs600_gart_disable(struct radeon_device *rdev)
 621 {
 622         u32 tmp;
 623
 624         /* FIXME: disable out of gart access */
 625         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
 626         tmp = RREG32_MC(R_000009_MC_CNTL1);
 627         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
 628         radeon_gart_table_vram_unpin(rdev);
 629 }
 630
 631 static void rs600_gart_fini(struct radeon_device *rdev)
 632 {
 633         radeon_gart_fini(rdev);
 634         rs600_gart_disable(rdev);
 635         radeon_gart_table_vram_free(rdev);
 636 }
 637
 638 uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags)
 639 {
 640         addr = addr & 0xFFFFFFFFFFFFF000ULL;
 641         addr |= R600_PTE_SYSTEM;
 642         if (flags & RADEON_GART_PAGE_VALID)
 643                 addr |= R600_PTE_VALID;
 644         if (flags & RADEON_GART_PAGE_READ)
 645                 addr |= R600_PTE_READABLE;
 646         if (flags & RADEON_GART_PAGE_WRITE)
 647                 addr |= R600_PTE_WRITEABLE;
 648         if (flags & RADEON_GART_PAGE_SNOOP)
 649                 addr |= R600_PTE_SNOOPED;
 650         return addr;
 651 }
 652
 653 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
 654                          uint64_t entry)
 655 {
 656         void __iomem *ptr = (void *)rdev->gart.ptr;
 657         writeq(entry, ptr + (i * 8));
 658 }
 659
 660 int rs600_irq_set(struct radeon_device *rdev)
 661 {
 662         uint32_t tmp = 0;
 663         uint32_t mode_int = 0;
 664         u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
 665                 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 666         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
 667                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 668         u32 hdmi0;
 669         if (ASIC_IS_DCE2(rdev))
 670                 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
 671                         ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 672         else
 673                 hdmi0 = 0;
 674
 675         if (!rdev->irq.installed) {
 676                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 677                 WREG32(R_000040_GEN_INT_CNTL, 0);
 678                 return -EINVAL;
 679         }
 680         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 681                 tmp |= S_000040_SW_INT_EN(1);
 682         }
 683         if (rdev->irq.crtc_vblank_int[0] ||
 684             atomic_read(&rdev->irq.pflip[0])) {
 685                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
 686         }
 687         if (rdev->irq.crtc_vblank_int[1] ||
 688             atomic_read(&rdev->irq.pflip[1])) {
 689                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
 690         }
 691         if (rdev->irq.hpd[0]) {
 692                 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 693         }
 694         if (rdev->irq.hpd[1]) {
 695                 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 696         }
 697         if (rdev->irq.afmt[0]) {
 698                 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 699         }
 700         WREG32(R_000040_GEN_INT_CNTL, tmp);
 701         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
 702         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
 703         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
 704         if (ASIC_IS_DCE2(rdev))
 705                 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
 706
 707         /* posting read */
 708         RREG32(R_000040_GEN_INT_CNTL);
 709
 710         return 0;
 711 }
 712
 713 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
 714 {
 715         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
 716         uint32_t irq_mask = S_000044_SW_INT(1);
 717         u32 tmp;
 718
 719         if (G_000044_DISPLAY_INT_STAT(irqs)) {
 720                 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
 721                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 722                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
 723                                 S_006534_D1MODE_VBLANK_ACK(1));
 724                 }
 725                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 726                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
 727                                 S_006D34_D2MODE_VBLANK_ACK(1));
 728                 }
 729                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 730                         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 731                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
 732                         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 733                 }
 734                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 735                         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 736                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
 737                         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 738                 }
 739         } else {
 740                 rdev->irq.stat_regs.r500.disp_int = 0;
 741         }
 742
 743         if (ASIC_IS_DCE2(rdev)) {
 744                 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
 745                         S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
 746                 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
 747                         tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
 748                         tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
 749                         WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
 750                 }
 751         } else
 752                 rdev->irq.stat_regs.r500.hdmi0_status = 0;
 753
 754         if (irqs) {
 755                 WREG32(R_000044_GEN_INT_STATUS, irqs);
 756         }
 757         return irqs & irq_mask;
 758 }
 759
 760 void rs600_irq_disable(struct radeon_device *rdev)
 761 {
 762         u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
 763                 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 764         WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
 765         WREG32(R_000040_GEN_INT_CNTL, 0);
 766         WREG32(R_006540_DxMODE_INT_MASK, 0);
 767         /* Wait and acknowledge irq */
 768         mdelay(1);
 769         rs600_irq_ack(rdev);
 770 }
 771
 772 int rs600_irq_process(struct radeon_device *rdev)
 773 {
 774         u32 status, msi_rearm;
 775         bool queue_hotplug = false;
 776         bool queue_hdmi = false;
 777
 778         status = rs600_irq_ack(rdev);
 779         if (!status &&
 780             !rdev->irq.stat_regs.r500.disp_int &&
 781             !rdev->irq.stat_regs.r500.hdmi0_status) {
 782                 return IRQ_NONE;
 783         }
 784         while (status ||
 785                rdev->irq.stat_regs.r500.disp_int ||
 786                rdev->irq.stat_regs.r500.hdmi0_status) {
 787                 /* SW interrupt */
 788                 if (G_000044_SW_INT(status)) {
 789                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 790                 }
 791                 /* Vertical blank interrupts */
 792                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 793                         if (rdev->irq.crtc_vblank_int[0]) {
 794                                 drm_handle_vblank(rdev->ddev, 0);
 795                                 rdev->pm.vblank_sync = true;
 796                                 wake_up(&rdev->irq.vblank_queue);
 797                         }
 798                         if (atomic_read(&rdev->irq.pflip[0]))
 799                                 radeon_crtc_handle_vblank(rdev, 0);
 800                 }
 801                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 802                         if (rdev->irq.crtc_vblank_int[1]) {
 803                                 drm_handle_vblank(rdev->ddev, 1);
 804                                 rdev->pm.vblank_sync = true;
 805                                 wake_up(&rdev->irq.vblank_queue);
 806                         }
 807                         if (atomic_read(&rdev->irq.pflip[1]))
 808                                 radeon_crtc_handle_vblank(rdev, 1);
 809                 }
 810                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 811                         queue_hotplug = true;
 812                         DRM_DEBUG("HPD1\n");
 813                 }
 814                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 815                         queue_hotplug = true;
 816                         DRM_DEBUG("HPD2\n");
 817                 }
 818                 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
 819                         queue_hdmi = true;
 820                         DRM_DEBUG("HDMI0\n");
 821                 }
 822                 status = rs600_irq_ack(rdev);
 823         }
 824         if (queue_hotplug)
 825                 schedule_delayed_work(&rdev->hotplug_work, 0);
 826         if (queue_hdmi)
 827                 schedule_work(&rdev->audio_work);
 828         if (rdev->msi_enabled) {
 829                 switch (rdev->family) {
 830                 case CHIP_RS600:
 831                 case CHIP_RS690:
 832                 case CHIP_RS740:
 833                         msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
 834                         WREG32(RADEON_BUS_CNTL, msi_rearm);
 835                         WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
 836                         break;
 837                 default:
 838                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 839                         break;
 840                 }
 841         }
 842         return IRQ_HANDLED;
 843 }
 844
 845 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
 846 {
 847         if (crtc == 0)
 848                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
 849         else
 850                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
 851 }
 852
 853 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
 854 {
 855         unsigned i;
 856
 857         for (i = 0; i < rdev->usec_timeout; i++) {
 858                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
 859                         return 0;
 860                 udelay(1);
 861         }
 862         return -1;
 863 }
 864
 865 static void rs600_gpu_init(struct radeon_device *rdev)
 866 {
 867         r420_pipes_init(rdev);
 868         /* Wait for mc idle */
 869         if (rs600_mc_wait_for_idle(rdev))
 870                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 871 }
 872
 873 static void rs600_mc_init(struct radeon_device *rdev)
 874 {
 875         u64 base;
 876
 877         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
 878         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
 879         rdev->mc.vram_is_ddr = true;
 880         rdev->mc.vram_width = 128;
 881         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 882         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 883         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 884         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 885         base = RREG32_MC(R_000004_MC_FB_LOCATION);
 886         base = G_000004_MC_FB_START(base) << 16;
 887         radeon_vram_location(rdev, &rdev->mc, base);
 888         rdev->mc.gtt_base_align = 0;
 889         radeon_gtt_location(rdev, &rdev->mc);
 890         radeon_update_bandwidth_info(rdev);
 891 }
 892
 893 void rs600_bandwidth_update(struct radeon_device *rdev)
 894 {
 895         struct drm_display_mode *mode0 = NULL;
 896         struct drm_display_mode *mode1 = NULL;
 897         u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
 898         /* FIXME: implement full support */
 899
 900         if (!rdev->mode_info.mode_config_initialized)
 901                 return;
 902
 903         radeon_update_display_priority(rdev);
 904
 905         if (rdev->mode_info.crtcs[0]->base.enabled)
 906                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 907         if (rdev->mode_info.crtcs[1]->base.enabled)
 908                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 909
 910         rs690_line_buffer_adjust(rdev, mode0, mode1);
 911
 912         if (rdev->disp_priority == 2) {
 913                 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
 914                 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
 915                 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 916                 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 917                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
 918                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
 919                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
 920                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 921         }
 922 }
 923
 924 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 925 {
 926         unsigned long flags;
 927         u32 r;
 928
 929         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 930         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 931                 S_000070_MC_IND_CITF_ARB0(1));
 932         r = RREG32(R_000074_MC_IND_DATA);
 933         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 934         return r;
 935 }
 936
 937 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 938 {
 939         unsigned long flags;
 940
 941         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 942         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 943                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
 944         WREG32(R_000074_MC_IND_DATA, v);
 945         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 946 }
 947
 948 void rs600_set_safe_registers(struct radeon_device *rdev)
 949 {
 950         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
 951         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
 952 }
 953
 954 static void rs600_mc_program(struct radeon_device *rdev)
 955 {
 956         struct rv515_mc_save save;
 957
 958         /* Stops all mc clients */
 959         rv515_mc_stop(rdev, &save);
 960
 961         /* Wait for mc idle */
 962         if (rs600_mc_wait_for_idle(rdev))
 963                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 964
 965         /* FIXME: What does AGP means for such chipset ? */
 966         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
 967         WREG32_MC(R_000006_AGP_BASE, 0);
 968         WREG32_MC(R_000007_AGP_BASE_2, 0);
 969         /* Program MC */
 970         WREG32_MC(R_000004_MC_FB_LOCATION,
 971                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
 972                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
 973         WREG32(R_000134_HDP_FB_LOCATION,
 974                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 975
 976         rv515_mc_resume(rdev, &save);
 977 }
 978
 979 static int rs600_startup(struct radeon_device *rdev)
 980 {
 981         int r;
 982
 983         rs600_mc_program(rdev);
 984         /* Resume clock */
 985         rv515_clock_startup(rdev);
 986         /* Initialize GPU configuration (# pipes, ...) */
 987         rs600_gpu_init(rdev);
 988         /* Initialize GART (initialize after TTM so we can allocate
 989          * memory through TTM but finalize after TTM) */
 990         r = rs600_gart_enable(rdev);
 991         if (r)
 992                 return r;
 993
 994         /* allocate wb buffer */
 995         r = radeon_wb_init(rdev);
 996         if (r)
 997                 return r;
 998
 999         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1000         if (r) {
1001                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1002                 return r;
1003         }
1004
1005         /* Enable IRQ */
1006         if (!rdev->irq.installed) {
1007                 r = radeon_irq_kms_init(rdev);
1008                 if (r)
1009                         return r;
1010         }
1011
1012         rs600_irq_set(rdev);
1013         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1014         /* 1M ring buffer */
1015         r = r100_cp_init(rdev, 1024 * 1024);
1016         if (r) {
1017                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1018                 return r;
1019         }
1020
1021         r = radeon_ib_pool_init(rdev);
1022         if (r) {
1023                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1024                 return r;
1025         }
1026
1027         r = radeon_audio_init(rdev);
1028         if (r) {
1029                 dev_err(rdev->dev, "failed initializing audio\n");
1030                 return r;
1031         }
1032
1033         return 0;
1034 }
1035
1036 int rs600_resume(struct radeon_device *rdev)
1037 {
1038         int r;
1039
1040         /* Make sur GART are not working */
1041         rs600_gart_disable(rdev);
1042         /* Resume clock before doing reset */
1043         rv515_clock_startup(rdev);
1044         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1045         if (radeon_asic_reset(rdev)) {
1046                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1047                         RREG32(R_000E40_RBBM_STATUS),
1048                         RREG32(R_0007C0_CP_STAT));
1049         }
1050         /* post */
1051         atom_asic_init(rdev->mode_info.atom_context);
1052         /* Resume clock after posting */
1053         rv515_clock_startup(rdev);
1054         /* Initialize surface registers */
1055         radeon_surface_init(rdev);
1056
1057         rdev->accel_working = true;
1058         r = rs600_startup(rdev);
1059         if (r) {
1060                 rdev->accel_working = false;
1061         }
1062         return r;
1063 }
1064
1065 int rs600_suspend(struct radeon_device *rdev)
1066 {
1067         radeon_pm_suspend(rdev);
1068         radeon_audio_fini(rdev);
1069         r100_cp_disable(rdev);
1070         radeon_wb_disable(rdev);
1071         rs600_irq_disable(rdev);
1072         rs600_gart_disable(rdev);
1073         return 0;
1074 }
1075
1076 void rs600_fini(struct radeon_device *rdev)
1077 {
1078         radeon_pm_fini(rdev);
1079         radeon_audio_fini(rdev);
1080         r100_cp_fini(rdev);
1081         radeon_wb_fini(rdev);
1082         radeon_ib_pool_fini(rdev);
1083         radeon_gem_fini(rdev);
1084         rs600_gart_fini(rdev);
1085         radeon_irq_kms_fini(rdev);
1086         radeon_fence_driver_fini(rdev);
1087         radeon_bo_fini(rdev);
1088         radeon_atombios_fini(rdev);
1089         kfree(rdev->bios);
1090         rdev->bios = NULL;
1091 }
1092
1093 int rs600_init(struct radeon_device *rdev)
1094 {
1095         int r;
1096
1097         /* Disable VGA */
1098         rv515_vga_render_disable(rdev);
1099         /* Initialize scratch registers */
1100         radeon_scratch_init(rdev);
1101         /* Initialize surface registers */
1102         radeon_surface_init(rdev);
1103         /* restore some register to sane defaults */
1104         r100_restore_sanity(rdev);
1105         /* BIOS */
1106         if (!radeon_get_bios(rdev)) {
1107                 if (ASIC_IS_AVIVO(rdev))
1108                         return -EINVAL;
1109         }
1110         if (rdev->is_atom_bios) {
1111                 r = radeon_atombios_init(rdev);
1112                 if (r)
1113                         return r;
1114         } else {
1115                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1116                 return -EINVAL;
1117         }
1118         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1119         if (radeon_asic_reset(rdev)) {
1120                 dev_warn(rdev->dev,
1121                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1122                         RREG32(R_000E40_RBBM_STATUS),
1123                         RREG32(R_0007C0_CP_STAT));
1124         }
1125         /* check if cards are posted or not */
1126         if (radeon_boot_test_post_card(rdev) == false)
1127                 return -EINVAL;
1128
1129         /* Initialize clocks */
1130         radeon_get_clock_info(rdev->ddev);
1131         /* initialize memory controller */
1132         rs600_mc_init(rdev);
1133         r100_debugfs_rbbm_init(rdev);
1134         /* Fence driver */
1135         radeon_fence_driver_init(rdev);
1136         /* Memory manager */
1137         r = radeon_bo_init(rdev);
1138         if (r)
1139                 return r;
1140         r = rs600_gart_init(rdev);
1141         if (r)
1142                 return r;
1143         rs600_set_safe_registers(rdev);
1144
1145         /* Initialize power management */
1146         radeon_pm_init(rdev);
1147
1148         rdev->accel_working = true;
1149         r = rs600_startup(rdev);
1150         if (r) {
1151                 /* Somethings want wront with the accel init stop accel */
1152                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1153                 r100_cp_fini(rdev);
1154                 radeon_wb_fini(rdev);
1155                 radeon_ib_pool_fini(rdev);
1156                 rs600_gart_fini(rdev);
1157                 radeon_irq_kms_fini(rdev);
1158                 rdev->accel_working = false;
1159         }
1160         return 0;
1161 }