2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
40 #define FIRMWARE_RV710 "radeon/RV710_uvd.bin"
41 #define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin"
42 #define FIRMWARE_SUMO "radeon/SUMO_uvd.bin"
43 #define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin"
45 MODULE_FIRMWARE(FIRMWARE_RV710);
46 MODULE_FIRMWARE(FIRMWARE_CYPRESS);
47 MODULE_FIRMWARE(FIRMWARE_SUMO);
48 MODULE_FIRMWARE(FIRMWARE_TAHITI);
50 int radeon_uvd_init(struct radeon_device *rdev)
52 struct platform_device *pdev;
53 unsigned long bo_size;
57 pdev = platform_device_register_simple("radeon_uvd", 0, NULL, 0);
60 dev_err(rdev->dev, "radeon_uvd: Failed to register firmware\n");
64 switch (rdev->family) {
68 fw_name = FIRMWARE_RV710;
76 fw_name = FIRMWARE_CYPRESS;
86 fw_name = FIRMWARE_SUMO;
93 fw_name = FIRMWARE_TAHITI;
100 r = request_firmware(&rdev->uvd_fw, fw_name, &pdev->dev);
102 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
104 platform_device_unregister(pdev);
108 platform_device_unregister(pdev);
110 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
111 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
112 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
113 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
115 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
119 r = radeon_uvd_resume(rdev);
123 memset(rdev->uvd.cpu_addr, 0, bo_size);
124 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
126 r = radeon_uvd_suspend(rdev);
130 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
131 atomic_set(&rdev->uvd.handles[i], 0);
132 rdev->uvd.filp[i] = NULL;
138 void radeon_uvd_fini(struct radeon_device *rdev)
140 radeon_uvd_suspend(rdev);
141 radeon_bo_unref(&rdev->uvd.vcpu_bo);
144 int radeon_uvd_suspend(struct radeon_device *rdev)
148 if (rdev->uvd.vcpu_bo == NULL)
151 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
153 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
154 radeon_bo_unpin(rdev->uvd.vcpu_bo);
155 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
160 int radeon_uvd_resume(struct radeon_device *rdev)
164 if (rdev->uvd.vcpu_bo == NULL)
167 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
169 radeon_bo_unref(&rdev->uvd.vcpu_bo);
170 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
174 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
175 &rdev->uvd.gpu_addr);
177 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
178 radeon_bo_unref(&rdev->uvd.vcpu_bo);
179 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
183 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
185 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
189 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
191 radeon_set_uvd_clocks(rdev, 53300, 40000);
196 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
198 rbo->placement.fpfn = 0 >> PAGE_SHIFT;
199 rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
202 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
205 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
206 if (rdev->uvd.filp[i] == filp) {
207 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
208 struct radeon_fence *fence;
210 r = radeon_uvd_get_destroy_msg(rdev,
211 R600_RING_TYPE_UVD_INDEX, handle, &fence);
213 DRM_ERROR("Error destroying UVD (%d)!\n", r);
217 radeon_fence_wait(fence, false);
218 radeon_fence_unref(&fence);
220 rdev->uvd.filp[i] = NULL;
221 atomic_set(&rdev->uvd.handles[i], 0);
226 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
228 unsigned stream_type = msg[4];
229 unsigned width = msg[6];
230 unsigned height = msg[7];
231 unsigned dpb_size = msg[9];
232 unsigned pitch = msg[28];
234 unsigned width_in_mb = width / 16;
235 unsigned height_in_mb = ALIGN(height / 16, 2);
237 unsigned image_size, tmp, min_dpb_size;
239 image_size = width * height;
240 image_size += image_size / 2;
241 image_size = ALIGN(image_size, 1024);
243 switch (stream_type) {
246 /* reference picture buffer */
247 min_dpb_size = image_size * 17;
249 /* macroblock context buffer */
250 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
252 /* IT surface buffer */
253 min_dpb_size += width_in_mb * height_in_mb * 32;
258 /* reference picture buffer */
259 min_dpb_size = image_size * 3;
262 min_dpb_size += width_in_mb * height_in_mb * 128;
264 /* IT surface buffer */
265 min_dpb_size += width_in_mb * 64;
267 /* DB surface buffer */
268 min_dpb_size += width_in_mb * 128;
271 tmp = max(width_in_mb, height_in_mb);
272 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
277 /* reference picture buffer */
278 min_dpb_size = image_size * 3;
283 /* reference picture buffer */
284 min_dpb_size = image_size * 3;
287 min_dpb_size += width_in_mb * height_in_mb * 64;
289 /* IT surface buffer */
290 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
294 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
299 DRM_ERROR("Invalid UVD decoding target pitch!\n");
303 if (dpb_size < min_dpb_size) {
304 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
305 dpb_size, min_dpb_size);
309 buf_sizes[0x1] = dpb_size;
310 buf_sizes[0x2] = image_size;
314 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
315 unsigned offset, unsigned buf_sizes[])
317 int32_t *msg, msg_type, handle;
323 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
327 r = radeon_bo_kmap(bo, &ptr);
337 DRM_ERROR("Invalid UVD handle!\n");
342 /* it's a decode msg, calc buffer sizes */
343 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
344 radeon_bo_kunmap(bo);
348 } else if (msg_type == 2) {
349 /* it's a destroy msg, free the handle */
350 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
351 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
352 radeon_bo_kunmap(bo);
355 /* it's a create msg, no special handling needed */
356 radeon_bo_kunmap(bo);
359 /* create or decode, validate the handle */
360 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
361 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
365 /* handle not found try to alloc a new one */
366 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
367 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
368 p->rdev->uvd.filp[i] = p->filp;
373 DRM_ERROR("No more free UVD handles!\n");
377 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
378 int data0, int data1,
379 unsigned buf_sizes[])
381 struct radeon_cs_chunk *relocs_chunk;
382 struct radeon_cs_reloc *reloc;
383 unsigned idx, cmd, offset;
387 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
388 offset = radeon_get_ib_value(p, data0);
389 idx = radeon_get_ib_value(p, data1);
390 if (idx >= relocs_chunk->length_dw) {
391 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
392 idx, relocs_chunk->length_dw);
396 reloc = p->relocs_ptr[(idx / 4)];
397 start = reloc->lobj.gpu_offset;
398 end = start + radeon_bo_size(reloc->robj);
401 p->ib.ptr[data0] = start & 0xFFFFFFFF;
402 p->ib.ptr[data1] = start >> 32;
404 cmd = radeon_get_ib_value(p, p->idx) >> 1;
407 if ((end - start) < buf_sizes[cmd]) {
408 DRM_ERROR("buffer to small (%d / %d)!\n",
409 (unsigned)(end - start), buf_sizes[cmd]);
413 } else if (cmd != 0x100) {
414 DRM_ERROR("invalid UVD command %X!\n", cmd);
418 if ((start >> 28) != (end >> 28)) {
419 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
424 /* TODO: is this still necessary on NI+ ? */
425 if ((cmd == 0 || cmd == 0x3) &&
426 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
427 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
433 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
441 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
442 struct radeon_cs_packet *pkt,
443 int *data0, int *data1,
444 unsigned buf_sizes[])
449 for (i = 0; i <= pkt->count; ++i) {
450 switch (pkt->reg + i*4) {
451 case UVD_GPCOM_VCPU_DATA0:
454 case UVD_GPCOM_VCPU_DATA1:
457 case UVD_GPCOM_VCPU_CMD:
458 r = radeon_uvd_cs_reloc(p, *data0, *data1, buf_sizes);
462 case UVD_ENGINE_CNTL:
465 DRM_ERROR("Invalid reg 0x%X!\n",
474 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
476 struct radeon_cs_packet pkt;
477 int r, data0 = 0, data1 = 0;
479 /* minimum buffer sizes */
480 unsigned buf_sizes[] = {
482 [0x00000001] = 32 * 1024 * 1024,
483 [0x00000002] = 2048 * 1152 * 3,
487 if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
488 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
489 p->chunks[p->chunk_ib_idx].length_dw);
493 if (p->chunk_relocs_idx == -1) {
494 DRM_ERROR("No relocation chunk !\n");
500 r = radeon_cs_packet_parse(p, &pkt, p->idx);
504 case RADEON_PACKET_TYPE0:
505 r = radeon_uvd_cs_reg(p, &pkt, &data0,
510 case RADEON_PACKET_TYPE2:
511 p->idx += pkt.count + 2;
514 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
517 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
521 static int radeon_uvd_send_msg(struct radeon_device *rdev,
522 int ring, struct radeon_bo *bo,
523 struct radeon_fence **fence)
525 struct ttm_validate_buffer tv;
526 struct list_head head;
531 memset(&tv, 0, sizeof(tv));
534 INIT_LIST_HEAD(&head);
535 list_add(&tv.head, &head);
537 r = ttm_eu_reserve_buffers(&head);
541 radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM);
542 radeon_uvd_force_into_uvd_segment(bo);
544 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
546 ttm_eu_backoff_reservation(&head);
550 r = radeon_ib_get(rdev, ring, &ib, NULL, 16);
552 ttm_eu_backoff_reservation(&head);
556 addr = radeon_bo_gpu_offset(bo);
557 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
559 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
560 ib.ptr[3] = addr >> 32;
561 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
563 for (i = 6; i < 16; ++i)
564 ib.ptr[i] = PACKET2(0);
567 r = radeon_ib_schedule(rdev, &ib, NULL);
569 ttm_eu_backoff_reservation(&head);
572 ttm_eu_fence_buffer_objects(&head, ib.fence);
575 *fence = radeon_fence_ref(ib.fence);
577 radeon_ib_free(rdev, &ib);
578 radeon_bo_unref(&bo);
582 /* multiple fence commands without any stream commands in between can
583 crash the vcpu so just try to emmit a dummy create/destroy msg to
585 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
586 uint32_t handle, struct radeon_fence **fence)
588 struct radeon_bo *bo;
592 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
593 RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
597 r = radeon_bo_reserve(bo, false);
599 radeon_bo_unref(&bo);
603 r = radeon_bo_kmap(bo, (void **)&msg);
605 radeon_bo_unreserve(bo);
606 radeon_bo_unref(&bo);
610 /* stitch together an UVD create msg */
621 msg[10] = 0x01b37000;
622 for (i = 11; i < 1024; ++i)
625 radeon_bo_kunmap(bo);
626 radeon_bo_unreserve(bo);
628 return radeon_uvd_send_msg(rdev, ring, bo, fence);
631 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
632 uint32_t handle, struct radeon_fence **fence)
634 struct radeon_bo *bo;
638 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
639 RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
643 r = radeon_bo_reserve(bo, false);
645 radeon_bo_unref(&bo);
649 r = radeon_bo_kmap(bo, (void **)&msg);
651 radeon_bo_unreserve(bo);
652 radeon_bo_unref(&bo);
656 /* stitch together an UVD destroy msg */
661 for (i = 4; i < 1024; ++i)
664 radeon_bo_kunmap(bo);
665 radeon_bo_unreserve(bo);
667 return radeon_uvd_send_msg(rdev, ring, bo, fence);