2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
33 #include <linux/dma-mapping.h>
34 #include <linux/pagemap.h>
35 #include <linux/pci.h>
36 #include <linux/seq_file.h>
37 #include <linux/slab.h>
38 #include <linux/swap.h>
39 #include <linux/swiotlb.h>
41 #include <drm/drm_agpsupport.h>
42 #include <drm/drm_debugfs.h>
43 #include <drm/drm_device.h>
44 #include <drm/drm_file.h>
45 #include <drm/drm_prime.h>
46 #include <drm/radeon_drm.h>
47 #include <drm/ttm/ttm_bo_api.h>
48 #include <drm/ttm/ttm_bo_driver.h>
49 #include <drm/ttm/ttm_placement.h>
51 #include "radeon_reg.h"
53 #include "radeon_ttm.h"
55 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
56 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
58 static int radeon_ttm_tt_bind(struct ttm_bo_device *bdev,
60 struct ttm_resource *bo_mem);
61 static void radeon_ttm_tt_unbind(struct ttm_bo_device *bdev,
64 struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
66 struct radeon_mman *mman;
67 struct radeon_device *rdev;
69 mman = container_of(bdev, struct radeon_mman, bdev);
70 rdev = container_of(mman, struct radeon_device, mman);
74 static int radeon_ttm_init_vram(struct radeon_device *rdev)
76 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_VRAM,
77 false, rdev->mc.real_vram_size >> PAGE_SHIFT);
80 static int radeon_ttm_init_gtt(struct radeon_device *rdev)
82 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_TT,
83 true, rdev->mc.gtt_size >> PAGE_SHIFT);
86 static void radeon_evict_flags(struct ttm_buffer_object *bo,
87 struct ttm_placement *placement)
89 static const struct ttm_place placements = {
92 .mem_type = TTM_PL_SYSTEM,
96 struct radeon_bo *rbo;
98 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
99 placement->placement = &placements;
100 placement->busy_placement = &placements;
101 placement->num_placement = 1;
102 placement->num_busy_placement = 1;
105 rbo = container_of(bo, struct radeon_bo, tbo);
106 switch (bo->mem.mem_type) {
108 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
109 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
110 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
111 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
112 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
115 /* Try evicting to the CPU inaccessible part of VRAM
116 * first, but only set GTT as busy placement, so this
117 * BO will be evicted to GTT rather than causing other
118 * BOs to be evicted from VRAM
120 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
121 RADEON_GEM_DOMAIN_GTT);
122 rbo->placement.num_busy_placement = 0;
123 for (i = 0; i < rbo->placement.num_placement; i++) {
124 if (rbo->placements[i].mem_type == TTM_PL_VRAM) {
125 if (rbo->placements[i].fpfn < fpfn)
126 rbo->placements[i].fpfn = fpfn;
128 rbo->placement.busy_placement =
130 rbo->placement.num_busy_placement = 1;
134 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
138 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
140 *placement = rbo->placement;
143 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
145 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
146 struct radeon_device *rdev = radeon_get_rdev(bo->bdev);
148 if (radeon_ttm_tt_has_userptr(rdev, bo->ttm))
150 return drm_vma_node_verify_access(&rbo->tbo.base.vma_node,
154 static int radeon_move_blit(struct ttm_buffer_object *bo,
156 struct ttm_resource *new_mem,
157 struct ttm_resource *old_mem)
159 struct radeon_device *rdev;
160 uint64_t old_start, new_start;
161 struct radeon_fence *fence;
165 rdev = radeon_get_rdev(bo->bdev);
166 ridx = radeon_copy_ring_index(rdev);
167 old_start = (u64)old_mem->start << PAGE_SHIFT;
168 new_start = (u64)new_mem->start << PAGE_SHIFT;
170 switch (old_mem->mem_type) {
172 old_start += rdev->mc.vram_start;
175 old_start += rdev->mc.gtt_start;
178 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
181 switch (new_mem->mem_type) {
183 new_start += rdev->mc.vram_start;
186 new_start += rdev->mc.gtt_start;
189 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
192 if (!rdev->ring[ridx].ready) {
193 DRM_ERROR("Trying to move memory with ring turned off.\n");
197 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
199 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
200 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv);
202 return PTR_ERR(fence);
204 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false, new_mem);
205 radeon_fence_unref(&fence);
209 static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict,
210 struct ttm_operation_ctx *ctx,
211 struct ttm_resource *new_mem,
212 struct ttm_place *hop)
214 struct radeon_device *rdev;
215 struct radeon_bo *rbo;
216 struct ttm_resource *old_mem = &bo->mem;
219 if (new_mem->mem_type == TTM_PL_TT) {
220 r = radeon_ttm_tt_bind(bo->bdev, bo->ttm, new_mem);
225 r = ttm_bo_wait_ctx(bo, ctx);
229 /* Can't move a pinned BO */
230 rbo = container_of(bo, struct radeon_bo, tbo);
231 if (WARN_ON_ONCE(rbo->tbo.pin_count > 0))
234 rdev = radeon_get_rdev(bo->bdev);
235 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
236 ttm_bo_move_null(bo, new_mem);
239 if (old_mem->mem_type == TTM_PL_SYSTEM &&
240 new_mem->mem_type == TTM_PL_TT) {
241 ttm_bo_move_null(bo, new_mem);
245 if (old_mem->mem_type == TTM_PL_TT &&
246 new_mem->mem_type == TTM_PL_SYSTEM) {
247 radeon_ttm_tt_unbind(bo->bdev, bo->ttm);
248 ttm_resource_free(bo, &bo->mem);
249 ttm_bo_assign_mem(bo, new_mem);
252 if (rdev->ring[radeon_copy_ring_index(rdev)].ready &&
253 rdev->asic->copy.copy != NULL) {
254 if ((old_mem->mem_type == TTM_PL_SYSTEM &&
255 new_mem->mem_type == TTM_PL_VRAM) ||
256 (old_mem->mem_type == TTM_PL_VRAM &&
257 new_mem->mem_type == TTM_PL_SYSTEM)) {
260 hop->mem_type = TTM_PL_TT;
265 r = radeon_move_blit(bo, evict, new_mem, old_mem);
271 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
277 /* update statistics */
278 atomic64_add(bo->base.size, &rdev->num_bytes_moved);
279 radeon_bo_move_notify(bo, evict, new_mem);
283 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
285 struct radeon_device *rdev = radeon_get_rdev(bdev);
286 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
288 switch (mem->mem_type) {
293 #if IS_ENABLED(CONFIG_AGP)
294 if (rdev->flags & RADEON_IS_AGP) {
295 /* RADEON_IS_AGP is set only if AGP is active */
296 mem->bus.offset = (mem->start << PAGE_SHIFT) +
298 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
299 mem->bus.caching = ttm_write_combined;
304 mem->bus.offset = mem->start << PAGE_SHIFT;
305 /* check if it's visible */
306 if ((mem->bus.offset + bus_size) > rdev->mc.visible_vram_size)
308 mem->bus.offset += rdev->mc.aper_base;
309 mem->bus.is_iomem = true;
310 mem->bus.caching = ttm_write_combined;
313 * Alpha: use bus.addr to hold the ioremap() return,
314 * so we can modify bus.base below.
316 mem->bus.addr = ioremap_wc(mem->bus.offset, bus_size);
321 * Alpha: Use just the bus offset plus
322 * the hose/domain memory base for bus.base.
323 * It then can be used to build PTEs for VRAM
324 * access, as done in ttm_bo_vm_fault().
326 mem->bus.offset = (mem->bus.offset & 0x0ffffffffUL) +
327 rdev->hose->dense_mem_base;
337 * TTM backend functions.
339 struct radeon_ttm_tt {
344 struct mm_struct *usermm;
349 /* prepare the sg table with the user pages */
350 static int radeon_ttm_tt_pin_userptr(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
352 struct radeon_device *rdev = radeon_get_rdev(bdev);
353 struct radeon_ttm_tt *gtt = (void *)ttm;
357 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
358 enum dma_data_direction direction = write ?
359 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
361 if (current->mm != gtt->usermm)
364 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
365 /* check that we only pin down anonymous memory
366 to prevent problems with writeback */
367 unsigned long end = gtt->userptr + (u64)ttm->num_pages * PAGE_SIZE;
368 struct vm_area_struct *vma;
369 vma = find_vma(gtt->usermm, gtt->userptr);
370 if (!vma || vma->vm_file || vma->vm_end < end)
375 unsigned num_pages = ttm->num_pages - pinned;
376 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
377 struct page **pages = ttm->pages + pinned;
379 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
386 } while (pinned < ttm->num_pages);
388 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
389 (u64)ttm->num_pages << PAGE_SHIFT,
394 r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0);
398 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
407 release_pages(ttm->pages, pinned);
411 static void radeon_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
413 struct radeon_device *rdev = radeon_get_rdev(bdev);
414 struct radeon_ttm_tt *gtt = (void *)ttm;
415 struct sg_page_iter sg_iter;
417 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
418 enum dma_data_direction direction = write ?
419 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
421 /* double check that we don't free the table twice */
425 /* free the sg table and pages again */
426 dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0);
428 for_each_sgtable_page(ttm->sg, &sg_iter, 0) {
429 struct page *page = sg_page_iter_page(&sg_iter);
430 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
431 set_page_dirty(page);
433 mark_page_accessed(page);
437 sg_free_table(ttm->sg);
440 static bool radeon_ttm_backend_is_bound(struct ttm_tt *ttm)
442 struct radeon_ttm_tt *gtt = (void*)ttm;
447 static int radeon_ttm_backend_bind(struct ttm_bo_device *bdev,
449 struct ttm_resource *bo_mem)
451 struct radeon_ttm_tt *gtt = (void*)ttm;
452 struct radeon_device *rdev = radeon_get_rdev(bdev);
453 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
454 RADEON_GART_PAGE_WRITE;
461 radeon_ttm_tt_pin_userptr(bdev, ttm);
462 flags &= ~RADEON_GART_PAGE_WRITE;
465 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
466 if (!ttm->num_pages) {
467 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
468 ttm->num_pages, bo_mem, ttm);
470 if (ttm->caching == ttm_cached)
471 flags |= RADEON_GART_PAGE_SNOOP;
472 r = radeon_gart_bind(rdev, gtt->offset, ttm->num_pages,
473 ttm->pages, gtt->ttm.dma_address, flags);
475 DRM_ERROR("failed to bind %u pages at 0x%08X\n",
476 ttm->num_pages, (unsigned)gtt->offset);
483 static void radeon_ttm_backend_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
485 struct radeon_ttm_tt *gtt = (void *)ttm;
486 struct radeon_device *rdev = radeon_get_rdev(bdev);
491 radeon_gart_unbind(rdev, gtt->offset, ttm->num_pages);
494 radeon_ttm_tt_unpin_userptr(bdev, ttm);
498 static void radeon_ttm_backend_destroy(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
500 struct radeon_ttm_tt *gtt = (void *)ttm;
502 radeon_ttm_backend_unbind(bdev, ttm);
503 ttm_tt_destroy_common(bdev, ttm);
505 ttm_tt_fini(>t->ttm);
509 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo,
512 struct radeon_ttm_tt *gtt;
513 enum ttm_caching caching;
514 struct radeon_bo *rbo;
515 #if IS_ENABLED(CONFIG_AGP)
516 struct radeon_device *rdev = radeon_get_rdev(bo->bdev);
518 if (rdev->flags & RADEON_IS_AGP) {
519 return ttm_agp_tt_create(bo, rdev->ddev->agp->bridge,
523 rbo = container_of(bo, struct radeon_bo, tbo);
525 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
530 if (rbo->flags & RADEON_GEM_GTT_UC)
531 caching = ttm_uncached;
532 else if (rbo->flags & RADEON_GEM_GTT_WC)
533 caching = ttm_write_combined;
535 caching = ttm_cached;
537 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) {
544 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct radeon_device *rdev,
547 #if IS_ENABLED(CONFIG_AGP)
548 if (rdev->flags & RADEON_IS_AGP)
554 return container_of(ttm, struct radeon_ttm_tt, ttm);
557 static int radeon_ttm_tt_populate(struct ttm_bo_device *bdev,
559 struct ttm_operation_ctx *ctx)
561 struct radeon_device *rdev = radeon_get_rdev(bdev);
562 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
563 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
565 if (gtt && gtt->userptr) {
566 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
570 ttm->page_flags |= TTM_PAGE_FLAG_SG;
574 if (slave && ttm->sg) {
575 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
580 return ttm_pool_alloc(&rdev->mman.bdev.pool, ttm, ctx);
583 static void radeon_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
585 struct radeon_device *rdev = radeon_get_rdev(bdev);
586 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
587 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
589 if (gtt && gtt->userptr) {
591 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
598 return ttm_pool_free(&rdev->mman.bdev.pool, ttm);
601 int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
602 struct ttm_tt *ttm, uint64_t addr,
605 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
611 gtt->usermm = current->mm;
612 gtt->userflags = flags;
616 bool radeon_ttm_tt_is_bound(struct ttm_bo_device *bdev,
619 #if IS_ENABLED(CONFIG_AGP)
620 struct radeon_device *rdev = radeon_get_rdev(bdev);
621 if (rdev->flags & RADEON_IS_AGP)
622 return ttm_agp_is_bound(ttm);
624 return radeon_ttm_backend_is_bound(ttm);
627 static int radeon_ttm_tt_bind(struct ttm_bo_device *bdev,
629 struct ttm_resource *bo_mem)
631 #if IS_ENABLED(CONFIG_AGP)
632 struct radeon_device *rdev = radeon_get_rdev(bdev);
637 #if IS_ENABLED(CONFIG_AGP)
638 if (rdev->flags & RADEON_IS_AGP)
639 return ttm_agp_bind(ttm, bo_mem);
642 return radeon_ttm_backend_bind(bdev, ttm, bo_mem);
645 static void radeon_ttm_tt_unbind(struct ttm_bo_device *bdev,
648 #if IS_ENABLED(CONFIG_AGP)
649 struct radeon_device *rdev = radeon_get_rdev(bdev);
651 if (rdev->flags & RADEON_IS_AGP) {
656 radeon_ttm_backend_unbind(bdev, ttm);
659 static void radeon_ttm_tt_destroy(struct ttm_bo_device *bdev,
662 #if IS_ENABLED(CONFIG_AGP)
663 struct radeon_device *rdev = radeon_get_rdev(bdev);
665 if (rdev->flags & RADEON_IS_AGP) {
667 ttm_tt_destroy_common(bdev, ttm);
668 ttm_agp_destroy(ttm);
672 radeon_ttm_backend_destroy(bdev, ttm);
675 bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev,
678 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
683 return !!gtt->userptr;
686 bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev,
689 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
694 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
698 radeon_bo_delete_mem_notify(struct ttm_buffer_object *bo)
700 radeon_bo_move_notify(bo, false, NULL);
703 static struct ttm_bo_driver radeon_bo_driver = {
704 .ttm_tt_create = &radeon_ttm_tt_create,
705 .ttm_tt_populate = &radeon_ttm_tt_populate,
706 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
707 .ttm_tt_destroy = &radeon_ttm_tt_destroy,
708 .eviction_valuable = ttm_bo_eviction_valuable,
709 .evict_flags = &radeon_evict_flags,
710 .move = &radeon_bo_move,
711 .verify_access = &radeon_verify_access,
712 .delete_mem_notify = &radeon_bo_delete_mem_notify,
713 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
716 int radeon_ttm_init(struct radeon_device *rdev)
720 /* No others user of address space so set it to 0 */
721 r = ttm_bo_device_init(&rdev->mman.bdev, &radeon_bo_driver, rdev->dev,
722 rdev->ddev->anon_inode->i_mapping,
723 rdev->ddev->vma_offset_manager,
725 dma_addressing_limited(&rdev->pdev->dev));
727 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
730 rdev->mman.initialized = true;
732 r = radeon_ttm_init_vram(rdev);
734 DRM_ERROR("Failed initializing VRAM heap.\n");
737 /* Change the size here instead of the init above so only lpfn is affected */
738 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
740 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
741 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
742 NULL, &rdev->stolen_vga_memory);
746 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
749 r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
750 radeon_bo_unreserve(rdev->stolen_vga_memory);
752 radeon_bo_unref(&rdev->stolen_vga_memory);
755 DRM_INFO("radeon: %uM of VRAM memory ready\n",
756 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
758 r = radeon_ttm_init_gtt(rdev);
760 DRM_ERROR("Failed initializing GTT heap.\n");
763 DRM_INFO("radeon: %uM of GTT memory ready.\n",
764 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
766 r = radeon_ttm_debugfs_init(rdev);
768 DRM_ERROR("Failed to init debugfs\n");
774 void radeon_ttm_fini(struct radeon_device *rdev)
778 if (!rdev->mman.initialized)
780 radeon_ttm_debugfs_fini(rdev);
781 if (rdev->stolen_vga_memory) {
782 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
784 radeon_bo_unpin(rdev->stolen_vga_memory);
785 radeon_bo_unreserve(rdev->stolen_vga_memory);
787 radeon_bo_unref(&rdev->stolen_vga_memory);
789 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_VRAM);
790 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_TT);
791 ttm_bo_device_release(&rdev->mman.bdev);
792 radeon_gart_fini(rdev);
793 rdev->mman.initialized = false;
794 DRM_INFO("radeon: ttm finalized\n");
797 /* this should only be called at bootup or when userspace
799 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
801 struct ttm_resource_manager *man;
803 if (!rdev->mman.initialized)
806 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
807 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
808 man->size = size >> PAGE_SHIFT;
811 static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf)
813 struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
814 struct radeon_device *rdev = radeon_get_rdev(bo->bdev);
817 down_read(&rdev->pm.mclk_lock);
819 ret = ttm_bo_vm_reserve(bo, vmf);
823 ret = radeon_bo_fault_reserve_notify(bo);
827 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
828 TTM_BO_VM_NUM_PREFAULT, 1);
829 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
833 dma_resv_unlock(bo->base.resv);
836 up_read(&rdev->pm.mclk_lock);
840 static struct vm_operations_struct radeon_ttm_vm_ops = {
841 .fault = radeon_ttm_fault,
842 .open = ttm_bo_vm_open,
843 .close = ttm_bo_vm_close,
844 .access = ttm_bo_vm_access
847 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
850 struct drm_file *file_priv = filp->private_data;
851 struct radeon_device *rdev = file_priv->minor->dev->dev_private;
856 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
857 if (unlikely(r != 0))
860 vma->vm_ops = &radeon_ttm_vm_ops;
864 #if defined(CONFIG_DEBUG_FS)
866 static int radeon_mm_dump_table(struct seq_file *m, void *data)
868 struct drm_info_node *node = (struct drm_info_node *)m->private;
869 unsigned ttm_pl = *(int*)node->info_ent->data;
870 struct drm_device *dev = node->minor->dev;
871 struct radeon_device *rdev = dev->dev_private;
872 struct ttm_resource_manager *man = ttm_manager_type(&rdev->mman.bdev, ttm_pl);
873 struct drm_printer p = drm_seq_file_printer(m);
875 man->func->debug(man, &p);
879 static int radeon_ttm_pool_debugfs(struct seq_file *m, void *data)
881 struct drm_info_node *node = (struct drm_info_node *)m->private;
882 struct drm_device *dev = node->minor->dev;
883 struct radeon_device *rdev = dev->dev_private;
885 return ttm_pool_debugfs(&rdev->mman.bdev.pool, m);
888 static int ttm_pl_vram = TTM_PL_VRAM;
889 static int ttm_pl_tt = TTM_PL_TT;
891 static struct drm_info_list radeon_ttm_debugfs_list[] = {
892 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
893 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
894 {"ttm_page_pool", radeon_ttm_pool_debugfs, 0, NULL}
897 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
899 struct radeon_device *rdev = inode->i_private;
900 i_size_write(inode, rdev->mc.mc_vram_size);
901 filep->private_data = inode->i_private;
905 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
906 size_t size, loff_t *pos)
908 struct radeon_device *rdev = f->private_data;
912 if (size & 0x3 || *pos & 0x3)
919 if (*pos >= rdev->mc.mc_vram_size)
922 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
923 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
924 if (rdev->family >= CHIP_CEDAR)
925 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
926 value = RREG32(RADEON_MM_DATA);
927 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
929 r = put_user(value, (uint32_t *)buf);
942 static const struct file_operations radeon_ttm_vram_fops = {
943 .owner = THIS_MODULE,
944 .open = radeon_ttm_vram_open,
945 .read = radeon_ttm_vram_read,
946 .llseek = default_llseek
949 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
951 struct radeon_device *rdev = inode->i_private;
952 i_size_write(inode, rdev->mc.gtt_size);
953 filep->private_data = inode->i_private;
957 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
958 size_t size, loff_t *pos)
960 struct radeon_device *rdev = f->private_data;
965 loff_t p = *pos / PAGE_SIZE;
966 unsigned off = *pos & ~PAGE_MASK;
967 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
971 if (p >= rdev->gart.num_cpu_pages)
974 page = rdev->gart.pages[p];
979 r = copy_to_user(buf, ptr, cur_size);
980 kunmap(rdev->gart.pages[p]);
982 r = clear_user(buf, cur_size);
996 static const struct file_operations radeon_ttm_gtt_fops = {
997 .owner = THIS_MODULE,
998 .open = radeon_ttm_gtt_open,
999 .read = radeon_ttm_gtt_read,
1000 .llseek = default_llseek
1005 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1007 #if defined(CONFIG_DEBUG_FS)
1010 struct drm_minor *minor = rdev->ddev->primary;
1011 struct dentry *root = minor->debugfs_root;
1013 rdev->mman.vram = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO,
1015 &radeon_ttm_vram_fops);
1017 rdev->mman.gtt = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO,
1018 root, rdev, &radeon_ttm_gtt_fops);
1020 count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1022 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1029 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1031 #if defined(CONFIG_DEBUG_FS)
1033 debugfs_remove(rdev->mman.vram);
1034 rdev->mman.vram = NULL;
1036 debugfs_remove(rdev->mman.gtt);
1037 rdev->mman.gtt = NULL;