drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/io.h>
  34 #include <linux/list.h>
  35 #include <linux/slab.h>
  36
  37 #include <drm/drm_cache.h>
  38 #include <drm/drm_prime.h>
  39 #include <drm/radeon_drm.h>
  40
  41 #include "radeon.h"
  42 #include "radeon_trace.h"
  43
  44 int radeon_ttm_init(struct radeon_device *rdev);
  45 void radeon_ttm_fini(struct radeon_device *rdev);
  46 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  47
  48 /*
  49  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  50  * function are calling it.
  51  */
  52
  53 static void radeon_update_memory_usage(struct radeon_bo *bo,
  54                                        unsigned mem_type, int sign)
  55 {
  56         struct radeon_device *rdev = bo->rdev;
  57         u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
  58
  59         switch (mem_type) {
  60         case TTM_PL_TT:
  61                 if (sign > 0)
  62                         atomic64_add(size, &rdev->gtt_usage);
  63                 else
  64                         atomic64_sub(size, &rdev->gtt_usage);
  65                 break;
  66         case TTM_PL_VRAM:
  67                 if (sign > 0)
  68                         atomic64_add(size, &rdev->vram_usage);
  69                 else
  70                         atomic64_sub(size, &rdev->vram_usage);
  71                 break;
  72         }
  73 }
  74
  75 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  76 {
  77         struct radeon_bo *bo;
  78
  79         bo = container_of(tbo, struct radeon_bo, tbo);
  80
  81         radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
  82
  83         mutex_lock(&bo->rdev->gem.mutex);
  84         list_del_init(&bo->list);
  85         mutex_unlock(&bo->rdev->gem.mutex);
  86         radeon_bo_clear_surface_reg(bo);
  87         WARN_ON_ONCE(!list_empty(&bo->va));
  88         if (bo->tbo.base.import_attach)
  89                 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
  90         drm_gem_object_release(&bo->tbo.base);
  91         kfree(bo);
  92 }
  93
  94 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  95 {
  96         if (bo->destroy == &radeon_ttm_bo_destroy)
  97                 return true;
  98         return false;
  99 }
 100
 101 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
 102 {
 103         u32 c = 0, i;
 104
 105         rbo->placement.placement = rbo->placements;
 106         rbo->placement.busy_placement = rbo->placements;
 107         if (domain & RADEON_GEM_DOMAIN_VRAM) {
 108                 /* Try placing BOs which don't need CPU access outside of the
 109                  * CPU accessible part of VRAM
 110                  */
 111                 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 112                     rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
 113                         rbo->placements[c].fpfn =
 114                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 115                         rbo->placements[c].mem_type = TTM_PL_VRAM;
 116                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 117                                                      TTM_PL_FLAG_UNCACHED;
 118                 }
 119
 120                 rbo->placements[c].fpfn = 0;
 121                 rbo->placements[c].mem_type = TTM_PL_VRAM;
 122                 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 123                                              TTM_PL_FLAG_UNCACHED;
 124         }
 125
 126         if (domain & RADEON_GEM_DOMAIN_GTT) {
 127                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 128                         rbo->placements[c].fpfn = 0;
 129                         rbo->placements[c].mem_type = TTM_PL_TT;
 130                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED;
 131
 132                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 133                            (rbo->rdev->flags & RADEON_IS_AGP)) {
 134                         rbo->placements[c].fpfn = 0;
 135                         rbo->placements[c].mem_type = TTM_PL_TT;
 136                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 137                                 TTM_PL_FLAG_UNCACHED;
 138                 } else {
 139                         rbo->placements[c].fpfn = 0;
 140                         rbo->placements[c].mem_type = TTM_PL_TT;
 141                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED;
 142                 }
 143         }
 144
 145         if (domain & RADEON_GEM_DOMAIN_CPU) {
 146                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 147                         rbo->placements[c].fpfn = 0;
 148                         rbo->placements[c].mem_type = TTM_PL_SYSTEM;
 149                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED;
 150
 151                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 152                     rbo->rdev->flags & RADEON_IS_AGP) {
 153                         rbo->placements[c].fpfn = 0;
 154                         rbo->placements[c].mem_type = TTM_PL_SYSTEM;
 155                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 156                                 TTM_PL_FLAG_UNCACHED;
 157                 } else {
 158                         rbo->placements[c].fpfn = 0;
 159                         rbo->placements[c].mem_type = TTM_PL_SYSTEM;
 160                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED;
 161                 }
 162         }
 163         if (!c) {
 164                 rbo->placements[c].fpfn = 0;
 165                 rbo->placements[c].mem_type = TTM_PL_SYSTEM;
 166                 rbo->placements[c++].flags = TTM_PL_MASK_CACHING;
 167         }
 168
 169         rbo->placement.num_placement = c;
 170         rbo->placement.num_busy_placement = c;
 171
 172         for (i = 0; i < c; ++i) {
 173                 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 174                     (rbo->placements[i].mem_type == TTM_PL_VRAM) &&
 175                     !rbo->placements[i].fpfn)
 176                         rbo->placements[i].lpfn =
 177                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 178                 else
 179                         rbo->placements[i].lpfn = 0;
 180         }
 181 }
 182
 183 int radeon_bo_create(struct radeon_device *rdev,
 184                      unsigned long size, int byte_align, bool kernel,
 185                      u32 domain, u32 flags, struct sg_table *sg,
 186                      struct dma_resv *resv,
 187                      struct radeon_bo **bo_ptr)
 188 {
 189         struct radeon_bo *bo;
 190         enum ttm_bo_type type;
 191         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 192         size_t acc_size;
 193         int r;
 194
 195         size = ALIGN(size, PAGE_SIZE);
 196
 197         if (kernel) {
 198                 type = ttm_bo_type_kernel;
 199         } else if (sg) {
 200                 type = ttm_bo_type_sg;
 201         } else {
 202                 type = ttm_bo_type_device;
 203         }
 204         *bo_ptr = NULL;
 205
 206         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 207                                        sizeof(struct radeon_bo));
 208
 209         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 210         if (bo == NULL)
 211                 return -ENOMEM;
 212         drm_gem_private_object_init(rdev->ddev, &bo->tbo.base, size);
 213         bo->rdev = rdev;
 214         bo->surface_reg = -1;
 215         INIT_LIST_HEAD(&bo->list);
 216         INIT_LIST_HEAD(&bo->va);
 217         bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
 218                                        RADEON_GEM_DOMAIN_GTT |
 219                                        RADEON_GEM_DOMAIN_CPU);
 220
 221         bo->flags = flags;
 222         /* PCI GART is always snooped */
 223         if (!(rdev->flags & RADEON_IS_PCIE))
 224                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 225
 226         /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx
 227          * See https://bugs.freedesktop.org/show_bug.cgi?id=91268
 228          */
 229         if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635)
 230                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 231
 232 #ifdef CONFIG_X86_32
 233         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 234          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 235          */
 236         bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 237 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 238         /* Don't try to enable write-combining when it can't work, or things
 239          * may be slow
 240          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 241          */
 242 #ifndef CONFIG_COMPILE_TEST
 243 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 244          thanks to write-combining
 245 #endif
 246
 247         if (bo->flags & RADEON_GEM_GTT_WC)
 248                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 249                               "better performance thanks to write-combining\n");
 250         bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 251 #else
 252         /* For architectures that don't support WC memory,
 253          * mask out the WC flag from the BO
 254          */
 255         if (!drm_arch_can_wc_memory())
 256                 bo->flags &= ~RADEON_GEM_GTT_WC;
 257 #endif
 258
 259         radeon_ttm_placement_from_domain(bo, domain);
 260         /* Kernel allocation are uninterruptible */
 261         down_read(&rdev->pm.mclk_lock);
 262         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 263                         &bo->placement, page_align, !kernel, acc_size,
 264                         sg, resv, &radeon_ttm_bo_destroy);
 265         up_read(&rdev->pm.mclk_lock);
 266         if (unlikely(r != 0)) {
 267                 return r;
 268         }
 269         *bo_ptr = bo;
 270
 271         trace_radeon_bo_create(bo);
 272
 273         return 0;
 274 }
 275
 276 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 277 {
 278         bool is_iomem;
 279         int r;
 280
 281         if (bo->kptr) {
 282                 if (ptr) {
 283                         *ptr = bo->kptr;
 284                 }
 285                 return 0;
 286         }
 287         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 288         if (r) {
 289                 return r;
 290         }
 291         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 292         if (ptr) {
 293                 *ptr = bo->kptr;
 294         }
 295         radeon_bo_check_tiling(bo, 0, 0);
 296         return 0;
 297 }
 298
 299 void radeon_bo_kunmap(struct radeon_bo *bo)
 300 {
 301         if (bo->kptr == NULL)
 302                 return;
 303         bo->kptr = NULL;
 304         radeon_bo_check_tiling(bo, 0, 0);
 305         ttm_bo_kunmap(&bo->kmap);
 306 }
 307
 308 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
 309 {
 310         if (bo == NULL)
 311                 return NULL;
 312
 313         ttm_bo_get(&bo->tbo);
 314         return bo;
 315 }
 316
 317 void radeon_bo_unref(struct radeon_bo **bo)
 318 {
 319         struct ttm_buffer_object *tbo;
 320
 321         if ((*bo) == NULL)
 322                 return;
 323         tbo = &((*bo)->tbo);
 324         ttm_bo_put(tbo);
 325         *bo = NULL;
 326 }
 327
 328 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 329                              u64 *gpu_addr)
 330 {
 331         struct ttm_operation_ctx ctx = { false, false };
 332         int r, i;
 333
 334         if (radeon_ttm_tt_has_userptr(bo->rdev, bo->tbo.ttm))
 335                 return -EPERM;
 336
 337         if (bo->tbo.pin_count) {
 338                 ttm_bo_pin(&bo->tbo);
 339                 if (gpu_addr)
 340                         *gpu_addr = radeon_bo_gpu_offset(bo);
 341
 342                 if (max_offset != 0) {
 343                         u64 domain_start;
 344
 345                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 346                                 domain_start = bo->rdev->mc.vram_start;
 347                         else
 348                                 domain_start = bo->rdev->mc.gtt_start;
 349                         WARN_ON_ONCE(max_offset <
 350                                      (radeon_bo_gpu_offset(bo) - domain_start));
 351                 }
 352
 353                 return 0;
 354         }
 355         if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) {
 356                 /* A BO shared as a dma-buf cannot be sensibly migrated to VRAM */
 357                 return -EINVAL;
 358         }
 359
 360         radeon_ttm_placement_from_domain(bo, domain);
 361         for (i = 0; i < bo->placement.num_placement; i++) {
 362                 /* force to pin into visible video ram */
 363                 if ((bo->placements[i].mem_type == TTM_PL_VRAM) &&
 364                     !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 365                     (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
 366                         bo->placements[i].lpfn =
 367                                 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 368                 else
 369                         bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
 370         }
 371
 372         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 373         if (likely(r == 0)) {
 374                 ttm_bo_pin(&bo->tbo);
 375                 if (gpu_addr != NULL)
 376                         *gpu_addr = radeon_bo_gpu_offset(bo);
 377                 if (domain == RADEON_GEM_DOMAIN_VRAM)
 378                         bo->rdev->vram_pin_size += radeon_bo_size(bo);
 379                 else
 380                         bo->rdev->gart_pin_size += radeon_bo_size(bo);
 381         } else {
 382                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 383         }
 384         return r;
 385 }
 386
 387 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 388 {
 389         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 390 }
 391
 392 void radeon_bo_unpin(struct radeon_bo *bo)
 393 {
 394         ttm_bo_unpin(&bo->tbo);
 395         if (!bo->tbo.pin_count) {
 396                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 397                         bo->rdev->vram_pin_size -= radeon_bo_size(bo);
 398                 else
 399                         bo->rdev->gart_pin_size -= radeon_bo_size(bo);
 400         }
 401 }
 402
 403 int radeon_bo_evict_vram(struct radeon_device *rdev)
 404 {
 405         struct ttm_bo_device *bdev = &rdev->mman.bdev;
 406         struct ttm_resource_manager *man;
 407
 408         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 409 #ifndef CONFIG_HIBERNATION
 410         if (rdev->flags & RADEON_IS_IGP) {
 411                 if (rdev->mc.igp_sideport_enabled == false)
 412                         /* Useless to evict on IGP chips */
 413                         return 0;
 414         }
 415 #endif
 416         man = ttm_manager_type(bdev, TTM_PL_VRAM);
 417         return ttm_resource_manager_evict_all(bdev, man);
 418 }
 419
 420 void radeon_bo_force_delete(struct radeon_device *rdev)
 421 {
 422         struct radeon_bo *bo, *n;
 423
 424         if (list_empty(&rdev->gem.objects)) {
 425                 return;
 426         }
 427         dev_err(rdev->dev, "Userspace still has active objects !\n");
 428         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 429                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 430                         &bo->tbo.base, bo, (unsigned long)bo->tbo.base.size,
 431                         *((unsigned long *)&bo->tbo.base.refcount));
 432                 mutex_lock(&bo->rdev->gem.mutex);
 433                 list_del_init(&bo->list);
 434                 mutex_unlock(&bo->rdev->gem.mutex);
 435                 /* this should unref the ttm bo */
 436                 drm_gem_object_put(&bo->tbo.base);
 437         }
 438 }
 439
 440 int radeon_bo_init(struct radeon_device *rdev)
 441 {
 442         /* reserve PAT memory space to WC for VRAM */
 443         arch_io_reserve_memtype_wc(rdev->mc.aper_base,
 444                                    rdev->mc.aper_size);
 445
 446         /* Add an MTRR for the VRAM */
 447         if (!rdev->fastfb_working) {
 448                 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
 449                                                       rdev->mc.aper_size);
 450         }
 451         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 452                 rdev->mc.mc_vram_size >> 20,
 453                 (unsigned long long)rdev->mc.aper_size >> 20);
 454         DRM_INFO("RAM width %dbits %cDR\n",
 455                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 456         return radeon_ttm_init(rdev);
 457 }
 458
 459 void radeon_bo_fini(struct radeon_device *rdev)
 460 {
 461         radeon_ttm_fini(rdev);
 462         arch_phys_wc_del(rdev->mc.vram_mtrr);
 463         arch_io_free_memtype_wc(rdev->mc.aper_base, rdev->mc.aper_size);
 464 }
 465
 466 /* Returns how many bytes TTM can move per IB.
 467  */
 468 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
 469 {
 470         u64 real_vram_size = rdev->mc.real_vram_size;
 471         u64 vram_usage = atomic64_read(&rdev->vram_usage);
 472
 473         /* This function is based on the current VRAM usage.
 474          *
 475          * - If all of VRAM is free, allow relocating the number of bytes that
 476          *   is equal to 1/4 of the size of VRAM for this IB.
 477
 478          * - If more than one half of VRAM is occupied, only allow relocating
 479          *   1 MB of data for this IB.
 480          *
 481          * - From 0 to one half of used VRAM, the threshold decreases
 482          *   linearly.
 483          *         __________________
 484          * 1/4 of -|\               |
 485          * VRAM    | \              |
 486          *         |  \             |
 487          *         |   \            |
 488          *         |    \           |
 489          *         |     \          |
 490          *         |      \         |
 491          *         |       \________|1 MB
 492          *         |----------------|
 493          *    VRAM 0 %             100 %
 494          *         used            used
 495          *
 496          * Note: It's a threshold, not a limit. The threshold must be crossed
 497          * for buffer relocations to stop, so any buffer of an arbitrary size
 498          * can be moved as long as the threshold isn't crossed before
 499          * the relocation takes place. We don't want to disable buffer
 500          * relocations completely.
 501          *
 502          * The idea is that buffers should be placed in VRAM at creation time
 503          * and TTM should only do a minimum number of relocations during
 504          * command submission. In practice, you need to submit at least
 505          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 506          *
 507          * Also, things can get pretty crazy under memory pressure and actual
 508          * VRAM usage can change a lot, so playing safe even at 50% does
 509          * consistently increase performance.
 510          */
 511
 512         u64 half_vram = real_vram_size >> 1;
 513         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 514         u64 bytes_moved_threshold = half_free_vram >> 1;
 515         return max(bytes_moved_threshold, 1024*1024ull);
 516 }
 517
 518 int radeon_bo_list_validate(struct radeon_device *rdev,
 519                             struct ww_acquire_ctx *ticket,
 520                             struct list_head *head, int ring)
 521 {
 522         struct ttm_operation_ctx ctx = { true, false };
 523         struct radeon_bo_list *lobj;
 524         struct list_head duplicates;
 525         int r;
 526         u64 bytes_moved = 0, initial_bytes_moved;
 527         u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
 528
 529         INIT_LIST_HEAD(&duplicates);
 530         r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates);
 531         if (unlikely(r != 0)) {
 532                 return r;
 533         }
 534
 535         list_for_each_entry(lobj, head, tv.head) {
 536                 struct radeon_bo *bo = lobj->robj;
 537                 if (!bo->tbo.pin_count) {
 538                         u32 domain = lobj->preferred_domains;
 539                         u32 allowed = lobj->allowed_domains;
 540                         u32 current_domain =
 541                                 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
 542
 543                         /* Check if this buffer will be moved and don't move it
 544                          * if we have moved too many buffers for this IB already.
 545                          *
 546                          * Note that this allows moving at least one buffer of
 547                          * any size, because it doesn't take the current "bo"
 548                          * into account. We don't want to disallow buffer moves
 549                          * completely.
 550                          */
 551                         if ((allowed & current_domain) != 0 &&
 552                             (domain & current_domain) == 0 && /* will be moved */
 553                             bytes_moved > bytes_moved_threshold) {
 554                                 /* don't move it */
 555                                 domain = current_domain;
 556                         }
 557
 558                 retry:
 559                         radeon_ttm_placement_from_domain(bo, domain);
 560                         if (ring == R600_RING_TYPE_UVD_INDEX)
 561                                 radeon_uvd_force_into_uvd_segment(bo, allowed);
 562
 563                         initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
 564                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 565                         bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
 566                                        initial_bytes_moved;
 567
 568                         if (unlikely(r)) {
 569                                 if (r != -ERESTARTSYS &&
 570                                     domain != lobj->allowed_domains) {
 571                                         domain = lobj->allowed_domains;
 572                                         goto retry;
 573                                 }
 574                                 ttm_eu_backoff_reservation(ticket, head);
 575                                 return r;
 576                         }
 577                 }
 578                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 579                 lobj->tiling_flags = bo->tiling_flags;
 580         }
 581
 582         list_for_each_entry(lobj, &duplicates, tv.head) {
 583                 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj);
 584                 lobj->tiling_flags = lobj->robj->tiling_flags;
 585         }
 586
 587         return 0;
 588 }
 589
 590 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 591 {
 592         struct radeon_device *rdev = bo->rdev;
 593         struct radeon_surface_reg *reg;
 594         struct radeon_bo *old_object;
 595         int steal;
 596         int i;
 597
 598         dma_resv_assert_held(bo->tbo.base.resv);
 599
 600         if (!bo->tiling_flags)
 601                 return 0;
 602
 603         if (bo->surface_reg >= 0) {
 604                 reg = &rdev->surface_regs[bo->surface_reg];
 605                 i = bo->surface_reg;
 606                 goto out;
 607         }
 608
 609         steal = -1;
 610         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 611
 612                 reg = &rdev->surface_regs[i];
 613                 if (!reg->bo)
 614                         break;
 615
 616                 old_object = reg->bo;
 617                 if (old_object->tbo.pin_count == 0)
 618                         steal = i;
 619         }
 620
 621         /* if we are all out */
 622         if (i == RADEON_GEM_MAX_SURFACES) {
 623                 if (steal == -1)
 624                         return -ENOMEM;
 625                 /* find someone with a surface reg and nuke their BO */
 626                 reg = &rdev->surface_regs[steal];
 627                 old_object = reg->bo;
 628                 /* blow away the mapping */
 629                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 630                 ttm_bo_unmap_virtual(&old_object->tbo);
 631                 old_object->surface_reg = -1;
 632                 i = steal;
 633         }
 634
 635         bo->surface_reg = i;
 636         reg->bo = bo;
 637
 638 out:
 639         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 640                                bo->tbo.mem.start << PAGE_SHIFT,
 641                                bo->tbo.num_pages << PAGE_SHIFT);
 642         return 0;
 643 }
 644
 645 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 646 {
 647         struct radeon_device *rdev = bo->rdev;
 648         struct radeon_surface_reg *reg;
 649
 650         if (bo->surface_reg == -1)
 651                 return;
 652
 653         reg = &rdev->surface_regs[bo->surface_reg];
 654         radeon_clear_surface_reg(rdev, bo->surface_reg);
 655
 656         reg->bo = NULL;
 657         bo->surface_reg = -1;
 658 }
 659
 660 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 661                                 uint32_t tiling_flags, uint32_t pitch)
 662 {
 663         struct radeon_device *rdev = bo->rdev;
 664         int r;
 665
 666         if (rdev->family >= CHIP_CEDAR) {
 667                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 668
 669                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 670                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 671                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 672                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 673                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 674                 switch (bankw) {
 675                 case 0:
 676                 case 1:
 677                 case 2:
 678                 case 4:
 679                 case 8:
 680                         break;
 681                 default:
 682                         return -EINVAL;
 683                 }
 684                 switch (bankh) {
 685                 case 0:
 686                 case 1:
 687                 case 2:
 688                 case 4:
 689                 case 8:
 690                         break;
 691                 default:
 692                         return -EINVAL;
 693                 }
 694                 switch (mtaspect) {
 695                 case 0:
 696                 case 1:
 697                 case 2:
 698                 case 4:
 699                 case 8:
 700                         break;
 701                 default:
 702                         return -EINVAL;
 703                 }
 704                 if (tilesplit > 6) {
 705                         return -EINVAL;
 706                 }
 707                 if (stilesplit > 6) {
 708                         return -EINVAL;
 709                 }
 710         }
 711         r = radeon_bo_reserve(bo, false);
 712         if (unlikely(r != 0))
 713                 return r;
 714         bo->tiling_flags = tiling_flags;
 715         bo->pitch = pitch;
 716         radeon_bo_unreserve(bo);
 717         return 0;
 718 }
 719
 720 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 721                                 uint32_t *tiling_flags,
 722                                 uint32_t *pitch)
 723 {
 724         dma_resv_assert_held(bo->tbo.base.resv);
 725
 726         if (tiling_flags)
 727                 *tiling_flags = bo->tiling_flags;
 728         if (pitch)
 729                 *pitch = bo->pitch;
 730 }
 731
 732 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 733                                 bool force_drop)
 734 {
 735         if (!force_drop)
 736                 dma_resv_assert_held(bo->tbo.base.resv);
 737
 738         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 739                 return 0;
 740
 741         if (force_drop) {
 742                 radeon_bo_clear_surface_reg(bo);
 743                 return 0;
 744         }
 745
 746         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 747                 if (!has_moved)
 748                         return 0;
 749
 750                 if (bo->surface_reg >= 0)
 751                         radeon_bo_clear_surface_reg(bo);
 752                 return 0;
 753         }
 754
 755         if ((bo->surface_reg >= 0) && !has_moved)
 756                 return 0;
 757
 758         return radeon_bo_get_surface_reg(bo);
 759 }
 760
 761 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 762                            bool evict,
 763                            struct ttm_resource *new_mem)
 764 {
 765         struct radeon_bo *rbo;
 766
 767         if (!radeon_ttm_bo_is_radeon_bo(bo))
 768                 return;
 769
 770         rbo = container_of(bo, struct radeon_bo, tbo);
 771         radeon_bo_check_tiling(rbo, 0, 1);
 772         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 773
 774         /* update statistics */
 775         if (!new_mem)
 776                 return;
 777
 778         radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
 779         radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
 780 }
 781
 782 vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 783 {
 784         struct ttm_operation_ctx ctx = { false, false };
 785         struct radeon_device *rdev;
 786         struct radeon_bo *rbo;
 787         unsigned long offset, size, lpfn;
 788         int i, r;
 789
 790         if (!radeon_ttm_bo_is_radeon_bo(bo))
 791                 return 0;
 792         rbo = container_of(bo, struct radeon_bo, tbo);
 793         radeon_bo_check_tiling(rbo, 0, 0);
 794         rdev = rbo->rdev;
 795         if (bo->mem.mem_type != TTM_PL_VRAM)
 796                 return 0;
 797
 798         size = bo->mem.num_pages << PAGE_SHIFT;
 799         offset = bo->mem.start << PAGE_SHIFT;
 800         if ((offset + size) <= rdev->mc.visible_vram_size)
 801                 return 0;
 802
 803         /* Can't move a pinned BO to visible VRAM */
 804         if (rbo->tbo.pin_count > 0)
 805                 return VM_FAULT_SIGBUS;
 806
 807         /* hurrah the memory is not visible ! */
 808         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 809         lpfn =  rdev->mc.visible_vram_size >> PAGE_SHIFT;
 810         for (i = 0; i < rbo->placement.num_placement; i++) {
 811                 /* Force into visible VRAM */
 812                 if ((rbo->placements[i].mem_type == TTM_PL_VRAM) &&
 813                     (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
 814                         rbo->placements[i].lpfn = lpfn;
 815         }
 816         r = ttm_bo_validate(bo, &rbo->placement, &ctx);
 817         if (unlikely(r == -ENOMEM)) {
 818                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 819                 r = ttm_bo_validate(bo, &rbo->placement, &ctx);
 820         } else if (likely(!r)) {
 821                 offset = bo->mem.start << PAGE_SHIFT;
 822                 /* this should never happen */
 823                 if ((offset + size) > rdev->mc.visible_vram_size)
 824                         return VM_FAULT_SIGBUS;
 825         }
 826
 827         if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
 828                 return VM_FAULT_NOPAGE;
 829         else if (unlikely(r))
 830                 return VM_FAULT_SIGBUS;
 831
 832         ttm_bo_move_to_lru_tail_unlocked(bo);
 833         return 0;
 834 }
 835
 836 /**
 837  * radeon_bo_fence - add fence to buffer object
 838  *
 839  * @bo: buffer object in question
 840  * @fence: fence to add
 841  * @shared: true if fence should be added shared
 842  *
 843  */
 844 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
 845                      bool shared)
 846 {
 847         struct dma_resv *resv = bo->tbo.base.resv;
 848
 849         if (shared)
 850                 dma_resv_add_shared_fence(resv, &fence->base);
 851         else
 852                 dma_resv_add_excl_fence(resv, &fence->base);
 853 }