drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/io.h>
  34 #include <linux/list.h>
  35 #include <linux/slab.h>
  36
  37 #include <drm/drm_cache.h>
  38 #include <drm/drm_prime.h>
  39 #include <drm/radeon_drm.h>
  40
  41 #include "radeon.h"
  42 #include "radeon_trace.h"
  43
  44 int radeon_ttm_init(struct radeon_device *rdev);
  45 void radeon_ttm_fini(struct radeon_device *rdev);
  46 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  47
  48 /*
  49  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  50  * function are calling it.
  51  */
  52
  53 static void radeon_update_memory_usage(struct radeon_bo *bo,
  54                                        unsigned mem_type, int sign)
  55 {
  56         struct radeon_device *rdev = bo->rdev;
  57         u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
  58
  59         switch (mem_type) {
  60         case TTM_PL_TT:
  61                 if (sign > 0)
  62                         atomic64_add(size, &rdev->gtt_usage);
  63                 else
  64                         atomic64_sub(size, &rdev->gtt_usage);
  65                 break;
  66         case TTM_PL_VRAM:
  67                 if (sign > 0)
  68                         atomic64_add(size, &rdev->vram_usage);
  69                 else
  70                         atomic64_sub(size, &rdev->vram_usage);
  71                 break;
  72         }
  73 }
  74
  75 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  76 {
  77         struct radeon_bo *bo;
  78
  79         bo = container_of(tbo, struct radeon_bo, tbo);
  80
  81         radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
  82
  83         mutex_lock(&bo->rdev->gem.mutex);
  84         list_del_init(&bo->list);
  85         mutex_unlock(&bo->rdev->gem.mutex);
  86         radeon_bo_clear_surface_reg(bo);
  87         WARN_ON_ONCE(!list_empty(&bo->va));
  88         if (bo->tbo.base.import_attach)
  89                 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
  90         drm_gem_object_release(&bo->tbo.base);
  91         kfree(bo);
  92 }
  93
  94 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  95 {
  96         if (bo->destroy == &radeon_ttm_bo_destroy)
  97                 return true;
  98         return false;
  99 }
 100
 101 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
 102 {
 103         u32 c = 0, i;
 104
 105         rbo->placement.placement = rbo->placements;
 106         rbo->placement.busy_placement = rbo->placements;
 107         if (domain & RADEON_GEM_DOMAIN_VRAM) {
 108                 /* Try placing BOs which don't need CPU access outside of the
 109                  * CPU accessible part of VRAM
 110                  */
 111                 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 112                     rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
 113                         rbo->placements[c].fpfn =
 114                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 115                         rbo->placements[c].mem_type = TTM_PL_VRAM;
 116                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 117                                                      TTM_PL_FLAG_UNCACHED;
 118                 }
 119
 120                 rbo->placements[c].fpfn = 0;
 121                 rbo->placements[c].mem_type = TTM_PL_VRAM;
 122                 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 123                                              TTM_PL_FLAG_UNCACHED;
 124         }
 125
 126         if (domain & RADEON_GEM_DOMAIN_GTT) {
 127                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 128                         rbo->placements[c].fpfn = 0;
 129                         rbo->placements[c].mem_type = TTM_PL_TT;
 130                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED;
 131
 132                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 133                            (rbo->rdev->flags & RADEON_IS_AGP)) {
 134                         rbo->placements[c].fpfn = 0;
 135                         rbo->placements[c].mem_type = TTM_PL_TT;
 136                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 137                                 TTM_PL_FLAG_UNCACHED;
 138                 } else {
 139                         rbo->placements[c].fpfn = 0;
 140                         rbo->placements[c].mem_type = TTM_PL_TT;
 141                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED;
 142                 }
 143         }
 144
 145         if (domain & RADEON_GEM_DOMAIN_CPU) {
 146                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 147                         rbo->placements[c].fpfn = 0;
 148                         rbo->placements[c].mem_type = TTM_PL_SYSTEM;
 149                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED;
 150
 151                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 152                     rbo->rdev->flags & RADEON_IS_AGP) {
 153                         rbo->placements[c].fpfn = 0;
 154                         rbo->placements[c].mem_type = TTM_PL_SYSTEM;
 155                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 156                                 TTM_PL_FLAG_UNCACHED;
 157                 } else {
 158                         rbo->placements[c].fpfn = 0;
 159                         rbo->placements[c].mem_type = TTM_PL_SYSTEM;
 160                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED;
 161                 }
 162         }
 163         if (!c) {
 164                 rbo->placements[c].fpfn = 0;
 165                 rbo->placements[c].mem_type = TTM_PL_SYSTEM;
 166                 rbo->placements[c++].flags = TTM_PL_MASK_CACHING;
 167         }
 168
 169         rbo->placement.num_placement = c;
 170         rbo->placement.num_busy_placement = c;
 171
 172         for (i = 0; i < c; ++i) {
 173                 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 174                     (rbo->placements[i].mem_type == TTM_PL_VRAM) &&
 175                     !rbo->placements[i].fpfn)
 176                         rbo->placements[i].lpfn =
 177                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 178                 else
 179                         rbo->placements[i].lpfn = 0;
 180         }
 181 }
 182
 183 int radeon_bo_create(struct radeon_device *rdev,
 184                      unsigned long size, int byte_align, bool kernel,
 185                      u32 domain, u32 flags, struct sg_table *sg,
 186                      struct dma_resv *resv,
 187                      struct radeon_bo **bo_ptr)
 188 {
 189         struct radeon_bo *bo;
 190         enum ttm_bo_type type;
 191         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 192         size_t acc_size;
 193         int r;
 194
 195         size = ALIGN(size, PAGE_SIZE);
 196
 197         if (kernel) {
 198                 type = ttm_bo_type_kernel;
 199         } else if (sg) {
 200                 type = ttm_bo_type_sg;
 201         } else {
 202                 type = ttm_bo_type_device;
 203         }
 204         *bo_ptr = NULL;
 205
 206         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 207                                        sizeof(struct radeon_bo));
 208
 209         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 210         if (bo == NULL)
 211                 return -ENOMEM;
 212         drm_gem_private_object_init(rdev->ddev, &bo->tbo.base, size);
 213         bo->rdev = rdev;
 214         bo->surface_reg = -1;
 215         INIT_LIST_HEAD(&bo->list);
 216         INIT_LIST_HEAD(&bo->va);
 217         bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
 218                                        RADEON_GEM_DOMAIN_GTT |
 219                                        RADEON_GEM_DOMAIN_CPU);
 220
 221         bo->flags = flags;
 222         /* PCI GART is always snooped */
 223         if (!(rdev->flags & RADEON_IS_PCIE))
 224                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 225
 226         /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx
 227          * See https://bugs.freedesktop.org/show_bug.cgi?id=91268
 228          */
 229         if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635)
 230                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 231
 232 #ifdef CONFIG_X86_32
 233         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 234          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 235          */
 236         bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 237 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 238         /* Don't try to enable write-combining when it can't work, or things
 239          * may be slow
 240          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 241          */
 242 #ifndef CONFIG_COMPILE_TEST
 243 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 244          thanks to write-combining
 245 #endif
 246
 247         if (bo->flags & RADEON_GEM_GTT_WC)
 248                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 249                               "better performance thanks to write-combining\n");
 250         bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 251 #else
 252         /* For architectures that don't support WC memory,
 253          * mask out the WC flag from the BO
 254          */
 255         if (!drm_arch_can_wc_memory())
 256                 bo->flags &= ~RADEON_GEM_GTT_WC;
 257 #endif
 258
 259         radeon_ttm_placement_from_domain(bo, domain);
 260         /* Kernel allocation are uninterruptible */
 261         down_read(&rdev->pm.mclk_lock);
 262         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 263                         &bo->placement, page_align, !kernel, acc_size,
 264                         sg, resv, &radeon_ttm_bo_destroy);
 265         up_read(&rdev->pm.mclk_lock);
 266         if (unlikely(r != 0)) {
 267                 return r;
 268         }
 269         *bo_ptr = bo;
 270
 271         trace_radeon_bo_create(bo);
 272
 273         return 0;
 274 }
 275
 276 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 277 {
 278         bool is_iomem;
 279         int r;
 280
 281         if (bo->kptr) {
 282                 if (ptr) {
 283                         *ptr = bo->kptr;
 284                 }
 285                 return 0;
 286         }
 287         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 288         if (r) {
 289                 return r;
 290         }
 291         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 292         if (ptr) {
 293                 *ptr = bo->kptr;
 294         }
 295         radeon_bo_check_tiling(bo, 0, 0);
 296         return 0;
 297 }
 298
 299 void radeon_bo_kunmap(struct radeon_bo *bo)
 300 {
 301         if (bo->kptr == NULL)
 302                 return;
 303         bo->kptr = NULL;
 304         radeon_bo_check_tiling(bo, 0, 0);
 305         ttm_bo_kunmap(&bo->kmap);
 306 }
 307
 308 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
 309 {
 310         if (bo == NULL)
 311                 return NULL;
 312
 313         ttm_bo_get(&bo->tbo);
 314         return bo;
 315 }
 316
 317 void radeon_bo_unref(struct radeon_bo **bo)
 318 {
 319         struct ttm_buffer_object *tbo;
 320
 321         if ((*bo) == NULL)
 322                 return;
 323         tbo = &((*bo)->tbo);
 324         ttm_bo_put(tbo);
 325         *bo = NULL;
 326 }
 327
 328 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 329                              u64 *gpu_addr)
 330 {
 331         struct ttm_operation_ctx ctx = { false, false };
 332         int r, i;
 333
 334         if (radeon_ttm_tt_has_userptr(bo->rdev, bo->tbo.ttm))
 335                 return -EPERM;
 336
 337         if (bo->tbo.pin_count) {
 338                 ttm_bo_pin(&bo->tbo);
 339                 if (gpu_addr)
 340                         *gpu_addr = radeon_bo_gpu_offset(bo);
 341
 342                 if (max_offset != 0) {
 343                         u64 domain_start;
 344
 345                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 346                                 domain_start = bo->rdev->mc.vram_start;
 347                         else
 348                                 domain_start = bo->rdev->mc.gtt_start;
 349                         WARN_ON_ONCE(max_offset <
 350                                      (radeon_bo_gpu_offset(bo) - domain_start));
 351                 }
 352
 353                 return 0;
 354         }
 355         if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) {
 356                 /* A BO shared as a dma-buf cannot be sensibly migrated to VRAM */
 357                 return -EINVAL;
 358         }
 359
 360         radeon_ttm_placement_from_domain(bo, domain);
 361         for (i = 0; i < bo->placement.num_placement; i++) {
 362                 /* force to pin into visible video ram */
 363                 if ((bo->placements[i].mem_type == TTM_PL_VRAM) &&
 364                     !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 365                     (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
 366                         bo->placements[i].lpfn =
 367                                 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 368                 else
 369                         bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
 370         }
 371
 372         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 373         if (likely(r == 0)) {
 374                 ttm_bo_pin(&bo->tbo);
 375                 if (gpu_addr != NULL)
 376                         *gpu_addr = radeon_bo_gpu_offset(bo);
 377                 if (domain == RADEON_GEM_DOMAIN_VRAM)
 378                         bo->rdev->vram_pin_size += radeon_bo_size(bo);
 379                 else
 380                         bo->rdev->gart_pin_size += radeon_bo_size(bo);
 381         } else {
 382                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 383         }
 384         return r;
 385 }
 386
 387 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 388 {
 389         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 390 }
 391
 392 void radeon_bo_unpin(struct radeon_bo *bo)
 393 {
 394         ttm_bo_unpin(&bo->tbo);
 395         if (!bo->tbo.pin_count) {
 396                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 397                         bo->rdev->vram_pin_size -= radeon_bo_size(bo);
 398                 else
 399                         bo->rdev->gart_pin_size -= radeon_bo_size(bo);
 400         }
 401 }
 402
 403 int radeon_bo_evict_vram(struct radeon_device *rdev)
 404 {
 405         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 406 #ifndef CONFIG_HIBERNATION
 407         if (rdev->flags & RADEON_IS_IGP) {
 408                 if (rdev->mc.igp_sideport_enabled == false)
 409                         /* Useless to evict on IGP chips */
 410                         return 0;
 411         }
 412 #endif
 413         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 414 }
 415
 416 void radeon_bo_force_delete(struct radeon_device *rdev)
 417 {
 418         struct radeon_bo *bo, *n;
 419
 420         if (list_empty(&rdev->gem.objects)) {
 421                 return;
 422         }
 423         dev_err(rdev->dev, "Userspace still has active objects !\n");
 424         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 425                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 426                         &bo->tbo.base, bo, (unsigned long)bo->tbo.base.size,
 427                         *((unsigned long *)&bo->tbo.base.refcount));
 428                 mutex_lock(&bo->rdev->gem.mutex);
 429                 list_del_init(&bo->list);
 430                 mutex_unlock(&bo->rdev->gem.mutex);
 431                 /* this should unref the ttm bo */
 432                 drm_gem_object_put(&bo->tbo.base);
 433         }
 434 }
 435
 436 int radeon_bo_init(struct radeon_device *rdev)
 437 {
 438         /* reserve PAT memory space to WC for VRAM */
 439         arch_io_reserve_memtype_wc(rdev->mc.aper_base,
 440                                    rdev->mc.aper_size);
 441
 442         /* Add an MTRR for the VRAM */
 443         if (!rdev->fastfb_working) {
 444                 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
 445                                                       rdev->mc.aper_size);
 446         }
 447         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 448                 rdev->mc.mc_vram_size >> 20,
 449                 (unsigned long long)rdev->mc.aper_size >> 20);
 450         DRM_INFO("RAM width %dbits %cDR\n",
 451                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 452         return radeon_ttm_init(rdev);
 453 }
 454
 455 void radeon_bo_fini(struct radeon_device *rdev)
 456 {
 457         radeon_ttm_fini(rdev);
 458         arch_phys_wc_del(rdev->mc.vram_mtrr);
 459         arch_io_free_memtype_wc(rdev->mc.aper_base, rdev->mc.aper_size);
 460 }
 461
 462 /* Returns how many bytes TTM can move per IB.
 463  */
 464 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
 465 {
 466         u64 real_vram_size = rdev->mc.real_vram_size;
 467         u64 vram_usage = atomic64_read(&rdev->vram_usage);
 468
 469         /* This function is based on the current VRAM usage.
 470          *
 471          * - If all of VRAM is free, allow relocating the number of bytes that
 472          *   is equal to 1/4 of the size of VRAM for this IB.
 473
 474          * - If more than one half of VRAM is occupied, only allow relocating
 475          *   1 MB of data for this IB.
 476          *
 477          * - From 0 to one half of used VRAM, the threshold decreases
 478          *   linearly.
 479          *         __________________
 480          * 1/4 of -|\               |
 481          * VRAM    | \              |
 482          *         |  \             |
 483          *         |   \            |
 484          *         |    \           |
 485          *         |     \          |
 486          *         |      \         |
 487          *         |       \________|1 MB
 488          *         |----------------|
 489          *    VRAM 0 %             100 %
 490          *         used            used
 491          *
 492          * Note: It's a threshold, not a limit. The threshold must be crossed
 493          * for buffer relocations to stop, so any buffer of an arbitrary size
 494          * can be moved as long as the threshold isn't crossed before
 495          * the relocation takes place. We don't want to disable buffer
 496          * relocations completely.
 497          *
 498          * The idea is that buffers should be placed in VRAM at creation time
 499          * and TTM should only do a minimum number of relocations during
 500          * command submission. In practice, you need to submit at least
 501          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 502          *
 503          * Also, things can get pretty crazy under memory pressure and actual
 504          * VRAM usage can change a lot, so playing safe even at 50% does
 505          * consistently increase performance.
 506          */
 507
 508         u64 half_vram = real_vram_size >> 1;
 509         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 510         u64 bytes_moved_threshold = half_free_vram >> 1;
 511         return max(bytes_moved_threshold, 1024*1024ull);
 512 }
 513
 514 int radeon_bo_list_validate(struct radeon_device *rdev,
 515                             struct ww_acquire_ctx *ticket,
 516                             struct list_head *head, int ring)
 517 {
 518         struct ttm_operation_ctx ctx = { true, false };
 519         struct radeon_bo_list *lobj;
 520         struct list_head duplicates;
 521         int r;
 522         u64 bytes_moved = 0, initial_bytes_moved;
 523         u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
 524
 525         INIT_LIST_HEAD(&duplicates);
 526         r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates);
 527         if (unlikely(r != 0)) {
 528                 return r;
 529         }
 530
 531         list_for_each_entry(lobj, head, tv.head) {
 532                 struct radeon_bo *bo = lobj->robj;
 533                 if (!bo->tbo.pin_count) {
 534                         u32 domain = lobj->preferred_domains;
 535                         u32 allowed = lobj->allowed_domains;
 536                         u32 current_domain =
 537                                 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
 538
 539                         /* Check if this buffer will be moved and don't move it
 540                          * if we have moved too many buffers for this IB already.
 541                          *
 542                          * Note that this allows moving at least one buffer of
 543                          * any size, because it doesn't take the current "bo"
 544                          * into account. We don't want to disallow buffer moves
 545                          * completely.
 546                          */
 547                         if ((allowed & current_domain) != 0 &&
 548                             (domain & current_domain) == 0 && /* will be moved */
 549                             bytes_moved > bytes_moved_threshold) {
 550                                 /* don't move it */
 551                                 domain = current_domain;
 552                         }
 553
 554                 retry:
 555                         radeon_ttm_placement_from_domain(bo, domain);
 556                         if (ring == R600_RING_TYPE_UVD_INDEX)
 557                                 radeon_uvd_force_into_uvd_segment(bo, allowed);
 558
 559                         initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
 560                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 561                         bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
 562                                        initial_bytes_moved;
 563
 564                         if (unlikely(r)) {
 565                                 if (r != -ERESTARTSYS &&
 566                                     domain != lobj->allowed_domains) {
 567                                         domain = lobj->allowed_domains;
 568                                         goto retry;
 569                                 }
 570                                 ttm_eu_backoff_reservation(ticket, head);
 571                                 return r;
 572                         }
 573                 }
 574                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 575                 lobj->tiling_flags = bo->tiling_flags;
 576         }
 577
 578         list_for_each_entry(lobj, &duplicates, tv.head) {
 579                 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj);
 580                 lobj->tiling_flags = lobj->robj->tiling_flags;
 581         }
 582
 583         return 0;
 584 }
 585
 586 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 587 {
 588         struct radeon_device *rdev = bo->rdev;
 589         struct radeon_surface_reg *reg;
 590         struct radeon_bo *old_object;
 591         int steal;
 592         int i;
 593
 594         dma_resv_assert_held(bo->tbo.base.resv);
 595
 596         if (!bo->tiling_flags)
 597                 return 0;
 598
 599         if (bo->surface_reg >= 0) {
 600                 reg = &rdev->surface_regs[bo->surface_reg];
 601                 i = bo->surface_reg;
 602                 goto out;
 603         }
 604
 605         steal = -1;
 606         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 607
 608                 reg = &rdev->surface_regs[i];
 609                 if (!reg->bo)
 610                         break;
 611
 612                 old_object = reg->bo;
 613                 if (old_object->tbo.pin_count == 0)
 614                         steal = i;
 615         }
 616
 617         /* if we are all out */
 618         if (i == RADEON_GEM_MAX_SURFACES) {
 619                 if (steal == -1)
 620                         return -ENOMEM;
 621                 /* find someone with a surface reg and nuke their BO */
 622                 reg = &rdev->surface_regs[steal];
 623                 old_object = reg->bo;
 624                 /* blow away the mapping */
 625                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 626                 ttm_bo_unmap_virtual(&old_object->tbo);
 627                 old_object->surface_reg = -1;
 628                 i = steal;
 629         }
 630
 631         bo->surface_reg = i;
 632         reg->bo = bo;
 633
 634 out:
 635         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 636                                bo->tbo.mem.start << PAGE_SHIFT,
 637                                bo->tbo.num_pages << PAGE_SHIFT);
 638         return 0;
 639 }
 640
 641 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 642 {
 643         struct radeon_device *rdev = bo->rdev;
 644         struct radeon_surface_reg *reg;
 645
 646         if (bo->surface_reg == -1)
 647                 return;
 648
 649         reg = &rdev->surface_regs[bo->surface_reg];
 650         radeon_clear_surface_reg(rdev, bo->surface_reg);
 651
 652         reg->bo = NULL;
 653         bo->surface_reg = -1;
 654 }
 655
 656 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 657                                 uint32_t tiling_flags, uint32_t pitch)
 658 {
 659         struct radeon_device *rdev = bo->rdev;
 660         int r;
 661
 662         if (rdev->family >= CHIP_CEDAR) {
 663                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 664
 665                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 666                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 667                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 668                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 669                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 670                 switch (bankw) {
 671                 case 0:
 672                 case 1:
 673                 case 2:
 674                 case 4:
 675                 case 8:
 676                         break;
 677                 default:
 678                         return -EINVAL;
 679                 }
 680                 switch (bankh) {
 681                 case 0:
 682                 case 1:
 683                 case 2:
 684                 case 4:
 685                 case 8:
 686                         break;
 687                 default:
 688                         return -EINVAL;
 689                 }
 690                 switch (mtaspect) {
 691                 case 0:
 692                 case 1:
 693                 case 2:
 694                 case 4:
 695                 case 8:
 696                         break;
 697                 default:
 698                         return -EINVAL;
 699                 }
 700                 if (tilesplit > 6) {
 701                         return -EINVAL;
 702                 }
 703                 if (stilesplit > 6) {
 704                         return -EINVAL;
 705                 }
 706         }
 707         r = radeon_bo_reserve(bo, false);
 708         if (unlikely(r != 0))
 709                 return r;
 710         bo->tiling_flags = tiling_flags;
 711         bo->pitch = pitch;
 712         radeon_bo_unreserve(bo);
 713         return 0;
 714 }
 715
 716 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 717                                 uint32_t *tiling_flags,
 718                                 uint32_t *pitch)
 719 {
 720         dma_resv_assert_held(bo->tbo.base.resv);
 721
 722         if (tiling_flags)
 723                 *tiling_flags = bo->tiling_flags;
 724         if (pitch)
 725                 *pitch = bo->pitch;
 726 }
 727
 728 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 729                                 bool force_drop)
 730 {
 731         if (!force_drop)
 732                 dma_resv_assert_held(bo->tbo.base.resv);
 733
 734         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 735                 return 0;
 736
 737         if (force_drop) {
 738                 radeon_bo_clear_surface_reg(bo);
 739                 return 0;
 740         }
 741
 742         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 743                 if (!has_moved)
 744                         return 0;
 745
 746                 if (bo->surface_reg >= 0)
 747                         radeon_bo_clear_surface_reg(bo);
 748                 return 0;
 749         }
 750
 751         if ((bo->surface_reg >= 0) && !has_moved)
 752                 return 0;
 753
 754         return radeon_bo_get_surface_reg(bo);
 755 }
 756
 757 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 758                            bool evict,
 759                            struct ttm_resource *new_mem)
 760 {
 761         struct radeon_bo *rbo;
 762
 763         if (!radeon_ttm_bo_is_radeon_bo(bo))
 764                 return;
 765
 766         rbo = container_of(bo, struct radeon_bo, tbo);
 767         radeon_bo_check_tiling(rbo, 0, 1);
 768         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 769
 770         /* update statistics */
 771         if (!new_mem)
 772                 return;
 773
 774         radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
 775         radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
 776 }
 777
 778 vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 779 {
 780         struct ttm_operation_ctx ctx = { false, false };
 781         struct radeon_device *rdev;
 782         struct radeon_bo *rbo;
 783         unsigned long offset, size, lpfn;
 784         int i, r;
 785
 786         if (!radeon_ttm_bo_is_radeon_bo(bo))
 787                 return 0;
 788         rbo = container_of(bo, struct radeon_bo, tbo);
 789         radeon_bo_check_tiling(rbo, 0, 0);
 790         rdev = rbo->rdev;
 791         if (bo->mem.mem_type != TTM_PL_VRAM)
 792                 return 0;
 793
 794         size = bo->mem.num_pages << PAGE_SHIFT;
 795         offset = bo->mem.start << PAGE_SHIFT;
 796         if ((offset + size) <= rdev->mc.visible_vram_size)
 797                 return 0;
 798
 799         /* Can't move a pinned BO to visible VRAM */
 800         if (rbo->tbo.pin_count > 0)
 801                 return VM_FAULT_SIGBUS;
 802
 803         /* hurrah the memory is not visible ! */
 804         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 805         lpfn =  rdev->mc.visible_vram_size >> PAGE_SHIFT;
 806         for (i = 0; i < rbo->placement.num_placement; i++) {
 807                 /* Force into visible VRAM */
 808                 if ((rbo->placements[i].mem_type == TTM_PL_VRAM) &&
 809                     (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
 810                         rbo->placements[i].lpfn = lpfn;
 811         }
 812         r = ttm_bo_validate(bo, &rbo->placement, &ctx);
 813         if (unlikely(r == -ENOMEM)) {
 814                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 815                 r = ttm_bo_validate(bo, &rbo->placement, &ctx);
 816         } else if (likely(!r)) {
 817                 offset = bo->mem.start << PAGE_SHIFT;
 818                 /* this should never happen */
 819                 if ((offset + size) > rdev->mc.visible_vram_size)
 820                         return VM_FAULT_SIGBUS;
 821         }
 822
 823         if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
 824                 return VM_FAULT_NOPAGE;
 825         else if (unlikely(r))
 826                 return VM_FAULT_SIGBUS;
 827
 828         ttm_bo_move_to_lru_tail_unlocked(bo);
 829         return 0;
 830 }
 831
 832 /**
 833  * radeon_bo_fence - add fence to buffer object
 834  *
 835  * @bo: buffer object in question
 836  * @fence: fence to add
 837  * @shared: true if fence should be added shared
 838  *
 839  */
 840 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
 841                      bool shared)
 842 {
 843         struct dma_resv *resv = bo->tbo.base.resv;
 844
 845         if (shared)
 846                 dma_resv_add_shared_fence(resv, &fence->base);
 847         else
 848                 dma_resv_add_excl_fence(resv, &fence->base);
 849 }