2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/pm_runtime.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/vga_switcheroo.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_file.h>
36 #include <drm/drm_ioctl.h>
37 #include <drm/drm_pci.h>
38 #include <drm/radeon_drm.h>
41 #include "radeon_asic.h"
43 #if defined(CONFIG_VGA_SWITCHEROO)
44 bool radeon_has_atpx(void);
46 static inline bool radeon_has_atpx(void) { return false; }
50 * radeon_driver_unload_kms - Main unload function for KMS.
52 * @dev: drm dev pointer
54 * This is the main unload function for KMS (all asics).
55 * It calls radeon_modeset_fini() to tear down the
56 * displays, and radeon_device_fini() to tear down
57 * the rest of the device (CP, writeback, etc.).
58 * Returns 0 on success.
60 void radeon_driver_unload_kms(struct drm_device *dev)
62 struct radeon_device *rdev = dev->dev_private;
67 if (rdev->rmmio == NULL)
70 if (radeon_is_px(dev)) {
71 pm_runtime_get_sync(dev->dev);
72 pm_runtime_forbid(dev->dev);
75 radeon_acpi_fini(rdev);
77 radeon_modeset_fini(rdev);
78 radeon_device_fini(rdev);
82 dev->dev_private = NULL;
86 * radeon_driver_load_kms - Main load function for KMS.
88 * @dev: drm dev pointer
89 * @flags: device flags
91 * This is the main load function for KMS (all asics).
92 * It calls radeon_device_init() to set up the non-display
93 * parts of the chip (asic init, CP, writeback, etc.), and
94 * radeon_modeset_init() to set up the display parts
95 * (crtcs, encoders, hotplug detect, etc.).
96 * Returns 0 on success, error on failure.
98 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
100 struct radeon_device *rdev;
103 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
107 dev->dev_private = (void *)rdev;
109 /* update BUS flag */
110 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) {
111 flags |= RADEON_IS_AGP;
112 } else if (pci_is_pcie(dev->pdev)) {
113 flags |= RADEON_IS_PCIE;
115 flags |= RADEON_IS_PCI;
118 if ((radeon_runtime_pm != 0) &&
120 ((flags & RADEON_IS_IGP) == 0) &&
121 !pci_is_thunderbolt_attached(dev->pdev))
122 flags |= RADEON_IS_PX;
124 /* radeon_device_init should report only fatal error
125 * like memory allocation failure or iomapping failure,
126 * or memory manager initialization failure, it must
127 * properly initialize the GPU MC controller and permit
130 r = radeon_device_init(rdev, dev, dev->pdev, flags);
132 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
136 /* Again modeset_init should fail only on fatal error
137 * otherwise it should provide enough functionalities
138 * for shadowfb to run
140 r = radeon_modeset_init(rdev);
142 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
144 /* Call ACPI methods: require modeset init
145 * but failure is not fatal
148 acpi_status = radeon_acpi_init(rdev);
150 dev_dbg(&dev->pdev->dev,
151 "Error during ACPI methods call\n");
154 if (radeon_is_px(dev)) {
155 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
156 pm_runtime_use_autosuspend(dev->dev);
157 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
158 pm_runtime_set_active(dev->dev);
159 pm_runtime_allow(dev->dev);
160 pm_runtime_mark_last_busy(dev->dev);
161 pm_runtime_put_autosuspend(dev->dev);
166 radeon_driver_unload_kms(dev);
173 * radeon_set_filp_rights - Set filp right.
175 * @dev: drm dev pointer
180 * Sets the filp rights for the device (all asics).
182 static void radeon_set_filp_rights(struct drm_device *dev,
183 struct drm_file **owner,
184 struct drm_file *applier,
187 struct radeon_device *rdev = dev->dev_private;
189 mutex_lock(&rdev->gem.mutex);
194 } else if (*value == 0) {
196 if (*owner == applier)
199 *value = *owner == applier ? 1 : 0;
200 mutex_unlock(&rdev->gem.mutex);
204 * Userspace get information ioctl
207 * radeon_info_ioctl - answer a device specific request.
209 * @rdev: radeon device pointer
210 * @data: request object
213 * This function is used to pass device specific parameters to the userspace
214 * drivers. Examples include: pci device id, pipeline parms, tiling params,
216 * Returns 0 on success, -EINVAL on failure.
218 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
220 struct radeon_device *rdev = dev->dev_private;
221 struct drm_radeon_info *info = data;
222 struct radeon_mode_info *minfo = &rdev->mode_info;
223 uint32_t *value, value_tmp, *value_ptr, value_size;
225 struct drm_crtc *crtc;
228 value_ptr = (uint32_t *)((unsigned long)info->value);
230 value_size = sizeof(uint32_t);
232 switch (info->request) {
233 case RADEON_INFO_DEVICE_ID:
234 *value = dev->pdev->device;
236 case RADEON_INFO_NUM_GB_PIPES:
237 *value = rdev->num_gb_pipes;
239 case RADEON_INFO_NUM_Z_PIPES:
240 *value = rdev->num_z_pipes;
242 case RADEON_INFO_ACCEL_WORKING:
243 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
244 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
247 *value = rdev->accel_working;
249 case RADEON_INFO_CRTC_FROM_ID:
250 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
251 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
254 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
255 crtc = (struct drm_crtc *)minfo->crtcs[i];
256 if (crtc && crtc->base.id == *value) {
257 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
258 *value = radeon_crtc->crtc_id;
264 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
268 case RADEON_INFO_ACCEL_WORKING2:
269 if (rdev->family == CHIP_HAWAII) {
270 if (rdev->accel_working) {
279 *value = rdev->accel_working;
282 case RADEON_INFO_TILING_CONFIG:
283 if (rdev->family >= CHIP_BONAIRE)
284 *value = rdev->config.cik.tile_config;
285 else if (rdev->family >= CHIP_TAHITI)
286 *value = rdev->config.si.tile_config;
287 else if (rdev->family >= CHIP_CAYMAN)
288 *value = rdev->config.cayman.tile_config;
289 else if (rdev->family >= CHIP_CEDAR)
290 *value = rdev->config.evergreen.tile_config;
291 else if (rdev->family >= CHIP_RV770)
292 *value = rdev->config.rv770.tile_config;
293 else if (rdev->family >= CHIP_R600)
294 *value = rdev->config.r600.tile_config;
296 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
300 case RADEON_INFO_WANT_HYPERZ:
301 /* The "value" here is both an input and output parameter.
302 * If the input value is 1, filp requests hyper-z access.
303 * If the input value is 0, filp revokes its hyper-z access.
305 * When returning, the value is 1 if filp owns hyper-z access,
307 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
308 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
312 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
315 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
317 case RADEON_INFO_WANT_CMASK:
318 /* The same logic as Hyper-Z. */
319 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
320 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
324 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
327 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
329 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
330 /* return clock value in KHz */
331 if (rdev->asic->get_xclk)
332 *value = radeon_get_xclk(rdev) * 10;
334 *value = rdev->clock.spll.reference_freq * 10;
336 case RADEON_INFO_NUM_BACKENDS:
337 if (rdev->family >= CHIP_BONAIRE)
338 *value = rdev->config.cik.max_backends_per_se *
339 rdev->config.cik.max_shader_engines;
340 else if (rdev->family >= CHIP_TAHITI)
341 *value = rdev->config.si.max_backends_per_se *
342 rdev->config.si.max_shader_engines;
343 else if (rdev->family >= CHIP_CAYMAN)
344 *value = rdev->config.cayman.max_backends_per_se *
345 rdev->config.cayman.max_shader_engines;
346 else if (rdev->family >= CHIP_CEDAR)
347 *value = rdev->config.evergreen.max_backends;
348 else if (rdev->family >= CHIP_RV770)
349 *value = rdev->config.rv770.max_backends;
350 else if (rdev->family >= CHIP_R600)
351 *value = rdev->config.r600.max_backends;
356 case RADEON_INFO_NUM_TILE_PIPES:
357 if (rdev->family >= CHIP_BONAIRE)
358 *value = rdev->config.cik.max_tile_pipes;
359 else if (rdev->family >= CHIP_TAHITI)
360 *value = rdev->config.si.max_tile_pipes;
361 else if (rdev->family >= CHIP_CAYMAN)
362 *value = rdev->config.cayman.max_tile_pipes;
363 else if (rdev->family >= CHIP_CEDAR)
364 *value = rdev->config.evergreen.max_tile_pipes;
365 else if (rdev->family >= CHIP_RV770)
366 *value = rdev->config.rv770.max_tile_pipes;
367 else if (rdev->family >= CHIP_R600)
368 *value = rdev->config.r600.max_tile_pipes;
373 case RADEON_INFO_FUSION_GART_WORKING:
376 case RADEON_INFO_BACKEND_MAP:
377 if (rdev->family >= CHIP_BONAIRE)
378 *value = rdev->config.cik.backend_map;
379 else if (rdev->family >= CHIP_TAHITI)
380 *value = rdev->config.si.backend_map;
381 else if (rdev->family >= CHIP_CAYMAN)
382 *value = rdev->config.cayman.backend_map;
383 else if (rdev->family >= CHIP_CEDAR)
384 *value = rdev->config.evergreen.backend_map;
385 else if (rdev->family >= CHIP_RV770)
386 *value = rdev->config.rv770.backend_map;
387 else if (rdev->family >= CHIP_R600)
388 *value = rdev->config.r600.backend_map;
393 case RADEON_INFO_VA_START:
394 /* this is where we report if vm is supported or not */
395 if (rdev->family < CHIP_CAYMAN)
397 *value = RADEON_VA_RESERVED_SIZE;
399 case RADEON_INFO_IB_VM_MAX_SIZE:
400 /* this is where we report if vm is supported or not */
401 if (rdev->family < CHIP_CAYMAN)
403 *value = RADEON_IB_VM_MAX_SIZE;
405 case RADEON_INFO_MAX_PIPES:
406 if (rdev->family >= CHIP_BONAIRE)
407 *value = rdev->config.cik.max_cu_per_sh;
408 else if (rdev->family >= CHIP_TAHITI)
409 *value = rdev->config.si.max_cu_per_sh;
410 else if (rdev->family >= CHIP_CAYMAN)
411 *value = rdev->config.cayman.max_pipes_per_simd;
412 else if (rdev->family >= CHIP_CEDAR)
413 *value = rdev->config.evergreen.max_pipes;
414 else if (rdev->family >= CHIP_RV770)
415 *value = rdev->config.rv770.max_pipes;
416 else if (rdev->family >= CHIP_R600)
417 *value = rdev->config.r600.max_pipes;
422 case RADEON_INFO_TIMESTAMP:
423 if (rdev->family < CHIP_R600) {
424 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
427 value = (uint32_t*)&value64;
428 value_size = sizeof(uint64_t);
429 value64 = radeon_get_gpu_clock_counter(rdev);
431 case RADEON_INFO_MAX_SE:
432 if (rdev->family >= CHIP_BONAIRE)
433 *value = rdev->config.cik.max_shader_engines;
434 else if (rdev->family >= CHIP_TAHITI)
435 *value = rdev->config.si.max_shader_engines;
436 else if (rdev->family >= CHIP_CAYMAN)
437 *value = rdev->config.cayman.max_shader_engines;
438 else if (rdev->family >= CHIP_CEDAR)
439 *value = rdev->config.evergreen.num_ses;
443 case RADEON_INFO_MAX_SH_PER_SE:
444 if (rdev->family >= CHIP_BONAIRE)
445 *value = rdev->config.cik.max_sh_per_se;
446 else if (rdev->family >= CHIP_TAHITI)
447 *value = rdev->config.si.max_sh_per_se;
451 case RADEON_INFO_FASTFB_WORKING:
452 *value = rdev->fastfb_working;
454 case RADEON_INFO_RING_WORKING:
455 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
456 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
460 case RADEON_CS_RING_GFX:
461 case RADEON_CS_RING_COMPUTE:
462 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
464 case RADEON_CS_RING_DMA:
465 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
466 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
468 case RADEON_CS_RING_UVD:
469 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
471 case RADEON_CS_RING_VCE:
472 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
478 case RADEON_INFO_SI_TILE_MODE_ARRAY:
479 if (rdev->family >= CHIP_BONAIRE) {
480 value = rdev->config.cik.tile_mode_array;
481 value_size = sizeof(uint32_t)*32;
482 } else if (rdev->family >= CHIP_TAHITI) {
483 value = rdev->config.si.tile_mode_array;
484 value_size = sizeof(uint32_t)*32;
486 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
490 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
491 if (rdev->family >= CHIP_BONAIRE) {
492 value = rdev->config.cik.macrotile_mode_array;
493 value_size = sizeof(uint32_t)*16;
495 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
499 case RADEON_INFO_SI_CP_DMA_COMPUTE:
502 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
503 if (rdev->family >= CHIP_BONAIRE) {
504 *value = rdev->config.cik.backend_enable_mask;
505 } else if (rdev->family >= CHIP_TAHITI) {
506 *value = rdev->config.si.backend_enable_mask;
508 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
511 case RADEON_INFO_MAX_SCLK:
512 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
513 rdev->pm.dpm_enabled)
514 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
516 *value = rdev->pm.default_sclk * 10;
518 case RADEON_INFO_VCE_FW_VERSION:
519 *value = rdev->vce.fw_version;
521 case RADEON_INFO_VCE_FB_VERSION:
522 *value = rdev->vce.fb_version;
524 case RADEON_INFO_NUM_BYTES_MOVED:
525 value = (uint32_t*)&value64;
526 value_size = sizeof(uint64_t);
527 value64 = atomic64_read(&rdev->num_bytes_moved);
529 case RADEON_INFO_VRAM_USAGE:
530 value = (uint32_t*)&value64;
531 value_size = sizeof(uint64_t);
532 value64 = atomic64_read(&rdev->vram_usage);
534 case RADEON_INFO_GTT_USAGE:
535 value = (uint32_t*)&value64;
536 value_size = sizeof(uint64_t);
537 value64 = atomic64_read(&rdev->gtt_usage);
539 case RADEON_INFO_ACTIVE_CU_COUNT:
540 if (rdev->family >= CHIP_BONAIRE)
541 *value = rdev->config.cik.active_cus;
542 else if (rdev->family >= CHIP_TAHITI)
543 *value = rdev->config.si.active_cus;
544 else if (rdev->family >= CHIP_CAYMAN)
545 *value = rdev->config.cayman.active_simds;
546 else if (rdev->family >= CHIP_CEDAR)
547 *value = rdev->config.evergreen.active_simds;
548 else if (rdev->family >= CHIP_RV770)
549 *value = rdev->config.rv770.active_simds;
550 else if (rdev->family >= CHIP_R600)
551 *value = rdev->config.r600.active_simds;
555 case RADEON_INFO_CURRENT_GPU_TEMP:
556 /* get temperature in millidegrees C */
557 if (rdev->asic->pm.get_temperature)
558 *value = radeon_get_temperature(rdev);
562 case RADEON_INFO_CURRENT_GPU_SCLK:
563 /* get sclk in Mhz */
564 if (rdev->pm.dpm_enabled)
565 *value = radeon_dpm_get_current_sclk(rdev) / 100;
567 *value = rdev->pm.current_sclk / 100;
569 case RADEON_INFO_CURRENT_GPU_MCLK:
570 /* get mclk in Mhz */
571 if (rdev->pm.dpm_enabled)
572 *value = radeon_dpm_get_current_mclk(rdev) / 100;
574 *value = rdev->pm.current_mclk / 100;
576 case RADEON_INFO_READ_REG:
577 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
578 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
581 if (radeon_get_allowed_info_register(rdev, *value, value))
584 case RADEON_INFO_VA_UNMAP_WORKING:
587 case RADEON_INFO_GPU_RESET_COUNTER:
588 *value = atomic_read(&rdev->gpu_reset_counter);
591 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
594 if (copy_to_user(value_ptr, (char*)value, value_size)) {
595 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
603 * Outdated mess for old drm with Xorg being in charge (void function now).
606 * radeon_driver_lastclose_kms - drm callback for last close
608 * @dev: drm dev pointer
610 * Switch vga_switcheroo state after last close (all asics).
612 void radeon_driver_lastclose_kms(struct drm_device *dev)
614 drm_fb_helper_lastclose(dev);
615 vga_switcheroo_process_delayed_switch();
619 * radeon_driver_open_kms - drm callback for open
621 * @dev: drm dev pointer
622 * @file_priv: drm file
624 * On device open, init vm on cayman+ (all asics).
625 * Returns 0 on success, error on failure.
627 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
629 struct radeon_device *rdev = dev->dev_private;
632 file_priv->driver_priv = NULL;
634 r = pm_runtime_get_sync(dev->dev);
638 /* new gpu have virtual address space support */
639 if (rdev->family >= CHIP_CAYMAN) {
640 struct radeon_fpriv *fpriv;
641 struct radeon_vm *vm;
643 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
644 if (unlikely(!fpriv)) {
649 if (rdev->accel_working) {
651 r = radeon_vm_init(rdev, vm);
657 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
659 radeon_vm_fini(rdev, vm);
664 /* map the ib pool buffer read only into
665 * virtual address space */
666 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
667 rdev->ring_tmp_bo.bo);
668 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
670 RADEON_VM_PAGE_READABLE |
671 RADEON_VM_PAGE_SNOOPED);
673 radeon_vm_fini(rdev, vm);
678 file_priv->driver_priv = fpriv;
682 pm_runtime_mark_last_busy(dev->dev);
683 pm_runtime_put_autosuspend(dev->dev);
688 * radeon_driver_postclose_kms - drm callback for post close
690 * @dev: drm dev pointer
691 * @file_priv: drm file
693 * On device close, tear down hyperz and cmask filps on r1xx-r5xx
694 * (all asics). And tear down vm on cayman+ (all asics).
696 void radeon_driver_postclose_kms(struct drm_device *dev,
697 struct drm_file *file_priv)
699 struct radeon_device *rdev = dev->dev_private;
701 pm_runtime_get_sync(dev->dev);
703 mutex_lock(&rdev->gem.mutex);
704 if (rdev->hyperz_filp == file_priv)
705 rdev->hyperz_filp = NULL;
706 if (rdev->cmask_filp == file_priv)
707 rdev->cmask_filp = NULL;
708 mutex_unlock(&rdev->gem.mutex);
710 radeon_uvd_free_handles(rdev, file_priv);
711 radeon_vce_free_handles(rdev, file_priv);
713 /* new gpu have virtual address space support */
714 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
715 struct radeon_fpriv *fpriv = file_priv->driver_priv;
716 struct radeon_vm *vm = &fpriv->vm;
719 if (rdev->accel_working) {
720 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
723 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
724 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
726 radeon_vm_fini(rdev, vm);
730 file_priv->driver_priv = NULL;
732 pm_runtime_mark_last_busy(dev->dev);
733 pm_runtime_put_autosuspend(dev->dev);
737 * VBlank related functions.
740 * radeon_get_vblank_counter_kms - get frame count
742 * @dev: drm dev pointer
743 * @pipe: crtc to get the frame count from
745 * Gets the frame count on the requested crtc (all asics).
746 * Returns frame count on success, -EINVAL on failure.
748 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
750 int vpos, hpos, stat;
752 struct radeon_device *rdev = dev->dev_private;
754 if (pipe >= rdev->num_crtc) {
755 DRM_ERROR("Invalid crtc %u\n", pipe);
759 /* The hw increments its frame counter at start of vsync, not at start
760 * of vblank, as is required by DRM core vblank counter handling.
761 * Cook the hw count here to make it appear to the caller as if it
762 * incremented at start of vblank. We measure distance to start of
763 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
764 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
765 * result by 1 to give the proper appearance to caller.
767 if (rdev->mode_info.crtcs[pipe]) {
768 /* Repeat readout if needed to provide stable result if
769 * we cross start of vsync during the queries.
772 count = radeon_get_vblank_counter(rdev, pipe);
773 /* Ask radeon_get_crtc_scanoutpos to return vpos as
774 * distance to start of vblank, instead of regular
775 * vertical scanout pos.
777 stat = radeon_get_crtc_scanoutpos(
778 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
779 &vpos, &hpos, NULL, NULL,
780 &rdev->mode_info.crtcs[pipe]->base.hwmode);
781 } while (count != radeon_get_vblank_counter(rdev, pipe));
783 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
784 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
785 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
788 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
791 /* Bump counter if we are at >= leading edge of vblank,
792 * but before vsync where vpos would turn negative and
793 * the hw counter really increments.
800 /* Fallback to use value as is. */
801 count = radeon_get_vblank_counter(rdev, pipe);
802 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
809 * radeon_enable_vblank_kms - enable vblank interrupt
811 * @dev: drm dev pointer
812 * @crtc: crtc to enable vblank interrupt for
814 * Enable the interrupt on the requested crtc (all asics).
815 * Returns 0 on success, -EINVAL on failure.
817 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
819 struct radeon_device *rdev = dev->dev_private;
820 unsigned long irqflags;
823 if (crtc < 0 || crtc >= rdev->num_crtc) {
824 DRM_ERROR("Invalid crtc %d\n", crtc);
828 spin_lock_irqsave(&rdev->irq.lock, irqflags);
829 rdev->irq.crtc_vblank_int[crtc] = true;
830 r = radeon_irq_set(rdev);
831 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
836 * radeon_disable_vblank_kms - disable vblank interrupt
838 * @dev: drm dev pointer
839 * @crtc: crtc to disable vblank interrupt for
841 * Disable the interrupt on the requested crtc (all asics).
843 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
845 struct radeon_device *rdev = dev->dev_private;
846 unsigned long irqflags;
848 if (crtc < 0 || crtc >= rdev->num_crtc) {
849 DRM_ERROR("Invalid crtc %d\n", crtc);
853 spin_lock_irqsave(&rdev->irq.lock, irqflags);
854 rdev->irq.crtc_vblank_int[crtc] = false;
855 radeon_irq_set(rdev);
856 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
859 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
860 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
861 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
862 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
863 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
864 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
865 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
866 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
867 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
868 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
869 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
870 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
871 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
872 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
873 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
874 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
875 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
876 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
877 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
878 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
879 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
880 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
881 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
882 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
883 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
884 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
885 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
886 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
888 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
889 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
890 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
891 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
892 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
893 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
894 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
895 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
896 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
897 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
898 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
899 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
900 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
901 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
902 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
904 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);