2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/radeon_drm.h>
31 #include "radeon_asic.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
35 #include <linux/pm_runtime.h>
37 #if defined(CONFIG_VGA_SWITCHEROO)
38 bool radeon_has_atpx(void);
40 static inline bool radeon_has_atpx(void) { return false; }
44 * radeon_driver_unload_kms - Main unload function for KMS.
46 * @dev: drm dev pointer
48 * This is the main unload function for KMS (all asics).
49 * It calls radeon_modeset_fini() to tear down the
50 * displays, and radeon_device_fini() to tear down
51 * the rest of the device (CP, writeback, etc.).
52 * Returns 0 on success.
54 int radeon_driver_unload_kms(struct drm_device *dev)
56 struct radeon_device *rdev = dev->dev_private;
61 if (rdev->rmmio == NULL)
64 pm_runtime_get_sync(dev->dev);
66 radeon_acpi_fini(rdev);
68 radeon_modeset_fini(rdev);
69 radeon_device_fini(rdev);
73 dev->dev_private = NULL;
78 * radeon_driver_load_kms - Main load function for KMS.
80 * @dev: drm dev pointer
81 * @flags: device flags
83 * This is the main load function for KMS (all asics).
84 * It calls radeon_device_init() to set up the non-display
85 * parts of the chip (asic init, CP, writeback, etc.), and
86 * radeon_modeset_init() to set up the display parts
87 * (crtcs, encoders, hotplug detect, etc.).
88 * Returns 0 on success, error on failure.
90 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
92 struct radeon_device *rdev;
95 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
99 dev->dev_private = (void *)rdev;
101 /* update BUS flag */
102 if (drm_pci_device_is_agp(dev)) {
103 flags |= RADEON_IS_AGP;
104 } else if (pci_is_pcie(dev->pdev)) {
105 flags |= RADEON_IS_PCIE;
107 flags |= RADEON_IS_PCI;
110 if (radeon_runtime_pm == 1)
111 flags |= RADEON_IS_PX;
112 else if ((radeon_runtime_pm == -1) &&
114 ((flags & RADEON_IS_IGP) == 0))
115 flags |= RADEON_IS_PX;
117 /* radeon_device_init should report only fatal error
118 * like memory allocation failure or iomapping failure,
119 * or memory manager initialization failure, it must
120 * properly initialize the GPU MC controller and permit
123 r = radeon_device_init(rdev, dev, dev->pdev, flags);
125 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
129 /* Again modeset_init should fail only on fatal error
130 * otherwise it should provide enough functionalities
131 * for shadowfb to run
133 r = radeon_modeset_init(rdev);
135 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
137 /* Call ACPI methods: require modeset init
138 * but failure is not fatal
141 acpi_status = radeon_acpi_init(rdev);
143 dev_dbg(&dev->pdev->dev,
144 "Error during ACPI methods call\n");
147 if (radeon_is_px(dev)) {
148 pm_runtime_use_autosuspend(dev->dev);
149 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
150 pm_runtime_set_active(dev->dev);
151 pm_runtime_allow(dev->dev);
152 pm_runtime_mark_last_busy(dev->dev);
153 pm_runtime_put_autosuspend(dev->dev);
158 radeon_driver_unload_kms(dev);
165 * radeon_set_filp_rights - Set filp right.
167 * @dev: drm dev pointer
172 * Sets the filp rights for the device (all asics).
174 static void radeon_set_filp_rights(struct drm_device *dev,
175 struct drm_file **owner,
176 struct drm_file *applier,
179 mutex_lock(&dev->struct_mutex);
184 } else if (*value == 0) {
186 if (*owner == applier)
189 *value = *owner == applier ? 1 : 0;
190 mutex_unlock(&dev->struct_mutex);
194 * Userspace get information ioctl
197 * radeon_info_ioctl - answer a device specific request.
199 * @rdev: radeon device pointer
200 * @data: request object
203 * This function is used to pass device specific parameters to the userspace
204 * drivers. Examples include: pci device id, pipeline parms, tiling params,
206 * Returns 0 on success, -EINVAL on failure.
208 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
210 struct radeon_device *rdev = dev->dev_private;
211 struct drm_radeon_info *info = data;
212 struct radeon_mode_info *minfo = &rdev->mode_info;
213 uint32_t *value, value_tmp, *value_ptr, value_size;
215 struct drm_crtc *crtc;
218 value_ptr = (uint32_t *)((unsigned long)info->value);
220 value_size = sizeof(uint32_t);
222 switch (info->request) {
223 case RADEON_INFO_DEVICE_ID:
224 *value = dev->pdev->device;
226 case RADEON_INFO_NUM_GB_PIPES:
227 *value = rdev->num_gb_pipes;
229 case RADEON_INFO_NUM_Z_PIPES:
230 *value = rdev->num_z_pipes;
232 case RADEON_INFO_ACCEL_WORKING:
233 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
234 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
237 *value = rdev->accel_working;
239 case RADEON_INFO_CRTC_FROM_ID:
240 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
241 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
244 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
245 crtc = (struct drm_crtc *)minfo->crtcs[i];
246 if (crtc && crtc->base.id == *value) {
247 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
248 *value = radeon_crtc->crtc_id;
254 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
258 case RADEON_INFO_ACCEL_WORKING2:
259 *value = rdev->accel_working;
261 case RADEON_INFO_TILING_CONFIG:
262 if (rdev->family >= CHIP_BONAIRE)
263 *value = rdev->config.cik.tile_config;
264 else if (rdev->family >= CHIP_TAHITI)
265 *value = rdev->config.si.tile_config;
266 else if (rdev->family >= CHIP_CAYMAN)
267 *value = rdev->config.cayman.tile_config;
268 else if (rdev->family >= CHIP_CEDAR)
269 *value = rdev->config.evergreen.tile_config;
270 else if (rdev->family >= CHIP_RV770)
271 *value = rdev->config.rv770.tile_config;
272 else if (rdev->family >= CHIP_R600)
273 *value = rdev->config.r600.tile_config;
275 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
279 case RADEON_INFO_WANT_HYPERZ:
280 /* The "value" here is both an input and output parameter.
281 * If the input value is 1, filp requests hyper-z access.
282 * If the input value is 0, filp revokes its hyper-z access.
284 * When returning, the value is 1 if filp owns hyper-z access,
286 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
287 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
291 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
294 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
296 case RADEON_INFO_WANT_CMASK:
297 /* The same logic as Hyper-Z. */
298 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
299 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
303 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
306 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
308 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
309 /* return clock value in KHz */
310 if (rdev->asic->get_xclk)
311 *value = radeon_get_xclk(rdev) * 10;
313 *value = rdev->clock.spll.reference_freq * 10;
315 case RADEON_INFO_NUM_BACKENDS:
316 if (rdev->family >= CHIP_BONAIRE)
317 *value = rdev->config.cik.max_backends_per_se *
318 rdev->config.cik.max_shader_engines;
319 else if (rdev->family >= CHIP_TAHITI)
320 *value = rdev->config.si.max_backends_per_se *
321 rdev->config.si.max_shader_engines;
322 else if (rdev->family >= CHIP_CAYMAN)
323 *value = rdev->config.cayman.max_backends_per_se *
324 rdev->config.cayman.max_shader_engines;
325 else if (rdev->family >= CHIP_CEDAR)
326 *value = rdev->config.evergreen.max_backends;
327 else if (rdev->family >= CHIP_RV770)
328 *value = rdev->config.rv770.max_backends;
329 else if (rdev->family >= CHIP_R600)
330 *value = rdev->config.r600.max_backends;
335 case RADEON_INFO_NUM_TILE_PIPES:
336 if (rdev->family >= CHIP_BONAIRE)
337 *value = rdev->config.cik.max_tile_pipes;
338 else if (rdev->family >= CHIP_TAHITI)
339 *value = rdev->config.si.max_tile_pipes;
340 else if (rdev->family >= CHIP_CAYMAN)
341 *value = rdev->config.cayman.max_tile_pipes;
342 else if (rdev->family >= CHIP_CEDAR)
343 *value = rdev->config.evergreen.max_tile_pipes;
344 else if (rdev->family >= CHIP_RV770)
345 *value = rdev->config.rv770.max_tile_pipes;
346 else if (rdev->family >= CHIP_R600)
347 *value = rdev->config.r600.max_tile_pipes;
352 case RADEON_INFO_FUSION_GART_WORKING:
355 case RADEON_INFO_BACKEND_MAP:
356 if (rdev->family >= CHIP_BONAIRE)
357 *value = rdev->config.cik.backend_map;
358 else if (rdev->family >= CHIP_TAHITI)
359 *value = rdev->config.si.backend_map;
360 else if (rdev->family >= CHIP_CAYMAN)
361 *value = rdev->config.cayman.backend_map;
362 else if (rdev->family >= CHIP_CEDAR)
363 *value = rdev->config.evergreen.backend_map;
364 else if (rdev->family >= CHIP_RV770)
365 *value = rdev->config.rv770.backend_map;
366 else if (rdev->family >= CHIP_R600)
367 *value = rdev->config.r600.backend_map;
372 case RADEON_INFO_VA_START:
373 /* this is where we report if vm is supported or not */
374 if (rdev->family < CHIP_CAYMAN)
376 *value = RADEON_VA_RESERVED_SIZE;
378 case RADEON_INFO_IB_VM_MAX_SIZE:
379 /* this is where we report if vm is supported or not */
380 if (rdev->family < CHIP_CAYMAN)
382 *value = RADEON_IB_VM_MAX_SIZE;
384 case RADEON_INFO_MAX_PIPES:
385 if (rdev->family >= CHIP_BONAIRE)
386 *value = rdev->config.cik.max_cu_per_sh;
387 else if (rdev->family >= CHIP_TAHITI)
388 *value = rdev->config.si.max_cu_per_sh;
389 else if (rdev->family >= CHIP_CAYMAN)
390 *value = rdev->config.cayman.max_pipes_per_simd;
391 else if (rdev->family >= CHIP_CEDAR)
392 *value = rdev->config.evergreen.max_pipes;
393 else if (rdev->family >= CHIP_RV770)
394 *value = rdev->config.rv770.max_pipes;
395 else if (rdev->family >= CHIP_R600)
396 *value = rdev->config.r600.max_pipes;
401 case RADEON_INFO_TIMESTAMP:
402 if (rdev->family < CHIP_R600) {
403 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
406 value = (uint32_t*)&value64;
407 value_size = sizeof(uint64_t);
408 value64 = radeon_get_gpu_clock_counter(rdev);
410 case RADEON_INFO_MAX_SE:
411 if (rdev->family >= CHIP_BONAIRE)
412 *value = rdev->config.cik.max_shader_engines;
413 else if (rdev->family >= CHIP_TAHITI)
414 *value = rdev->config.si.max_shader_engines;
415 else if (rdev->family >= CHIP_CAYMAN)
416 *value = rdev->config.cayman.max_shader_engines;
417 else if (rdev->family >= CHIP_CEDAR)
418 *value = rdev->config.evergreen.num_ses;
422 case RADEON_INFO_MAX_SH_PER_SE:
423 if (rdev->family >= CHIP_BONAIRE)
424 *value = rdev->config.cik.max_sh_per_se;
425 else if (rdev->family >= CHIP_TAHITI)
426 *value = rdev->config.si.max_sh_per_se;
430 case RADEON_INFO_FASTFB_WORKING:
431 *value = rdev->fastfb_working;
433 case RADEON_INFO_RING_WORKING:
434 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
435 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
439 case RADEON_CS_RING_GFX:
440 case RADEON_CS_RING_COMPUTE:
441 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
443 case RADEON_CS_RING_DMA:
444 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
445 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
447 case RADEON_CS_RING_UVD:
448 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
450 case RADEON_CS_RING_VCE:
451 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
457 case RADEON_INFO_SI_TILE_MODE_ARRAY:
458 if (rdev->family >= CHIP_BONAIRE) {
459 value = rdev->config.cik.tile_mode_array;
460 value_size = sizeof(uint32_t)*32;
461 } else if (rdev->family >= CHIP_TAHITI) {
462 value = rdev->config.si.tile_mode_array;
463 value_size = sizeof(uint32_t)*32;
465 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
469 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
470 if (rdev->family >= CHIP_BONAIRE) {
471 value = rdev->config.cik.macrotile_mode_array;
472 value_size = sizeof(uint32_t)*16;
474 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
478 case RADEON_INFO_SI_CP_DMA_COMPUTE:
481 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
482 if (rdev->family >= CHIP_BONAIRE) {
483 *value = rdev->config.cik.backend_enable_mask;
484 } else if (rdev->family >= CHIP_TAHITI) {
485 *value = rdev->config.si.backend_enable_mask;
487 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
490 case RADEON_INFO_MAX_SCLK:
491 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
492 rdev->pm.dpm_enabled)
493 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
495 *value = rdev->pm.default_sclk * 10;
497 case RADEON_INFO_VCE_FW_VERSION:
498 *value = rdev->vce.fw_version;
500 case RADEON_INFO_VCE_FB_VERSION:
501 *value = rdev->vce.fb_version;
503 case RADEON_INFO_NUM_BYTES_MOVED:
504 value = (uint32_t*)&value64;
505 value_size = sizeof(uint64_t);
506 value64 = atomic64_read(&rdev->num_bytes_moved);
508 case RADEON_INFO_VRAM_USAGE:
509 value = (uint32_t*)&value64;
510 value_size = sizeof(uint64_t);
511 value64 = atomic64_read(&rdev->vram_usage);
513 case RADEON_INFO_GTT_USAGE:
514 value = (uint32_t*)&value64;
515 value_size = sizeof(uint64_t);
516 value64 = atomic64_read(&rdev->gtt_usage);
519 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
522 if (copy_to_user(value_ptr, (char*)value, value_size)) {
523 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
531 * Outdated mess for old drm with Xorg being in charge (void function now).
534 * radeon_driver_firstopen_kms - drm callback for last close
536 * @dev: drm dev pointer
538 * Switch vga switcheroo state after last close (all asics).
540 void radeon_driver_lastclose_kms(struct drm_device *dev)
542 vga_switcheroo_process_delayed_switch();
546 * radeon_driver_open_kms - drm callback for open
548 * @dev: drm dev pointer
549 * @file_priv: drm file
551 * On device open, init vm on cayman+ (all asics).
552 * Returns 0 on success, error on failure.
554 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
556 struct radeon_device *rdev = dev->dev_private;
559 file_priv->driver_priv = NULL;
561 r = pm_runtime_get_sync(dev->dev);
565 /* new gpu have virtual address space support */
566 if (rdev->family >= CHIP_CAYMAN) {
567 struct radeon_fpriv *fpriv;
568 struct radeon_bo_va *bo_va;
571 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
572 if (unlikely(!fpriv)) {
576 r = radeon_vm_init(rdev, &fpriv->vm);
580 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
584 /* map the ib pool buffer read only into
585 * virtual address space */
586 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
587 rdev->ring_tmp_bo.bo);
588 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
589 RADEON_VM_PAGE_READABLE |
590 RADEON_VM_PAGE_SNOOPED);
592 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
594 radeon_vm_fini(rdev, &fpriv->vm);
599 file_priv->driver_priv = fpriv;
602 pm_runtime_mark_last_busy(dev->dev);
603 pm_runtime_put_autosuspend(dev->dev);
608 * radeon_driver_postclose_kms - drm callback for post close
610 * @dev: drm dev pointer
611 * @file_priv: drm file
613 * On device post close, tear down vm on cayman+ (all asics).
615 void radeon_driver_postclose_kms(struct drm_device *dev,
616 struct drm_file *file_priv)
618 struct radeon_device *rdev = dev->dev_private;
620 /* new gpu have virtual address space support */
621 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
622 struct radeon_fpriv *fpriv = file_priv->driver_priv;
623 struct radeon_bo_va *bo_va;
626 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
628 bo_va = radeon_vm_bo_find(&fpriv->vm,
629 rdev->ring_tmp_bo.bo);
631 radeon_vm_bo_rmv(rdev, bo_va);
632 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
635 radeon_vm_fini(rdev, &fpriv->vm);
637 file_priv->driver_priv = NULL;
642 * radeon_driver_preclose_kms - drm callback for pre close
644 * @dev: drm dev pointer
645 * @file_priv: drm file
647 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
650 void radeon_driver_preclose_kms(struct drm_device *dev,
651 struct drm_file *file_priv)
653 struct radeon_device *rdev = dev->dev_private;
654 if (rdev->hyperz_filp == file_priv)
655 rdev->hyperz_filp = NULL;
656 if (rdev->cmask_filp == file_priv)
657 rdev->cmask_filp = NULL;
658 radeon_uvd_free_handles(rdev, file_priv);
659 radeon_vce_free_handles(rdev, file_priv);
663 * VBlank related functions.
666 * radeon_get_vblank_counter_kms - get frame count
668 * @dev: drm dev pointer
669 * @crtc: crtc to get the frame count from
671 * Gets the frame count on the requested crtc (all asics).
672 * Returns frame count on success, -EINVAL on failure.
674 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
676 struct radeon_device *rdev = dev->dev_private;
678 if (crtc < 0 || crtc >= rdev->num_crtc) {
679 DRM_ERROR("Invalid crtc %d\n", crtc);
683 return radeon_get_vblank_counter(rdev, crtc);
687 * radeon_enable_vblank_kms - enable vblank interrupt
689 * @dev: drm dev pointer
690 * @crtc: crtc to enable vblank interrupt for
692 * Enable the interrupt on the requested crtc (all asics).
693 * Returns 0 on success, -EINVAL on failure.
695 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
697 struct radeon_device *rdev = dev->dev_private;
698 unsigned long irqflags;
701 if (crtc < 0 || crtc >= rdev->num_crtc) {
702 DRM_ERROR("Invalid crtc %d\n", crtc);
706 spin_lock_irqsave(&rdev->irq.lock, irqflags);
707 rdev->irq.crtc_vblank_int[crtc] = true;
708 r = radeon_irq_set(rdev);
709 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
714 * radeon_disable_vblank_kms - disable vblank interrupt
716 * @dev: drm dev pointer
717 * @crtc: crtc to disable vblank interrupt for
719 * Disable the interrupt on the requested crtc (all asics).
721 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
723 struct radeon_device *rdev = dev->dev_private;
724 unsigned long irqflags;
726 if (crtc < 0 || crtc >= rdev->num_crtc) {
727 DRM_ERROR("Invalid crtc %d\n", crtc);
731 spin_lock_irqsave(&rdev->irq.lock, irqflags);
732 rdev->irq.crtc_vblank_int[crtc] = false;
733 radeon_irq_set(rdev);
734 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
738 * radeon_get_vblank_timestamp_kms - get vblank timestamp
740 * @dev: drm dev pointer
741 * @crtc: crtc to get the timestamp for
742 * @max_error: max error
743 * @vblank_time: time value
744 * @flags: flags passed to the driver
746 * Gets the timestamp on the requested crtc based on the
747 * scanout position. (all asics).
748 * Returns postive status flags on success, negative error on failure.
750 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
752 struct timeval *vblank_time,
755 struct drm_crtc *drmcrtc;
756 struct radeon_device *rdev = dev->dev_private;
758 if (crtc < 0 || crtc >= dev->num_crtcs) {
759 DRM_ERROR("Invalid crtc %d\n", crtc);
763 /* Get associated drm_crtc: */
764 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
766 /* Helper routine in DRM core does all the work: */
767 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
769 drmcrtc, &drmcrtc->hwmode);
772 #define KMS_INVALID_IOCTL(name) \
773 static int name(struct drm_device *dev, void *data, struct drm_file \
776 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
781 * All these ioctls are invalid in kms world.
783 KMS_INVALID_IOCTL(radeon_cp_init_kms)
784 KMS_INVALID_IOCTL(radeon_cp_start_kms)
785 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
786 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
787 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
788 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
789 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
790 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
791 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
792 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
793 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
794 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
795 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
796 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
797 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
798 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
799 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
800 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
801 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
802 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
803 KMS_INVALID_IOCTL(radeon_mem_free_kms)
804 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
805 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
806 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
807 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
808 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
809 KMS_INVALID_IOCTL(radeon_surface_free_kms)
812 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
813 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
814 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
815 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
816 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
817 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
818 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
819 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
820 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
821 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
822 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
823 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
824 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
825 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
826 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
827 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
828 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
829 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
830 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
831 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
832 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
833 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
834 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
835 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
836 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
837 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
838 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
839 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
841 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
842 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
843 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
844 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
845 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
846 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
847 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
848 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
849 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
850 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
851 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
852 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
853 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
854 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
856 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);