drivers/gpu/drm/radeon/radeon_dp_mst.c

   1 // SPDX-License-Identifier: MIT
   2
   3 #include <drm/drmP.h>
   4 #include <drm/drm_dp_mst_helper.h>
   5 #include <drm/drm_fb_helper.h>
   6 #include <drm/drm_probe_helper.h>
   7
   8 #include "radeon.h"
   9 #include "atom.h"
  10 #include "ni_reg.h"
  11
  12 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
  13
  14 static int radeon_atom_set_enc_offset(int id)
  15 {
  16         static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
  17                                        EVERGREEN_CRTC1_REGISTER_OFFSET,
  18                                        EVERGREEN_CRTC2_REGISTER_OFFSET,
  19                                        EVERGREEN_CRTC3_REGISTER_OFFSET,
  20                                        EVERGREEN_CRTC4_REGISTER_OFFSET,
  21                                        EVERGREEN_CRTC5_REGISTER_OFFSET,
  22                                        0x13830 - 0x7030 };
  23
  24         return offsets[id];
  25 }
  26
  27 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
  28                                      struct radeon_encoder_mst *mst_enc,
  29                                      enum radeon_hpd_id hpd, bool enable)
  30 {
  31         struct drm_device *dev = primary->base.dev;
  32         struct radeon_device *rdev = dev->dev_private;
  33         uint32_t reg;
  34         int retries = 0;
  35         uint32_t temp;
  36
  37         reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
  38
  39         /* set MST mode */
  40         reg &= ~NI_DIG_FE_DIG_MODE(7);
  41         reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
  42
  43         if (enable)
  44                 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
  45         else
  46                 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
  47
  48         reg |= NI_DIG_HPD_SELECT(hpd);
  49         DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
  50         WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
  51
  52         if (enable) {
  53                 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
  54
  55                 do {
  56                         temp = RREG32(NI_DIG_FE_CNTL + offset);
  57                 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
  58                 if (retries == 10000)
  59                         DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
  60         }
  61         return 0;
  62 }
  63
  64 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
  65                                            int stream_number,
  66                                            int fe,
  67                                            int slots)
  68 {
  69         struct drm_device *dev = primary->base.dev;
  70         struct radeon_device *rdev = dev->dev_private;
  71         u32 temp, val;
  72         int retries  = 0;
  73         int satreg, satidx;
  74
  75         satreg = stream_number >> 1;
  76         satidx = stream_number & 1;
  77
  78         temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
  79
  80         val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
  81
  82         val <<= (16 * satidx);
  83
  84         temp &= ~(0xffff << (16 * satidx));
  85
  86         temp |= val;
  87
  88         DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
  89         WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
  90
  91         WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
  92
  93         do {
  94                 unsigned value1, value2;
  95                 udelay(10);
  96                 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
  97
  98                 value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
  99                 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
 100
 101                 if (!value1 && !value2)
 102                         break;
 103         } while (retries++ < 50);
 104
 105         if (retries == 10000)
 106                 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
 107
 108         /* MTP 16 ? */
 109         return 0;
 110 }
 111
 112 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
 113                                                struct radeon_encoder *primary)
 114 {
 115         struct drm_device *dev = mst_conn->base.dev;
 116         struct stream_attribs new_attribs[6];
 117         int i;
 118         int idx = 0;
 119         struct radeon_connector *radeon_connector;
 120         struct drm_connector *connector;
 121
 122         memset(new_attribs, 0, sizeof(new_attribs));
 123         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 124                 struct radeon_encoder *subenc;
 125                 struct radeon_encoder_mst *mst_enc;
 126
 127                 radeon_connector = to_radeon_connector(connector);
 128                 if (!radeon_connector->is_mst_connector)
 129                         continue;
 130
 131                 if (radeon_connector->mst_port != mst_conn)
 132                         continue;
 133
 134                 subenc = radeon_connector->mst_encoder;
 135                 mst_enc = subenc->enc_priv;
 136
 137                 if (!mst_enc->enc_active)
 138                         continue;
 139
 140                 new_attribs[idx].fe = mst_enc->fe;
 141                 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
 142                 idx++;
 143         }
 144
 145         for (i = 0; i < idx; i++) {
 146                 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
 147                     new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
 148                         radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
 149                         mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
 150                         mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
 151                 }
 152         }
 153
 154         for (i = idx; i < mst_conn->enabled_attribs; i++) {
 155                 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
 156                 mst_conn->cur_stream_attribs[i].fe = 0;
 157                 mst_conn->cur_stream_attribs[i].slots = 0;
 158         }
 159         mst_conn->enabled_attribs = idx;
 160         return 0;
 161 }
 162
 163 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
 164 {
 165         struct drm_device *dev = mst->base.dev;
 166         struct radeon_device *rdev = dev->dev_private;
 167         struct radeon_encoder_mst *mst_enc = mst->enc_priv;
 168         uint32_t val, temp;
 169         uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
 170         int retries = 0;
 171         uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
 172         uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
 173
 174         val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
 175
 176         WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
 177
 178         do {
 179                 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
 180                 udelay(10);
 181         } while ((temp & 0x1) && (retries++ < 10000));
 182
 183         if (retries >= 10000)
 184                 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
 185         return 0;
 186 }
 187
 188 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
 189 {
 190         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 191         struct radeon_connector *master = radeon_connector->mst_port;
 192         struct edid *edid;
 193         int ret = 0;
 194
 195         edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
 196         radeon_connector->edid = edid;
 197         DRM_DEBUG_KMS("edid retrieved %p\n", edid);
 198         if (radeon_connector->edid) {
 199                 drm_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 200                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 201                 return ret;
 202         }
 203         drm_connector_update_edid_property(&radeon_connector->base, NULL);
 204
 205         return ret;
 206 }
 207
 208 static int radeon_dp_mst_get_modes(struct drm_connector *connector)
 209 {
 210         return radeon_dp_mst_get_ddc_modes(connector);
 211 }
 212
 213 static enum drm_mode_status
 214 radeon_dp_mst_mode_valid(struct drm_connector *connector,
 215                         struct drm_display_mode *mode)
 216 {
 217         /* TODO - validate mode against available PBN for link */
 218         if (mode->clock < 10000)
 219                 return MODE_CLOCK_LOW;
 220
 221         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 222                 return MODE_H_ILLEGAL;
 223
 224         return MODE_OK;
 225 }
 226
 227 static struct
 228 drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
 229 {
 230         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 231
 232         return &radeon_connector->mst_encoder->base;
 233 }
 234
 235 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
 236         .get_modes = radeon_dp_mst_get_modes,
 237         .mode_valid = radeon_dp_mst_mode_valid,
 238         .best_encoder = radeon_mst_best_encoder,
 239 };
 240
 241 static enum drm_connector_status
 242 radeon_dp_mst_detect(struct drm_connector *connector, bool force)
 243 {
 244         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 245         struct radeon_connector *master = radeon_connector->mst_port;
 246
 247         return drm_dp_mst_detect_port(connector, &master->mst_mgr, radeon_connector->port);
 248 }
 249
 250 static void
 251 radeon_dp_mst_connector_destroy(struct drm_connector *connector)
 252 {
 253         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 254         struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
 255
 256         drm_encoder_cleanup(&radeon_encoder->base);
 257         kfree(radeon_encoder);
 258         drm_connector_cleanup(connector);
 259         kfree(radeon_connector);
 260 }
 261
 262 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
 263         .dpms = drm_helper_connector_dpms,
 264         .detect = radeon_dp_mst_detect,
 265         .fill_modes = drm_helper_probe_single_connector_modes,
 266         .destroy = radeon_dp_mst_connector_destroy,
 267 };
 268
 269 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 270                                                          struct drm_dp_mst_port *port,
 271                                                          const char *pathprop)
 272 {
 273         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 274         struct drm_device *dev = master->base.dev;
 275         struct radeon_connector *radeon_connector;
 276         struct drm_connector *connector;
 277
 278         radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
 279         if (!radeon_connector)
 280                 return NULL;
 281
 282         radeon_connector->is_mst_connector = true;
 283         connector = &radeon_connector->base;
 284         radeon_connector->port = port;
 285         radeon_connector->mst_port = master;
 286         DRM_DEBUG_KMS("\n");
 287
 288         drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
 289         drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
 290         radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
 291
 292         drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
 293         drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
 294         drm_connector_set_path_property(connector, pathprop);
 295
 296         return connector;
 297 }
 298
 299 static void radeon_dp_register_mst_connector(struct drm_connector *connector)
 300 {
 301         struct drm_device *dev = connector->dev;
 302         struct radeon_device *rdev = dev->dev_private;
 303
 304         radeon_fb_add_connector(rdev, connector);
 305
 306         drm_connector_register(connector);
 307 }
 308
 309 static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 310                                             struct drm_connector *connector)
 311 {
 312         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 313         struct drm_device *dev = master->base.dev;
 314         struct radeon_device *rdev = dev->dev_private;
 315
 316         drm_connector_unregister(connector);
 317         radeon_fb_remove_connector(rdev, connector);
 318         drm_connector_cleanup(connector);
 319
 320         kfree(connector);
 321         DRM_DEBUG_KMS("\n");
 322 }
 323
 324 static const struct drm_dp_mst_topology_cbs mst_cbs = {
 325         .add_connector = radeon_dp_add_mst_connector,
 326         .register_connector = radeon_dp_register_mst_connector,
 327         .destroy_connector = radeon_dp_destroy_mst_connector,
 328 };
 329
 330 static struct
 331 radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
 332 {
 333         struct drm_device *dev = encoder->dev;
 334         struct drm_connector *connector;
 335
 336         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 337                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 338                 if (!connector->encoder)
 339                         continue;
 340                 if (!radeon_connector->is_mst_connector)
 341                         continue;
 342
 343                 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
 344                 if (connector->encoder == encoder)
 345                         return radeon_connector;
 346         }
 347         return NULL;
 348 }
 349
 350 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 351 {
 352         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 353         struct drm_device *dev = crtc->dev;
 354         struct radeon_device *rdev = dev->dev_private;
 355         struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
 356         struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
 357         struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
 358         int dp_clock;
 359         struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
 360
 361         if (radeon_connector) {
 362                 radeon_connector->pixelclock_for_modeset = mode->clock;
 363                 if (radeon_connector->base.display_info.bpc)
 364                         radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
 365                 else
 366                         radeon_crtc->bpc = 8;
 367         }
 368
 369         DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
 370         dp_clock = dig_connector->dp_clock;
 371         radeon_crtc->ss_enabled =
 372                 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 373                                                  ASIC_INTERNAL_SS_ON_DP,
 374                                                  dp_clock);
 375 }
 376
 377 static void
 378 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
 379 {
 380         struct drm_device *dev = encoder->dev;
 381         struct radeon_device *rdev = dev->dev_private;
 382         struct radeon_encoder *radeon_encoder, *primary;
 383         struct radeon_encoder_mst *mst_enc;
 384         struct radeon_encoder_atom_dig *dig_enc;
 385         struct radeon_connector *radeon_connector;
 386         struct drm_crtc *crtc;
 387         struct radeon_crtc *radeon_crtc;
 388         int ret, slots;
 389         s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
 390         if (!ASIC_IS_DCE5(rdev)) {
 391                 DRM_ERROR("got mst dpms on non-DCE5\n");
 392                 return;
 393         }
 394
 395         radeon_connector = radeon_mst_find_connector(encoder);
 396         if (!radeon_connector)
 397                 return;
 398
 399         radeon_encoder = to_radeon_encoder(encoder);
 400
 401         mst_enc = radeon_encoder->enc_priv;
 402
 403         primary = mst_enc->primary;
 404
 405         dig_enc = primary->enc_priv;
 406
 407         crtc = encoder->crtc;
 408         DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
 409
 410         switch (mode) {
 411         case DRM_MODE_DPMS_ON:
 412                 dig_enc->active_mst_links++;
 413
 414                 radeon_crtc = to_radeon_crtc(crtc);
 415
 416                 if (dig_enc->active_mst_links == 1) {
 417                         mst_enc->fe = dig_enc->dig_encoder;
 418                         mst_enc->fe_from_be = true;
 419                         atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
 420
 421                         atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
 422                         atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
 423                                                         0, 0, dig_enc->dig_encoder);
 424
 425                         if (radeon_dp_needs_link_train(mst_enc->connector) ||
 426                             dig_enc->active_mst_links == 1) {
 427                                 radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
 428                         }
 429
 430                 } else {
 431                         mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
 432                         if (mst_enc->fe == -1)
 433                                 DRM_ERROR("failed to get frontend for dig encoder\n");
 434                         mst_enc->fe_from_be = false;
 435                         atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
 436                 }
 437
 438                 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
 439                               dig_enc->linkb, radeon_crtc->crtc_id);
 440
 441                 slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr,
 442                                                mst_enc->pbn);
 443                 ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
 444                                                radeon_connector->port,
 445                                                mst_enc->pbn, slots);
 446                 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
 447
 448                 radeon_dp_mst_set_be_cntl(primary, mst_enc,
 449                                           radeon_connector->mst_port->hpd.hpd, true);
 450
 451                 mst_enc->enc_active = true;
 452                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
 453
 454                 fixed_pbn = drm_int2fixp(mst_enc->pbn);
 455                 fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
 456                 avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
 457                 radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
 458
 459                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
 460                                             mst_enc->fe);
 461                 ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
 462
 463                 ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
 464
 465                 break;
 466         case DRM_MODE_DPMS_STANDBY:
 467         case DRM_MODE_DPMS_SUSPEND:
 468         case DRM_MODE_DPMS_OFF:
 469                 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
 470
 471                 if (!mst_enc->enc_active)
 472                         return;
 473
 474                 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
 475                 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
 476
 477                 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
 478                 /* and this can also fail */
 479                 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
 480
 481                 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
 482
 483                 mst_enc->enc_active = false;
 484                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
 485
 486                 radeon_dp_mst_set_be_cntl(primary, mst_enc,
 487                                           radeon_connector->mst_port->hpd.hpd, false);
 488                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
 489                                             mst_enc->fe);
 490
 491                 if (!mst_enc->fe_from_be)
 492                         radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
 493
 494                 mst_enc->fe_from_be = false;
 495                 dig_enc->active_mst_links--;
 496                 if (dig_enc->active_mst_links == 0) {
 497                         /* drop link */
 498                 }
 499
 500                 break;
 501         }
 502
 503 }
 504
 505 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
 506                                    const struct drm_display_mode *mode,
 507                                    struct drm_display_mode *adjusted_mode)
 508 {
 509         struct radeon_encoder_mst *mst_enc;
 510         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 511         struct radeon_connector_atom_dig *dig_connector;
 512         int bpp = 24;
 513
 514         mst_enc = radeon_encoder->enc_priv;
 515
 516         mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);
 517
 518         mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
 519         DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
 520                       mst_enc->primary->active_device, mst_enc->primary->devices,
 521                       mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
 522
 523
 524         drm_mode_set_crtcinfo(adjusted_mode, 0);
 525         dig_connector = mst_enc->connector->con_priv;
 526         dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
 527         dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
 528         DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
 529                       dig_connector->dp_lane_count, dig_connector->dp_clock);
 530         return true;
 531 }
 532
 533 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
 534 {
 535         struct radeon_connector *radeon_connector;
 536         struct radeon_encoder *radeon_encoder, *primary;
 537         struct radeon_encoder_mst *mst_enc;
 538         struct radeon_encoder_atom_dig *dig_enc;
 539
 540         radeon_connector = radeon_mst_find_connector(encoder);
 541         if (!radeon_connector) {
 542                 DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
 543                 return;
 544         }
 545         radeon_encoder = to_radeon_encoder(encoder);
 546
 547         radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
 548
 549         mst_enc = radeon_encoder->enc_priv;
 550
 551         primary = mst_enc->primary;
 552
 553         dig_enc = primary->enc_priv;
 554
 555         mst_enc->port = radeon_connector->port;
 556
 557         if (dig_enc->dig_encoder == -1) {
 558                 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
 559                 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
 560                 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
 561
 562
 563         }
 564         DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
 565 }
 566
 567 static void
 568 radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
 569                              struct drm_display_mode *mode,
 570                              struct drm_display_mode *adjusted_mode)
 571 {
 572         DRM_DEBUG_KMS("\n");
 573 }
 574
 575 static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
 576 {
 577         radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
 578         DRM_DEBUG_KMS("\n");
 579 }
 580
 581 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
 582         .dpms = radeon_mst_encoder_dpms,
 583         .mode_fixup = radeon_mst_mode_fixup,
 584         .prepare = radeon_mst_encoder_prepare,
 585         .mode_set = radeon_mst_encoder_mode_set,
 586         .commit = radeon_mst_encoder_commit,
 587 };
 588
 589 static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
 590 {
 591         drm_encoder_cleanup(encoder);
 592         kfree(encoder);
 593 }
 594
 595 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
 596         .destroy = radeon_dp_mst_encoder_destroy,
 597 };
 598
 599 static struct radeon_encoder *
 600 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
 601 {
 602         struct drm_device *dev = connector->base.dev;
 603         struct radeon_device *rdev = dev->dev_private;
 604         struct radeon_encoder *radeon_encoder;
 605         struct radeon_encoder_mst *mst_enc;
 606         struct drm_encoder *encoder;
 607         const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
 608         struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
 609
 610         DRM_DEBUG_KMS("enc master is %p\n", enc_master);
 611         radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
 612         if (!radeon_encoder)
 613                 return NULL;
 614
 615         radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
 616         if (!radeon_encoder->enc_priv) {
 617                 kfree(radeon_encoder);
 618                 return NULL;
 619         }
 620         encoder = &radeon_encoder->base;
 621         switch (rdev->num_crtc) {
 622         case 1:
 623                 encoder->possible_crtcs = 0x1;
 624                 break;
 625         case 2:
 626         default:
 627                 encoder->possible_crtcs = 0x3;
 628                 break;
 629         case 4:
 630                 encoder->possible_crtcs = 0xf;
 631                 break;
 632         case 6:
 633                 encoder->possible_crtcs = 0x3f;
 634                 break;
 635         }
 636
 637         drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
 638                          DRM_MODE_ENCODER_DPMST, NULL);
 639         drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
 640
 641         mst_enc = radeon_encoder->enc_priv;
 642         mst_enc->connector = connector;
 643         mst_enc->primary = to_radeon_encoder(enc_master);
 644         radeon_encoder->is_mst_encoder = true;
 645         return radeon_encoder;
 646 }
 647
 648 int
 649 radeon_dp_mst_init(struct radeon_connector *radeon_connector)
 650 {
 651         struct drm_device *dev = radeon_connector->base.dev;
 652
 653         if (!radeon_connector->ddc_bus->has_aux)
 654                 return 0;
 655
 656         radeon_connector->mst_mgr.cbs = &mst_cbs;
 657         return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev,
 658                                             &radeon_connector->ddc_bus->aux, 16, 6,
 659                                             radeon_connector->base.base.id);
 660 }
 661
 662 int
 663 radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
 664 {
 665         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 666         struct drm_device *dev = radeon_connector->base.dev;
 667         struct radeon_device *rdev = dev->dev_private;
 668         int ret;
 669         u8 msg[1];
 670
 671         if (!radeon_mst)
 672                 return 0;
 673
 674         if (!ASIC_IS_DCE5(rdev))
 675                 return 0;
 676
 677         if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
 678                 return 0;
 679
 680         ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
 681                                1);
 682         if (ret) {
 683                 if (msg[0] & DP_MST_CAP) {
 684                         DRM_DEBUG_KMS("Sink is MST capable\n");
 685                         dig_connector->is_mst = true;
 686                 } else {
 687                         DRM_DEBUG_KMS("Sink is not MST capable\n");
 688                         dig_connector->is_mst = false;
 689                 }
 690
 691         }
 692         drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
 693                                         dig_connector->is_mst);
 694         return dig_connector->is_mst;
 695 }
 696
 697 int
 698 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
 699 {
 700         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 701         int retry;
 702
 703         if (dig_connector->is_mst) {
 704                 u8 esi[16] = { 0 };
 705                 int dret;
 706                 int ret = 0;
 707                 bool handled;
 708
 709                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
 710                                        DP_SINK_COUNT_ESI, esi, 8);
 711 go_again:
 712                 if (dret == 8) {
 713                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
 714                         ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
 715
 716                         if (handled) {
 717                                 for (retry = 0; retry < 3; retry++) {
 718                                         int wret;
 719                                         wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
 720                                                                  DP_SINK_COUNT_ESI + 1, &esi[1], 3);
 721                                         if (wret == 3)
 722                                                 break;
 723                                 }
 724
 725                                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
 726                                                         DP_SINK_COUNT_ESI, esi, 8);
 727                                 if (dret == 8) {
 728                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
 729                                         goto go_again;
 730                                 }
 731                         } else
 732                                 ret = 0;
 733
 734                         return ret;
 735                 } else {
 736                         DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
 737                         dig_connector->is_mst = false;
 738                         drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
 739                                                         dig_connector->is_mst);
 740                         /* send a hotplug event */
 741                 }
 742         }
 743         return -EINVAL;
 744 }
 745
 746 #if defined(CONFIG_DEBUG_FS)
 747
 748 static int radeon_debugfs_mst_info(struct seq_file *m, void *data)
 749 {
 750         struct drm_info_node *node = (struct drm_info_node *)m->private;
 751         struct drm_device *dev = node->minor->dev;
 752         struct drm_connector *connector;
 753         struct radeon_connector *radeon_connector;
 754         struct radeon_connector_atom_dig *dig_connector;
 755         int i;
 756
 757         drm_modeset_lock_all(dev);
 758         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 759                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 760                         continue;
 761
 762                 radeon_connector = to_radeon_connector(connector);
 763                 dig_connector = radeon_connector->con_priv;
 764                 if (radeon_connector->is_mst_connector)
 765                         continue;
 766                 if (!dig_connector->is_mst)
 767                         continue;
 768                 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
 769
 770                 for (i = 0; i < radeon_connector->enabled_attribs; i++)
 771                         seq_printf(m, "attrib %d: %d %d\n", i,
 772                                    radeon_connector->cur_stream_attribs[i].fe,
 773                                    radeon_connector->cur_stream_attribs[i].slots);
 774         }
 775         drm_modeset_unlock_all(dev);
 776         return 0;
 777 }
 778
 779 static struct drm_info_list radeon_debugfs_mst_list[] = {
 780         {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL},
 781 };
 782 #endif
 783
 784 int radeon_mst_debugfs_init(struct radeon_device *rdev)
 785 {
 786 #if defined(CONFIG_DEBUG_FS)
 787         return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1);
 788 #endif
 789         return 0;
 790 }