drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <linux/pci.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/gcd.h>
  30
  31 #include <asm/div64.h>
  32
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_device.h>
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_fourcc.h>
  38 #include <drm/drm_framebuffer.h>
  39 #include <drm/drm_gem_framebuffer_helper.h>
  40 #include <drm/drm_modeset_helper.h>
  41 #include <drm/drm_probe_helper.h>
  42 #include <drm/drm_vblank.h>
  43 #include <drm/radeon_drm.h>
  44
  45 #include "atom.h"
  46 #include "radeon.h"
  47 #include "radeon_kms.h"
  48
  49 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  50 {
  51         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  52         struct drm_device *dev = crtc->dev;
  53         struct radeon_device *rdev = dev->dev_private;
  54         u16 *r, *g, *b;
  55         int i;
  56
  57         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  58         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  59
  60         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  61         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  62         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  63
  64         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  65         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  66         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  67
  68         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  69         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  70         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  71
  72         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  73         r = crtc->gamma_store;
  74         g = r + crtc->gamma_size;
  75         b = g + crtc->gamma_size;
  76         for (i = 0; i < 256; i++) {
  77                 WREG32(AVIVO_DC_LUT_30_COLOR,
  78                        ((*r++ & 0xffc0) << 14) |
  79                        ((*g++ & 0xffc0) << 4) |
  80                        (*b++ >> 6));
  81         }
  82
  83         /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
  84         WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
  85 }
  86
  87 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  88 {
  89         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  90         struct drm_device *dev = crtc->dev;
  91         struct radeon_device *rdev = dev->dev_private;
  92         u16 *r, *g, *b;
  93         int i;
  94
  95         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  96         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  97
  98         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  99         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 100         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 101
 102         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 103         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 104         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 105
 106         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 107         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 108
 109         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 110         r = crtc->gamma_store;
 111         g = r + crtc->gamma_size;
 112         b = g + crtc->gamma_size;
 113         for (i = 0; i < 256; i++) {
 114                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 115                        ((*r++ & 0xffc0) << 14) |
 116                        ((*g++ & 0xffc0) << 4) |
 117                        (*b++ >> 6));
 118         }
 119 }
 120
 121 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 122 {
 123         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 124         struct drm_device *dev = crtc->dev;
 125         struct radeon_device *rdev = dev->dev_private;
 126         u16 *r, *g, *b;
 127         int i;
 128
 129         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 130
 131         msleep(10);
 132
 133         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 134                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 135                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 136         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 137                NI_GRPH_PRESCALE_BYPASS);
 138         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 139                NI_OVL_PRESCALE_BYPASS);
 140         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 141                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 142                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 143
 144         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 145
 146         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 147         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 148         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 149
 150         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 151         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 152         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 153
 154         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 155         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 156
 157         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 158         r = crtc->gamma_store;
 159         g = r + crtc->gamma_size;
 160         b = g + crtc->gamma_size;
 161         for (i = 0; i < 256; i++) {
 162                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 163                        ((*r++ & 0xffc0) << 14) |
 164                        ((*g++ & 0xffc0) << 4) |
 165                        (*b++ >> 6));
 166         }
 167
 168         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 169                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 170                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 171                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 172                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 173         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 174                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 175                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 176         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 177                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 178                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 179         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 180                (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
 181                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 182         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 183         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 184         if (ASIC_IS_DCE8(rdev)) {
 185                 /* XXX this only needs to be programmed once per crtc at startup,
 186                  * not sure where the best place for it is
 187                  */
 188                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 189                        CIK_CURSOR_ALPHA_BLND_ENA);
 190         }
 191 }
 192
 193 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 194 {
 195         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 196         struct drm_device *dev = crtc->dev;
 197         struct radeon_device *rdev = dev->dev_private;
 198         u16 *r, *g, *b;
 199         int i;
 200         uint32_t dac2_cntl;
 201
 202         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 203         if (radeon_crtc->crtc_id == 0)
 204                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 205         else
 206                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 207         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 208
 209         WREG8(RADEON_PALETTE_INDEX, 0);
 210         r = crtc->gamma_store;
 211         g = r + crtc->gamma_size;
 212         b = g + crtc->gamma_size;
 213         for (i = 0; i < 256; i++) {
 214                 WREG32(RADEON_PALETTE_30_DATA,
 215                        ((*r++ & 0xffc0) << 14) |
 216                        ((*g++ & 0xffc0) << 4) |
 217                        (*b++ >> 6));
 218         }
 219 }
 220
 221 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 222 {
 223         struct drm_device *dev = crtc->dev;
 224         struct radeon_device *rdev = dev->dev_private;
 225
 226         if (!crtc->enabled)
 227                 return;
 228
 229         if (ASIC_IS_DCE5(rdev))
 230                 dce5_crtc_load_lut(crtc);
 231         else if (ASIC_IS_DCE4(rdev))
 232                 dce4_crtc_load_lut(crtc);
 233         else if (ASIC_IS_AVIVO(rdev))
 234                 avivo_crtc_load_lut(crtc);
 235         else
 236                 legacy_crtc_load_lut(crtc);
 237 }
 238
 239 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 240                                  u16 *blue, uint32_t size,
 241                                  struct drm_modeset_acquire_ctx *ctx)
 242 {
 243         radeon_crtc_load_lut(crtc);
 244
 245         return 0;
 246 }
 247
 248 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 249 {
 250         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 251
 252         drm_crtc_cleanup(crtc);
 253         destroy_workqueue(radeon_crtc->flip_queue);
 254         kfree(radeon_crtc);
 255 }
 256
 257 /**
 258  * radeon_unpin_work_func - unpin old buffer object
 259  *
 260  * @__work: kernel work item
 261  *
 262  * Unpin the old frame buffer object outside of the interrupt handler
 263  */
 264 static void radeon_unpin_work_func(struct work_struct *__work)
 265 {
 266         struct radeon_flip_work *work =
 267                 container_of(__work, struct radeon_flip_work, unpin_work);
 268         int r;
 269
 270         /* unpin of the old buffer */
 271         r = radeon_bo_reserve(work->old_rbo, false);
 272         if (likely(r == 0)) {
 273                 radeon_bo_unpin(work->old_rbo);
 274                 radeon_bo_unreserve(work->old_rbo);
 275         } else
 276                 DRM_ERROR("failed to reserve buffer after flip\n");
 277
 278         drm_gem_object_put(&work->old_rbo->tbo.base);
 279         kfree(work);
 280 }
 281
 282 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
 283 {
 284         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 285         unsigned long flags;
 286         u32 update_pending;
 287         int vpos, hpos;
 288
 289         /* can happen during initialization */
 290         if (radeon_crtc == NULL)
 291                 return;
 292
 293         /* Skip the pageflip completion check below (based on polling) on
 294          * asics which reliably support hw pageflip completion irqs. pflip
 295          * irqs are a reliable and race-free method of handling pageflip
 296          * completion detection. A use_pflipirq module parameter < 2 allows
 297          * to override this in case of asics with faulty pflip irqs.
 298          * A module parameter of 0 would only use this polling based path,
 299          * a parameter of 1 would use pflip irq only as a backup to this
 300          * path, as in Linux 3.16.
 301          */
 302         if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
 303                 return;
 304
 305         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 306         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 307                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 308                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 309                                  radeon_crtc->flip_status,
 310                                  RADEON_FLIP_SUBMITTED);
 311                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 312                 return;
 313         }
 314
 315         update_pending = radeon_page_flip_pending(rdev, crtc_id);
 316
 317         /* Has the pageflip already completed in crtc, or is it certain
 318          * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
 319          * distance to start of "fudged earlier" vblank in vpos, distance to
 320          * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
 321          * the last few scanlines before start of real vblank, where the vblank
 322          * irq can fire, so we have sampled update_pending a bit too early and
 323          * know the flip will complete at leading edge of the upcoming real
 324          * vblank. On pre-AVIVO hardware, flips also complete inside the real
 325          * vblank, not only at leading edge, so if update_pending for hpos >= 0
 326          *  == inside real vblank, the flip will complete almost immediately.
 327          * Note that this method of completion handling is still not 100% race
 328          * free, as we could execute before the radeon_flip_work_func managed
 329          * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
 330          * but the flip still gets programmed into hw and completed during
 331          * vblank, leading to a delayed emission of the flip completion event.
 332          * This applies at least to pre-AVIVO hardware, where flips are always
 333          * completing inside vblank, not only at leading edge of vblank.
 334          */
 335         if (update_pending &&
 336             (DRM_SCANOUTPOS_VALID &
 337              radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 338                                         GET_DISTANCE_TO_VBLANKSTART,
 339                                         &vpos, &hpos, NULL, NULL,
 340                                         &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
 341             ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
 342                 /* crtc didn't flip in this target vblank interval,
 343                  * but flip is pending in crtc. Based on the current
 344                  * scanout position we know that the current frame is
 345                  * (nearly) complete and the flip will (likely)
 346                  * complete before the start of the next frame.
 347                  */
 348                 update_pending = 0;
 349         }
 350         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 351         if (!update_pending)
 352                 radeon_crtc_handle_flip(rdev, crtc_id);
 353 }
 354
 355 /**
 356  * radeon_crtc_handle_flip - page flip completed
 357  *
 358  * @rdev: radeon device pointer
 359  * @crtc_id: crtc number this event is for
 360  *
 361  * Called when we are sure that a page flip for this crtc is completed.
 362  */
 363 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 364 {
 365         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 366         struct radeon_flip_work *work;
 367         unsigned long flags;
 368
 369         /* this can happen at init */
 370         if (radeon_crtc == NULL)
 371                 return;
 372
 373         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 374         work = radeon_crtc->flip_work;
 375         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 376                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 377                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 378                                  radeon_crtc->flip_status,
 379                                  RADEON_FLIP_SUBMITTED);
 380                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 381                 return;
 382         }
 383
 384         /* Pageflip completed. Clean up. */
 385         radeon_crtc->flip_status = RADEON_FLIP_NONE;
 386         radeon_crtc->flip_work = NULL;
 387
 388         /* wakeup userspace */
 389         if (work->event)
 390                 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
 391
 392         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 393
 394         drm_crtc_vblank_put(&radeon_crtc->base);
 395         radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
 396         queue_work(radeon_crtc->flip_queue, &work->unpin_work);
 397 }
 398
 399 /**
 400  * radeon_flip_work_func - page flip framebuffer
 401  *
 402  * @__work: kernel work item
 403  *
 404  * Wait for the buffer object to become idle and do the actual page flip
 405  */
 406 static void radeon_flip_work_func(struct work_struct *__work)
 407 {
 408         struct radeon_flip_work *work =
 409                 container_of(__work, struct radeon_flip_work, flip_work);
 410         struct radeon_device *rdev = work->rdev;
 411         struct drm_device *dev = rdev->ddev;
 412         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
 413
 414         struct drm_crtc *crtc = &radeon_crtc->base;
 415         unsigned long flags;
 416         int r;
 417         int vpos, hpos;
 418
 419         down_read(&rdev->exclusive_lock);
 420         if (work->fence) {
 421                 struct radeon_fence *fence;
 422
 423                 fence = to_radeon_fence(work->fence);
 424                 if (fence && fence->rdev == rdev) {
 425                         r = radeon_fence_wait(fence, false);
 426                         if (r == -EDEADLK) {
 427                                 up_read(&rdev->exclusive_lock);
 428                                 do {
 429                                         r = radeon_gpu_reset(rdev);
 430                                 } while (r == -EAGAIN);
 431                                 down_read(&rdev->exclusive_lock);
 432                         }
 433                 } else
 434                         r = dma_fence_wait(work->fence, false);
 435
 436                 if (r)
 437                         DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
 438
 439                 /* We continue with the page flip even if we failed to wait on
 440                  * the fence, otherwise the DRM core and userspace will be
 441                  * confused about which BO the CRTC is scanning out
 442                  */
 443
 444                 dma_fence_put(work->fence);
 445                 work->fence = NULL;
 446         }
 447
 448         /* Wait until we're out of the vertical blank period before the one
 449          * targeted by the flip. Always wait on pre DCE4 to avoid races with
 450          * flip completion handling from vblank irq, as these old asics don't
 451          * have reliable pageflip completion interrupts.
 452          */
 453         while (radeon_crtc->enabled &&
 454                 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
 455                                             &vpos, &hpos, NULL, NULL,
 456                                             &crtc->hwmode)
 457                 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 458                 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 459                 (!ASIC_IS_AVIVO(rdev) ||
 460                 ((int) (work->target_vblank -
 461                 crtc->funcs->get_vblank_counter(crtc)) > 0)))
 462                 usleep_range(1000, 2000);
 463
 464         /* We borrow the event spin lock for protecting flip_status */
 465         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 466
 467         /* set the proper interrupt */
 468         radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
 469
 470         /* do the flip (mmio) */
 471         radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
 472
 473         radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
 474         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 475         up_read(&rdev->exclusive_lock);
 476 }
 477
 478 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
 479                                         struct drm_framebuffer *fb,
 480                                         struct drm_pending_vblank_event *event,
 481                                         uint32_t page_flip_flags,
 482                                         uint32_t target,
 483                                         struct drm_modeset_acquire_ctx *ctx)
 484 {
 485         struct drm_device *dev = crtc->dev;
 486         struct radeon_device *rdev = dev->dev_private;
 487         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 488         struct drm_gem_object *obj;
 489         struct radeon_flip_work *work;
 490         struct radeon_bo *new_rbo;
 491         uint32_t tiling_flags, pitch_pixels;
 492         uint64_t base;
 493         unsigned long flags;
 494         int r;
 495
 496         work = kzalloc(sizeof *work, GFP_KERNEL);
 497         if (work == NULL)
 498                 return -ENOMEM;
 499
 500         INIT_WORK(&work->flip_work, radeon_flip_work_func);
 501         INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
 502
 503         work->rdev = rdev;
 504         work->crtc_id = radeon_crtc->crtc_id;
 505         work->event = event;
 506         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 507
 508         /* schedule unpin of the old buffer */
 509         obj = crtc->primary->fb->obj[0];
 510
 511         /* take a reference to the old object */
 512         drm_gem_object_get(obj);
 513         work->old_rbo = gem_to_radeon_bo(obj);
 514
 515         obj = fb->obj[0];
 516         new_rbo = gem_to_radeon_bo(obj);
 517
 518         /* pin the new buffer */
 519         DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
 520                          work->old_rbo, new_rbo);
 521
 522         r = radeon_bo_reserve(new_rbo, false);
 523         if (unlikely(r != 0)) {
 524                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 525                 goto cleanup;
 526         }
 527         /* Only 27 bit offset for legacy CRTC */
 528         r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
 529                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 530         if (unlikely(r != 0)) {
 531                 radeon_bo_unreserve(new_rbo);
 532                 r = -EINVAL;
 533                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 534                 goto cleanup;
 535         }
 536         r = dma_resv_get_singleton(new_rbo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
 537                                    &work->fence);
 538         if (r) {
 539                 radeon_bo_unreserve(new_rbo);
 540                 DRM_ERROR("failed to get new rbo buffer fences\n");
 541                 goto cleanup;
 542         }
 543         radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
 544         radeon_bo_unreserve(new_rbo);
 545
 546         if (!ASIC_IS_AVIVO(rdev)) {
 547                 /* crtc offset is from display base addr not FB location */
 548                 base -= radeon_crtc->legacy_display_base_addr;
 549                 pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
 550
 551                 if (tiling_flags & RADEON_TILING_MACRO) {
 552                         if (ASIC_IS_R300(rdev)) {
 553                                 base &= ~0x7ff;
 554                         } else {
 555                                 int byteshift = fb->format->cpp[0] * 8 >> 4;
 556                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 557                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 558                         }
 559                 } else {
 560                         int offset = crtc->y * pitch_pixels + crtc->x;
 561                         switch (fb->format->cpp[0] * 8) {
 562                         case 8:
 563                         default:
 564                                 offset *= 1;
 565                                 break;
 566                         case 15:
 567                         case 16:
 568                                 offset *= 2;
 569                                 break;
 570                         case 24:
 571                                 offset *= 3;
 572                                 break;
 573                         case 32:
 574                                 offset *= 4;
 575                                 break;
 576                         }
 577                         base += offset;
 578                 }
 579                 base &= ~7;
 580         }
 581         work->base = base;
 582         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 583                 crtc->funcs->get_vblank_counter(crtc);
 584
 585         /* We borrow the event spin lock for protecting flip_work */
 586         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 587
 588         if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
 589                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 590                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 591                 r = -EBUSY;
 592                 goto pflip_cleanup;
 593         }
 594         radeon_crtc->flip_status = RADEON_FLIP_PENDING;
 595         radeon_crtc->flip_work = work;
 596
 597         /* update crtc fb */
 598         crtc->primary->fb = fb;
 599
 600         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 601
 602         queue_work(radeon_crtc->flip_queue, &work->flip_work);
 603         return 0;
 604
 605 pflip_cleanup:
 606         if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
 607                 DRM_ERROR("failed to reserve new rbo in error path\n");
 608                 goto cleanup;
 609         }
 610         radeon_bo_unpin(new_rbo);
 611         radeon_bo_unreserve(new_rbo);
 612
 613 cleanup:
 614         drm_gem_object_put(&work->old_rbo->tbo.base);
 615         dma_fence_put(work->fence);
 616         kfree(work);
 617         return r;
 618 }
 619
 620 static int
 621 radeon_crtc_set_config(struct drm_mode_set *set,
 622                        struct drm_modeset_acquire_ctx *ctx)
 623 {
 624         struct drm_device *dev;
 625         struct radeon_device *rdev;
 626         struct drm_crtc *crtc;
 627         bool active = false;
 628         int ret;
 629
 630         if (!set || !set->crtc)
 631                 return -EINVAL;
 632
 633         dev = set->crtc->dev;
 634
 635         ret = pm_runtime_get_sync(dev->dev);
 636         if (ret < 0) {
 637                 pm_runtime_put_autosuspend(dev->dev);
 638                 return ret;
 639         }
 640
 641         ret = drm_crtc_helper_set_config(set, ctx);
 642
 643         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 644                 if (crtc->enabled)
 645                         active = true;
 646
 647         pm_runtime_mark_last_busy(dev->dev);
 648
 649         rdev = dev->dev_private;
 650         /* if we have active crtcs and we don't have a power ref,
 651            take the current one */
 652         if (active && !rdev->have_disp_power_ref) {
 653                 rdev->have_disp_power_ref = true;
 654                 return ret;
 655         }
 656         /* if we have no active crtcs, then drop the power ref
 657            we got before */
 658         if (!active && rdev->have_disp_power_ref) {
 659                 pm_runtime_put_autosuspend(dev->dev);
 660                 rdev->have_disp_power_ref = false;
 661         }
 662
 663         /* drop the power reference we got coming in here */
 664         pm_runtime_put_autosuspend(dev->dev);
 665         return ret;
 666 }
 667
 668 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 669         .cursor_set2 = radeon_crtc_cursor_set2,
 670         .cursor_move = radeon_crtc_cursor_move,
 671         .gamma_set = radeon_crtc_gamma_set,
 672         .set_config = radeon_crtc_set_config,
 673         .destroy = radeon_crtc_destroy,
 674         .page_flip_target = radeon_crtc_page_flip_target,
 675         .get_vblank_counter = radeon_get_vblank_counter_kms,
 676         .enable_vblank = radeon_enable_vblank_kms,
 677         .disable_vblank = radeon_disable_vblank_kms,
 678         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
 679 };
 680
 681 static void radeon_crtc_init(struct drm_device *dev, int index)
 682 {
 683         struct radeon_device *rdev = dev->dev_private;
 684         struct radeon_crtc *radeon_crtc;
 685
 686         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 687         if (radeon_crtc == NULL)
 688                 return;
 689
 690         radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
 691         if (!radeon_crtc->flip_queue) {
 692                 kfree(radeon_crtc);
 693                 return;
 694         }
 695
 696         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 697
 698         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 699         radeon_crtc->crtc_id = index;
 700         rdev->mode_info.crtcs[index] = radeon_crtc;
 701
 702         if (rdev->family >= CHIP_BONAIRE) {
 703                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 704                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 705         } else {
 706                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 707                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 708         }
 709         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 710         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 711
 712 #if 0
 713         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 714         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 715         radeon_crtc->mode_set.num_connectors = 0;
 716 #endif
 717
 718         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 719                 radeon_atombios_init_crtc(dev, radeon_crtc);
 720         else
 721                 radeon_legacy_init_crtc(dev, radeon_crtc);
 722 }
 723
 724 static const char *encoder_names[38] = {
 725         "NONE",
 726         "INTERNAL_LVDS",
 727         "INTERNAL_TMDS1",
 728         "INTERNAL_TMDS2",
 729         "INTERNAL_DAC1",
 730         "INTERNAL_DAC2",
 731         "INTERNAL_SDVOA",
 732         "INTERNAL_SDVOB",
 733         "SI170B",
 734         "CH7303",
 735         "CH7301",
 736         "INTERNAL_DVO1",
 737         "EXTERNAL_SDVOA",
 738         "EXTERNAL_SDVOB",
 739         "TITFP513",
 740         "INTERNAL_LVTM1",
 741         "VT1623",
 742         "HDMI_SI1930",
 743         "HDMI_INTERNAL",
 744         "INTERNAL_KLDSCP_TMDS1",
 745         "INTERNAL_KLDSCP_DVO1",
 746         "INTERNAL_KLDSCP_DAC1",
 747         "INTERNAL_KLDSCP_DAC2",
 748         "SI178",
 749         "MVPU_FPGA",
 750         "INTERNAL_DDI",
 751         "VT1625",
 752         "HDMI_SI1932",
 753         "DP_AN9801",
 754         "DP_DP501",
 755         "INTERNAL_UNIPHY",
 756         "INTERNAL_KLDSCP_LVTMA",
 757         "INTERNAL_UNIPHY1",
 758         "INTERNAL_UNIPHY2",
 759         "NUTMEG",
 760         "TRAVIS",
 761         "INTERNAL_VCE",
 762         "INTERNAL_UNIPHY3",
 763 };
 764
 765 static const char *hpd_names[6] = {
 766         "HPD1",
 767         "HPD2",
 768         "HPD3",
 769         "HPD4",
 770         "HPD5",
 771         "HPD6",
 772 };
 773
 774 static void radeon_print_display_setup(struct drm_device *dev)
 775 {
 776         struct drm_connector *connector;
 777         struct radeon_connector *radeon_connector;
 778         struct drm_encoder *encoder;
 779         struct radeon_encoder *radeon_encoder;
 780         uint32_t devices;
 781         int i = 0;
 782
 783         DRM_INFO("Radeon Display Connectors\n");
 784         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 785                 radeon_connector = to_radeon_connector(connector);
 786                 DRM_INFO("Connector %d:\n", i);
 787                 DRM_INFO("  %s\n", connector->name);
 788                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 789                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 790                 if (radeon_connector->ddc_bus) {
 791                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 792                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 793                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 794                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 795                                  radeon_connector->ddc_bus->rec.a_data_reg,
 796                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 797                                  radeon_connector->ddc_bus->rec.en_data_reg,
 798                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 799                                  radeon_connector->ddc_bus->rec.y_data_reg);
 800                         if (radeon_connector->router.ddc_valid)
 801                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 802                                          radeon_connector->router.ddc_mux_control_pin,
 803                                          radeon_connector->router.ddc_mux_state);
 804                         if (radeon_connector->router.cd_valid)
 805                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 806                                          radeon_connector->router.cd_mux_control_pin,
 807                                          radeon_connector->router.cd_mux_state);
 808                 } else {
 809                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 810                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 811                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 812                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 813                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 814                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 815                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 816                 }
 817                 DRM_INFO("  Encoders:\n");
 818                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 819                         radeon_encoder = to_radeon_encoder(encoder);
 820                         devices = radeon_encoder->devices & radeon_connector->devices;
 821                         if (devices) {
 822                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 823                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 824                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 825                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 826                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 827                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 828                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 829                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 830                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 831                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 832                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 833                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 834                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 835                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 836                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 837                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 838                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 839                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 840                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 841                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 842                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 843                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 844                         }
 845                 }
 846                 i++;
 847         }
 848 }
 849
 850 static bool radeon_setup_enc_conn(struct drm_device *dev)
 851 {
 852         struct radeon_device *rdev = dev->dev_private;
 853         bool ret = false;
 854
 855         if (rdev->bios) {
 856                 if (rdev->is_atom_bios) {
 857                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 858                         if (!ret)
 859                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 860                 } else {
 861                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 862                         if (!ret)
 863                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 864                 }
 865         } else {
 866                 if (!ASIC_IS_AVIVO(rdev))
 867                         ret = radeon_get_legacy_connector_info_from_table(dev);
 868         }
 869         if (ret) {
 870                 radeon_setup_encoder_clones(dev);
 871                 radeon_print_display_setup(dev);
 872         }
 873
 874         return ret;
 875 }
 876
 877 /* avivo */
 878
 879 /**
 880  * avivo_reduce_ratio - fractional number reduction
 881  *
 882  * @nom: nominator
 883  * @den: denominator
 884  * @nom_min: minimum value for nominator
 885  * @den_min: minimum value for denominator
 886  *
 887  * Find the greatest common divisor and apply it on both nominator and
 888  * denominator, but make nominator and denominator are at least as large
 889  * as their minimum values.
 890  */
 891 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 892                                unsigned nom_min, unsigned den_min)
 893 {
 894         unsigned tmp;
 895
 896         /* reduce the numbers to a simpler ratio */
 897         tmp = gcd(*nom, *den);
 898         *nom /= tmp;
 899         *den /= tmp;
 900
 901         /* make sure nominator is large enough */
 902         if (*nom < nom_min) {
 903                 tmp = DIV_ROUND_UP(nom_min, *nom);
 904                 *nom *= tmp;
 905                 *den *= tmp;
 906         }
 907
 908         /* make sure the denominator is large enough */
 909         if (*den < den_min) {
 910                 tmp = DIV_ROUND_UP(den_min, *den);
 911                 *nom *= tmp;
 912                 *den *= tmp;
 913         }
 914 }
 915
 916 /**
 917  * avivo_get_fb_ref_div - feedback and ref divider calculation
 918  *
 919  * @nom: nominator
 920  * @den: denominator
 921  * @post_div: post divider
 922  * @fb_div_max: feedback divider maximum
 923  * @ref_div_max: reference divider maximum
 924  * @fb_div: resulting feedback divider
 925  * @ref_div: resulting reference divider
 926  *
 927  * Calculate feedback and reference divider for a given post divider. Makes
 928  * sure we stay within the limits.
 929  */
 930 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 931                                  unsigned fb_div_max, unsigned ref_div_max,
 932                                  unsigned *fb_div, unsigned *ref_div)
 933 {
 934         /* limit reference * post divider to a maximum */
 935         ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
 936
 937         /* get matching reference and feedback divider */
 938         *ref_div = min(max(den/post_div, 1u), ref_div_max);
 939         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 940
 941         /* limit fb divider to its maximum */
 942         if (*fb_div > fb_div_max) {
 943                 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
 944                 *fb_div = fb_div_max;
 945         }
 946 }
 947
 948 /**
 949  * radeon_compute_pll_avivo - compute PLL paramaters
 950  *
 951  * @pll: information about the PLL
 952  * @freq: target frequency
 953  * @dot_clock_p: resulting pixel clock
 954  * @fb_div_p: resulting feedback divider
 955  * @frac_fb_div_p: fractional part of the feedback divider
 956  * @ref_div_p: resulting reference divider
 957  * @post_div_p: resulting reference divider
 958  *
 959  * Try to calculate the PLL parameters to generate the given frequency:
 960  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 961  */
 962 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 963                               u32 freq,
 964                               u32 *dot_clock_p,
 965                               u32 *fb_div_p,
 966                               u32 *frac_fb_div_p,
 967                               u32 *ref_div_p,
 968                               u32 *post_div_p)
 969 {
 970         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
 971                 freq : freq / 10;
 972
 973         unsigned fb_div_min, fb_div_max, fb_div;
 974         unsigned post_div_min, post_div_max, post_div;
 975         unsigned ref_div_min, ref_div_max, ref_div;
 976         unsigned post_div_best, diff_best;
 977         unsigned nom, den;
 978
 979         /* determine allowed feedback divider range */
 980         fb_div_min = pll->min_feedback_div;
 981         fb_div_max = pll->max_feedback_div;
 982
 983         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 984                 fb_div_min *= 10;
 985                 fb_div_max *= 10;
 986         }
 987
 988         /* determine allowed ref divider range */
 989         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 990                 ref_div_min = pll->reference_div;
 991         else
 992                 ref_div_min = pll->min_ref_div;
 993
 994         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
 995             pll->flags & RADEON_PLL_USE_REF_DIV)
 996                 ref_div_max = pll->reference_div;
 997         else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
 998                 /* fix for problems on RS880 */
 999                 ref_div_max = min(pll->max_ref_div, 7u);
1000         else
1001                 ref_div_max = pll->max_ref_div;
1002
1003         /* determine allowed post divider range */
1004         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1005                 post_div_min = pll->post_div;
1006                 post_div_max = pll->post_div;
1007         } else {
1008                 unsigned vco_min, vco_max;
1009
1010                 if (pll->flags & RADEON_PLL_IS_LCD) {
1011                         vco_min = pll->lcd_pll_out_min;
1012                         vco_max = pll->lcd_pll_out_max;
1013                 } else {
1014                         vco_min = pll->pll_out_min;
1015                         vco_max = pll->pll_out_max;
1016                 }
1017
1018                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1019                         vco_min *= 10;
1020                         vco_max *= 10;
1021                 }
1022
1023                 post_div_min = vco_min / target_clock;
1024                 if ((target_clock * post_div_min) < vco_min)
1025                         ++post_div_min;
1026                 if (post_div_min < pll->min_post_div)
1027                         post_div_min = pll->min_post_div;
1028
1029                 post_div_max = vco_max / target_clock;
1030                 if ((target_clock * post_div_max) > vco_max)
1031                         --post_div_max;
1032                 if (post_div_max > pll->max_post_div)
1033                         post_div_max = pll->max_post_div;
1034         }
1035
1036         /* represent the searched ratio as fractional number */
1037         nom = target_clock;
1038         den = pll->reference_freq;
1039
1040         /* reduce the numbers to a simpler ratio */
1041         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1042
1043         /* now search for a post divider */
1044         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1045                 post_div_best = post_div_min;
1046         else
1047                 post_div_best = post_div_max;
1048         diff_best = ~0;
1049
1050         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1051                 unsigned diff;
1052                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1053                                      ref_div_max, &fb_div, &ref_div);
1054                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1055                         (ref_div * post_div));
1056
1057                 if (diff < diff_best || (diff == diff_best &&
1058                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1059
1060                         post_div_best = post_div;
1061                         diff_best = diff;
1062                 }
1063         }
1064         post_div = post_div_best;
1065
1066         /* get the feedback and reference divider for the optimal value */
1067         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1068                              &fb_div, &ref_div);
1069
1070         /* reduce the numbers to a simpler ratio once more */
1071         /* this also makes sure that the reference divider is large enough */
1072         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1073
1074         /* avoid high jitter with small fractional dividers */
1075         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1076                 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1077                 if (fb_div < fb_div_min) {
1078                         unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1079                         fb_div *= tmp;
1080                         ref_div *= tmp;
1081                 }
1082         }
1083
1084         /* and finally save the result */
1085         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1086                 *fb_div_p = fb_div / 10;
1087                 *frac_fb_div_p = fb_div % 10;
1088         } else {
1089                 *fb_div_p = fb_div;
1090                 *frac_fb_div_p = 0;
1091         }
1092
1093         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1094                         (pll->reference_freq * *frac_fb_div_p)) /
1095                        (ref_div * post_div * 10);
1096         *ref_div_p = ref_div;
1097         *post_div_p = post_div;
1098
1099         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1100                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1101                       ref_div, post_div);
1102 }
1103
1104 /* pre-avivo */
1105 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1106 {
1107         n += d / 2;
1108
1109         do_div(n, d);
1110         return n;
1111 }
1112
1113 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1114                                uint64_t freq,
1115                                uint32_t *dot_clock_p,
1116                                uint32_t *fb_div_p,
1117                                uint32_t *frac_fb_div_p,
1118                                uint32_t *ref_div_p,
1119                                uint32_t *post_div_p)
1120 {
1121         uint32_t min_ref_div = pll->min_ref_div;
1122         uint32_t max_ref_div = pll->max_ref_div;
1123         uint32_t min_post_div = pll->min_post_div;
1124         uint32_t max_post_div = pll->max_post_div;
1125         uint32_t min_fractional_feed_div = 0;
1126         uint32_t max_fractional_feed_div = 0;
1127         uint32_t best_vco = pll->best_vco;
1128         uint32_t best_post_div = 1;
1129         uint32_t best_ref_div = 1;
1130         uint32_t best_feedback_div = 1;
1131         uint32_t best_frac_feedback_div = 0;
1132         uint32_t best_freq = -1;
1133         uint32_t best_error = 0xffffffff;
1134         uint32_t best_vco_diff = 1;
1135         uint32_t post_div;
1136         u32 pll_out_min, pll_out_max;
1137
1138         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1139         freq = freq * 1000;
1140
1141         if (pll->flags & RADEON_PLL_IS_LCD) {
1142                 pll_out_min = pll->lcd_pll_out_min;
1143                 pll_out_max = pll->lcd_pll_out_max;
1144         } else {
1145                 pll_out_min = pll->pll_out_min;
1146                 pll_out_max = pll->pll_out_max;
1147         }
1148
1149         if (pll_out_min > 64800)
1150                 pll_out_min = 64800;
1151
1152         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1153                 min_ref_div = max_ref_div = pll->reference_div;
1154         else {
1155                 while (min_ref_div < max_ref_div-1) {
1156                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1157                         uint32_t pll_in = pll->reference_freq / mid;
1158                         if (pll_in < pll->pll_in_min)
1159                                 max_ref_div = mid;
1160                         else if (pll_in > pll->pll_in_max)
1161                                 min_ref_div = mid;
1162                         else
1163                                 break;
1164                 }
1165         }
1166
1167         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1168                 min_post_div = max_post_div = pll->post_div;
1169
1170         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1171                 min_fractional_feed_div = pll->min_frac_feedback_div;
1172                 max_fractional_feed_div = pll->max_frac_feedback_div;
1173         }
1174
1175         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1176                 uint32_t ref_div;
1177
1178                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1179                         continue;
1180
1181                 /* legacy radeons only have a few post_divs */
1182                 if (pll->flags & RADEON_PLL_LEGACY) {
1183                         if ((post_div == 5) ||
1184                             (post_div == 7) ||
1185                             (post_div == 9) ||
1186                             (post_div == 10) ||
1187                             (post_div == 11) ||
1188                             (post_div == 13) ||
1189                             (post_div == 14) ||
1190                             (post_div == 15))
1191                                 continue;
1192                 }
1193
1194                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1195                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1196                         uint32_t pll_in = pll->reference_freq / ref_div;
1197                         uint32_t min_feed_div = pll->min_feedback_div;
1198                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1199
1200                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1201                                 continue;
1202
1203                         while (min_feed_div < max_feed_div) {
1204                                 uint32_t vco;
1205                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1206                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1207                                 uint32_t frac_feedback_div;
1208                                 uint64_t tmp;
1209
1210                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1211
1212                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1213                                 vco = radeon_div(tmp, ref_div);
1214
1215                                 if (vco < pll_out_min) {
1216                                         min_feed_div = feedback_div + 1;
1217                                         continue;
1218                                 } else if (vco > pll_out_max) {
1219                                         max_feed_div = feedback_div;
1220                                         continue;
1221                                 }
1222
1223                                 while (min_frac_feed_div < max_frac_feed_div) {
1224                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1225                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1226                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1227                                         current_freq = radeon_div(tmp, ref_div * post_div);
1228
1229                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1230                                                 if (freq < current_freq)
1231                                                         error = 0xffffffff;
1232                                                 else
1233                                                         error = freq - current_freq;
1234                                         } else
1235                                                 error = abs(current_freq - freq);
1236                                         vco_diff = abs(vco - best_vco);
1237
1238                                         if ((best_vco == 0 && error < best_error) ||
1239                                             (best_vco != 0 &&
1240                                              ((best_error > 100 && error < best_error - 100) ||
1241                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1242                                                 best_post_div = post_div;
1243                                                 best_ref_div = ref_div;
1244                                                 best_feedback_div = feedback_div;
1245                                                 best_frac_feedback_div = frac_feedback_div;
1246                                                 best_freq = current_freq;
1247                                                 best_error = error;
1248                                                 best_vco_diff = vco_diff;
1249                                         } else if (current_freq == freq) {
1250                                                 if (best_freq == -1) {
1251                                                         best_post_div = post_div;
1252                                                         best_ref_div = ref_div;
1253                                                         best_feedback_div = feedback_div;
1254                                                         best_frac_feedback_div = frac_feedback_div;
1255                                                         best_freq = current_freq;
1256                                                         best_error = error;
1257                                                         best_vco_diff = vco_diff;
1258                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1259                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1260                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1261                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1262                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1263                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1264                                                         best_post_div = post_div;
1265                                                         best_ref_div = ref_div;
1266                                                         best_feedback_div = feedback_div;
1267                                                         best_frac_feedback_div = frac_feedback_div;
1268                                                         best_freq = current_freq;
1269                                                         best_error = error;
1270                                                         best_vco_diff = vco_diff;
1271                                                 }
1272                                         }
1273                                         if (current_freq < freq)
1274                                                 min_frac_feed_div = frac_feedback_div + 1;
1275                                         else
1276                                                 max_frac_feed_div = frac_feedback_div;
1277                                 }
1278                                 if (current_freq < freq)
1279                                         min_feed_div = feedback_div + 1;
1280                                 else
1281                                         max_feed_div = feedback_div;
1282                         }
1283                 }
1284         }
1285
1286         *dot_clock_p = best_freq / 10000;
1287         *fb_div_p = best_feedback_div;
1288         *frac_fb_div_p = best_frac_feedback_div;
1289         *ref_div_p = best_ref_div;
1290         *post_div_p = best_post_div;
1291         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1292                       (long long)freq,
1293                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1294                       best_ref_div, best_post_div);
1295
1296 }
1297
1298 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1299         .destroy = drm_gem_fb_destroy,
1300         .create_handle = drm_gem_fb_create_handle,
1301 };
1302
1303 int
1304 radeon_framebuffer_init(struct drm_device *dev,
1305                         struct drm_framebuffer *fb,
1306                         const struct drm_mode_fb_cmd2 *mode_cmd,
1307                         struct drm_gem_object *obj)
1308 {
1309         int ret;
1310         fb->obj[0] = obj;
1311         drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd);
1312         ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs);
1313         if (ret) {
1314                 fb->obj[0] = NULL;
1315                 return ret;
1316         }
1317         return 0;
1318 }
1319
1320 static struct drm_framebuffer *
1321 radeon_user_framebuffer_create(struct drm_device *dev,
1322                                struct drm_file *file_priv,
1323                                const struct drm_mode_fb_cmd2 *mode_cmd)
1324 {
1325         struct drm_gem_object *obj;
1326         struct drm_framebuffer *fb;
1327         int ret;
1328
1329         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1330         if (obj ==  NULL) {
1331                 dev_err(dev->dev, "No GEM object associated to handle 0x%08X, "
1332                         "can't create framebuffer\n", mode_cmd->handles[0]);
1333                 return ERR_PTR(-ENOENT);
1334         }
1335
1336         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1337         if (obj->import_attach) {
1338                 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1339                 drm_gem_object_put(obj);
1340                 return ERR_PTR(-EINVAL);
1341         }
1342
1343         fb = kzalloc(sizeof(*fb), GFP_KERNEL);
1344         if (fb == NULL) {
1345                 drm_gem_object_put(obj);
1346                 return ERR_PTR(-ENOMEM);
1347         }
1348
1349         ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj);
1350         if (ret) {
1351                 kfree(fb);
1352                 drm_gem_object_put(obj);
1353                 return ERR_PTR(ret);
1354         }
1355
1356         return fb;
1357 }
1358
1359 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1360         .fb_create = radeon_user_framebuffer_create,
1361 };
1362
1363 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1364 {       { 0, "driver" },
1365         { 1, "bios" },
1366 };
1367
1368 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1369 {       { TV_STD_NTSC, "ntsc" },
1370         { TV_STD_PAL, "pal" },
1371         { TV_STD_PAL_M, "pal-m" },
1372         { TV_STD_PAL_60, "pal-60" },
1373         { TV_STD_NTSC_J, "ntsc-j" },
1374         { TV_STD_SCART_PAL, "scart-pal" },
1375         { TV_STD_PAL_CN, "pal-cn" },
1376         { TV_STD_SECAM, "secam" },
1377 };
1378
1379 static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1380 {       { UNDERSCAN_OFF, "off" },
1381         { UNDERSCAN_ON, "on" },
1382         { UNDERSCAN_AUTO, "auto" },
1383 };
1384
1385 static const struct drm_prop_enum_list radeon_audio_enum_list[] =
1386 {       { RADEON_AUDIO_DISABLE, "off" },
1387         { RADEON_AUDIO_ENABLE, "on" },
1388         { RADEON_AUDIO_AUTO, "auto" },
1389 };
1390
1391 /* XXX support different dither options? spatial, temporal, both, etc. */
1392 static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1393 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1394         { RADEON_FMT_DITHER_ENABLE, "on" },
1395 };
1396
1397 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1398 {       { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1399         { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1400         { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1401         { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1402 };
1403
1404 static int radeon_modeset_create_props(struct radeon_device *rdev)
1405 {
1406         int sz;
1407
1408         if (rdev->is_atom_bios) {
1409                 rdev->mode_info.coherent_mode_property =
1410                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1411                 if (!rdev->mode_info.coherent_mode_property)
1412                         return -ENOMEM;
1413         }
1414
1415         if (!ASIC_IS_AVIVO(rdev)) {
1416                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1417                 rdev->mode_info.tmds_pll_property =
1418                         drm_property_create_enum(rdev->ddev, 0,
1419                                             "tmds_pll",
1420                                             radeon_tmds_pll_enum_list, sz);
1421         }
1422
1423         rdev->mode_info.load_detect_property =
1424                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1425         if (!rdev->mode_info.load_detect_property)
1426                 return -ENOMEM;
1427
1428         drm_mode_create_scaling_mode_property(rdev->ddev);
1429
1430         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1431         rdev->mode_info.tv_std_property =
1432                 drm_property_create_enum(rdev->ddev, 0,
1433                                     "tv standard",
1434                                     radeon_tv_std_enum_list, sz);
1435
1436         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1437         rdev->mode_info.underscan_property =
1438                 drm_property_create_enum(rdev->ddev, 0,
1439                                     "underscan",
1440                                     radeon_underscan_enum_list, sz);
1441
1442         rdev->mode_info.underscan_hborder_property =
1443                 drm_property_create_range(rdev->ddev, 0,
1444                                         "underscan hborder", 0, 128);
1445         if (!rdev->mode_info.underscan_hborder_property)
1446                 return -ENOMEM;
1447
1448         rdev->mode_info.underscan_vborder_property =
1449                 drm_property_create_range(rdev->ddev, 0,
1450                                         "underscan vborder", 0, 128);
1451         if (!rdev->mode_info.underscan_vborder_property)
1452                 return -ENOMEM;
1453
1454         sz = ARRAY_SIZE(radeon_audio_enum_list);
1455         rdev->mode_info.audio_property =
1456                 drm_property_create_enum(rdev->ddev, 0,
1457                                          "audio",
1458                                          radeon_audio_enum_list, sz);
1459
1460         sz = ARRAY_SIZE(radeon_dither_enum_list);
1461         rdev->mode_info.dither_property =
1462                 drm_property_create_enum(rdev->ddev, 0,
1463                                          "dither",
1464                                          radeon_dither_enum_list, sz);
1465
1466         sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1467         rdev->mode_info.output_csc_property =
1468                 drm_property_create_enum(rdev->ddev, 0,
1469                                          "output_csc",
1470                                          radeon_output_csc_enum_list, sz);
1471
1472         return 0;
1473 }
1474
1475 void radeon_update_display_priority(struct radeon_device *rdev)
1476 {
1477         /* adjustment options for the display watermarks */
1478         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1479                 /* set display priority to high for r3xx, rv515 chips
1480                  * this avoids flickering due to underflow to the
1481                  * display controllers during heavy acceleration.
1482                  * Don't force high on rs4xx igp chips as it seems to
1483                  * affect the sound card.  See kernel bug 15982.
1484                  */
1485                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1486                     !(rdev->flags & RADEON_IS_IGP))
1487                         rdev->disp_priority = 2;
1488                 else
1489                         rdev->disp_priority = 0;
1490         } else
1491                 rdev->disp_priority = radeon_disp_priority;
1492
1493 }
1494
1495 /*
1496  * Allocate hdmi structs and determine register offsets
1497  */
1498 static void radeon_afmt_init(struct radeon_device *rdev)
1499 {
1500         int i;
1501
1502         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1503                 rdev->mode_info.afmt[i] = NULL;
1504
1505         if (ASIC_IS_NODCE(rdev)) {
1506                 /* nothing to do */
1507         } else if (ASIC_IS_DCE4(rdev)) {
1508                 static uint32_t eg_offsets[] = {
1509                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1510                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1511                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1512                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1513                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1514                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1515                         0x13830 - 0x7030,
1516                 };
1517                 int num_afmt;
1518
1519                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1520                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1521                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1522                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1523                 if (ASIC_IS_DCE8(rdev))
1524                         num_afmt = 7;
1525                 else if (ASIC_IS_DCE6(rdev))
1526                         num_afmt = 6;
1527                 else if (ASIC_IS_DCE5(rdev))
1528                         num_afmt = 6;
1529                 else if (ASIC_IS_DCE41(rdev))
1530                         num_afmt = 2;
1531                 else /* DCE4 */
1532                         num_afmt = 6;
1533
1534                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1535                 for (i = 0; i < num_afmt; i++) {
1536                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1537                         if (rdev->mode_info.afmt[i]) {
1538                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1539                                 rdev->mode_info.afmt[i]->id = i;
1540                         }
1541                 }
1542         } else if (ASIC_IS_DCE3(rdev)) {
1543                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1544                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1545                 if (rdev->mode_info.afmt[0]) {
1546                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1547                         rdev->mode_info.afmt[0]->id = 0;
1548                 }
1549                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1550                 if (rdev->mode_info.afmt[1]) {
1551                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1552                         rdev->mode_info.afmt[1]->id = 1;
1553                 }
1554         } else if (ASIC_IS_DCE2(rdev)) {
1555                 /* DCE2 has at least 1 routable audio block */
1556                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1557                 if (rdev->mode_info.afmt[0]) {
1558                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1559                         rdev->mode_info.afmt[0]->id = 0;
1560                 }
1561                 /* r6xx has 2 routable audio blocks */
1562                 if (rdev->family >= CHIP_R600) {
1563                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1564                         if (rdev->mode_info.afmt[1]) {
1565                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1566                                 rdev->mode_info.afmt[1]->id = 1;
1567                         }
1568                 }
1569         }
1570 }
1571
1572 static void radeon_afmt_fini(struct radeon_device *rdev)
1573 {
1574         int i;
1575
1576         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1577                 kfree(rdev->mode_info.afmt[i]);
1578                 rdev->mode_info.afmt[i] = NULL;
1579         }
1580 }
1581
1582 int radeon_modeset_init(struct radeon_device *rdev)
1583 {
1584         int i;
1585         int ret;
1586
1587         drm_mode_config_init(rdev->ddev);
1588         rdev->mode_info.mode_config_initialized = true;
1589
1590         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1591
1592         if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1593                 rdev->ddev->mode_config.async_page_flip = true;
1594
1595         if (ASIC_IS_DCE5(rdev)) {
1596                 rdev->ddev->mode_config.max_width = 16384;
1597                 rdev->ddev->mode_config.max_height = 16384;
1598         } else if (ASIC_IS_AVIVO(rdev)) {
1599                 rdev->ddev->mode_config.max_width = 8192;
1600                 rdev->ddev->mode_config.max_height = 8192;
1601         } else {
1602                 rdev->ddev->mode_config.max_width = 4096;
1603                 rdev->ddev->mode_config.max_height = 4096;
1604         }
1605
1606         rdev->ddev->mode_config.preferred_depth = 24;
1607         rdev->ddev->mode_config.prefer_shadow = 1;
1608
1609         rdev->ddev->mode_config.fb_modifiers_not_supported = true;
1610
1611         ret = radeon_modeset_create_props(rdev);
1612         if (ret) {
1613                 return ret;
1614         }
1615
1616         /* init i2c buses */
1617         radeon_i2c_init(rdev);
1618
1619         /* check combios for a valid hardcoded EDID - Sun servers */
1620         if (!rdev->is_atom_bios) {
1621                 /* check for hardcoded EDID in BIOS */
1622                 radeon_combios_check_hardcoded_edid(rdev);
1623         }
1624
1625         /* allocate crtcs */
1626         for (i = 0; i < rdev->num_crtc; i++) {
1627                 radeon_crtc_init(rdev->ddev, i);
1628         }
1629
1630         /* okay we should have all the bios connectors */
1631         ret = radeon_setup_enc_conn(rdev->ddev);
1632         if (!ret) {
1633                 return ret;
1634         }
1635
1636         /* init dig PHYs, disp eng pll */
1637         if (rdev->is_atom_bios) {
1638                 radeon_atom_encoder_init(rdev);
1639                 radeon_atom_disp_eng_pll_init(rdev);
1640         }
1641
1642         /* initialize hpd */
1643         radeon_hpd_init(rdev);
1644
1645         /* setup afmt */
1646         radeon_afmt_init(rdev);
1647
1648         drm_kms_helper_poll_init(rdev->ddev);
1649
1650         /* do pm late init */
1651         ret = radeon_pm_late_init(rdev);
1652
1653         return 0;
1654 }
1655
1656 void radeon_modeset_fini(struct radeon_device *rdev)
1657 {
1658         if (rdev->mode_info.mode_config_initialized) {
1659                 drm_kms_helper_poll_fini(rdev->ddev);
1660                 radeon_hpd_fini(rdev);
1661                 drm_helper_force_disable_all(rdev->ddev);
1662                 radeon_afmt_fini(rdev);
1663                 drm_mode_config_cleanup(rdev->ddev);
1664                 rdev->mode_info.mode_config_initialized = false;
1665         }
1666
1667         kfree(rdev->mode_info.bios_hardcoded_edid);
1668
1669         /* free i2c buses */
1670         radeon_i2c_fini(rdev);
1671 }
1672
1673 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1674 {
1675         /* try and guess if this is a tv or a monitor */
1676         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1677             (mode->vdisplay == 576) || /* 576p */
1678             (mode->vdisplay == 720) || /* 720p */
1679             (mode->vdisplay == 1080)) /* 1080p */
1680                 return true;
1681         else
1682                 return false;
1683 }
1684
1685 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1686                                 const struct drm_display_mode *mode,
1687                                 struct drm_display_mode *adjusted_mode)
1688 {
1689         struct drm_device *dev = crtc->dev;
1690         struct radeon_device *rdev = dev->dev_private;
1691         struct drm_encoder *encoder;
1692         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1693         struct radeon_encoder *radeon_encoder;
1694         struct drm_connector *connector;
1695         bool first = true;
1696         u32 src_v = 1, dst_v = 1;
1697         u32 src_h = 1, dst_h = 1;
1698
1699         radeon_crtc->h_border = 0;
1700         radeon_crtc->v_border = 0;
1701
1702         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1703                 if (encoder->crtc != crtc)
1704                         continue;
1705                 radeon_encoder = to_radeon_encoder(encoder);
1706                 connector = radeon_get_connector_for_encoder(encoder);
1707
1708                 if (first) {
1709                         /* set scaling */
1710                         if (radeon_encoder->rmx_type == RMX_OFF)
1711                                 radeon_crtc->rmx_type = RMX_OFF;
1712                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1713                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1714                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1715                         else
1716                                 radeon_crtc->rmx_type = RMX_OFF;
1717                         /* copy native mode */
1718                         memcpy(&radeon_crtc->native_mode,
1719                                &radeon_encoder->native_mode,
1720                                 sizeof(struct drm_display_mode));
1721                         src_v = crtc->mode.vdisplay;
1722                         dst_v = radeon_crtc->native_mode.vdisplay;
1723                         src_h = crtc->mode.hdisplay;
1724                         dst_h = radeon_crtc->native_mode.hdisplay;
1725
1726                         /* fix up for overscan on hdmi */
1727                         if (ASIC_IS_AVIVO(rdev) &&
1728                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1729                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1730                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1731                               drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1732                               is_hdtv_mode(mode)))) {
1733                                 if (radeon_encoder->underscan_hborder != 0)
1734                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1735                                 else
1736                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1737                                 if (radeon_encoder->underscan_vborder != 0)
1738                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1739                                 else
1740                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1741                                 radeon_crtc->rmx_type = RMX_FULL;
1742                                 src_v = crtc->mode.vdisplay;
1743                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1744                                 src_h = crtc->mode.hdisplay;
1745                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1746                         }
1747                         first = false;
1748                 } else {
1749                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1750                                 /* WARNING: Right now this can't happen but
1751                                  * in the future we need to check that scaling
1752                                  * are consistent across different encoder
1753                                  * (ie all encoder can work with the same
1754                                  *  scaling).
1755                                  */
1756                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1757                                 return false;
1758                         }
1759                 }
1760         }
1761         if (radeon_crtc->rmx_type != RMX_OFF) {
1762                 fixed20_12 a, b;
1763                 a.full = dfixed_const(src_v);
1764                 b.full = dfixed_const(dst_v);
1765                 radeon_crtc->vsc.full = dfixed_div(a, b);
1766                 a.full = dfixed_const(src_h);
1767                 b.full = dfixed_const(dst_h);
1768                 radeon_crtc->hsc.full = dfixed_div(a, b);
1769         } else {
1770                 radeon_crtc->vsc.full = dfixed_const(1);
1771                 radeon_crtc->hsc.full = dfixed_const(1);
1772         }
1773         return true;
1774 }
1775
1776 /*
1777  * Retrieve current video scanout position of crtc on a given gpu, and
1778  * an optional accurate timestamp of when query happened.
1779  *
1780  * \param dev Device to query.
1781  * \param crtc Crtc to query.
1782  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1783  *              For driver internal use only also supports these flags:
1784  *
1785  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1786  *              of a fudged earlier start of vblank.
1787  *
1788  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1789  *              fudged earlier start of vblank in *vpos and the distance
1790  *              to true start of vblank in *hpos.
1791  *
1792  * \param *vpos Location where vertical scanout position should be stored.
1793  * \param *hpos Location where horizontal scanout position should go.
1794  * \param *stime Target location for timestamp taken immediately before
1795  *               scanout position query. Can be NULL to skip timestamp.
1796  * \param *etime Target location for timestamp taken immediately after
1797  *               scanout position query. Can be NULL to skip timestamp.
1798  *
1799  * Returns vpos as a positive number while in active scanout area.
1800  * Returns vpos as a negative number inside vblank, counting the number
1801  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1802  * until start of active scanout / end of vblank."
1803  *
1804  * \return Flags, or'ed together as follows:
1805  *
1806  * DRM_SCANOUTPOS_VALID = Query successful.
1807  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1808  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1809  * this flag means that returned position may be offset by a constant but
1810  * unknown small number of scanlines wrt. real scanout position.
1811  *
1812  */
1813 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1814                                unsigned int flags, int *vpos, int *hpos,
1815                                ktime_t *stime, ktime_t *etime,
1816                                const struct drm_display_mode *mode)
1817 {
1818         u32 stat_crtc = 0, vbl = 0, position = 0;
1819         int vbl_start, vbl_end, vtotal, ret = 0;
1820         bool in_vbl = true;
1821
1822         struct radeon_device *rdev = dev->dev_private;
1823
1824         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1825
1826         /* Get optional system timestamp before query. */
1827         if (stime)
1828                 *stime = ktime_get();
1829
1830         if (ASIC_IS_DCE4(rdev)) {
1831                 if (pipe == 0) {
1832                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1833                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1834                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1835                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1836                         ret |= DRM_SCANOUTPOS_VALID;
1837                 }
1838                 if (pipe == 1) {
1839                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1840                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1841                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1842                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1843                         ret |= DRM_SCANOUTPOS_VALID;
1844                 }
1845                 if (pipe == 2) {
1846                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1847                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1848                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1849                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1850                         ret |= DRM_SCANOUTPOS_VALID;
1851                 }
1852                 if (pipe == 3) {
1853                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1854                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1855                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1856                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1857                         ret |= DRM_SCANOUTPOS_VALID;
1858                 }
1859                 if (pipe == 4) {
1860                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1861                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1862                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1863                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1864                         ret |= DRM_SCANOUTPOS_VALID;
1865                 }
1866                 if (pipe == 5) {
1867                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1868                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1869                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1870                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1871                         ret |= DRM_SCANOUTPOS_VALID;
1872                 }
1873         } else if (ASIC_IS_AVIVO(rdev)) {
1874                 if (pipe == 0) {
1875                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1876                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1877                         ret |= DRM_SCANOUTPOS_VALID;
1878                 }
1879                 if (pipe == 1) {
1880                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1881                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1882                         ret |= DRM_SCANOUTPOS_VALID;
1883                 }
1884         } else {
1885                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1886                 if (pipe == 0) {
1887                         /* Assume vbl_end == 0, get vbl_start from
1888                          * upper 16 bits.
1889                          */
1890                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1891                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1892                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1893                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1894                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1895                         if (!(stat_crtc & 1))
1896                                 in_vbl = false;
1897
1898                         ret |= DRM_SCANOUTPOS_VALID;
1899                 }
1900                 if (pipe == 1) {
1901                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1902                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1903                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1904                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1905                         if (!(stat_crtc & 1))
1906                                 in_vbl = false;
1907
1908                         ret |= DRM_SCANOUTPOS_VALID;
1909                 }
1910         }
1911
1912         /* Get optional system timestamp after query. */
1913         if (etime)
1914                 *etime = ktime_get();
1915
1916         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1917
1918         /* Decode into vertical and horizontal scanout position. */
1919         *vpos = position & 0x1fff;
1920         *hpos = (position >> 16) & 0x1fff;
1921
1922         /* Valid vblank area boundaries from gpu retrieved? */
1923         if (vbl > 0) {
1924                 /* Yes: Decode. */
1925                 ret |= DRM_SCANOUTPOS_ACCURATE;
1926                 vbl_start = vbl & 0x1fff;
1927                 vbl_end = (vbl >> 16) & 0x1fff;
1928         }
1929         else {
1930                 /* No: Fake something reasonable which gives at least ok results. */
1931                 vbl_start = mode->crtc_vdisplay;
1932                 vbl_end = 0;
1933         }
1934
1935         /* Called from driver internal vblank counter query code? */
1936         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1937             /* Caller wants distance from real vbl_start in *hpos */
1938             *hpos = *vpos - vbl_start;
1939         }
1940
1941         /* Fudge vblank to start a few scanlines earlier to handle the
1942          * problem that vblank irqs fire a few scanlines before start
1943          * of vblank. Some driver internal callers need the true vblank
1944          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1945          *
1946          * The cause of the "early" vblank irq is that the irq is triggered
1947          * by the line buffer logic when the line buffer read position enters
1948          * the vblank, whereas our crtc scanout position naturally lags the
1949          * line buffer read position.
1950          */
1951         if (!(flags & USE_REAL_VBLANKSTART))
1952                 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1953
1954         /* Test scanout position against vblank region. */
1955         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1956                 in_vbl = false;
1957
1958         /* In vblank? */
1959         if (in_vbl)
1960             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1961
1962         /* Called from driver internal vblank counter query code? */
1963         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1964                 /* Caller wants distance from fudged earlier vbl_start */
1965                 *vpos -= vbl_start;
1966                 return ret;
1967         }
1968
1969         /* Check if inside vblank area and apply corrective offsets:
1970          * vpos will then be >=0 in video scanout area, but negative
1971          * within vblank area, counting down the number of lines until
1972          * start of scanout.
1973          */
1974
1975         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1976         if (in_vbl && (*vpos >= vbl_start)) {
1977                 vtotal = mode->crtc_vtotal;
1978                 *vpos = *vpos - vtotal;
1979         }
1980
1981         /* Correct for shifted end of vbl at vbl_end. */
1982         *vpos = *vpos - vbl_end;
1983
1984         return ret;
1985 }
1986
1987 bool
1988 radeon_get_crtc_scanout_position(struct drm_crtc *crtc,
1989                                  bool in_vblank_irq, int *vpos, int *hpos,
1990                                  ktime_t *stime, ktime_t *etime,
1991                                  const struct drm_display_mode *mode)
1992 {
1993         struct drm_device *dev = crtc->dev;
1994         unsigned int pipe = crtc->index;
1995
1996         return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1997                                           stime, etime, mode);
1998 }