drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <linux/pci.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/gcd.h>
  30
  31 #include <asm/div64.h>
  32
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_device.h>
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_fourcc.h>
  39 #include <drm/drm_gem_framebuffer_helper.h>
  40 #include <drm/drm_plane_helper.h>
  41 #include <drm/drm_probe_helper.h>
  42 #include <drm/drm_vblank.h>
  43 #include <drm/radeon_drm.h>
  44
  45 #include "atom.h"
  46 #include "radeon.h"
  47 #include "radeon_kms.h"
  48
  49 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  50 {
  51         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  52         struct drm_device *dev = crtc->dev;
  53         struct radeon_device *rdev = dev->dev_private;
  54         u16 *r, *g, *b;
  55         int i;
  56
  57         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  58         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  59
  60         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  61         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  62         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  63
  64         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  65         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  66         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  67
  68         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  69         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  70         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  71
  72         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  73         r = crtc->gamma_store;
  74         g = r + crtc->gamma_size;
  75         b = g + crtc->gamma_size;
  76         for (i = 0; i < 256; i++) {
  77                 WREG32(AVIVO_DC_LUT_30_COLOR,
  78                        ((*r++ & 0xffc0) << 14) |
  79                        ((*g++ & 0xffc0) << 4) |
  80                        (*b++ >> 6));
  81         }
  82
  83         /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
  84         WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
  85 }
  86
  87 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  88 {
  89         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  90         struct drm_device *dev = crtc->dev;
  91         struct radeon_device *rdev = dev->dev_private;
  92         u16 *r, *g, *b;
  93         int i;
  94
  95         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  96         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  97
  98         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  99         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 100         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 101
 102         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 103         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 104         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 105
 106         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 107         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 108
 109         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 110         r = crtc->gamma_store;
 111         g = r + crtc->gamma_size;
 112         b = g + crtc->gamma_size;
 113         for (i = 0; i < 256; i++) {
 114                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 115                        ((*r++ & 0xffc0) << 14) |
 116                        ((*g++ & 0xffc0) << 4) |
 117                        (*b++ >> 6));
 118         }
 119 }
 120
 121 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 122 {
 123         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 124         struct drm_device *dev = crtc->dev;
 125         struct radeon_device *rdev = dev->dev_private;
 126         u16 *r, *g, *b;
 127         int i;
 128
 129         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 130
 131         msleep(10);
 132
 133         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 134                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 135                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 136         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 137                NI_GRPH_PRESCALE_BYPASS);
 138         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 139                NI_OVL_PRESCALE_BYPASS);
 140         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 141                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 142                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 143
 144         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 145
 146         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 147         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 148         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 149
 150         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 151         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 152         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 153
 154         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 155         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 156
 157         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 158         r = crtc->gamma_store;
 159         g = r + crtc->gamma_size;
 160         b = g + crtc->gamma_size;
 161         for (i = 0; i < 256; i++) {
 162                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 163                        ((*r++ & 0xffc0) << 14) |
 164                        ((*g++ & 0xffc0) << 4) |
 165                        (*b++ >> 6));
 166         }
 167
 168         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 169                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 170                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 171                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 172                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 173         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 174                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 175                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 176         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 177                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 178                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 179         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 180                (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
 181                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 182         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 183         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 184         if (ASIC_IS_DCE8(rdev)) {
 185                 /* XXX this only needs to be programmed once per crtc at startup,
 186                  * not sure where the best place for it is
 187                  */
 188                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 189                        CIK_CURSOR_ALPHA_BLND_ENA);
 190         }
 191 }
 192
 193 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 194 {
 195         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 196         struct drm_device *dev = crtc->dev;
 197         struct radeon_device *rdev = dev->dev_private;
 198         u16 *r, *g, *b;
 199         int i;
 200         uint32_t dac2_cntl;
 201
 202         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 203         if (radeon_crtc->crtc_id == 0)
 204                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 205         else
 206                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 207         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 208
 209         WREG8(RADEON_PALETTE_INDEX, 0);
 210         r = crtc->gamma_store;
 211         g = r + crtc->gamma_size;
 212         b = g + crtc->gamma_size;
 213         for (i = 0; i < 256; i++) {
 214                 WREG32(RADEON_PALETTE_30_DATA,
 215                        ((*r++ & 0xffc0) << 14) |
 216                        ((*g++ & 0xffc0) << 4) |
 217                        (*b++ >> 6));
 218         }
 219 }
 220
 221 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 222 {
 223         struct drm_device *dev = crtc->dev;
 224         struct radeon_device *rdev = dev->dev_private;
 225
 226         if (!crtc->enabled)
 227                 return;
 228
 229         if (ASIC_IS_DCE5(rdev))
 230                 dce5_crtc_load_lut(crtc);
 231         else if (ASIC_IS_DCE4(rdev))
 232                 dce4_crtc_load_lut(crtc);
 233         else if (ASIC_IS_AVIVO(rdev))
 234                 avivo_crtc_load_lut(crtc);
 235         else
 236                 legacy_crtc_load_lut(crtc);
 237 }
 238
 239 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 240                                  u16 *blue, uint32_t size,
 241                                  struct drm_modeset_acquire_ctx *ctx)
 242 {
 243         radeon_crtc_load_lut(crtc);
 244
 245         return 0;
 246 }
 247
 248 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 249 {
 250         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 251
 252         drm_crtc_cleanup(crtc);
 253         destroy_workqueue(radeon_crtc->flip_queue);
 254         kfree(radeon_crtc);
 255 }
 256
 257 /**
 258  * radeon_unpin_work_func - unpin old buffer object
 259  *
 260  * @__work: kernel work item
 261  *
 262  * Unpin the old frame buffer object outside of the interrupt handler
 263  */
 264 static void radeon_unpin_work_func(struct work_struct *__work)
 265 {
 266         struct radeon_flip_work *work =
 267                 container_of(__work, struct radeon_flip_work, unpin_work);
 268         int r;
 269
 270         /* unpin of the old buffer */
 271         r = radeon_bo_reserve(work->old_rbo, false);
 272         if (likely(r == 0)) {
 273                 radeon_bo_unpin(work->old_rbo);
 274                 radeon_bo_unreserve(work->old_rbo);
 275         } else
 276                 DRM_ERROR("failed to reserve buffer after flip\n");
 277
 278         drm_gem_object_put(&work->old_rbo->tbo.base);
 279         kfree(work);
 280 }
 281
 282 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
 283 {
 284         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 285         unsigned long flags;
 286         u32 update_pending;
 287         int vpos, hpos;
 288
 289         /* can happen during initialization */
 290         if (radeon_crtc == NULL)
 291                 return;
 292
 293         /* Skip the pageflip completion check below (based on polling) on
 294          * asics which reliably support hw pageflip completion irqs. pflip
 295          * irqs are a reliable and race-free method of handling pageflip
 296          * completion detection. A use_pflipirq module parameter < 2 allows
 297          * to override this in case of asics with faulty pflip irqs.
 298          * A module parameter of 0 would only use this polling based path,
 299          * a parameter of 1 would use pflip irq only as a backup to this
 300          * path, as in Linux 3.16.
 301          */
 302         if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
 303                 return;
 304
 305         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 306         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 307                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 308                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 309                                  radeon_crtc->flip_status,
 310                                  RADEON_FLIP_SUBMITTED);
 311                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 312                 return;
 313         }
 314
 315         update_pending = radeon_page_flip_pending(rdev, crtc_id);
 316
 317         /* Has the pageflip already completed in crtc, or is it certain
 318          * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
 319          * distance to start of "fudged earlier" vblank in vpos, distance to
 320          * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
 321          * the last few scanlines before start of real vblank, where the vblank
 322          * irq can fire, so we have sampled update_pending a bit too early and
 323          * know the flip will complete at leading edge of the upcoming real
 324          * vblank. On pre-AVIVO hardware, flips also complete inside the real
 325          * vblank, not only at leading edge, so if update_pending for hpos >= 0
 326          *  == inside real vblank, the flip will complete almost immediately.
 327          * Note that this method of completion handling is still not 100% race
 328          * free, as we could execute before the radeon_flip_work_func managed
 329          * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
 330          * but the flip still gets programmed into hw and completed during
 331          * vblank, leading to a delayed emission of the flip completion event.
 332          * This applies at least to pre-AVIVO hardware, where flips are always
 333          * completing inside vblank, not only at leading edge of vblank.
 334          */
 335         if (update_pending &&
 336             (DRM_SCANOUTPOS_VALID &
 337              radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 338                                         GET_DISTANCE_TO_VBLANKSTART,
 339                                         &vpos, &hpos, NULL, NULL,
 340                                         &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
 341             ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
 342                 /* crtc didn't flip in this target vblank interval,
 343                  * but flip is pending in crtc. Based on the current
 344                  * scanout position we know that the current frame is
 345                  * (nearly) complete and the flip will (likely)
 346                  * complete before the start of the next frame.
 347                  */
 348                 update_pending = 0;
 349         }
 350         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 351         if (!update_pending)
 352                 radeon_crtc_handle_flip(rdev, crtc_id);
 353 }
 354
 355 /**
 356  * radeon_crtc_handle_flip - page flip completed
 357  *
 358  * @rdev: radeon device pointer
 359  * @crtc_id: crtc number this event is for
 360  *
 361  * Called when we are sure that a page flip for this crtc is completed.
 362  */
 363 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 364 {
 365         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 366         struct radeon_flip_work *work;
 367         unsigned long flags;
 368
 369         /* this can happen at init */
 370         if (radeon_crtc == NULL)
 371                 return;
 372
 373         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 374         work = radeon_crtc->flip_work;
 375         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 376                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 377                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 378                                  radeon_crtc->flip_status,
 379                                  RADEON_FLIP_SUBMITTED);
 380                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 381                 return;
 382         }
 383
 384         /* Pageflip completed. Clean up. */
 385         radeon_crtc->flip_status = RADEON_FLIP_NONE;
 386         radeon_crtc->flip_work = NULL;
 387
 388         /* wakeup userspace */
 389         if (work->event)
 390                 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
 391
 392         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 393
 394         drm_crtc_vblank_put(&radeon_crtc->base);
 395         radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
 396         queue_work(radeon_crtc->flip_queue, &work->unpin_work);
 397 }
 398
 399 /**
 400  * radeon_flip_work_func - page flip framebuffer
 401  *
 402  * @__work: kernel work item
 403  *
 404  * Wait for the buffer object to become idle and do the actual page flip
 405  */
 406 static void radeon_flip_work_func(struct work_struct *__work)
 407 {
 408         struct radeon_flip_work *work =
 409                 container_of(__work, struct radeon_flip_work, flip_work);
 410         struct radeon_device *rdev = work->rdev;
 411         struct drm_device *dev = rdev->ddev;
 412         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
 413
 414         struct drm_crtc *crtc = &radeon_crtc->base;
 415         unsigned long flags;
 416         int r;
 417         int vpos, hpos;
 418
 419         down_read(&rdev->exclusive_lock);
 420         if (work->fence) {
 421                 struct radeon_fence *fence;
 422
 423                 fence = to_radeon_fence(work->fence);
 424                 if (fence && fence->rdev == rdev) {
 425                         r = radeon_fence_wait(fence, false);
 426                         if (r == -EDEADLK) {
 427                                 up_read(&rdev->exclusive_lock);
 428                                 do {
 429                                         r = radeon_gpu_reset(rdev);
 430                                 } while (r == -EAGAIN);
 431                                 down_read(&rdev->exclusive_lock);
 432                         }
 433                 } else
 434                         r = dma_fence_wait(work->fence, false);
 435
 436                 if (r)
 437                         DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
 438
 439                 /* We continue with the page flip even if we failed to wait on
 440                  * the fence, otherwise the DRM core and userspace will be
 441                  * confused about which BO the CRTC is scanning out
 442                  */
 443
 444                 dma_fence_put(work->fence);
 445                 work->fence = NULL;
 446         }
 447
 448         /* Wait until we're out of the vertical blank period before the one
 449          * targeted by the flip. Always wait on pre DCE4 to avoid races with
 450          * flip completion handling from vblank irq, as these old asics don't
 451          * have reliable pageflip completion interrupts.
 452          */
 453         while (radeon_crtc->enabled &&
 454                 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
 455                                             &vpos, &hpos, NULL, NULL,
 456                                             &crtc->hwmode)
 457                 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 458                 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 459                 (!ASIC_IS_AVIVO(rdev) ||
 460                 ((int) (work->target_vblank -
 461                 crtc->funcs->get_vblank_counter(crtc)) > 0)))
 462                 usleep_range(1000, 2000);
 463
 464         /* We borrow the event spin lock for protecting flip_status */
 465         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 466
 467         /* set the proper interrupt */
 468         radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
 469
 470         /* do the flip (mmio) */
 471         radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
 472
 473         radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
 474         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 475         up_read(&rdev->exclusive_lock);
 476 }
 477
 478 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
 479                                         struct drm_framebuffer *fb,
 480                                         struct drm_pending_vblank_event *event,
 481                                         uint32_t page_flip_flags,
 482                                         uint32_t target,
 483                                         struct drm_modeset_acquire_ctx *ctx)
 484 {
 485         struct drm_device *dev = crtc->dev;
 486         struct radeon_device *rdev = dev->dev_private;
 487         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 488         struct drm_gem_object *obj;
 489         struct radeon_flip_work *work;
 490         struct radeon_bo *new_rbo;
 491         uint32_t tiling_flags, pitch_pixels;
 492         uint64_t base;
 493         unsigned long flags;
 494         int r;
 495
 496         work = kzalloc(sizeof *work, GFP_KERNEL);
 497         if (work == NULL)
 498                 return -ENOMEM;
 499
 500         INIT_WORK(&work->flip_work, radeon_flip_work_func);
 501         INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
 502
 503         work->rdev = rdev;
 504         work->crtc_id = radeon_crtc->crtc_id;
 505         work->event = event;
 506         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 507
 508         /* schedule unpin of the old buffer */
 509         obj = crtc->primary->fb->obj[0];
 510
 511         /* take a reference to the old object */
 512         drm_gem_object_get(obj);
 513         work->old_rbo = gem_to_radeon_bo(obj);
 514
 515         obj = fb->obj[0];
 516         new_rbo = gem_to_radeon_bo(obj);
 517
 518         /* pin the new buffer */
 519         DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
 520                          work->old_rbo, new_rbo);
 521
 522         r = radeon_bo_reserve(new_rbo, false);
 523         if (unlikely(r != 0)) {
 524                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 525                 goto cleanup;
 526         }
 527         /* Only 27 bit offset for legacy CRTC */
 528         r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
 529                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 530         if (unlikely(r != 0)) {
 531                 radeon_bo_unreserve(new_rbo);
 532                 r = -EINVAL;
 533                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 534                 goto cleanup;
 535         }
 536         r = dma_resv_get_singleton(new_rbo->tbo.base.resv, false, &work->fence);
 537         if (r) {
 538                 radeon_bo_unreserve(new_rbo);
 539                 DRM_ERROR("failed to get new rbo buffer fences\n");
 540                 goto cleanup;
 541         }
 542         radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
 543         radeon_bo_unreserve(new_rbo);
 544
 545         if (!ASIC_IS_AVIVO(rdev)) {
 546                 /* crtc offset is from display base addr not FB location */
 547                 base -= radeon_crtc->legacy_display_base_addr;
 548                 pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
 549
 550                 if (tiling_flags & RADEON_TILING_MACRO) {
 551                         if (ASIC_IS_R300(rdev)) {
 552                                 base &= ~0x7ff;
 553                         } else {
 554                                 int byteshift = fb->format->cpp[0] * 8 >> 4;
 555                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 556                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 557                         }
 558                 } else {
 559                         int offset = crtc->y * pitch_pixels + crtc->x;
 560                         switch (fb->format->cpp[0] * 8) {
 561                         case 8:
 562                         default:
 563                                 offset *= 1;
 564                                 break;
 565                         case 15:
 566                         case 16:
 567                                 offset *= 2;
 568                                 break;
 569                         case 24:
 570                                 offset *= 3;
 571                                 break;
 572                         case 32:
 573                                 offset *= 4;
 574                                 break;
 575                         }
 576                         base += offset;
 577                 }
 578                 base &= ~7;
 579         }
 580         work->base = base;
 581         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 582                 crtc->funcs->get_vblank_counter(crtc);
 583
 584         /* We borrow the event spin lock for protecting flip_work */
 585         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 586
 587         if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
 588                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 589                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 590                 r = -EBUSY;
 591                 goto pflip_cleanup;
 592         }
 593         radeon_crtc->flip_status = RADEON_FLIP_PENDING;
 594         radeon_crtc->flip_work = work;
 595
 596         /* update crtc fb */
 597         crtc->primary->fb = fb;
 598
 599         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 600
 601         queue_work(radeon_crtc->flip_queue, &work->flip_work);
 602         return 0;
 603
 604 pflip_cleanup:
 605         if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
 606                 DRM_ERROR("failed to reserve new rbo in error path\n");
 607                 goto cleanup;
 608         }
 609         radeon_bo_unpin(new_rbo);
 610         radeon_bo_unreserve(new_rbo);
 611
 612 cleanup:
 613         drm_gem_object_put(&work->old_rbo->tbo.base);
 614         dma_fence_put(work->fence);
 615         kfree(work);
 616         return r;
 617 }
 618
 619 static int
 620 radeon_crtc_set_config(struct drm_mode_set *set,
 621                        struct drm_modeset_acquire_ctx *ctx)
 622 {
 623         struct drm_device *dev;
 624         struct radeon_device *rdev;
 625         struct drm_crtc *crtc;
 626         bool active = false;
 627         int ret;
 628
 629         if (!set || !set->crtc)
 630                 return -EINVAL;
 631
 632         dev = set->crtc->dev;
 633
 634         ret = pm_runtime_get_sync(dev->dev);
 635         if (ret < 0) {
 636                 pm_runtime_put_autosuspend(dev->dev);
 637                 return ret;
 638         }
 639
 640         ret = drm_crtc_helper_set_config(set, ctx);
 641
 642         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 643                 if (crtc->enabled)
 644                         active = true;
 645
 646         pm_runtime_mark_last_busy(dev->dev);
 647
 648         rdev = dev->dev_private;
 649         /* if we have active crtcs and we don't have a power ref,
 650            take the current one */
 651         if (active && !rdev->have_disp_power_ref) {
 652                 rdev->have_disp_power_ref = true;
 653                 return ret;
 654         }
 655         /* if we have no active crtcs, then drop the power ref
 656            we got before */
 657         if (!active && rdev->have_disp_power_ref) {
 658                 pm_runtime_put_autosuspend(dev->dev);
 659                 rdev->have_disp_power_ref = false;
 660         }
 661
 662         /* drop the power reference we got coming in here */
 663         pm_runtime_put_autosuspend(dev->dev);
 664         return ret;
 665 }
 666
 667 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 668         .cursor_set2 = radeon_crtc_cursor_set2,
 669         .cursor_move = radeon_crtc_cursor_move,
 670         .gamma_set = radeon_crtc_gamma_set,
 671         .set_config = radeon_crtc_set_config,
 672         .destroy = radeon_crtc_destroy,
 673         .page_flip_target = radeon_crtc_page_flip_target,
 674         .get_vblank_counter = radeon_get_vblank_counter_kms,
 675         .enable_vblank = radeon_enable_vblank_kms,
 676         .disable_vblank = radeon_disable_vblank_kms,
 677         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
 678 };
 679
 680 static void radeon_crtc_init(struct drm_device *dev, int index)
 681 {
 682         struct radeon_device *rdev = dev->dev_private;
 683         struct radeon_crtc *radeon_crtc;
 684
 685         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 686         if (radeon_crtc == NULL)
 687                 return;
 688
 689         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 690
 691         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 692         radeon_crtc->crtc_id = index;
 693         radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
 694         rdev->mode_info.crtcs[index] = radeon_crtc;
 695
 696         if (rdev->family >= CHIP_BONAIRE) {
 697                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 698                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 699         } else {
 700                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 701                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 702         }
 703         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 704         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 705
 706 #if 0
 707         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 708         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 709         radeon_crtc->mode_set.num_connectors = 0;
 710 #endif
 711
 712         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 713                 radeon_atombios_init_crtc(dev, radeon_crtc);
 714         else
 715                 radeon_legacy_init_crtc(dev, radeon_crtc);
 716 }
 717
 718 static const char *encoder_names[38] = {
 719         "NONE",
 720         "INTERNAL_LVDS",
 721         "INTERNAL_TMDS1",
 722         "INTERNAL_TMDS2",
 723         "INTERNAL_DAC1",
 724         "INTERNAL_DAC2",
 725         "INTERNAL_SDVOA",
 726         "INTERNAL_SDVOB",
 727         "SI170B",
 728         "CH7303",
 729         "CH7301",
 730         "INTERNAL_DVO1",
 731         "EXTERNAL_SDVOA",
 732         "EXTERNAL_SDVOB",
 733         "TITFP513",
 734         "INTERNAL_LVTM1",
 735         "VT1623",
 736         "HDMI_SI1930",
 737         "HDMI_INTERNAL",
 738         "INTERNAL_KLDSCP_TMDS1",
 739         "INTERNAL_KLDSCP_DVO1",
 740         "INTERNAL_KLDSCP_DAC1",
 741         "INTERNAL_KLDSCP_DAC2",
 742         "SI178",
 743         "MVPU_FPGA",
 744         "INTERNAL_DDI",
 745         "VT1625",
 746         "HDMI_SI1932",
 747         "DP_AN9801",
 748         "DP_DP501",
 749         "INTERNAL_UNIPHY",
 750         "INTERNAL_KLDSCP_LVTMA",
 751         "INTERNAL_UNIPHY1",
 752         "INTERNAL_UNIPHY2",
 753         "NUTMEG",
 754         "TRAVIS",
 755         "INTERNAL_VCE",
 756         "INTERNAL_UNIPHY3",
 757 };
 758
 759 static const char *hpd_names[6] = {
 760         "HPD1",
 761         "HPD2",
 762         "HPD3",
 763         "HPD4",
 764         "HPD5",
 765         "HPD6",
 766 };
 767
 768 static void radeon_print_display_setup(struct drm_device *dev)
 769 {
 770         struct drm_connector *connector;
 771         struct radeon_connector *radeon_connector;
 772         struct drm_encoder *encoder;
 773         struct radeon_encoder *radeon_encoder;
 774         uint32_t devices;
 775         int i = 0;
 776
 777         DRM_INFO("Radeon Display Connectors\n");
 778         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 779                 radeon_connector = to_radeon_connector(connector);
 780                 DRM_INFO("Connector %d:\n", i);
 781                 DRM_INFO("  %s\n", connector->name);
 782                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 783                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 784                 if (radeon_connector->ddc_bus) {
 785                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 786                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 787                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 788                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 789                                  radeon_connector->ddc_bus->rec.a_data_reg,
 790                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 791                                  radeon_connector->ddc_bus->rec.en_data_reg,
 792                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 793                                  radeon_connector->ddc_bus->rec.y_data_reg);
 794                         if (radeon_connector->router.ddc_valid)
 795                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 796                                          radeon_connector->router.ddc_mux_control_pin,
 797                                          radeon_connector->router.ddc_mux_state);
 798                         if (radeon_connector->router.cd_valid)
 799                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 800                                          radeon_connector->router.cd_mux_control_pin,
 801                                          radeon_connector->router.cd_mux_state);
 802                 } else {
 803                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 804                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 805                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 806                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 807                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 808                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 809                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 810                 }
 811                 DRM_INFO("  Encoders:\n");
 812                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 813                         radeon_encoder = to_radeon_encoder(encoder);
 814                         devices = radeon_encoder->devices & radeon_connector->devices;
 815                         if (devices) {
 816                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 817                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 818                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 819                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 820                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 821                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 822                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 823                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 824                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 825                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 826                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 827                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 828                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 829                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 830                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 831                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 832                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 833                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 834                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 835                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 836                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 837                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 838                         }
 839                 }
 840                 i++;
 841         }
 842 }
 843
 844 static bool radeon_setup_enc_conn(struct drm_device *dev)
 845 {
 846         struct radeon_device *rdev = dev->dev_private;
 847         bool ret = false;
 848
 849         if (rdev->bios) {
 850                 if (rdev->is_atom_bios) {
 851                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 852                         if (!ret)
 853                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 854                 } else {
 855                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 856                         if (!ret)
 857                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 858                 }
 859         } else {
 860                 if (!ASIC_IS_AVIVO(rdev))
 861                         ret = radeon_get_legacy_connector_info_from_table(dev);
 862         }
 863         if (ret) {
 864                 radeon_setup_encoder_clones(dev);
 865                 radeon_print_display_setup(dev);
 866         }
 867
 868         return ret;
 869 }
 870
 871 /* avivo */
 872
 873 /**
 874  * avivo_reduce_ratio - fractional number reduction
 875  *
 876  * @nom: nominator
 877  * @den: denominator
 878  * @nom_min: minimum value for nominator
 879  * @den_min: minimum value for denominator
 880  *
 881  * Find the greatest common divisor and apply it on both nominator and
 882  * denominator, but make nominator and denominator are at least as large
 883  * as their minimum values.
 884  */
 885 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 886                                unsigned nom_min, unsigned den_min)
 887 {
 888         unsigned tmp;
 889
 890         /* reduce the numbers to a simpler ratio */
 891         tmp = gcd(*nom, *den);
 892         *nom /= tmp;
 893         *den /= tmp;
 894
 895         /* make sure nominator is large enough */
 896         if (*nom < nom_min) {
 897                 tmp = DIV_ROUND_UP(nom_min, *nom);
 898                 *nom *= tmp;
 899                 *den *= tmp;
 900         }
 901
 902         /* make sure the denominator is large enough */
 903         if (*den < den_min) {
 904                 tmp = DIV_ROUND_UP(den_min, *den);
 905                 *nom *= tmp;
 906                 *den *= tmp;
 907         }
 908 }
 909
 910 /**
 911  * avivo_get_fb_ref_div - feedback and ref divider calculation
 912  *
 913  * @nom: nominator
 914  * @den: denominator
 915  * @post_div: post divider
 916  * @fb_div_max: feedback divider maximum
 917  * @ref_div_max: reference divider maximum
 918  * @fb_div: resulting feedback divider
 919  * @ref_div: resulting reference divider
 920  *
 921  * Calculate feedback and reference divider for a given post divider. Makes
 922  * sure we stay within the limits.
 923  */
 924 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 925                                  unsigned fb_div_max, unsigned ref_div_max,
 926                                  unsigned *fb_div, unsigned *ref_div)
 927 {
 928         /* limit reference * post divider to a maximum */
 929         ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
 930
 931         /* get matching reference and feedback divider */
 932         *ref_div = min(max(den/post_div, 1u), ref_div_max);
 933         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 934
 935         /* limit fb divider to its maximum */
 936         if (*fb_div > fb_div_max) {
 937                 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
 938                 *fb_div = fb_div_max;
 939         }
 940 }
 941
 942 /**
 943  * radeon_compute_pll_avivo - compute PLL paramaters
 944  *
 945  * @pll: information about the PLL
 946  * @freq: target frequency
 947  * @dot_clock_p: resulting pixel clock
 948  * @fb_div_p: resulting feedback divider
 949  * @frac_fb_div_p: fractional part of the feedback divider
 950  * @ref_div_p: resulting reference divider
 951  * @post_div_p: resulting reference divider
 952  *
 953  * Try to calculate the PLL parameters to generate the given frequency:
 954  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 955  */
 956 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 957                               u32 freq,
 958                               u32 *dot_clock_p,
 959                               u32 *fb_div_p,
 960                               u32 *frac_fb_div_p,
 961                               u32 *ref_div_p,
 962                               u32 *post_div_p)
 963 {
 964         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
 965                 freq : freq / 10;
 966
 967         unsigned fb_div_min, fb_div_max, fb_div;
 968         unsigned post_div_min, post_div_max, post_div;
 969         unsigned ref_div_min, ref_div_max, ref_div;
 970         unsigned post_div_best, diff_best;
 971         unsigned nom, den;
 972
 973         /* determine allowed feedback divider range */
 974         fb_div_min = pll->min_feedback_div;
 975         fb_div_max = pll->max_feedback_div;
 976
 977         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 978                 fb_div_min *= 10;
 979                 fb_div_max *= 10;
 980         }
 981
 982         /* determine allowed ref divider range */
 983         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 984                 ref_div_min = pll->reference_div;
 985         else
 986                 ref_div_min = pll->min_ref_div;
 987
 988         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
 989             pll->flags & RADEON_PLL_USE_REF_DIV)
 990                 ref_div_max = pll->reference_div;
 991         else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
 992                 /* fix for problems on RS880 */
 993                 ref_div_max = min(pll->max_ref_div, 7u);
 994         else
 995                 ref_div_max = pll->max_ref_div;
 996
 997         /* determine allowed post divider range */
 998         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 999                 post_div_min = pll->post_div;
1000                 post_div_max = pll->post_div;
1001         } else {
1002                 unsigned vco_min, vco_max;
1003
1004                 if (pll->flags & RADEON_PLL_IS_LCD) {
1005                         vco_min = pll->lcd_pll_out_min;
1006                         vco_max = pll->lcd_pll_out_max;
1007                 } else {
1008                         vco_min = pll->pll_out_min;
1009                         vco_max = pll->pll_out_max;
1010                 }
1011
1012                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1013                         vco_min *= 10;
1014                         vco_max *= 10;
1015                 }
1016
1017                 post_div_min = vco_min / target_clock;
1018                 if ((target_clock * post_div_min) < vco_min)
1019                         ++post_div_min;
1020                 if (post_div_min < pll->min_post_div)
1021                         post_div_min = pll->min_post_div;
1022
1023                 post_div_max = vco_max / target_clock;
1024                 if ((target_clock * post_div_max) > vco_max)
1025                         --post_div_max;
1026                 if (post_div_max > pll->max_post_div)
1027                         post_div_max = pll->max_post_div;
1028         }
1029
1030         /* represent the searched ratio as fractional number */
1031         nom = target_clock;
1032         den = pll->reference_freq;
1033
1034         /* reduce the numbers to a simpler ratio */
1035         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1036
1037         /* now search for a post divider */
1038         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1039                 post_div_best = post_div_min;
1040         else
1041                 post_div_best = post_div_max;
1042         diff_best = ~0;
1043
1044         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1045                 unsigned diff;
1046                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1047                                      ref_div_max, &fb_div, &ref_div);
1048                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1049                         (ref_div * post_div));
1050
1051                 if (diff < diff_best || (diff == diff_best &&
1052                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1053
1054                         post_div_best = post_div;
1055                         diff_best = diff;
1056                 }
1057         }
1058         post_div = post_div_best;
1059
1060         /* get the feedback and reference divider for the optimal value */
1061         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1062                              &fb_div, &ref_div);
1063
1064         /* reduce the numbers to a simpler ratio once more */
1065         /* this also makes sure that the reference divider is large enough */
1066         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1067
1068         /* avoid high jitter with small fractional dividers */
1069         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1070                 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1071                 if (fb_div < fb_div_min) {
1072                         unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1073                         fb_div *= tmp;
1074                         ref_div *= tmp;
1075                 }
1076         }
1077
1078         /* and finally save the result */
1079         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1080                 *fb_div_p = fb_div / 10;
1081                 *frac_fb_div_p = fb_div % 10;
1082         } else {
1083                 *fb_div_p = fb_div;
1084                 *frac_fb_div_p = 0;
1085         }
1086
1087         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1088                         (pll->reference_freq * *frac_fb_div_p)) /
1089                        (ref_div * post_div * 10);
1090         *ref_div_p = ref_div;
1091         *post_div_p = post_div;
1092
1093         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1094                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1095                       ref_div, post_div);
1096 }
1097
1098 /* pre-avivo */
1099 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1100 {
1101         n += d / 2;
1102
1103         do_div(n, d);
1104         return n;
1105 }
1106
1107 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1108                                uint64_t freq,
1109                                uint32_t *dot_clock_p,
1110                                uint32_t *fb_div_p,
1111                                uint32_t *frac_fb_div_p,
1112                                uint32_t *ref_div_p,
1113                                uint32_t *post_div_p)
1114 {
1115         uint32_t min_ref_div = pll->min_ref_div;
1116         uint32_t max_ref_div = pll->max_ref_div;
1117         uint32_t min_post_div = pll->min_post_div;
1118         uint32_t max_post_div = pll->max_post_div;
1119         uint32_t min_fractional_feed_div = 0;
1120         uint32_t max_fractional_feed_div = 0;
1121         uint32_t best_vco = pll->best_vco;
1122         uint32_t best_post_div = 1;
1123         uint32_t best_ref_div = 1;
1124         uint32_t best_feedback_div = 1;
1125         uint32_t best_frac_feedback_div = 0;
1126         uint32_t best_freq = -1;
1127         uint32_t best_error = 0xffffffff;
1128         uint32_t best_vco_diff = 1;
1129         uint32_t post_div;
1130         u32 pll_out_min, pll_out_max;
1131
1132         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1133         freq = freq * 1000;
1134
1135         if (pll->flags & RADEON_PLL_IS_LCD) {
1136                 pll_out_min = pll->lcd_pll_out_min;
1137                 pll_out_max = pll->lcd_pll_out_max;
1138         } else {
1139                 pll_out_min = pll->pll_out_min;
1140                 pll_out_max = pll->pll_out_max;
1141         }
1142
1143         if (pll_out_min > 64800)
1144                 pll_out_min = 64800;
1145
1146         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1147                 min_ref_div = max_ref_div = pll->reference_div;
1148         else {
1149                 while (min_ref_div < max_ref_div-1) {
1150                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1151                         uint32_t pll_in = pll->reference_freq / mid;
1152                         if (pll_in < pll->pll_in_min)
1153                                 max_ref_div = mid;
1154                         else if (pll_in > pll->pll_in_max)
1155                                 min_ref_div = mid;
1156                         else
1157                                 break;
1158                 }
1159         }
1160
1161         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1162                 min_post_div = max_post_div = pll->post_div;
1163
1164         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1165                 min_fractional_feed_div = pll->min_frac_feedback_div;
1166                 max_fractional_feed_div = pll->max_frac_feedback_div;
1167         }
1168
1169         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1170                 uint32_t ref_div;
1171
1172                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1173                         continue;
1174
1175                 /* legacy radeons only have a few post_divs */
1176                 if (pll->flags & RADEON_PLL_LEGACY) {
1177                         if ((post_div == 5) ||
1178                             (post_div == 7) ||
1179                             (post_div == 9) ||
1180                             (post_div == 10) ||
1181                             (post_div == 11) ||
1182                             (post_div == 13) ||
1183                             (post_div == 14) ||
1184                             (post_div == 15))
1185                                 continue;
1186                 }
1187
1188                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1189                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1190                         uint32_t pll_in = pll->reference_freq / ref_div;
1191                         uint32_t min_feed_div = pll->min_feedback_div;
1192                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1193
1194                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1195                                 continue;
1196
1197                         while (min_feed_div < max_feed_div) {
1198                                 uint32_t vco;
1199                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1200                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1201                                 uint32_t frac_feedback_div;
1202                                 uint64_t tmp;
1203
1204                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1205
1206                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1207                                 vco = radeon_div(tmp, ref_div);
1208
1209                                 if (vco < pll_out_min) {
1210                                         min_feed_div = feedback_div + 1;
1211                                         continue;
1212                                 } else if (vco > pll_out_max) {
1213                                         max_feed_div = feedback_div;
1214                                         continue;
1215                                 }
1216
1217                                 while (min_frac_feed_div < max_frac_feed_div) {
1218                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1219                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1220                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1221                                         current_freq = radeon_div(tmp, ref_div * post_div);
1222
1223                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1224                                                 if (freq < current_freq)
1225                                                         error = 0xffffffff;
1226                                                 else
1227                                                         error = freq - current_freq;
1228                                         } else
1229                                                 error = abs(current_freq - freq);
1230                                         vco_diff = abs(vco - best_vco);
1231
1232                                         if ((best_vco == 0 && error < best_error) ||
1233                                             (best_vco != 0 &&
1234                                              ((best_error > 100 && error < best_error - 100) ||
1235                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1236                                                 best_post_div = post_div;
1237                                                 best_ref_div = ref_div;
1238                                                 best_feedback_div = feedback_div;
1239                                                 best_frac_feedback_div = frac_feedback_div;
1240                                                 best_freq = current_freq;
1241                                                 best_error = error;
1242                                                 best_vco_diff = vco_diff;
1243                                         } else if (current_freq == freq) {
1244                                                 if (best_freq == -1) {
1245                                                         best_post_div = post_div;
1246                                                         best_ref_div = ref_div;
1247                                                         best_feedback_div = feedback_div;
1248                                                         best_frac_feedback_div = frac_feedback_div;
1249                                                         best_freq = current_freq;
1250                                                         best_error = error;
1251                                                         best_vco_diff = vco_diff;
1252                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1253                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1254                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1255                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1256                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1257                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1258                                                         best_post_div = post_div;
1259                                                         best_ref_div = ref_div;
1260                                                         best_feedback_div = feedback_div;
1261                                                         best_frac_feedback_div = frac_feedback_div;
1262                                                         best_freq = current_freq;
1263                                                         best_error = error;
1264                                                         best_vco_diff = vco_diff;
1265                                                 }
1266                                         }
1267                                         if (current_freq < freq)
1268                                                 min_frac_feed_div = frac_feedback_div + 1;
1269                                         else
1270                                                 max_frac_feed_div = frac_feedback_div;
1271                                 }
1272                                 if (current_freq < freq)
1273                                         min_feed_div = feedback_div + 1;
1274                                 else
1275                                         max_feed_div = feedback_div;
1276                         }
1277                 }
1278         }
1279
1280         *dot_clock_p = best_freq / 10000;
1281         *fb_div_p = best_feedback_div;
1282         *frac_fb_div_p = best_frac_feedback_div;
1283         *ref_div_p = best_ref_div;
1284         *post_div_p = best_post_div;
1285         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1286                       (long long)freq,
1287                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1288                       best_ref_div, best_post_div);
1289
1290 }
1291
1292 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1293         .destroy = drm_gem_fb_destroy,
1294         .create_handle = drm_gem_fb_create_handle,
1295 };
1296
1297 int
1298 radeon_framebuffer_init(struct drm_device *dev,
1299                         struct drm_framebuffer *fb,
1300                         const struct drm_mode_fb_cmd2 *mode_cmd,
1301                         struct drm_gem_object *obj)
1302 {
1303         int ret;
1304         fb->obj[0] = obj;
1305         drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd);
1306         ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs);
1307         if (ret) {
1308                 fb->obj[0] = NULL;
1309                 return ret;
1310         }
1311         return 0;
1312 }
1313
1314 static struct drm_framebuffer *
1315 radeon_user_framebuffer_create(struct drm_device *dev,
1316                                struct drm_file *file_priv,
1317                                const struct drm_mode_fb_cmd2 *mode_cmd)
1318 {
1319         struct drm_gem_object *obj;
1320         struct drm_framebuffer *fb;
1321         int ret;
1322
1323         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1324         if (obj ==  NULL) {
1325                 dev_err(dev->dev, "No GEM object associated to handle 0x%08X, "
1326                         "can't create framebuffer\n", mode_cmd->handles[0]);
1327                 return ERR_PTR(-ENOENT);
1328         }
1329
1330         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1331         if (obj->import_attach) {
1332                 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1333                 drm_gem_object_put(obj);
1334                 return ERR_PTR(-EINVAL);
1335         }
1336
1337         fb = kzalloc(sizeof(*fb), GFP_KERNEL);
1338         if (fb == NULL) {
1339                 drm_gem_object_put(obj);
1340                 return ERR_PTR(-ENOMEM);
1341         }
1342
1343         ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj);
1344         if (ret) {
1345                 kfree(fb);
1346                 drm_gem_object_put(obj);
1347                 return ERR_PTR(ret);
1348         }
1349
1350         return fb;
1351 }
1352
1353 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1354         .fb_create = radeon_user_framebuffer_create,
1355         .output_poll_changed = drm_fb_helper_output_poll_changed,
1356 };
1357
1358 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1359 {       { 0, "driver" },
1360         { 1, "bios" },
1361 };
1362
1363 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1364 {       { TV_STD_NTSC, "ntsc" },
1365         { TV_STD_PAL, "pal" },
1366         { TV_STD_PAL_M, "pal-m" },
1367         { TV_STD_PAL_60, "pal-60" },
1368         { TV_STD_NTSC_J, "ntsc-j" },
1369         { TV_STD_SCART_PAL, "scart-pal" },
1370         { TV_STD_PAL_CN, "pal-cn" },
1371         { TV_STD_SECAM, "secam" },
1372 };
1373
1374 static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1375 {       { UNDERSCAN_OFF, "off" },
1376         { UNDERSCAN_ON, "on" },
1377         { UNDERSCAN_AUTO, "auto" },
1378 };
1379
1380 static const struct drm_prop_enum_list radeon_audio_enum_list[] =
1381 {       { RADEON_AUDIO_DISABLE, "off" },
1382         { RADEON_AUDIO_ENABLE, "on" },
1383         { RADEON_AUDIO_AUTO, "auto" },
1384 };
1385
1386 /* XXX support different dither options? spatial, temporal, both, etc. */
1387 static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1388 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1389         { RADEON_FMT_DITHER_ENABLE, "on" },
1390 };
1391
1392 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1393 {       { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1394         { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1395         { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1396         { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1397 };
1398
1399 static int radeon_modeset_create_props(struct radeon_device *rdev)
1400 {
1401         int sz;
1402
1403         if (rdev->is_atom_bios) {
1404                 rdev->mode_info.coherent_mode_property =
1405                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1406                 if (!rdev->mode_info.coherent_mode_property)
1407                         return -ENOMEM;
1408         }
1409
1410         if (!ASIC_IS_AVIVO(rdev)) {
1411                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1412                 rdev->mode_info.tmds_pll_property =
1413                         drm_property_create_enum(rdev->ddev, 0,
1414                                             "tmds_pll",
1415                                             radeon_tmds_pll_enum_list, sz);
1416         }
1417
1418         rdev->mode_info.load_detect_property =
1419                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1420         if (!rdev->mode_info.load_detect_property)
1421                 return -ENOMEM;
1422
1423         drm_mode_create_scaling_mode_property(rdev->ddev);
1424
1425         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1426         rdev->mode_info.tv_std_property =
1427                 drm_property_create_enum(rdev->ddev, 0,
1428                                     "tv standard",
1429                                     radeon_tv_std_enum_list, sz);
1430
1431         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1432         rdev->mode_info.underscan_property =
1433                 drm_property_create_enum(rdev->ddev, 0,
1434                                     "underscan",
1435                                     radeon_underscan_enum_list, sz);
1436
1437         rdev->mode_info.underscan_hborder_property =
1438                 drm_property_create_range(rdev->ddev, 0,
1439                                         "underscan hborder", 0, 128);
1440         if (!rdev->mode_info.underscan_hborder_property)
1441                 return -ENOMEM;
1442
1443         rdev->mode_info.underscan_vborder_property =
1444                 drm_property_create_range(rdev->ddev, 0,
1445                                         "underscan vborder", 0, 128);
1446         if (!rdev->mode_info.underscan_vborder_property)
1447                 return -ENOMEM;
1448
1449         sz = ARRAY_SIZE(radeon_audio_enum_list);
1450         rdev->mode_info.audio_property =
1451                 drm_property_create_enum(rdev->ddev, 0,
1452                                          "audio",
1453                                          radeon_audio_enum_list, sz);
1454
1455         sz = ARRAY_SIZE(radeon_dither_enum_list);
1456         rdev->mode_info.dither_property =
1457                 drm_property_create_enum(rdev->ddev, 0,
1458                                          "dither",
1459                                          radeon_dither_enum_list, sz);
1460
1461         sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1462         rdev->mode_info.output_csc_property =
1463                 drm_property_create_enum(rdev->ddev, 0,
1464                                          "output_csc",
1465                                          radeon_output_csc_enum_list, sz);
1466
1467         return 0;
1468 }
1469
1470 void radeon_update_display_priority(struct radeon_device *rdev)
1471 {
1472         /* adjustment options for the display watermarks */
1473         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1474                 /* set display priority to high for r3xx, rv515 chips
1475                  * this avoids flickering due to underflow to the
1476                  * display controllers during heavy acceleration.
1477                  * Don't force high on rs4xx igp chips as it seems to
1478                  * affect the sound card.  See kernel bug 15982.
1479                  */
1480                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1481                     !(rdev->flags & RADEON_IS_IGP))
1482                         rdev->disp_priority = 2;
1483                 else
1484                         rdev->disp_priority = 0;
1485         } else
1486                 rdev->disp_priority = radeon_disp_priority;
1487
1488 }
1489
1490 /*
1491  * Allocate hdmi structs and determine register offsets
1492  */
1493 static void radeon_afmt_init(struct radeon_device *rdev)
1494 {
1495         int i;
1496
1497         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1498                 rdev->mode_info.afmt[i] = NULL;
1499
1500         if (ASIC_IS_NODCE(rdev)) {
1501                 /* nothing to do */
1502         } else if (ASIC_IS_DCE4(rdev)) {
1503                 static uint32_t eg_offsets[] = {
1504                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1505                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1506                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1507                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1508                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1509                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1510                         0x13830 - 0x7030,
1511                 };
1512                 int num_afmt;
1513
1514                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1515                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1516                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1517                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1518                 if (ASIC_IS_DCE8(rdev))
1519                         num_afmt = 7;
1520                 else if (ASIC_IS_DCE6(rdev))
1521                         num_afmt = 6;
1522                 else if (ASIC_IS_DCE5(rdev))
1523                         num_afmt = 6;
1524                 else if (ASIC_IS_DCE41(rdev))
1525                         num_afmt = 2;
1526                 else /* DCE4 */
1527                         num_afmt = 6;
1528
1529                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1530                 for (i = 0; i < num_afmt; i++) {
1531                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1532                         if (rdev->mode_info.afmt[i]) {
1533                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1534                                 rdev->mode_info.afmt[i]->id = i;
1535                         }
1536                 }
1537         } else if (ASIC_IS_DCE3(rdev)) {
1538                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1539                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1540                 if (rdev->mode_info.afmt[0]) {
1541                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1542                         rdev->mode_info.afmt[0]->id = 0;
1543                 }
1544                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1545                 if (rdev->mode_info.afmt[1]) {
1546                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1547                         rdev->mode_info.afmt[1]->id = 1;
1548                 }
1549         } else if (ASIC_IS_DCE2(rdev)) {
1550                 /* DCE2 has at least 1 routable audio block */
1551                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1552                 if (rdev->mode_info.afmt[0]) {
1553                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1554                         rdev->mode_info.afmt[0]->id = 0;
1555                 }
1556                 /* r6xx has 2 routable audio blocks */
1557                 if (rdev->family >= CHIP_R600) {
1558                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1559                         if (rdev->mode_info.afmt[1]) {
1560                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1561                                 rdev->mode_info.afmt[1]->id = 1;
1562                         }
1563                 }
1564         }
1565 }
1566
1567 static void radeon_afmt_fini(struct radeon_device *rdev)
1568 {
1569         int i;
1570
1571         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1572                 kfree(rdev->mode_info.afmt[i]);
1573                 rdev->mode_info.afmt[i] = NULL;
1574         }
1575 }
1576
1577 int radeon_modeset_init(struct radeon_device *rdev)
1578 {
1579         int i;
1580         int ret;
1581
1582         drm_mode_config_init(rdev->ddev);
1583         rdev->mode_info.mode_config_initialized = true;
1584
1585         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1586
1587         if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1588                 rdev->ddev->mode_config.async_page_flip = true;
1589
1590         if (ASIC_IS_DCE5(rdev)) {
1591                 rdev->ddev->mode_config.max_width = 16384;
1592                 rdev->ddev->mode_config.max_height = 16384;
1593         } else if (ASIC_IS_AVIVO(rdev)) {
1594                 rdev->ddev->mode_config.max_width = 8192;
1595                 rdev->ddev->mode_config.max_height = 8192;
1596         } else {
1597                 rdev->ddev->mode_config.max_width = 4096;
1598                 rdev->ddev->mode_config.max_height = 4096;
1599         }
1600
1601         rdev->ddev->mode_config.preferred_depth = 24;
1602         rdev->ddev->mode_config.prefer_shadow = 1;
1603
1604         rdev->ddev->mode_config.fb_modifiers_not_supported = true;
1605
1606         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1607
1608         ret = radeon_modeset_create_props(rdev);
1609         if (ret) {
1610                 return ret;
1611         }
1612
1613         /* init i2c buses */
1614         radeon_i2c_init(rdev);
1615
1616         /* check combios for a valid hardcoded EDID - Sun servers */
1617         if (!rdev->is_atom_bios) {
1618                 /* check for hardcoded EDID in BIOS */
1619                 radeon_combios_check_hardcoded_edid(rdev);
1620         }
1621
1622         /* allocate crtcs */
1623         for (i = 0; i < rdev->num_crtc; i++) {
1624                 radeon_crtc_init(rdev->ddev, i);
1625         }
1626
1627         /* okay we should have all the bios connectors */
1628         ret = radeon_setup_enc_conn(rdev->ddev);
1629         if (!ret) {
1630                 return ret;
1631         }
1632
1633         /* init dig PHYs, disp eng pll */
1634         if (rdev->is_atom_bios) {
1635                 radeon_atom_encoder_init(rdev);
1636                 radeon_atom_disp_eng_pll_init(rdev);
1637         }
1638
1639         /* initialize hpd */
1640         radeon_hpd_init(rdev);
1641
1642         /* setup afmt */
1643         radeon_afmt_init(rdev);
1644
1645         radeon_fbdev_init(rdev);
1646         drm_kms_helper_poll_init(rdev->ddev);
1647
1648         /* do pm late init */
1649         ret = radeon_pm_late_init(rdev);
1650
1651         return 0;
1652 }
1653
1654 void radeon_modeset_fini(struct radeon_device *rdev)
1655 {
1656         if (rdev->mode_info.mode_config_initialized) {
1657                 drm_kms_helper_poll_fini(rdev->ddev);
1658                 radeon_hpd_fini(rdev);
1659                 drm_helper_force_disable_all(rdev->ddev);
1660                 radeon_fbdev_fini(rdev);
1661                 radeon_afmt_fini(rdev);
1662                 drm_mode_config_cleanup(rdev->ddev);
1663                 rdev->mode_info.mode_config_initialized = false;
1664         }
1665
1666         kfree(rdev->mode_info.bios_hardcoded_edid);
1667
1668         /* free i2c buses */
1669         radeon_i2c_fini(rdev);
1670 }
1671
1672 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1673 {
1674         /* try and guess if this is a tv or a monitor */
1675         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1676             (mode->vdisplay == 576) || /* 576p */
1677             (mode->vdisplay == 720) || /* 720p */
1678             (mode->vdisplay == 1080)) /* 1080p */
1679                 return true;
1680         else
1681                 return false;
1682 }
1683
1684 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1685                                 const struct drm_display_mode *mode,
1686                                 struct drm_display_mode *adjusted_mode)
1687 {
1688         struct drm_device *dev = crtc->dev;
1689         struct radeon_device *rdev = dev->dev_private;
1690         struct drm_encoder *encoder;
1691         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1692         struct radeon_encoder *radeon_encoder;
1693         struct drm_connector *connector;
1694         bool first = true;
1695         u32 src_v = 1, dst_v = 1;
1696         u32 src_h = 1, dst_h = 1;
1697
1698         radeon_crtc->h_border = 0;
1699         radeon_crtc->v_border = 0;
1700
1701         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1702                 if (encoder->crtc != crtc)
1703                         continue;
1704                 radeon_encoder = to_radeon_encoder(encoder);
1705                 connector = radeon_get_connector_for_encoder(encoder);
1706
1707                 if (first) {
1708                         /* set scaling */
1709                         if (radeon_encoder->rmx_type == RMX_OFF)
1710                                 radeon_crtc->rmx_type = RMX_OFF;
1711                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1712                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1713                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1714                         else
1715                                 radeon_crtc->rmx_type = RMX_OFF;
1716                         /* copy native mode */
1717                         memcpy(&radeon_crtc->native_mode,
1718                                &radeon_encoder->native_mode,
1719                                 sizeof(struct drm_display_mode));
1720                         src_v = crtc->mode.vdisplay;
1721                         dst_v = radeon_crtc->native_mode.vdisplay;
1722                         src_h = crtc->mode.hdisplay;
1723                         dst_h = radeon_crtc->native_mode.hdisplay;
1724
1725                         /* fix up for overscan on hdmi */
1726                         if (ASIC_IS_AVIVO(rdev) &&
1727                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1728                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1729                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1730                               drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1731                               is_hdtv_mode(mode)))) {
1732                                 if (radeon_encoder->underscan_hborder != 0)
1733                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1734                                 else
1735                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1736                                 if (radeon_encoder->underscan_vborder != 0)
1737                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1738                                 else
1739                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1740                                 radeon_crtc->rmx_type = RMX_FULL;
1741                                 src_v = crtc->mode.vdisplay;
1742                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1743                                 src_h = crtc->mode.hdisplay;
1744                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1745                         }
1746                         first = false;
1747                 } else {
1748                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1749                                 /* WARNING: Right now this can't happen but
1750                                  * in the future we need to check that scaling
1751                                  * are consistent across different encoder
1752                                  * (ie all encoder can work with the same
1753                                  *  scaling).
1754                                  */
1755                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1756                                 return false;
1757                         }
1758                 }
1759         }
1760         if (radeon_crtc->rmx_type != RMX_OFF) {
1761                 fixed20_12 a, b;
1762                 a.full = dfixed_const(src_v);
1763                 b.full = dfixed_const(dst_v);
1764                 radeon_crtc->vsc.full = dfixed_div(a, b);
1765                 a.full = dfixed_const(src_h);
1766                 b.full = dfixed_const(dst_h);
1767                 radeon_crtc->hsc.full = dfixed_div(a, b);
1768         } else {
1769                 radeon_crtc->vsc.full = dfixed_const(1);
1770                 radeon_crtc->hsc.full = dfixed_const(1);
1771         }
1772         return true;
1773 }
1774
1775 /*
1776  * Retrieve current video scanout position of crtc on a given gpu, and
1777  * an optional accurate timestamp of when query happened.
1778  *
1779  * \param dev Device to query.
1780  * \param crtc Crtc to query.
1781  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1782  *              For driver internal use only also supports these flags:
1783  *
1784  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1785  *              of a fudged earlier start of vblank.
1786  *
1787  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1788  *              fudged earlier start of vblank in *vpos and the distance
1789  *              to true start of vblank in *hpos.
1790  *
1791  * \param *vpos Location where vertical scanout position should be stored.
1792  * \param *hpos Location where horizontal scanout position should go.
1793  * \param *stime Target location for timestamp taken immediately before
1794  *               scanout position query. Can be NULL to skip timestamp.
1795  * \param *etime Target location for timestamp taken immediately after
1796  *               scanout position query. Can be NULL to skip timestamp.
1797  *
1798  * Returns vpos as a positive number while in active scanout area.
1799  * Returns vpos as a negative number inside vblank, counting the number
1800  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1801  * until start of active scanout / end of vblank."
1802  *
1803  * \return Flags, or'ed together as follows:
1804  *
1805  * DRM_SCANOUTPOS_VALID = Query successful.
1806  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1807  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1808  * this flag means that returned position may be offset by a constant but
1809  * unknown small number of scanlines wrt. real scanout position.
1810  *
1811  */
1812 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1813                                unsigned int flags, int *vpos, int *hpos,
1814                                ktime_t *stime, ktime_t *etime,
1815                                const struct drm_display_mode *mode)
1816 {
1817         u32 stat_crtc = 0, vbl = 0, position = 0;
1818         int vbl_start, vbl_end, vtotal, ret = 0;
1819         bool in_vbl = true;
1820
1821         struct radeon_device *rdev = dev->dev_private;
1822
1823         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1824
1825         /* Get optional system timestamp before query. */
1826         if (stime)
1827                 *stime = ktime_get();
1828
1829         if (ASIC_IS_DCE4(rdev)) {
1830                 if (pipe == 0) {
1831                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1832                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1833                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1834                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1835                         ret |= DRM_SCANOUTPOS_VALID;
1836                 }
1837                 if (pipe == 1) {
1838                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1839                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1840                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1841                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1842                         ret |= DRM_SCANOUTPOS_VALID;
1843                 }
1844                 if (pipe == 2) {
1845                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1846                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1847                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1848                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1849                         ret |= DRM_SCANOUTPOS_VALID;
1850                 }
1851                 if (pipe == 3) {
1852                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1853                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1854                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1855                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1856                         ret |= DRM_SCANOUTPOS_VALID;
1857                 }
1858                 if (pipe == 4) {
1859                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1860                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1861                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1862                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1863                         ret |= DRM_SCANOUTPOS_VALID;
1864                 }
1865                 if (pipe == 5) {
1866                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1867                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1868                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1869                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1870                         ret |= DRM_SCANOUTPOS_VALID;
1871                 }
1872         } else if (ASIC_IS_AVIVO(rdev)) {
1873                 if (pipe == 0) {
1874                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1875                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1876                         ret |= DRM_SCANOUTPOS_VALID;
1877                 }
1878                 if (pipe == 1) {
1879                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1880                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1881                         ret |= DRM_SCANOUTPOS_VALID;
1882                 }
1883         } else {
1884                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1885                 if (pipe == 0) {
1886                         /* Assume vbl_end == 0, get vbl_start from
1887                          * upper 16 bits.
1888                          */
1889                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1890                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1891                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1892                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1893                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1894                         if (!(stat_crtc & 1))
1895                                 in_vbl = false;
1896
1897                         ret |= DRM_SCANOUTPOS_VALID;
1898                 }
1899                 if (pipe == 1) {
1900                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1901                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1902                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1903                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1904                         if (!(stat_crtc & 1))
1905                                 in_vbl = false;
1906
1907                         ret |= DRM_SCANOUTPOS_VALID;
1908                 }
1909         }
1910
1911         /* Get optional system timestamp after query. */
1912         if (etime)
1913                 *etime = ktime_get();
1914
1915         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1916
1917         /* Decode into vertical and horizontal scanout position. */
1918         *vpos = position & 0x1fff;
1919         *hpos = (position >> 16) & 0x1fff;
1920
1921         /* Valid vblank area boundaries from gpu retrieved? */
1922         if (vbl > 0) {
1923                 /* Yes: Decode. */
1924                 ret |= DRM_SCANOUTPOS_ACCURATE;
1925                 vbl_start = vbl & 0x1fff;
1926                 vbl_end = (vbl >> 16) & 0x1fff;
1927         }
1928         else {
1929                 /* No: Fake something reasonable which gives at least ok results. */
1930                 vbl_start = mode->crtc_vdisplay;
1931                 vbl_end = 0;
1932         }
1933
1934         /* Called from driver internal vblank counter query code? */
1935         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1936             /* Caller wants distance from real vbl_start in *hpos */
1937             *hpos = *vpos - vbl_start;
1938         }
1939
1940         /* Fudge vblank to start a few scanlines earlier to handle the
1941          * problem that vblank irqs fire a few scanlines before start
1942          * of vblank. Some driver internal callers need the true vblank
1943          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1944          *
1945          * The cause of the "early" vblank irq is that the irq is triggered
1946          * by the line buffer logic when the line buffer read position enters
1947          * the vblank, whereas our crtc scanout position naturally lags the
1948          * line buffer read position.
1949          */
1950         if (!(flags & USE_REAL_VBLANKSTART))
1951                 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1952
1953         /* Test scanout position against vblank region. */
1954         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1955                 in_vbl = false;
1956
1957         /* In vblank? */
1958         if (in_vbl)
1959             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1960
1961         /* Called from driver internal vblank counter query code? */
1962         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1963                 /* Caller wants distance from fudged earlier vbl_start */
1964                 *vpos -= vbl_start;
1965                 return ret;
1966         }
1967
1968         /* Check if inside vblank area and apply corrective offsets:
1969          * vpos will then be >=0 in video scanout area, but negative
1970          * within vblank area, counting down the number of lines until
1971          * start of scanout.
1972          */
1973
1974         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1975         if (in_vbl && (*vpos >= vbl_start)) {
1976                 vtotal = mode->crtc_vtotal;
1977                 *vpos = *vpos - vtotal;
1978         }
1979
1980         /* Correct for shifted end of vbl at vbl_end. */
1981         *vpos = *vpos - vbl_end;
1982
1983         return ret;
1984 }
1985
1986 bool
1987 radeon_get_crtc_scanout_position(struct drm_crtc *crtc,
1988                                  bool in_vblank_irq, int *vpos, int *hpos,
1989                                  ktime_t *stime, ktime_t *etime,
1990                                  const struct drm_display_mode *mode)
1991 {
1992         struct drm_device *dev = crtc->dev;
1993         unsigned int pipe = crtc->index;
1994
1995         return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1996                                           stime, etime, mode);
1997 }