2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include <drm/radeon_drm.h>
29 #include "radeon_reg.h"
32 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
34 struct drm_device *ddev = p->rdev->ddev;
35 struct radeon_cs_chunk *chunk;
39 if (p->chunk_relocs_idx == -1) {
42 chunk = &p->chunks[p->chunk_relocs_idx];
44 /* FIXME: we assume that each relocs use 4 dwords */
45 p->nrelocs = chunk->length_dw / 4;
46 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
47 if (p->relocs_ptr == NULL) {
50 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
51 if (p->relocs == NULL) {
54 for (i = 0; i < p->nrelocs; i++) {
55 struct drm_radeon_cs_reloc *r;
58 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
59 for (j = 0; j < i; j++) {
60 if (r->handle == p->relocs[j].handle) {
61 p->relocs_ptr[i] = &p->relocs[j];
67 p->relocs[i].handle = 0;
71 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
73 if (p->relocs[i].gobj == NULL) {
74 DRM_ERROR("gem object lookup failed 0x%x\n",
78 p->relocs_ptr[i] = &p->relocs[i];
79 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
80 p->relocs[i].lobj.bo = p->relocs[i].robj;
81 p->relocs[i].lobj.written = !!r->write_domain;
83 /* the first reloc of an UVD job is the
84 msg and that must be in VRAM */
85 if (p->ring == R600_RING_TYPE_UVD_INDEX && i == 0) {
86 /* TODO: is this still needed for NI+ ? */
87 p->relocs[i].lobj.domain =
88 RADEON_GEM_DOMAIN_VRAM;
90 p->relocs[i].lobj.alt_domain =
91 RADEON_GEM_DOMAIN_VRAM;
94 uint32_t domain = r->write_domain ?
95 r->write_domain : r->read_domains;
97 p->relocs[i].lobj.domain = domain;
98 if (domain == RADEON_GEM_DOMAIN_VRAM)
99 domain |= RADEON_GEM_DOMAIN_GTT;
100 p->relocs[i].lobj.alt_domain = domain;
103 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
104 p->relocs[i].handle = r->handle;
106 radeon_bo_list_add_object(&p->relocs[i].lobj,
109 return radeon_bo_list_validate(&p->validated, p->ring);
112 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
114 p->priority = priority;
118 DRM_ERROR("unknown ring id: %d\n", ring);
120 case RADEON_CS_RING_GFX:
121 p->ring = RADEON_RING_TYPE_GFX_INDEX;
123 case RADEON_CS_RING_COMPUTE:
124 if (p->rdev->family >= CHIP_TAHITI) {
126 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
128 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
130 p->ring = RADEON_RING_TYPE_GFX_INDEX;
132 case RADEON_CS_RING_DMA:
133 if (p->rdev->family >= CHIP_CAYMAN) {
135 p->ring = R600_RING_TYPE_DMA_INDEX;
137 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
138 } else if (p->rdev->family >= CHIP_R600) {
139 p->ring = R600_RING_TYPE_DMA_INDEX;
144 case RADEON_CS_RING_UVD:
145 p->ring = R600_RING_TYPE_UVD_INDEX;
151 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
155 for (i = 0; i < p->nrelocs; i++) {
156 if (!p->relocs[i].robj)
159 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj);
163 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
164 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
166 struct drm_radeon_cs *cs = data;
167 uint64_t *chunk_array_ptr;
169 u32 ring = RADEON_CS_RING_GFX;
172 if (!cs->num_chunks) {
176 INIT_LIST_HEAD(&p->validated);
179 p->ib.semaphore = NULL;
180 p->const_ib.sa_bo = NULL;
181 p->const_ib.semaphore = NULL;
182 p->chunk_ib_idx = -1;
183 p->chunk_relocs_idx = -1;
184 p->chunk_flags_idx = -1;
185 p->chunk_const_ib_idx = -1;
186 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
187 if (p->chunks_array == NULL) {
190 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
191 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
192 sizeof(uint64_t)*cs->num_chunks)) {
196 p->nchunks = cs->num_chunks;
197 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
198 if (p->chunks == NULL) {
201 for (i = 0; i < p->nchunks; i++) {
202 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
203 struct drm_radeon_cs_chunk user_chunk;
204 uint32_t __user *cdata;
206 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
207 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
208 sizeof(struct drm_radeon_cs_chunk))) {
211 p->chunks[i].length_dw = user_chunk.length_dw;
212 p->chunks[i].kdata = NULL;
213 p->chunks[i].chunk_id = user_chunk.chunk_id;
214 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
215 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
216 p->chunk_relocs_idx = i;
218 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
220 /* zero length IB isn't useful */
221 if (p->chunks[i].length_dw == 0)
224 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
225 p->chunk_const_ib_idx = i;
226 /* zero length CONST IB isn't useful */
227 if (p->chunks[i].length_dw == 0)
230 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
231 p->chunk_flags_idx = i;
232 /* zero length flags aren't useful */
233 if (p->chunks[i].length_dw == 0)
237 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
238 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
239 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
240 size = p->chunks[i].length_dw * sizeof(uint32_t);
241 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
242 if (p->chunks[i].kdata == NULL) {
245 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
246 p->chunks[i].user_ptr, size)) {
249 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
250 p->cs_flags = p->chunks[i].kdata[0];
251 if (p->chunks[i].length_dw > 1)
252 ring = p->chunks[i].kdata[1];
253 if (p->chunks[i].length_dw > 2)
254 priority = (s32)p->chunks[i].kdata[2];
259 /* these are KMS only */
261 if ((p->cs_flags & RADEON_CS_USE_VM) &&
262 !p->rdev->vm_manager.enabled) {
263 DRM_ERROR("VM not active on asic!\n");
267 if (radeon_cs_get_ring(p, ring, priority))
270 /* we only support VM on some SI+ rings */
271 if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) &&
272 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
273 DRM_ERROR("Ring %d requires VM!\n", p->ring);
278 /* deal with non-vm */
279 if ((p->chunk_ib_idx != -1) &&
280 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
281 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
282 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
283 DRM_ERROR("cs IB too big: %d\n",
284 p->chunks[p->chunk_ib_idx].length_dw);
287 if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) {
288 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
289 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
290 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
291 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
292 kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
293 kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
294 p->chunks[p->chunk_ib_idx].kpage[0] = NULL;
295 p->chunks[p->chunk_ib_idx].kpage[1] = NULL;
299 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
300 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
301 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
302 p->chunks[p->chunk_ib_idx].last_page_index =
303 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
310 * cs_parser_fini() - clean parser states
311 * @parser: parser structure holding parsing context.
312 * @error: error number
314 * If error is set than unvalidate buffer, otherwise just free memory
315 * used by parsing context.
317 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
322 ttm_eu_fence_buffer_objects(&parser->validated,
325 ttm_eu_backoff_reservation(&parser->validated);
328 if (parser->relocs != NULL) {
329 for (i = 0; i < parser->nrelocs; i++) {
330 if (parser->relocs[i].gobj)
331 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
334 kfree(parser->track);
335 kfree(parser->relocs);
336 kfree(parser->relocs_ptr);
337 for (i = 0; i < parser->nchunks; i++) {
338 kfree(parser->chunks[i].kdata);
339 if ((parser->rdev->flags & RADEON_IS_AGP)) {
340 kfree(parser->chunks[i].kpage[0]);
341 kfree(parser->chunks[i].kpage[1]);
344 kfree(parser->chunks);
345 kfree(parser->chunks_array);
346 radeon_ib_free(parser->rdev, &parser->ib);
347 radeon_ib_free(parser->rdev, &parser->const_ib);
350 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
351 struct radeon_cs_parser *parser)
353 struct radeon_cs_chunk *ib_chunk;
356 if (parser->chunk_ib_idx == -1)
359 if (parser->cs_flags & RADEON_CS_USE_VM)
362 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
363 /* Copy the packet into the IB, the parser will read from the
364 * input memory (cached) and write to the IB (which can be
367 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
368 NULL, ib_chunk->length_dw * 4);
370 DRM_ERROR("Failed to get ib !\n");
373 parser->ib.length_dw = ib_chunk->length_dw;
374 r = radeon_cs_parse(rdev, parser->ring, parser);
375 if (r || parser->parser_error) {
376 DRM_ERROR("Invalid command stream !\n");
379 r = radeon_cs_finish_pages(parser);
381 DRM_ERROR("Invalid command stream !\n");
384 radeon_cs_sync_rings(parser);
385 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
387 DRM_ERROR("Failed to schedule IB !\n");
392 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
393 struct radeon_vm *vm)
395 struct radeon_device *rdev = parser->rdev;
396 struct radeon_bo_list *lobj;
397 struct radeon_bo *bo;
400 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
404 list_for_each_entry(lobj, &parser->validated, tv.head) {
406 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
414 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
415 struct radeon_cs_parser *parser)
417 struct radeon_cs_chunk *ib_chunk;
418 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
419 struct radeon_vm *vm = &fpriv->vm;
422 if (parser->chunk_ib_idx == -1)
424 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
427 if ((rdev->family >= CHIP_TAHITI) &&
428 (parser->chunk_const_ib_idx != -1)) {
429 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
430 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
431 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
434 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
435 vm, ib_chunk->length_dw * 4);
437 DRM_ERROR("Failed to get const ib !\n");
440 parser->const_ib.is_const_ib = true;
441 parser->const_ib.length_dw = ib_chunk->length_dw;
442 /* Copy the packet into the IB */
443 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
444 ib_chunk->length_dw * 4)) {
447 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
453 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
454 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
455 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
458 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
459 vm, ib_chunk->length_dw * 4);
461 DRM_ERROR("Failed to get ib !\n");
464 parser->ib.length_dw = ib_chunk->length_dw;
465 /* Copy the packet into the IB */
466 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
467 ib_chunk->length_dw * 4)) {
470 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
475 mutex_lock(&rdev->vm_manager.lock);
476 mutex_lock(&vm->mutex);
477 r = radeon_vm_alloc_pt(rdev, vm);
481 r = radeon_bo_vm_update_pte(parser, vm);
485 radeon_cs_sync_rings(parser);
486 radeon_ib_sync_to(&parser->ib, vm->fence);
487 radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id(
488 rdev, vm, parser->ring));
490 if ((rdev->family >= CHIP_TAHITI) &&
491 (parser->chunk_const_ib_idx != -1)) {
492 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
494 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
498 radeon_vm_fence(rdev, vm, parser->ib.fence);
502 radeon_vm_add_to_lru(rdev, vm);
503 mutex_unlock(&vm->mutex);
504 mutex_unlock(&rdev->vm_manager.lock);
508 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
511 r = radeon_gpu_reset(rdev);
518 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
520 struct radeon_device *rdev = dev->dev_private;
521 struct radeon_cs_parser parser;
524 down_read(&rdev->exclusive_lock);
525 if (!rdev->accel_working) {
526 up_read(&rdev->exclusive_lock);
529 /* initialize parser */
530 memset(&parser, 0, sizeof(struct radeon_cs_parser));
533 parser.dev = rdev->dev;
534 parser.family = rdev->family;
535 r = radeon_cs_parser_init(&parser, data);
537 DRM_ERROR("Failed to initialize parser !\n");
538 radeon_cs_parser_fini(&parser, r);
539 up_read(&rdev->exclusive_lock);
540 r = radeon_cs_handle_lockup(rdev, r);
543 r = radeon_cs_parser_relocs(&parser);
545 if (r != -ERESTARTSYS)
546 DRM_ERROR("Failed to parse relocation %d!\n", r);
547 radeon_cs_parser_fini(&parser, r);
548 up_read(&rdev->exclusive_lock);
549 r = radeon_cs_handle_lockup(rdev, r);
553 if (parser.ring == R600_RING_TYPE_UVD_INDEX)
554 radeon_uvd_note_usage(rdev);
556 r = radeon_cs_ib_chunk(rdev, &parser);
560 r = radeon_cs_ib_vm_chunk(rdev, &parser);
565 radeon_cs_parser_fini(&parser, r);
566 up_read(&rdev->exclusive_lock);
567 r = radeon_cs_handle_lockup(rdev, r);
571 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
573 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
575 int size = PAGE_SIZE;
577 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
578 if (i == ibc->last_page_index) {
579 size = (ibc->length_dw * 4) % PAGE_SIZE;
584 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
585 ibc->user_ptr + (i * PAGE_SIZE),
592 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
595 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
597 int size = PAGE_SIZE;
598 bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ?
601 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
602 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
603 ibc->user_ptr + (i * PAGE_SIZE),
605 p->parser_error = -EFAULT;
610 if (pg_idx == ibc->last_page_index) {
611 size = (ibc->length_dw * 4) % PAGE_SIZE;
616 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
618 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
620 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
621 ibc->user_ptr + (pg_idx * PAGE_SIZE),
623 p->parser_error = -EFAULT;
627 /* copy to IB for non single case */
629 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
631 ibc->last_copied_page = pg_idx;
632 ibc->kpage_idx[new_page] = pg_idx;
637 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
639 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
640 u32 pg_idx, pg_offset;
644 pg_idx = (idx * 4) / PAGE_SIZE;
645 pg_offset = (idx * 4) % PAGE_SIZE;
647 if (ibc->kpage_idx[0] == pg_idx)
648 return ibc->kpage[0][pg_offset/4];
649 if (ibc->kpage_idx[1] == pg_idx)
650 return ibc->kpage[1][pg_offset/4];
652 new_page = radeon_cs_update_pages(p, pg_idx);
654 p->parser_error = new_page;
658 idx_value = ibc->kpage[new_page][pg_offset/4];
663 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
664 * @parser: parser structure holding parsing context.
665 * @pkt: where to store packet information
667 * Assume that chunk_ib_index is properly set. Will return -EINVAL
668 * if packet is bigger than remaining ib size. or if packets is unknown.
670 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
671 struct radeon_cs_packet *pkt,
674 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
675 struct radeon_device *rdev = p->rdev;
678 if (idx >= ib_chunk->length_dw) {
679 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
680 idx, ib_chunk->length_dw);
683 header = radeon_get_ib_value(p, idx);
685 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
686 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
689 case RADEON_PACKET_TYPE0:
690 if (rdev->family < CHIP_R600) {
691 pkt->reg = R100_CP_PACKET0_GET_REG(header);
693 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
695 pkt->reg = R600_CP_PACKET0_GET_REG(header);
697 case RADEON_PACKET_TYPE3:
698 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
700 case RADEON_PACKET_TYPE2:
704 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
707 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
708 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
709 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
716 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
717 * @p: structure holding the parser context.
719 * Check if the next packet is NOP relocation packet3.
721 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
723 struct radeon_cs_packet p3reloc;
726 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
729 if (p3reloc.type != RADEON_PACKET_TYPE3)
731 if (p3reloc.opcode != RADEON_PACKET3_NOP)
737 * radeon_cs_dump_packet() - dump raw packet context
738 * @p: structure holding the parser context.
739 * @pkt: structure holding the packet.
741 * Used mostly for debugging and error reporting.
743 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
744 struct radeon_cs_packet *pkt)
746 volatile uint32_t *ib;
752 for (i = 0; i <= (pkt->count + 1); i++, idx++)
753 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
757 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
758 * @parser: parser structure holding parsing context.
759 * @data: pointer to relocation data
760 * @offset_start: starting offset
761 * @offset_mask: offset mask (to align start offset on)
762 * @reloc: reloc informations
764 * Check if next packet is relocation packet3, do bo validation and compute
765 * GPU offset using the provided start.
767 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
768 struct radeon_cs_reloc **cs_reloc,
771 struct radeon_cs_chunk *relocs_chunk;
772 struct radeon_cs_packet p3reloc;
776 if (p->chunk_relocs_idx == -1) {
777 DRM_ERROR("No relocation chunk !\n");
781 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
782 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
785 p->idx += p3reloc.count + 2;
786 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
787 p3reloc.opcode != RADEON_PACKET3_NOP) {
788 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
790 radeon_cs_dump_packet(p, &p3reloc);
793 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
794 if (idx >= relocs_chunk->length_dw) {
795 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
796 idx, relocs_chunk->length_dw);
797 radeon_cs_dump_packet(p, &p3reloc);
800 /* FIXME: we assume reloc size is 4 dwords */
802 *cs_reloc = p->relocs;
803 (*cs_reloc)->lobj.gpu_offset =
804 (u64)relocs_chunk->kdata[idx + 3] << 32;
805 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
807 *cs_reloc = p->relocs_ptr[(idx / 4)];