2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
114 enum radeon_combios_ddc {
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
149 struct radeon_device *rdev = dev->dev_private;
151 uint16_t offset = 0, check_offset;
154 /* absolute offset tables */
155 case COMBIOS_ASIC_INIT_1_TABLE:
156 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
158 offset = check_offset;
160 case COMBIOS_BIOS_SUPPORT_TABLE:
161 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
163 offset = check_offset;
165 case COMBIOS_DAC_PROGRAMMING_TABLE:
166 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
168 offset = check_offset;
170 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
171 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
173 offset = check_offset;
175 case COMBIOS_CRTC_INFO_TABLE:
176 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
178 offset = check_offset;
180 case COMBIOS_PLL_INFO_TABLE:
181 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
183 offset = check_offset;
185 case COMBIOS_TV_INFO_TABLE:
186 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
188 offset = check_offset;
190 case COMBIOS_DFP_INFO_TABLE:
191 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
193 offset = check_offset;
195 case COMBIOS_HW_CONFIG_INFO_TABLE:
196 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
198 offset = check_offset;
200 case COMBIOS_MULTIMEDIA_INFO_TABLE:
201 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
203 offset = check_offset;
205 case COMBIOS_TV_STD_PATCH_TABLE:
206 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
208 offset = check_offset;
210 case COMBIOS_LCD_INFO_TABLE:
211 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
213 offset = check_offset;
215 case COMBIOS_MOBILE_INFO_TABLE:
216 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
218 offset = check_offset;
220 case COMBIOS_PLL_INIT_TABLE:
221 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
223 offset = check_offset;
225 case COMBIOS_MEM_CONFIG_TABLE:
226 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
228 offset = check_offset;
230 case COMBIOS_SAVE_MASK_TABLE:
231 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
233 offset = check_offset;
235 case COMBIOS_HARDCODED_EDID_TABLE:
236 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
238 offset = check_offset;
240 case COMBIOS_ASIC_INIT_2_TABLE:
241 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
243 offset = check_offset;
245 case COMBIOS_CONNECTOR_INFO_TABLE:
246 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
248 offset = check_offset;
250 case COMBIOS_DYN_CLK_1_TABLE:
251 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
253 offset = check_offset;
255 case COMBIOS_RESERVED_MEM_TABLE:
256 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
258 offset = check_offset;
260 case COMBIOS_EXT_TMDS_INFO_TABLE:
261 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
263 offset = check_offset;
265 case COMBIOS_MEM_CLK_INFO_TABLE:
266 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
268 offset = check_offset;
270 case COMBIOS_EXT_DAC_INFO_TABLE:
271 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
273 offset = check_offset;
275 case COMBIOS_MISC_INFO_TABLE:
276 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
278 offset = check_offset;
280 case COMBIOS_CRT_INFO_TABLE:
281 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
283 offset = check_offset;
285 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
286 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
288 offset = check_offset;
290 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
291 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
293 offset = check_offset;
295 case COMBIOS_FAN_SPEED_INFO_TABLE:
296 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
298 offset = check_offset;
300 case COMBIOS_OVERDRIVE_INFO_TABLE:
301 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
303 offset = check_offset;
305 case COMBIOS_OEM_INFO_TABLE:
306 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
308 offset = check_offset;
310 case COMBIOS_DYN_CLK_2_TABLE:
311 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
313 offset = check_offset;
315 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
316 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
318 offset = check_offset;
320 case COMBIOS_I2C_INFO_TABLE:
321 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
323 offset = check_offset;
325 /* relative offset tables */
326 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
328 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
330 rev = RBIOS8(check_offset);
332 check_offset = RBIOS16(check_offset + 0x3);
334 offset = check_offset;
338 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
340 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
342 rev = RBIOS8(check_offset);
344 check_offset = RBIOS16(check_offset + 0x5);
346 offset = check_offset;
350 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
352 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
354 rev = RBIOS8(check_offset);
356 check_offset = RBIOS16(check_offset + 0x7);
358 offset = check_offset;
362 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
364 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
366 rev = RBIOS8(check_offset);
368 check_offset = RBIOS16(check_offset + 0x9);
370 offset = check_offset;
374 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
376 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
378 while (RBIOS8(check_offset++));
381 offset = check_offset;
384 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
386 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
388 check_offset = RBIOS16(check_offset + 0x11);
390 offset = check_offset;
393 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
395 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
397 check_offset = RBIOS16(check_offset + 0x13);
399 offset = check_offset;
402 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
404 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
406 check_offset = RBIOS16(check_offset + 0x15);
408 offset = check_offset;
411 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
413 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
415 check_offset = RBIOS16(check_offset + 0x17);
417 offset = check_offset;
420 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
422 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
424 check_offset = RBIOS16(check_offset + 0x2);
426 offset = check_offset;
429 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
431 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
433 check_offset = RBIOS16(check_offset + 0x4);
435 offset = check_offset;
446 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
454 edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1),
459 memcpy((unsigned char *)edid,
460 (unsigned char *)(rdev->bios + edid_info), EDID_LENGTH);
462 if (!drm_edid_is_valid(edid)) {
467 rdev->mode_info.bios_hardcoded_edid = edid;
472 radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
474 if (rdev->mode_info.bios_hardcoded_edid)
475 return rdev->mode_info.bios_hardcoded_edid;
479 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
482 struct radeon_i2c_bus_rec i2c;
484 if (ddc_line == RADEON_GPIOPAD_MASK) {
485 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
486 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
487 i2c.a_clk_reg = RADEON_GPIOPAD_A;
488 i2c.a_data_reg = RADEON_GPIOPAD_A;
489 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
490 i2c.en_data_reg = RADEON_GPIOPAD_EN;
491 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
492 i2c.y_data_reg = RADEON_GPIOPAD_Y;
493 } else if (ddc_line == RADEON_MDGPIO_MASK) {
494 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
495 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
496 i2c.a_clk_reg = RADEON_MDGPIO_A;
497 i2c.a_data_reg = RADEON_MDGPIO_A;
498 i2c.en_clk_reg = RADEON_MDGPIO_EN;
499 i2c.en_data_reg = RADEON_MDGPIO_EN;
500 i2c.y_clk_reg = RADEON_MDGPIO_Y;
501 i2c.y_data_reg = RADEON_MDGPIO_Y;
503 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
504 i2c.mask_data_mask = RADEON_GPIO_EN_0;
505 i2c.a_clk_mask = RADEON_GPIO_A_1;
506 i2c.a_data_mask = RADEON_GPIO_A_0;
507 i2c.en_clk_mask = RADEON_GPIO_EN_1;
508 i2c.en_data_mask = RADEON_GPIO_EN_0;
509 i2c.y_clk_mask = RADEON_GPIO_Y_1;
510 i2c.y_data_mask = RADEON_GPIO_Y_0;
512 i2c.mask_clk_reg = ddc_line;
513 i2c.mask_data_reg = ddc_line;
514 i2c.a_clk_reg = ddc_line;
515 i2c.a_data_reg = ddc_line;
516 i2c.en_clk_reg = ddc_line;
517 i2c.en_data_reg = ddc_line;
518 i2c.y_clk_reg = ddc_line;
519 i2c.y_data_reg = ddc_line;
522 switch (rdev->family) {
530 case RADEON_GPIO_DVI_DDC:
531 /* in theory this should be hw capable,
532 * but it doesn't seem to work
534 i2c.hw_capable = false;
537 i2c.hw_capable = false;
543 case RADEON_GPIO_DVI_DDC:
544 case RADEON_GPIO_MONID:
545 i2c.hw_capable = true;
548 i2c.hw_capable = false;
555 case RADEON_GPIO_VGA_DDC:
556 case RADEON_GPIO_DVI_DDC:
557 case RADEON_GPIO_CRT2_DDC:
558 i2c.hw_capable = true;
561 i2c.hw_capable = false;
568 case RADEON_GPIO_VGA_DDC:
569 case RADEON_GPIO_DVI_DDC:
570 i2c.hw_capable = true;
573 i2c.hw_capable = false;
582 case RADEON_GPIO_VGA_DDC:
583 case RADEON_GPIO_DVI_DDC:
584 i2c.hw_capable = true;
586 case RADEON_GPIO_MONID:
587 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
588 * reliably on some pre-r4xx hardware; not sure why.
590 i2c.hw_capable = false;
593 i2c.hw_capable = false;
598 i2c.hw_capable = false;
612 bool radeon_combios_get_clock_info(struct drm_device *dev)
614 struct radeon_device *rdev = dev->dev_private;
616 struct radeon_pll *p1pll = &rdev->clock.p1pll;
617 struct radeon_pll *p2pll = &rdev->clock.p2pll;
618 struct radeon_pll *spll = &rdev->clock.spll;
619 struct radeon_pll *mpll = &rdev->clock.mpll;
623 if (rdev->bios == NULL)
626 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
628 rev = RBIOS8(pll_info);
631 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
632 p1pll->reference_div = RBIOS16(pll_info + 0x10);
633 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
634 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
637 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
638 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
640 p1pll->pll_in_min = 40;
641 p1pll->pll_in_max = 500;
646 spll->reference_freq = RBIOS16(pll_info + 0x1a);
647 spll->reference_div = RBIOS16(pll_info + 0x1c);
648 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
649 spll->pll_out_max = RBIOS32(pll_info + 0x22);
652 spll->pll_in_min = RBIOS32(pll_info + 0x48);
653 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
656 spll->pll_in_min = 40;
657 spll->pll_in_max = 500;
661 mpll->reference_freq = RBIOS16(pll_info + 0x26);
662 mpll->reference_div = RBIOS16(pll_info + 0x28);
663 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
664 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
667 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
668 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
671 mpll->pll_in_min = 40;
672 mpll->pll_in_max = 500;
675 /* default sclk/mclk */
676 sclk = RBIOS16(pll_info + 0xa);
677 mclk = RBIOS16(pll_info + 0x8);
683 rdev->clock.default_sclk = sclk;
684 rdev->clock.default_mclk = mclk;
691 bool radeon_combios_sideport_present(struct radeon_device *rdev)
693 struct drm_device *dev = rdev->ddev;
696 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
699 if (RBIOS16(igp_info + 0x4))
705 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
706 0x00000808, /* r100 */
707 0x00000808, /* rv100 */
708 0x00000808, /* rs100 */
709 0x00000808, /* rv200 */
710 0x00000808, /* rs200 */
711 0x00000808, /* r200 */
712 0x00000808, /* rv250 */
713 0x00000000, /* rs300 */
714 0x00000808, /* rv280 */
715 0x00000808, /* r300 */
716 0x00000808, /* r350 */
717 0x00000808, /* rv350 */
718 0x00000808, /* rv380 */
719 0x00000808, /* r420 */
720 0x00000808, /* r423 */
721 0x00000808, /* rv410 */
722 0x00000000, /* rs400 */
723 0x00000000, /* rs480 */
726 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
727 struct radeon_encoder_primary_dac *p_dac)
729 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
733 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
737 struct drm_device *dev = encoder->base.dev;
738 struct radeon_device *rdev = dev->dev_private;
740 uint8_t rev, bg, dac;
741 struct radeon_encoder_primary_dac *p_dac = NULL;
744 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
750 if (rdev->bios == NULL)
753 /* check CRT table */
754 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
756 rev = RBIOS8(dac_info) & 0x3;
758 bg = RBIOS8(dac_info + 0x2) & 0xf;
759 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
760 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
762 bg = RBIOS8(dac_info + 0x2) & 0xf;
763 dac = RBIOS8(dac_info + 0x3) & 0xf;
764 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
770 if (!found) /* fallback to defaults */
771 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
777 radeon_combios_get_tv_info(struct radeon_device *rdev)
779 struct drm_device *dev = rdev->ddev;
781 enum radeon_tv_std tv_std = TV_STD_NTSC;
783 if (rdev->bios == NULL)
786 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
788 if (RBIOS8(tv_info + 6) == 'T') {
789 switch (RBIOS8(tv_info + 7) & 0xf) {
791 tv_std = TV_STD_NTSC;
792 DRM_INFO("Default TV standard: NTSC\n");
796 DRM_INFO("Default TV standard: PAL\n");
799 tv_std = TV_STD_PAL_M;
800 DRM_INFO("Default TV standard: PAL-M\n");
803 tv_std = TV_STD_PAL_60;
804 DRM_INFO("Default TV standard: PAL-60\n");
807 tv_std = TV_STD_NTSC_J;
808 DRM_INFO("Default TV standard: NTSC-J\n");
811 tv_std = TV_STD_SCART_PAL;
812 DRM_INFO("Default TV standard: SCART-PAL\n");
815 tv_std = TV_STD_NTSC;
817 ("Unknown TV standard; defaulting to NTSC\n");
821 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
823 DRM_INFO("29.498928713 MHz TV ref clk\n");
826 DRM_INFO("28.636360000 MHz TV ref clk\n");
829 DRM_INFO("14.318180000 MHz TV ref clk\n");
832 DRM_INFO("27.000000000 MHz TV ref clk\n");
842 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
843 0x00000000, /* r100 */
844 0x00280000, /* rv100 */
845 0x00000000, /* rs100 */
846 0x00880000, /* rv200 */
847 0x00000000, /* rs200 */
848 0x00000000, /* r200 */
849 0x00770000, /* rv250 */
850 0x00290000, /* rs300 */
851 0x00560000, /* rv280 */
852 0x00780000, /* r300 */
853 0x00770000, /* r350 */
854 0x00780000, /* rv350 */
855 0x00780000, /* rv380 */
856 0x01080000, /* r420 */
857 0x01080000, /* r423 */
858 0x01080000, /* rv410 */
859 0x00780000, /* rs400 */
860 0x00780000, /* rs480 */
863 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
864 struct radeon_encoder_tv_dac *tv_dac)
866 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
867 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
868 tv_dac->ps2_tvdac_adj = 0x00880000;
869 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
870 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
874 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
878 struct drm_device *dev = encoder->base.dev;
879 struct radeon_device *rdev = dev->dev_private;
881 uint8_t rev, bg, dac;
882 struct radeon_encoder_tv_dac *tv_dac = NULL;
885 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
889 if (rdev->bios == NULL)
892 /* first check TV table */
893 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
895 rev = RBIOS8(dac_info + 0x3);
897 bg = RBIOS8(dac_info + 0xc) & 0xf;
898 dac = RBIOS8(dac_info + 0xd) & 0xf;
899 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
901 bg = RBIOS8(dac_info + 0xe) & 0xf;
902 dac = RBIOS8(dac_info + 0xf) & 0xf;
903 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
905 bg = RBIOS8(dac_info + 0x10) & 0xf;
906 dac = RBIOS8(dac_info + 0x11) & 0xf;
907 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
909 } else if (rev > 1) {
910 bg = RBIOS8(dac_info + 0xc) & 0xf;
911 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
912 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
914 bg = RBIOS8(dac_info + 0xd) & 0xf;
915 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
916 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
918 bg = RBIOS8(dac_info + 0xe) & 0xf;
919 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
920 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
923 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
926 /* then check CRT table */
928 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
930 rev = RBIOS8(dac_info) & 0x3;
932 bg = RBIOS8(dac_info + 0x3) & 0xf;
933 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
934 tv_dac->ps2_tvdac_adj =
935 (bg << 16) | (dac << 20);
936 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
937 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
940 bg = RBIOS8(dac_info + 0x4) & 0xf;
941 dac = RBIOS8(dac_info + 0x5) & 0xf;
942 tv_dac->ps2_tvdac_adj =
943 (bg << 16) | (dac << 20);
944 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
945 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
949 DRM_INFO("No TV DAC info found in BIOS\n");
954 if (!found) /* fallback to defaults */
955 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
960 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
964 struct radeon_encoder_lvds *lvds = NULL;
965 uint32_t fp_vert_stretch, fp_horz_stretch;
966 uint32_t ppll_div_sel, ppll_val;
967 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
969 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
974 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
975 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
977 /* These should be fail-safe defaults, fingers crossed */
978 lvds->panel_pwr_delay = 200;
979 lvds->panel_vcc_delay = 2000;
981 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
982 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
983 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
985 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
986 lvds->native_mode.vdisplay =
987 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
988 RADEON_VERT_PANEL_SHIFT) + 1;
990 lvds->native_mode.vdisplay =
991 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
993 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
994 lvds->native_mode.hdisplay =
995 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
996 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
998 lvds->native_mode.hdisplay =
999 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1001 if ((lvds->native_mode.hdisplay < 640) ||
1002 (lvds->native_mode.vdisplay < 480)) {
1003 lvds->native_mode.hdisplay = 640;
1004 lvds->native_mode.vdisplay = 480;
1007 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1008 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1009 if ((ppll_val & 0x000707ff) == 0x1bb)
1010 lvds->use_bios_dividers = false;
1012 lvds->panel_ref_divider =
1013 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1014 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1015 lvds->panel_fb_divider = ppll_val & 0x7ff;
1017 if ((lvds->panel_ref_divider != 0) &&
1018 (lvds->panel_fb_divider > 3))
1019 lvds->use_bios_dividers = true;
1021 lvds->panel_vcc_delay = 200;
1023 DRM_INFO("Panel info derived from registers\n");
1024 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1025 lvds->native_mode.vdisplay);
1030 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1033 struct drm_device *dev = encoder->base.dev;
1034 struct radeon_device *rdev = dev->dev_private;
1036 uint32_t panel_setup;
1039 struct radeon_encoder_lvds *lvds = NULL;
1041 if (rdev->bios == NULL) {
1042 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1046 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1049 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1054 for (i = 0; i < 24; i++)
1055 stmp[i] = RBIOS8(lcd_info + i + 1);
1058 DRM_INFO("Panel ID String: %s\n", stmp);
1060 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1061 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1063 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1064 lvds->native_mode.vdisplay);
1066 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1067 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1069 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1070 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1071 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1073 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1074 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1075 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1076 if ((lvds->panel_ref_divider != 0) &&
1077 (lvds->panel_fb_divider > 3))
1078 lvds->use_bios_dividers = true;
1080 panel_setup = RBIOS32(lcd_info + 0x39);
1081 lvds->lvds_gen_cntl = 0xff00;
1082 if (panel_setup & 0x1)
1083 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1085 if ((panel_setup >> 4) & 0x1)
1086 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1088 switch ((panel_setup >> 8) & 0x7) {
1090 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1093 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1096 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1102 if ((panel_setup >> 16) & 0x1)
1103 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1105 if ((panel_setup >> 17) & 0x1)
1106 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1108 if ((panel_setup >> 18) & 0x1)
1109 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1111 if ((panel_setup >> 23) & 0x1)
1112 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1114 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1116 for (i = 0; i < 32; i++) {
1117 tmp = RBIOS16(lcd_info + 64 + i * 2);
1121 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1122 (RBIOS16(tmp + 2) ==
1123 lvds->native_mode.vdisplay)) {
1124 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
1125 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
1126 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
1127 RBIOS16(tmp + 21)) * 8;
1129 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
1130 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
1131 lvds->native_mode.vsync_end =
1132 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
1133 (RBIOS16(tmp + 28) & 0x7ff);
1135 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1136 lvds->native_mode.flags = 0;
1137 /* set crtc values */
1138 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1143 DRM_INFO("No panel info found in BIOS\n");
1144 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1148 encoder->native_mode = lvds->native_mode;
1152 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1153 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1154 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1155 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1156 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1157 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1158 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1159 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1160 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1161 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1162 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1163 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1164 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1165 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1166 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1167 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1168 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1169 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1170 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1173 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1174 struct radeon_encoder_int_tmds *tmds)
1176 struct drm_device *dev = encoder->base.dev;
1177 struct radeon_device *rdev = dev->dev_private;
1180 for (i = 0; i < 4; i++) {
1181 tmds->tmds_pll[i].value =
1182 default_tmds_pll[rdev->family][i].value;
1183 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1189 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1190 struct radeon_encoder_int_tmds *tmds)
1192 struct drm_device *dev = encoder->base.dev;
1193 struct radeon_device *rdev = dev->dev_private;
1198 if (rdev->bios == NULL)
1201 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1204 ver = RBIOS8(tmds_info);
1205 DRM_INFO("DFP table revision: %d\n", ver);
1207 n = RBIOS8(tmds_info + 5) + 1;
1210 for (i = 0; i < n; i++) {
1211 tmds->tmds_pll[i].value =
1212 RBIOS32(tmds_info + i * 10 + 0x08);
1213 tmds->tmds_pll[i].freq =
1214 RBIOS16(tmds_info + i * 10 + 0x10);
1215 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1216 tmds->tmds_pll[i].freq,
1217 tmds->tmds_pll[i].value);
1219 } else if (ver == 4) {
1221 n = RBIOS8(tmds_info + 5) + 1;
1224 for (i = 0; i < n; i++) {
1225 tmds->tmds_pll[i].value =
1226 RBIOS32(tmds_info + stride + 0x08);
1227 tmds->tmds_pll[i].freq =
1228 RBIOS16(tmds_info + stride + 0x10);
1233 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1234 tmds->tmds_pll[i].freq,
1235 tmds->tmds_pll[i].value);
1239 DRM_INFO("No TMDS info found in BIOS\n");
1245 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1246 struct radeon_encoder_ext_tmds *tmds)
1248 struct drm_device *dev = encoder->base.dev;
1249 struct radeon_device *rdev = dev->dev_private;
1250 struct radeon_i2c_bus_rec i2c_bus;
1252 /* default for macs */
1253 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1254 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1256 /* XXX some macs have duallink chips */
1257 switch (rdev->mode_info.connector_table) {
1258 case CT_POWERBOOK_EXTERNAL:
1259 case CT_MINI_EXTERNAL:
1261 tmds->dvo_chip = DVO_SIL164;
1262 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1269 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1270 struct radeon_encoder_ext_tmds *tmds)
1272 struct drm_device *dev = encoder->base.dev;
1273 struct radeon_device *rdev = dev->dev_private;
1275 uint8_t ver, id, blocks, clk, data;
1277 enum radeon_combios_ddc gpio;
1278 struct radeon_i2c_bus_rec i2c_bus;
1280 if (rdev->bios == NULL)
1283 tmds->i2c_bus = NULL;
1284 if (rdev->flags & RADEON_IS_IGP) {
1285 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1287 ver = RBIOS8(offset);
1288 DRM_INFO("GPIO Table revision: %d\n", ver);
1289 blocks = RBIOS8(offset + 2);
1290 for (i = 0; i < blocks; i++) {
1291 id = RBIOS8(offset + 3 + (i * 5) + 0);
1293 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1294 data = RBIOS8(offset + 3 + (i * 5) + 4);
1295 i2c_bus.valid = true;
1296 i2c_bus.mask_clk_mask = (1 << clk);
1297 i2c_bus.mask_data_mask = (1 << data);
1298 i2c_bus.a_clk_mask = (1 << clk);
1299 i2c_bus.a_data_mask = (1 << data);
1300 i2c_bus.en_clk_mask = (1 << clk);
1301 i2c_bus.en_data_mask = (1 << data);
1302 i2c_bus.y_clk_mask = (1 << clk);
1303 i2c_bus.y_data_mask = (1 << data);
1304 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1305 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1306 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1307 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1308 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1309 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1310 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1311 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1312 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1313 tmds->dvo_chip = DVO_SIL164;
1314 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1320 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1322 ver = RBIOS8(offset);
1323 DRM_INFO("External TMDS Table revision: %d\n", ver);
1324 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1325 tmds->slave_addr >>= 1; /* 7 bit addressing */
1326 gpio = RBIOS8(offset + 4 + 3);
1329 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1330 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1333 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1334 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1337 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1338 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1341 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1342 if (rdev->family >= CHIP_R300)
1343 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1345 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1346 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1348 case DDC_LCD: /* MM i2c */
1349 i2c_bus.valid = true;
1350 i2c_bus.hw_capable = true;
1351 i2c_bus.mm_i2c = true;
1352 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1355 DRM_ERROR("Unsupported gpio %d\n", gpio);
1361 if (!tmds->i2c_bus) {
1362 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1369 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1371 struct radeon_device *rdev = dev->dev_private;
1372 struct radeon_i2c_bus_rec ddc_i2c;
1373 struct radeon_hpd hpd;
1375 rdev->mode_info.connector_table = radeon_connector_table;
1376 if (rdev->mode_info.connector_table == CT_NONE) {
1377 #ifdef CONFIG_PPC_PMAC
1378 if (machine_is_compatible("PowerBook3,3")) {
1379 /* powerbook with VGA */
1380 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1381 } else if (machine_is_compatible("PowerBook3,4") ||
1382 machine_is_compatible("PowerBook3,5")) {
1383 /* powerbook with internal tmds */
1384 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1385 } else if (machine_is_compatible("PowerBook5,1") ||
1386 machine_is_compatible("PowerBook5,2") ||
1387 machine_is_compatible("PowerBook5,3") ||
1388 machine_is_compatible("PowerBook5,4") ||
1389 machine_is_compatible("PowerBook5,5")) {
1390 /* powerbook with external single link tmds (sil164) */
1391 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1392 } else if (machine_is_compatible("PowerBook5,6")) {
1393 /* powerbook with external dual or single link tmds */
1394 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1395 } else if (machine_is_compatible("PowerBook5,7") ||
1396 machine_is_compatible("PowerBook5,8") ||
1397 machine_is_compatible("PowerBook5,9")) {
1398 /* PowerBook6,2 ? */
1399 /* powerbook with external dual link tmds (sil1178?) */
1400 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1401 } else if (machine_is_compatible("PowerBook4,1") ||
1402 machine_is_compatible("PowerBook4,2") ||
1403 machine_is_compatible("PowerBook4,3") ||
1404 machine_is_compatible("PowerBook6,3") ||
1405 machine_is_compatible("PowerBook6,5") ||
1406 machine_is_compatible("PowerBook6,7")) {
1408 rdev->mode_info.connector_table = CT_IBOOK;
1409 } else if (machine_is_compatible("PowerMac4,4")) {
1411 rdev->mode_info.connector_table = CT_EMAC;
1412 } else if (machine_is_compatible("PowerMac10,1")) {
1413 /* mini with internal tmds */
1414 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1415 } else if (machine_is_compatible("PowerMac10,2")) {
1416 /* mini with external tmds */
1417 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1418 } else if (machine_is_compatible("PowerMac12,1")) {
1420 /* imac g5 isight */
1421 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1423 #endif /* CONFIG_PPC_PMAC */
1424 rdev->mode_info.connector_table = CT_GENERIC;
1427 switch (rdev->mode_info.connector_table) {
1429 DRM_INFO("Connector Table: %d (generic)\n",
1430 rdev->mode_info.connector_table);
1431 /* these are the most common settings */
1432 if (rdev->flags & RADEON_SINGLE_CRTC) {
1433 /* VGA - primary dac */
1434 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1435 hpd.hpd = RADEON_HPD_NONE;
1436 radeon_add_legacy_encoder(dev,
1437 radeon_get_encoder_id(dev,
1438 ATOM_DEVICE_CRT1_SUPPORT,
1440 ATOM_DEVICE_CRT1_SUPPORT);
1441 radeon_add_legacy_connector(dev, 0,
1442 ATOM_DEVICE_CRT1_SUPPORT,
1443 DRM_MODE_CONNECTOR_VGA,
1445 CONNECTOR_OBJECT_ID_VGA,
1447 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1449 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
1450 hpd.hpd = RADEON_HPD_NONE;
1451 radeon_add_legacy_encoder(dev,
1452 radeon_get_encoder_id(dev,
1453 ATOM_DEVICE_LCD1_SUPPORT,
1455 ATOM_DEVICE_LCD1_SUPPORT);
1456 radeon_add_legacy_connector(dev, 0,
1457 ATOM_DEVICE_LCD1_SUPPORT,
1458 DRM_MODE_CONNECTOR_LVDS,
1460 CONNECTOR_OBJECT_ID_LVDS,
1463 /* VGA - primary dac */
1464 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1465 hpd.hpd = RADEON_HPD_NONE;
1466 radeon_add_legacy_encoder(dev,
1467 radeon_get_encoder_id(dev,
1468 ATOM_DEVICE_CRT1_SUPPORT,
1470 ATOM_DEVICE_CRT1_SUPPORT);
1471 radeon_add_legacy_connector(dev, 1,
1472 ATOM_DEVICE_CRT1_SUPPORT,
1473 DRM_MODE_CONNECTOR_VGA,
1475 CONNECTOR_OBJECT_ID_VGA,
1478 /* DVI-I - tv dac, int tmds */
1479 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1480 hpd.hpd = RADEON_HPD_1;
1481 radeon_add_legacy_encoder(dev,
1482 radeon_get_encoder_id(dev,
1483 ATOM_DEVICE_DFP1_SUPPORT,
1485 ATOM_DEVICE_DFP1_SUPPORT);
1486 radeon_add_legacy_encoder(dev,
1487 radeon_get_encoder_id(dev,
1488 ATOM_DEVICE_CRT2_SUPPORT,
1490 ATOM_DEVICE_CRT2_SUPPORT);
1491 radeon_add_legacy_connector(dev, 0,
1492 ATOM_DEVICE_DFP1_SUPPORT |
1493 ATOM_DEVICE_CRT2_SUPPORT,
1494 DRM_MODE_CONNECTOR_DVII,
1496 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1499 /* VGA - primary dac */
1500 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1501 hpd.hpd = RADEON_HPD_NONE;
1502 radeon_add_legacy_encoder(dev,
1503 radeon_get_encoder_id(dev,
1504 ATOM_DEVICE_CRT1_SUPPORT,
1506 ATOM_DEVICE_CRT1_SUPPORT);
1507 radeon_add_legacy_connector(dev, 1,
1508 ATOM_DEVICE_CRT1_SUPPORT,
1509 DRM_MODE_CONNECTOR_VGA,
1511 CONNECTOR_OBJECT_ID_VGA,
1515 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1517 ddc_i2c.valid = false;
1518 hpd.hpd = RADEON_HPD_NONE;
1519 radeon_add_legacy_encoder(dev,
1520 radeon_get_encoder_id(dev,
1521 ATOM_DEVICE_TV1_SUPPORT,
1523 ATOM_DEVICE_TV1_SUPPORT);
1524 radeon_add_legacy_connector(dev, 2,
1525 ATOM_DEVICE_TV1_SUPPORT,
1526 DRM_MODE_CONNECTOR_SVIDEO,
1528 CONNECTOR_OBJECT_ID_SVIDEO,
1533 DRM_INFO("Connector Table: %d (ibook)\n",
1534 rdev->mode_info.connector_table);
1536 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1537 hpd.hpd = RADEON_HPD_NONE;
1538 radeon_add_legacy_encoder(dev,
1539 radeon_get_encoder_id(dev,
1540 ATOM_DEVICE_LCD1_SUPPORT,
1542 ATOM_DEVICE_LCD1_SUPPORT);
1543 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1544 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1545 CONNECTOR_OBJECT_ID_LVDS,
1548 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1549 hpd.hpd = RADEON_HPD_NONE;
1550 radeon_add_legacy_encoder(dev,
1551 radeon_get_encoder_id(dev,
1552 ATOM_DEVICE_CRT2_SUPPORT,
1554 ATOM_DEVICE_CRT2_SUPPORT);
1555 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1556 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1557 CONNECTOR_OBJECT_ID_VGA,
1560 ddc_i2c.valid = false;
1561 hpd.hpd = RADEON_HPD_NONE;
1562 radeon_add_legacy_encoder(dev,
1563 radeon_get_encoder_id(dev,
1564 ATOM_DEVICE_TV1_SUPPORT,
1566 ATOM_DEVICE_TV1_SUPPORT);
1567 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1568 DRM_MODE_CONNECTOR_SVIDEO,
1570 CONNECTOR_OBJECT_ID_SVIDEO,
1573 case CT_POWERBOOK_EXTERNAL:
1574 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1575 rdev->mode_info.connector_table);
1577 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1578 hpd.hpd = RADEON_HPD_NONE;
1579 radeon_add_legacy_encoder(dev,
1580 radeon_get_encoder_id(dev,
1581 ATOM_DEVICE_LCD1_SUPPORT,
1583 ATOM_DEVICE_LCD1_SUPPORT);
1584 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1585 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1586 CONNECTOR_OBJECT_ID_LVDS,
1588 /* DVI-I - primary dac, ext tmds */
1589 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1590 hpd.hpd = RADEON_HPD_2; /* ??? */
1591 radeon_add_legacy_encoder(dev,
1592 radeon_get_encoder_id(dev,
1593 ATOM_DEVICE_DFP2_SUPPORT,
1595 ATOM_DEVICE_DFP2_SUPPORT);
1596 radeon_add_legacy_encoder(dev,
1597 radeon_get_encoder_id(dev,
1598 ATOM_DEVICE_CRT1_SUPPORT,
1600 ATOM_DEVICE_CRT1_SUPPORT);
1601 /* XXX some are SL */
1602 radeon_add_legacy_connector(dev, 1,
1603 ATOM_DEVICE_DFP2_SUPPORT |
1604 ATOM_DEVICE_CRT1_SUPPORT,
1605 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1606 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1609 ddc_i2c.valid = false;
1610 hpd.hpd = RADEON_HPD_NONE;
1611 radeon_add_legacy_encoder(dev,
1612 radeon_get_encoder_id(dev,
1613 ATOM_DEVICE_TV1_SUPPORT,
1615 ATOM_DEVICE_TV1_SUPPORT);
1616 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1617 DRM_MODE_CONNECTOR_SVIDEO,
1619 CONNECTOR_OBJECT_ID_SVIDEO,
1622 case CT_POWERBOOK_INTERNAL:
1623 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1624 rdev->mode_info.connector_table);
1626 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1627 hpd.hpd = RADEON_HPD_NONE;
1628 radeon_add_legacy_encoder(dev,
1629 radeon_get_encoder_id(dev,
1630 ATOM_DEVICE_LCD1_SUPPORT,
1632 ATOM_DEVICE_LCD1_SUPPORT);
1633 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1634 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1635 CONNECTOR_OBJECT_ID_LVDS,
1637 /* DVI-I - primary dac, int tmds */
1638 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1639 hpd.hpd = RADEON_HPD_1; /* ??? */
1640 radeon_add_legacy_encoder(dev,
1641 radeon_get_encoder_id(dev,
1642 ATOM_DEVICE_DFP1_SUPPORT,
1644 ATOM_DEVICE_DFP1_SUPPORT);
1645 radeon_add_legacy_encoder(dev,
1646 radeon_get_encoder_id(dev,
1647 ATOM_DEVICE_CRT1_SUPPORT,
1649 ATOM_DEVICE_CRT1_SUPPORT);
1650 radeon_add_legacy_connector(dev, 1,
1651 ATOM_DEVICE_DFP1_SUPPORT |
1652 ATOM_DEVICE_CRT1_SUPPORT,
1653 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1654 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1657 ddc_i2c.valid = false;
1658 hpd.hpd = RADEON_HPD_NONE;
1659 radeon_add_legacy_encoder(dev,
1660 radeon_get_encoder_id(dev,
1661 ATOM_DEVICE_TV1_SUPPORT,
1663 ATOM_DEVICE_TV1_SUPPORT);
1664 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1665 DRM_MODE_CONNECTOR_SVIDEO,
1667 CONNECTOR_OBJECT_ID_SVIDEO,
1670 case CT_POWERBOOK_VGA:
1671 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1672 rdev->mode_info.connector_table);
1674 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1675 hpd.hpd = RADEON_HPD_NONE;
1676 radeon_add_legacy_encoder(dev,
1677 radeon_get_encoder_id(dev,
1678 ATOM_DEVICE_LCD1_SUPPORT,
1680 ATOM_DEVICE_LCD1_SUPPORT);
1681 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1682 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1683 CONNECTOR_OBJECT_ID_LVDS,
1685 /* VGA - primary dac */
1686 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1687 hpd.hpd = RADEON_HPD_NONE;
1688 radeon_add_legacy_encoder(dev,
1689 radeon_get_encoder_id(dev,
1690 ATOM_DEVICE_CRT1_SUPPORT,
1692 ATOM_DEVICE_CRT1_SUPPORT);
1693 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1694 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1695 CONNECTOR_OBJECT_ID_VGA,
1698 ddc_i2c.valid = false;
1699 hpd.hpd = RADEON_HPD_NONE;
1700 radeon_add_legacy_encoder(dev,
1701 radeon_get_encoder_id(dev,
1702 ATOM_DEVICE_TV1_SUPPORT,
1704 ATOM_DEVICE_TV1_SUPPORT);
1705 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1706 DRM_MODE_CONNECTOR_SVIDEO,
1708 CONNECTOR_OBJECT_ID_SVIDEO,
1711 case CT_MINI_EXTERNAL:
1712 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1713 rdev->mode_info.connector_table);
1714 /* DVI-I - tv dac, ext tmds */
1715 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1716 hpd.hpd = RADEON_HPD_2; /* ??? */
1717 radeon_add_legacy_encoder(dev,
1718 radeon_get_encoder_id(dev,
1719 ATOM_DEVICE_DFP2_SUPPORT,
1721 ATOM_DEVICE_DFP2_SUPPORT);
1722 radeon_add_legacy_encoder(dev,
1723 radeon_get_encoder_id(dev,
1724 ATOM_DEVICE_CRT2_SUPPORT,
1726 ATOM_DEVICE_CRT2_SUPPORT);
1727 /* XXX are any DL? */
1728 radeon_add_legacy_connector(dev, 0,
1729 ATOM_DEVICE_DFP2_SUPPORT |
1730 ATOM_DEVICE_CRT2_SUPPORT,
1731 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1732 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1735 ddc_i2c.valid = false;
1736 hpd.hpd = RADEON_HPD_NONE;
1737 radeon_add_legacy_encoder(dev,
1738 radeon_get_encoder_id(dev,
1739 ATOM_DEVICE_TV1_SUPPORT,
1741 ATOM_DEVICE_TV1_SUPPORT);
1742 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1743 DRM_MODE_CONNECTOR_SVIDEO,
1745 CONNECTOR_OBJECT_ID_SVIDEO,
1748 case CT_MINI_INTERNAL:
1749 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1750 rdev->mode_info.connector_table);
1751 /* DVI-I - tv dac, int tmds */
1752 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1753 hpd.hpd = RADEON_HPD_1; /* ??? */
1754 radeon_add_legacy_encoder(dev,
1755 radeon_get_encoder_id(dev,
1756 ATOM_DEVICE_DFP1_SUPPORT,
1758 ATOM_DEVICE_DFP1_SUPPORT);
1759 radeon_add_legacy_encoder(dev,
1760 radeon_get_encoder_id(dev,
1761 ATOM_DEVICE_CRT2_SUPPORT,
1763 ATOM_DEVICE_CRT2_SUPPORT);
1764 radeon_add_legacy_connector(dev, 0,
1765 ATOM_DEVICE_DFP1_SUPPORT |
1766 ATOM_DEVICE_CRT2_SUPPORT,
1767 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1768 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1771 ddc_i2c.valid = false;
1772 hpd.hpd = RADEON_HPD_NONE;
1773 radeon_add_legacy_encoder(dev,
1774 radeon_get_encoder_id(dev,
1775 ATOM_DEVICE_TV1_SUPPORT,
1777 ATOM_DEVICE_TV1_SUPPORT);
1778 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1779 DRM_MODE_CONNECTOR_SVIDEO,
1781 CONNECTOR_OBJECT_ID_SVIDEO,
1784 case CT_IMAC_G5_ISIGHT:
1785 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1786 rdev->mode_info.connector_table);
1787 /* DVI-D - int tmds */
1788 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1789 hpd.hpd = RADEON_HPD_1; /* ??? */
1790 radeon_add_legacy_encoder(dev,
1791 radeon_get_encoder_id(dev,
1792 ATOM_DEVICE_DFP1_SUPPORT,
1794 ATOM_DEVICE_DFP1_SUPPORT);
1795 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1796 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1797 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1800 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1801 hpd.hpd = RADEON_HPD_NONE;
1802 radeon_add_legacy_encoder(dev,
1803 radeon_get_encoder_id(dev,
1804 ATOM_DEVICE_CRT2_SUPPORT,
1806 ATOM_DEVICE_CRT2_SUPPORT);
1807 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1808 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1809 CONNECTOR_OBJECT_ID_VGA,
1812 ddc_i2c.valid = false;
1813 hpd.hpd = RADEON_HPD_NONE;
1814 radeon_add_legacy_encoder(dev,
1815 radeon_get_encoder_id(dev,
1816 ATOM_DEVICE_TV1_SUPPORT,
1818 ATOM_DEVICE_TV1_SUPPORT);
1819 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1820 DRM_MODE_CONNECTOR_SVIDEO,
1822 CONNECTOR_OBJECT_ID_SVIDEO,
1826 DRM_INFO("Connector Table: %d (emac)\n",
1827 rdev->mode_info.connector_table);
1828 /* VGA - primary dac */
1829 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1830 hpd.hpd = RADEON_HPD_NONE;
1831 radeon_add_legacy_encoder(dev,
1832 radeon_get_encoder_id(dev,
1833 ATOM_DEVICE_CRT1_SUPPORT,
1835 ATOM_DEVICE_CRT1_SUPPORT);
1836 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1837 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1838 CONNECTOR_OBJECT_ID_VGA,
1841 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1842 hpd.hpd = RADEON_HPD_NONE;
1843 radeon_add_legacy_encoder(dev,
1844 radeon_get_encoder_id(dev,
1845 ATOM_DEVICE_CRT2_SUPPORT,
1847 ATOM_DEVICE_CRT2_SUPPORT);
1848 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1849 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1850 CONNECTOR_OBJECT_ID_VGA,
1853 ddc_i2c.valid = false;
1854 hpd.hpd = RADEON_HPD_NONE;
1855 radeon_add_legacy_encoder(dev,
1856 radeon_get_encoder_id(dev,
1857 ATOM_DEVICE_TV1_SUPPORT,
1859 ATOM_DEVICE_TV1_SUPPORT);
1860 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1861 DRM_MODE_CONNECTOR_SVIDEO,
1863 CONNECTOR_OBJECT_ID_SVIDEO,
1867 DRM_INFO("Connector table: %d (invalid)\n",
1868 rdev->mode_info.connector_table);
1872 radeon_link_encoder_connector(dev);
1877 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1879 enum radeon_combios_connector
1881 struct radeon_i2c_bus_rec *ddc_i2c,
1882 struct radeon_hpd *hpd)
1884 struct radeon_device *rdev = dev->dev_private;
1886 /* XPRESS DDC quirks */
1887 if ((rdev->family == CHIP_RS400 ||
1888 rdev->family == CHIP_RS480) &&
1889 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1890 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1891 else if ((rdev->family == CHIP_RS400 ||
1892 rdev->family == CHIP_RS480) &&
1893 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1894 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1895 ddc_i2c->mask_clk_mask = (0x20 << 8);
1896 ddc_i2c->mask_data_mask = 0x80;
1897 ddc_i2c->a_clk_mask = (0x20 << 8);
1898 ddc_i2c->a_data_mask = 0x80;
1899 ddc_i2c->en_clk_mask = (0x20 << 8);
1900 ddc_i2c->en_data_mask = 0x80;
1901 ddc_i2c->y_clk_mask = (0x20 << 8);
1902 ddc_i2c->y_data_mask = 0x80;
1905 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1906 if ((rdev->family >= CHIP_R300) &&
1907 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1908 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1910 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1911 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1912 if (dev->pdev->device == 0x515e &&
1913 dev->pdev->subsystem_vendor == 0x1014) {
1914 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1915 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1919 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1920 if (dev->pdev->device == 0x5159 &&
1921 dev->pdev->subsystem_vendor == 0x1002 &&
1922 dev->pdev->subsystem_device == 0x013a) {
1923 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1924 *legacy_connector = CONNECTOR_CRT_LEGACY;
1928 /* X300 card with extra non-existent DVI port */
1929 if (dev->pdev->device == 0x5B60 &&
1930 dev->pdev->subsystem_vendor == 0x17af &&
1931 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1932 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1939 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1941 /* Acer 5102 has non-existent TV port */
1942 if (dev->pdev->device == 0x5975 &&
1943 dev->pdev->subsystem_vendor == 0x1025 &&
1944 dev->pdev->subsystem_device == 0x009f)
1947 /* HP dc5750 has non-existent TV port */
1948 if (dev->pdev->device == 0x5974 &&
1949 dev->pdev->subsystem_vendor == 0x103c &&
1950 dev->pdev->subsystem_device == 0x280a)
1953 /* MSI S270 has non-existent TV port */
1954 if (dev->pdev->device == 0x5955 &&
1955 dev->pdev->subsystem_vendor == 0x1462 &&
1956 dev->pdev->subsystem_device == 0x0131)
1962 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1964 struct radeon_device *rdev = dev->dev_private;
1965 uint32_t ext_tmds_info;
1967 if (rdev->flags & RADEON_IS_IGP) {
1969 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1971 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1973 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1974 if (ext_tmds_info) {
1975 uint8_t rev = RBIOS8(ext_tmds_info);
1976 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1979 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1981 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1985 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1987 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1992 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1994 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1997 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1999 struct radeon_device *rdev = dev->dev_private;
2000 uint32_t conn_info, entry, devices;
2001 uint16_t tmp, connector_object_id;
2002 enum radeon_combios_ddc ddc_type;
2003 enum radeon_combios_connector connector;
2005 struct radeon_i2c_bus_rec ddc_i2c;
2006 struct radeon_hpd hpd;
2008 if (rdev->bios == NULL)
2011 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2013 for (i = 0; i < 4; i++) {
2014 entry = conn_info + 2 + i * 2;
2016 if (!RBIOS16(entry))
2019 tmp = RBIOS16(entry);
2021 connector = (tmp >> 12) & 0xf;
2023 ddc_type = (tmp >> 8) & 0xf;
2027 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
2031 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2035 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2039 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
2045 switch (connector) {
2046 case CONNECTOR_PROPRIETARY_LEGACY:
2047 case CONNECTOR_DVI_I_LEGACY:
2048 case CONNECTOR_DVI_D_LEGACY:
2049 if ((tmp >> 4) & 0x1)
2050 hpd.hpd = RADEON_HPD_2;
2052 hpd.hpd = RADEON_HPD_1;
2055 hpd.hpd = RADEON_HPD_NONE;
2059 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2063 switch (connector) {
2064 case CONNECTOR_PROPRIETARY_LEGACY:
2065 if ((tmp >> 4) & 0x1)
2066 devices = ATOM_DEVICE_DFP2_SUPPORT;
2068 devices = ATOM_DEVICE_DFP1_SUPPORT;
2069 radeon_add_legacy_encoder(dev,
2070 radeon_get_encoder_id
2073 radeon_add_legacy_connector(dev, i, devices,
2074 legacy_connector_convert
2077 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2080 case CONNECTOR_CRT_LEGACY:
2082 devices = ATOM_DEVICE_CRT2_SUPPORT;
2083 radeon_add_legacy_encoder(dev,
2084 radeon_get_encoder_id
2086 ATOM_DEVICE_CRT2_SUPPORT,
2088 ATOM_DEVICE_CRT2_SUPPORT);
2090 devices = ATOM_DEVICE_CRT1_SUPPORT;
2091 radeon_add_legacy_encoder(dev,
2092 radeon_get_encoder_id
2094 ATOM_DEVICE_CRT1_SUPPORT,
2096 ATOM_DEVICE_CRT1_SUPPORT);
2098 radeon_add_legacy_connector(dev,
2101 legacy_connector_convert
2104 CONNECTOR_OBJECT_ID_VGA,
2107 case CONNECTOR_DVI_I_LEGACY:
2110 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2111 radeon_add_legacy_encoder(dev,
2112 radeon_get_encoder_id
2114 ATOM_DEVICE_CRT2_SUPPORT,
2116 ATOM_DEVICE_CRT2_SUPPORT);
2118 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2119 radeon_add_legacy_encoder(dev,
2120 radeon_get_encoder_id
2122 ATOM_DEVICE_CRT1_SUPPORT,
2124 ATOM_DEVICE_CRT1_SUPPORT);
2126 if ((tmp >> 4) & 0x1) {
2127 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2128 radeon_add_legacy_encoder(dev,
2129 radeon_get_encoder_id
2131 ATOM_DEVICE_DFP2_SUPPORT,
2133 ATOM_DEVICE_DFP2_SUPPORT);
2134 connector_object_id = combios_check_dl_dvi(dev, 0);
2136 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2137 radeon_add_legacy_encoder(dev,
2138 radeon_get_encoder_id
2140 ATOM_DEVICE_DFP1_SUPPORT,
2142 ATOM_DEVICE_DFP1_SUPPORT);
2143 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2145 radeon_add_legacy_connector(dev,
2148 legacy_connector_convert
2151 connector_object_id,
2154 case CONNECTOR_DVI_D_LEGACY:
2155 if ((tmp >> 4) & 0x1) {
2156 devices = ATOM_DEVICE_DFP2_SUPPORT;
2157 connector_object_id = combios_check_dl_dvi(dev, 1);
2159 devices = ATOM_DEVICE_DFP1_SUPPORT;
2160 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2162 radeon_add_legacy_encoder(dev,
2163 radeon_get_encoder_id
2166 radeon_add_legacy_connector(dev, i, devices,
2167 legacy_connector_convert
2170 connector_object_id,
2173 case CONNECTOR_CTV_LEGACY:
2174 case CONNECTOR_STV_LEGACY:
2175 radeon_add_legacy_encoder(dev,
2176 radeon_get_encoder_id
2178 ATOM_DEVICE_TV1_SUPPORT,
2180 ATOM_DEVICE_TV1_SUPPORT);
2181 radeon_add_legacy_connector(dev, i,
2182 ATOM_DEVICE_TV1_SUPPORT,
2183 legacy_connector_convert
2186 CONNECTOR_OBJECT_ID_SVIDEO,
2190 DRM_ERROR("Unknown connector type: %d\n",
2197 uint16_t tmds_info =
2198 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2200 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2202 radeon_add_legacy_encoder(dev,
2203 radeon_get_encoder_id(dev,
2204 ATOM_DEVICE_CRT1_SUPPORT,
2206 ATOM_DEVICE_CRT1_SUPPORT);
2207 radeon_add_legacy_encoder(dev,
2208 radeon_get_encoder_id(dev,
2209 ATOM_DEVICE_DFP1_SUPPORT,
2211 ATOM_DEVICE_DFP1_SUPPORT);
2213 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2214 hpd.hpd = RADEON_HPD_NONE;
2215 radeon_add_legacy_connector(dev,
2217 ATOM_DEVICE_CRT1_SUPPORT |
2218 ATOM_DEVICE_DFP1_SUPPORT,
2219 DRM_MODE_CONNECTOR_DVII,
2221 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2225 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2226 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2228 radeon_add_legacy_encoder(dev,
2229 radeon_get_encoder_id(dev,
2230 ATOM_DEVICE_CRT1_SUPPORT,
2232 ATOM_DEVICE_CRT1_SUPPORT);
2233 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2234 hpd.hpd = RADEON_HPD_NONE;
2235 radeon_add_legacy_connector(dev,
2237 ATOM_DEVICE_CRT1_SUPPORT,
2238 DRM_MODE_CONNECTOR_VGA,
2240 CONNECTOR_OBJECT_ID_VGA,
2243 DRM_DEBUG("No connector info found\n");
2249 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2251 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2253 uint16_t lcd_ddc_info =
2254 combios_get_table_offset(dev,
2255 COMBIOS_LCD_DDC_INFO_TABLE);
2257 radeon_add_legacy_encoder(dev,
2258 radeon_get_encoder_id(dev,
2259 ATOM_DEVICE_LCD1_SUPPORT,
2261 ATOM_DEVICE_LCD1_SUPPORT);
2264 ddc_type = RBIOS8(lcd_ddc_info + 2);
2268 combios_setup_i2c_bus
2269 (rdev, RADEON_GPIO_MONID);
2273 combios_setup_i2c_bus
2274 (rdev, RADEON_GPIO_DVI_DDC);
2278 combios_setup_i2c_bus
2279 (rdev, RADEON_GPIO_VGA_DDC);
2283 combios_setup_i2c_bus
2284 (rdev, RADEON_GPIO_CRT2_DDC);
2288 combios_setup_i2c_bus
2289 (rdev, RADEON_GPIOPAD_MASK);
2290 ddc_i2c.mask_clk_mask =
2291 RBIOS32(lcd_ddc_info + 3);
2292 ddc_i2c.mask_data_mask =
2293 RBIOS32(lcd_ddc_info + 7);
2294 ddc_i2c.a_clk_mask =
2295 RBIOS32(lcd_ddc_info + 3);
2296 ddc_i2c.a_data_mask =
2297 RBIOS32(lcd_ddc_info + 7);
2298 ddc_i2c.en_clk_mask =
2299 RBIOS32(lcd_ddc_info + 3);
2300 ddc_i2c.en_data_mask =
2301 RBIOS32(lcd_ddc_info + 7);
2302 ddc_i2c.y_clk_mask =
2303 RBIOS32(lcd_ddc_info + 3);
2304 ddc_i2c.y_data_mask =
2305 RBIOS32(lcd_ddc_info + 7);
2309 combios_setup_i2c_bus
2310 (rdev, RADEON_MDGPIO_MASK);
2311 ddc_i2c.mask_clk_mask =
2312 RBIOS32(lcd_ddc_info + 3);
2313 ddc_i2c.mask_data_mask =
2314 RBIOS32(lcd_ddc_info + 7);
2315 ddc_i2c.a_clk_mask =
2316 RBIOS32(lcd_ddc_info + 3);
2317 ddc_i2c.a_data_mask =
2318 RBIOS32(lcd_ddc_info + 7);
2319 ddc_i2c.en_clk_mask =
2320 RBIOS32(lcd_ddc_info + 3);
2321 ddc_i2c.en_data_mask =
2322 RBIOS32(lcd_ddc_info + 7);
2323 ddc_i2c.y_clk_mask =
2324 RBIOS32(lcd_ddc_info + 3);
2325 ddc_i2c.y_data_mask =
2326 RBIOS32(lcd_ddc_info + 7);
2329 ddc_i2c.valid = false;
2332 DRM_DEBUG("LCD DDC Info Table found!\n");
2334 ddc_i2c.valid = false;
2336 hpd.hpd = RADEON_HPD_NONE;
2337 radeon_add_legacy_connector(dev,
2339 ATOM_DEVICE_LCD1_SUPPORT,
2340 DRM_MODE_CONNECTOR_LVDS,
2342 CONNECTOR_OBJECT_ID_LVDS,
2347 /* check TV table */
2348 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2350 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2352 if (RBIOS8(tv_info + 6) == 'T') {
2353 if (radeon_apply_legacy_tv_quirks(dev)) {
2354 hpd.hpd = RADEON_HPD_NONE;
2355 radeon_add_legacy_encoder(dev,
2356 radeon_get_encoder_id
2358 ATOM_DEVICE_TV1_SUPPORT,
2360 ATOM_DEVICE_TV1_SUPPORT);
2361 radeon_add_legacy_connector(dev, 6,
2362 ATOM_DEVICE_TV1_SUPPORT,
2363 DRM_MODE_CONNECTOR_SVIDEO,
2365 CONNECTOR_OBJECT_ID_SVIDEO,
2372 radeon_link_encoder_connector(dev);
2377 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2379 struct drm_device *dev = rdev->ddev;
2380 u16 offset, misc, misc2 = 0;
2381 u8 rev, blocks, tmp;
2382 int state_index = 0;
2384 rdev->pm.default_power_state = NULL;
2385 rdev->pm.current_power_state = NULL;
2387 /* XXX mac/sparc cards */
2388 if (rdev->bios == NULL)
2391 if (rdev->flags & RADEON_IS_MOBILITY) {
2392 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2394 rev = RBIOS8(offset);
2395 blocks = RBIOS8(offset + 0x2);
2396 /* power mode 0 tends to be the only valid one */
2397 rdev->pm.power_state[state_index].num_clock_modes = 1;
2398 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2399 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2400 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2401 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2403 /* skip overclock modes for now */
2404 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
2405 rdev->clock.default_mclk) ||
2406 (rdev->pm.power_state[state_index].clock_info[0].sclk >
2407 rdev->clock.default_sclk))
2409 rdev->pm.power_state[state_index].type =
2410 POWER_STATE_TYPE_BATTERY;
2411 misc = RBIOS16(offset + 0x5 + 0x0);
2413 misc2 = RBIOS16(offset + 0x5 + 0xe);
2415 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2417 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2420 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2422 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2424 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2425 RBIOS16(offset + 0x5 + 0xb) * 4;
2426 tmp = RBIOS8(offset + 0x5 + 0xd);
2427 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2429 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2430 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2431 if (entries && voltage_table_offset) {
2432 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2433 RBIOS16(voltage_table_offset) * 4;
2434 tmp = RBIOS8(voltage_table_offset + 0x2);
2435 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2437 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2439 switch ((misc2 & 0x700) >> 8) {
2442 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2445 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2448 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2451 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2454 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2458 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2460 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
2461 RBIOS8(offset + 0x5 + 0x10);
2464 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2467 /* XXX figure out some good default low power mode for desktop cards */
2471 /* add the default mode */
2472 rdev->pm.power_state[state_index].type =
2473 POWER_STATE_TYPE_DEFAULT;
2474 rdev->pm.power_state[state_index].num_clock_modes = 1;
2475 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2476 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2477 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2478 rdev->pm.power_state[state_index].current_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2479 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2480 if (rdev->asic->get_pcie_lanes)
2481 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
2483 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
2484 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
2485 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
2486 rdev->pm.num_power_states = state_index + 1;
2489 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2491 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2492 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2497 switch (tmds->dvo_chip) {
2500 radeon_i2c_put_byte(tmds->i2c_bus,
2503 radeon_i2c_put_byte(tmds->i2c_bus,
2506 radeon_i2c_put_byte(tmds->i2c_bus,
2509 radeon_i2c_put_byte(tmds->i2c_bus,
2512 radeon_i2c_put_byte(tmds->i2c_bus,
2517 /* sil 1178 - untested */
2536 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2538 struct drm_device *dev = encoder->dev;
2539 struct radeon_device *rdev = dev->dev_private;
2540 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2542 uint8_t blocks, slave_addr, rev;
2544 uint32_t reg, val, and_mask, or_mask;
2545 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2547 if (rdev->bios == NULL)
2553 if (rdev->flags & RADEON_IS_IGP) {
2554 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2555 rev = RBIOS8(offset);
2557 rev = RBIOS8(offset);
2559 blocks = RBIOS8(offset + 3);
2561 while (blocks > 0) {
2562 id = RBIOS16(index);
2566 reg = (id & 0x1fff) * 4;
2567 val = RBIOS32(index);
2572 reg = (id & 0x1fff) * 4;
2573 and_mask = RBIOS32(index);
2575 or_mask = RBIOS32(index);
2578 val = (val & and_mask) | or_mask;
2582 val = RBIOS16(index);
2587 val = RBIOS16(index);
2592 slave_addr = id & 0xff;
2593 slave_addr >>= 1; /* 7 bit addressing */
2595 reg = RBIOS8(index);
2597 val = RBIOS8(index);
2599 radeon_i2c_put_byte(tmds->i2c_bus,
2604 DRM_ERROR("Unknown id %d\n", id >> 13);
2613 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2615 index = offset + 10;
2616 id = RBIOS16(index);
2617 while (id != 0xffff) {
2621 reg = (id & 0x1fff) * 4;
2622 val = RBIOS32(index);
2626 reg = (id & 0x1fff) * 4;
2627 and_mask = RBIOS32(index);
2629 or_mask = RBIOS32(index);
2632 val = (val & and_mask) | or_mask;
2636 val = RBIOS16(index);
2642 and_mask = RBIOS32(index);
2644 or_mask = RBIOS32(index);
2646 val = RREG32_PLL(reg);
2647 val = (val & and_mask) | or_mask;
2648 WREG32_PLL(reg, val);
2652 val = RBIOS8(index);
2654 radeon_i2c_put_byte(tmds->i2c_bus,
2659 DRM_ERROR("Unknown id %d\n", id >> 13);
2662 id = RBIOS16(index);
2670 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2672 struct radeon_device *rdev = dev->dev_private;
2675 while (RBIOS16(offset)) {
2676 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2677 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2678 uint32_t val, and_mask, or_mask;
2684 val = RBIOS32(offset);
2689 val = RBIOS32(offset);
2694 and_mask = RBIOS32(offset);
2696 or_mask = RBIOS32(offset);
2704 and_mask = RBIOS32(offset);
2706 or_mask = RBIOS32(offset);
2714 val = RBIOS16(offset);
2719 val = RBIOS16(offset);
2726 (RADEON_CLK_PWRMGT_CNTL) &
2733 if ((RREG32(RADEON_MC_STATUS) &
2749 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2751 struct radeon_device *rdev = dev->dev_private;
2754 while (RBIOS8(offset)) {
2755 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2756 uint8_t addr = (RBIOS8(offset) & 0x3f);
2757 uint32_t val, shift, tmp;
2758 uint32_t and_mask, or_mask;
2763 val = RBIOS32(offset);
2765 WREG32_PLL(addr, val);
2768 shift = RBIOS8(offset) * 8;
2770 and_mask = RBIOS8(offset) << shift;
2771 and_mask |= ~(0xff << shift);
2773 or_mask = RBIOS8(offset) << shift;
2775 tmp = RREG32_PLL(addr);
2778 WREG32_PLL(addr, tmp);
2794 (RADEON_CLK_PWRMGT_CNTL) &
2802 (RADEON_CLK_PWRMGT_CNTL) &
2809 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2810 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2812 uint32_t mclk_cntl =
2815 mclk_cntl &= 0xffff0000;
2816 /*mclk_cntl |= 0x00001111;*//* ??? */
2817 WREG32_PLL(RADEON_MCLK_CNTL,
2822 (RADEON_CLK_PWRMGT_CNTL,
2824 ~RADEON_CG_NO1_DEBUG_0);
2839 static void combios_parse_ram_reset_table(struct drm_device *dev,
2842 struct radeon_device *rdev = dev->dev_private;
2846 uint8_t val = RBIOS8(offset);
2847 while (val != 0xff) {
2851 uint32_t channel_complete_mask;
2853 if (ASIC_IS_R300(rdev))
2854 channel_complete_mask =
2855 R300_MEM_PWRUP_COMPLETE;
2857 channel_complete_mask =
2858 RADEON_MEM_PWRUP_COMPLETE;
2861 if ((RREG32(RADEON_MEM_STR_CNTL) &
2862 channel_complete_mask) ==
2863 channel_complete_mask)
2867 uint32_t or_mask = RBIOS16(offset);
2870 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2871 tmp &= RADEON_SDRAM_MODE_MASK;
2873 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2875 or_mask = val << 24;
2876 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2877 tmp &= RADEON_B3MEM_RESET_MASK;
2879 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2881 val = RBIOS8(offset);
2886 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2887 int mem_addr_mapping)
2889 struct radeon_device *rdev = dev->dev_private;
2894 mem_cntl = RREG32(RADEON_MEM_CNTL);
2895 if (mem_cntl & RV100_HALF_MODE)
2898 mem_cntl &= ~(0xff << 8);
2899 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2900 WREG32(RADEON_MEM_CNTL, mem_cntl);
2901 RREG32(RADEON_MEM_CNTL);
2905 /* something like this???? */
2907 addr = ram * 1024 * 1024;
2908 /* write to each page */
2909 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2910 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2911 /* read back and verify */
2912 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2913 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2920 static void combios_write_ram_size(struct drm_device *dev)
2922 struct radeon_device *rdev = dev->dev_private;
2925 uint32_t mem_size = 0;
2926 uint32_t mem_cntl = 0;
2928 /* should do something smarter here I guess... */
2929 if (rdev->flags & RADEON_IS_IGP)
2932 /* first check detected mem table */
2933 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2935 rev = RBIOS8(offset);
2937 mem_cntl = RBIOS32(offset + 1);
2938 mem_size = RBIOS16(offset + 5);
2939 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2940 ((dev->pdev->device != 0x515e)
2941 && (dev->pdev->device != 0x5969)))
2942 WREG32(RADEON_MEM_CNTL, mem_cntl);
2948 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2950 rev = RBIOS8(offset - 1);
2952 if (((rdev->flags & RADEON_FAMILY_MASK) <
2954 && ((dev->pdev->device != 0x515e)
2955 && (dev->pdev->device != 0x5969))) {
2957 int mem_addr_mapping = 0;
2959 while (RBIOS8(offset)) {
2960 ram = RBIOS8(offset);
2963 if (mem_addr_mapping != 0x25)
2966 combios_detect_ram(dev, ram,
2973 mem_size = RBIOS8(offset);
2975 mem_size = RBIOS8(offset);
2976 mem_size *= 2; /* convert to MB */
2981 mem_size *= (1024 * 1024); /* convert to bytes */
2982 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2985 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2987 uint16_t dyn_clk_info =
2988 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2991 combios_parse_pll_table(dev, dyn_clk_info);
2994 void radeon_combios_asic_init(struct drm_device *dev)
2996 struct radeon_device *rdev = dev->dev_private;
2999 /* port hardcoded mac stuff from radeonfb */
3000 if (rdev->bios == NULL)
3004 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3006 combios_parse_mmio_table(dev, table);
3009 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3011 combios_parse_pll_table(dev, table);
3014 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3016 combios_parse_mmio_table(dev, table);
3018 if (!(rdev->flags & RADEON_IS_IGP)) {
3021 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3023 combios_parse_mmio_table(dev, table);
3026 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3028 combios_parse_ram_reset_table(dev, table);
3032 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3034 combios_parse_mmio_table(dev, table);
3036 /* write CONFIG_MEMSIZE */
3037 combios_write_ram_size(dev);
3041 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3043 combios_parse_pll_table(dev, table);
3047 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3049 struct radeon_device *rdev = dev->dev_private;
3050 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3052 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3053 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3054 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3056 /* let the bios control the backlight */
3057 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3059 /* tell the bios not to handle mode switching */
3060 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3061 RADEON_ACC_MODE_CHANGE);
3063 /* tell the bios a driver is loaded */
3064 bios_7_scratch |= RADEON_DRV_LOADED;
3066 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3067 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3068 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3071 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3073 struct drm_device *dev = encoder->dev;
3074 struct radeon_device *rdev = dev->dev_private;
3075 uint32_t bios_6_scratch;
3077 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3080 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3082 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3084 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3088 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3089 struct drm_encoder *encoder,
3092 struct drm_device *dev = connector->dev;
3093 struct radeon_device *rdev = dev->dev_private;
3094 struct radeon_connector *radeon_connector =
3095 to_radeon_connector(connector);
3096 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3097 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3098 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3100 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3101 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3103 DRM_DEBUG("TV1 connected\n");
3105 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3106 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3107 bios_5_scratch |= RADEON_TV1_ON;
3108 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3110 DRM_DEBUG("TV1 disconnected\n");
3111 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3112 bios_5_scratch &= ~RADEON_TV1_ON;
3113 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3116 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3117 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3119 DRM_DEBUG("LCD1 connected\n");
3120 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3121 bios_5_scratch |= RADEON_LCD1_ON;
3122 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3124 DRM_DEBUG("LCD1 disconnected\n");
3125 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3126 bios_5_scratch &= ~RADEON_LCD1_ON;
3127 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3130 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3131 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3133 DRM_DEBUG("CRT1 connected\n");
3134 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3135 bios_5_scratch |= RADEON_CRT1_ON;
3136 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3138 DRM_DEBUG("CRT1 disconnected\n");
3139 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3140 bios_5_scratch &= ~RADEON_CRT1_ON;
3141 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3144 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3145 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3147 DRM_DEBUG("CRT2 connected\n");
3148 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3149 bios_5_scratch |= RADEON_CRT2_ON;
3150 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3152 DRM_DEBUG("CRT2 disconnected\n");
3153 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3154 bios_5_scratch &= ~RADEON_CRT2_ON;
3155 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3158 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3159 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3161 DRM_DEBUG("DFP1 connected\n");
3162 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3163 bios_5_scratch |= RADEON_DFP1_ON;
3164 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3166 DRM_DEBUG("DFP1 disconnected\n");
3167 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3168 bios_5_scratch &= ~RADEON_DFP1_ON;
3169 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3172 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3173 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3175 DRM_DEBUG("DFP2 connected\n");
3176 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3177 bios_5_scratch |= RADEON_DFP2_ON;
3178 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3180 DRM_DEBUG("DFP2 disconnected\n");
3181 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3182 bios_5_scratch &= ~RADEON_DFP2_ON;
3183 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3186 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3187 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3191 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3193 struct drm_device *dev = encoder->dev;
3194 struct radeon_device *rdev = dev->dev_private;
3195 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3196 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3198 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3199 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3200 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3202 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3203 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3204 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3206 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3207 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3208 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3210 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3211 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3212 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3214 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3215 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3216 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3218 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3219 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3220 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3222 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3226 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3228 struct drm_device *dev = encoder->dev;
3229 struct radeon_device *rdev = dev->dev_private;
3230 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3231 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3233 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3235 bios_6_scratch |= RADEON_TV_DPMS_ON;
3237 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3239 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3241 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3243 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3245 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3247 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3249 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3251 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3253 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3255 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3257 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);