drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <linux/pci.h>
  28
  29 #include <drm/drm_device.h>
  30 #include <drm/radeon_drm.h>
  31
  32 #include "radeon.h"
  33
  34 #include "atom.h"
  35 #include "atom-bits.h"
  36 #include "radeon_asic.h"
  37 #include "radeon_atombios.h"
  38 #include "radeon_legacy_encoders.h"
  39
  40 union atom_supported_devices {
  41         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  42         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  43         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  44 };
  45
  46 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
  47                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  48                                           u8 index)
  49 {
  50         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  51         if ((rdev->family == CHIP_R420) ||
  52             (rdev->family == CHIP_R423) ||
  53             (rdev->family == CHIP_RV410)) {
  54                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  55                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  56                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  57                         gpio->ucClkMaskShift = 0x19;
  58                         gpio->ucDataMaskShift = 0x18;
  59                 }
  60         }
  61
  62         /* some evergreen boards have bad data for this entry */
  63         if (ASIC_IS_DCE4(rdev)) {
  64                 if ((index == 7) &&
  65                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
  66                     (gpio->sucI2cId.ucAccess == 0)) {
  67                         gpio->sucI2cId.ucAccess = 0x97;
  68                         gpio->ucDataMaskShift = 8;
  69                         gpio->ucDataEnShift = 8;
  70                         gpio->ucDataY_Shift = 8;
  71                         gpio->ucDataA_Shift = 8;
  72                 }
  73         }
  74
  75         /* some DCE3 boards have bad data for this entry */
  76         if (ASIC_IS_DCE3(rdev)) {
  77                 if ((index == 4) &&
  78                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
  79                     (gpio->sucI2cId.ucAccess == 0x94))
  80                         gpio->sucI2cId.ucAccess = 0x14;
  81         }
  82 }
  83
  84 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  85 {
  86         struct radeon_i2c_bus_rec i2c;
  87
  88         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  89
  90         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  91         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  92         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  93         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  94         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  95         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  96         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  97         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  98         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  99         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 100         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 101         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 102         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 103         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 104         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 105         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 106
 107         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 108                 i2c.hw_capable = true;
 109         else
 110                 i2c.hw_capable = false;
 111
 112         if (gpio->sucI2cId.ucAccess == 0xa0)
 113                 i2c.mm_i2c = true;
 114         else
 115                 i2c.mm_i2c = false;
 116
 117         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 118
 119         if (i2c.mask_clk_reg)
 120                 i2c.valid = true;
 121         else
 122                 i2c.valid = false;
 123
 124         return i2c;
 125 }
 126
 127 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
 128                                                                uint8_t id)
 129 {
 130         struct atom_context *ctx = rdev->mode_info.atom_context;
 131         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 132         struct radeon_i2c_bus_rec i2c;
 133         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 134         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 135         uint16_t data_offset, size;
 136         int i, num_indices;
 137
 138         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 139         i2c.valid = false;
 140
 141         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 142                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 143
 144                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 145                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 146
 147                 gpio = &i2c_info->asGPIO_Info[0];
 148                 for (i = 0; i < num_indices; i++) {
 149
 150                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 151
 152                         if (gpio->sucI2cId.ucAccess == id) {
 153                                 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 154                                 break;
 155                         }
 156                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 157                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 158                 }
 159         }
 160
 161         return i2c;
 162 }
 163
 164 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 165 {
 166         struct atom_context *ctx = rdev->mode_info.atom_context;
 167         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 168         struct radeon_i2c_bus_rec i2c;
 169         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 170         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 171         uint16_t data_offset, size;
 172         int i, num_indices;
 173         char stmp[32];
 174
 175         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 176                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 177
 178                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 179                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 180
 181                 gpio = &i2c_info->asGPIO_Info[0];
 182                 for (i = 0; i < num_indices; i++) {
 183                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 184
 185                         i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 186
 187                         if (i2c.valid) {
 188                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 189                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 190                         }
 191                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 192                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 193                 }
 194         }
 195 }
 196
 197 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
 198                                                    u8 id)
 199 {
 200         struct atom_context *ctx = rdev->mode_info.atom_context;
 201         struct radeon_gpio_rec gpio;
 202         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 203         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 204         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 205         u16 data_offset, size;
 206         int i, num_indices;
 207
 208         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 209         gpio.valid = false;
 210
 211         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 212                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 213
 214                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 215                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 216
 217                 pin = gpio_info->asGPIO_Pin;
 218                 for (i = 0; i < num_indices; i++) {
 219                         if (id == pin->ucGPIO_ID) {
 220                                 gpio.id = pin->ucGPIO_ID;
 221                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 222                                 gpio.shift = pin->ucGpioPinBitShift;
 223                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 224                                 gpio.valid = true;
 225                                 break;
 226                         }
 227                         pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 228                                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 229                 }
 230         }
 231
 232         return gpio;
 233 }
 234
 235 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 236                                                             struct radeon_gpio_rec *gpio)
 237 {
 238         struct radeon_hpd hpd;
 239         u32 reg;
 240
 241         memset(&hpd, 0, sizeof(struct radeon_hpd));
 242
 243         if (ASIC_IS_DCE6(rdev))
 244                 reg = SI_DC_GPIO_HPD_A;
 245         else if (ASIC_IS_DCE4(rdev))
 246                 reg = EVERGREEN_DC_GPIO_HPD_A;
 247         else
 248                 reg = AVIVO_DC_GPIO_HPD_A;
 249
 250         hpd.gpio = *gpio;
 251         if (gpio->reg == reg) {
 252                 switch(gpio->mask) {
 253                 case (1 << 0):
 254                         hpd.hpd = RADEON_HPD_1;
 255                         break;
 256                 case (1 << 8):
 257                         hpd.hpd = RADEON_HPD_2;
 258                         break;
 259                 case (1 << 16):
 260                         hpd.hpd = RADEON_HPD_3;
 261                         break;
 262                 case (1 << 24):
 263                         hpd.hpd = RADEON_HPD_4;
 264                         break;
 265                 case (1 << 26):
 266                         hpd.hpd = RADEON_HPD_5;
 267                         break;
 268                 case (1 << 28):
 269                         hpd.hpd = RADEON_HPD_6;
 270                         break;
 271                 default:
 272                         hpd.hpd = RADEON_HPD_NONE;
 273                         break;
 274                 }
 275         } else
 276                 hpd.hpd = RADEON_HPD_NONE;
 277         return hpd;
 278 }
 279
 280 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 281                                      uint32_t supported_device,
 282                                      int *connector_type,
 283                                      struct radeon_i2c_bus_rec *i2c_bus,
 284                                      uint16_t *line_mux,
 285                                      struct radeon_hpd *hpd)
 286 {
 287         struct pci_dev *pdev = to_pci_dev(dev->dev);
 288
 289         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 290         if ((pdev->device == 0x791e) &&
 291             (pdev->subsystem_vendor == 0x1043) &&
 292             (pdev->subsystem_device == 0x826d)) {
 293                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 294                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 295                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 296         }
 297
 298         /* Asrock RS600 board lists the DVI port as HDMI */
 299         if ((pdev->device == 0x7941) &&
 300             (pdev->subsystem_vendor == 0x1849) &&
 301             (pdev->subsystem_device == 0x7941)) {
 302                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 303                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 304                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 305         }
 306
 307         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 308         if ((pdev->device == 0x796e) &&
 309             (pdev->subsystem_vendor == 0x1462) &&
 310             (pdev->subsystem_device == 0x7302)) {
 311                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 312                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 313                         return false;
 314         }
 315
 316         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 317         if ((pdev->device == 0x7941) &&
 318             (pdev->subsystem_vendor == 0x147b) &&
 319             (pdev->subsystem_device == 0x2412)) {
 320                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 321                         return false;
 322         }
 323
 324         /* Falcon NW laptop lists vga ddc line for LVDS */
 325         if ((pdev->device == 0x5653) &&
 326             (pdev->subsystem_vendor == 0x1462) &&
 327             (pdev->subsystem_device == 0x0291)) {
 328                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 329                         i2c_bus->valid = false;
 330                         *line_mux = 53;
 331                 }
 332         }
 333
 334         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 335         if ((pdev->device == 0x7146) &&
 336             (pdev->subsystem_vendor == 0x17af) &&
 337             (pdev->subsystem_device == 0x2058)) {
 338                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 339                         return false;
 340         }
 341
 342         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 343         if ((pdev->device == 0x7142) &&
 344             (pdev->subsystem_vendor == 0x1458) &&
 345             (pdev->subsystem_device == 0x2134)) {
 346                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 347                         return false;
 348         }
 349
 350
 351         /* Funky macbooks */
 352         if ((pdev->device == 0x71C5) &&
 353             (pdev->subsystem_vendor == 0x106b) &&
 354             (pdev->subsystem_device == 0x0080)) {
 355                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 356                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 357                         return false;
 358                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 359                         *line_mux = 0x90;
 360         }
 361
 362         /* mac rv630, rv730, others */
 363         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 364             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 365                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 366                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 367         }
 368
 369         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 370         if ((pdev->device == 0x9598) &&
 371             (pdev->subsystem_vendor == 0x1043) &&
 372             (pdev->subsystem_device == 0x01da)) {
 373                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 374                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 375                 }
 376         }
 377
 378         /* ASUS HD 3600 board lists the DVI port as HDMI */
 379         if ((pdev->device == 0x9598) &&
 380             (pdev->subsystem_vendor == 0x1043) &&
 381             (pdev->subsystem_device == 0x01e4)) {
 382                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 383                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 384                 }
 385         }
 386
 387         /* ASUS HD 3450 board lists the DVI port as HDMI */
 388         if ((pdev->device == 0x95C5) &&
 389             (pdev->subsystem_vendor == 0x1043) &&
 390             (pdev->subsystem_device == 0x01e2)) {
 391                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 392                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 393                 }
 394         }
 395
 396         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 397          * HDMI + VGA reporting as HDMI
 398          */
 399         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 400                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 401                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 402                         *line_mux = 0;
 403                 }
 404         }
 405
 406         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 407          * on the laptop and a DVI port on the docking station and
 408          * both share the same encoder, hpd pin, and ddc line.
 409          * So while the bios table is technically correct,
 410          * we drop the DVI port here since xrandr has no concept of
 411          * encoders and will try and drive both connectors
 412          * with different crtcs which isn't possible on the hardware
 413          * side and leaves no crtcs for LVDS or VGA.
 414          */
 415         if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) &&
 416             (pdev->subsystem_vendor == 0x1025) &&
 417             (pdev->subsystem_device == 0x013c)) {
 418                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 419                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 420                         /* actually it's a DVI-D port not DVI-I */
 421                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 422                         return false;
 423                 }
 424         }
 425
 426         /* XFX Pine Group device rv730 reports no VGA DDC lines
 427          * even though they are wired up to record 0x93
 428          */
 429         if ((pdev->device == 0x9498) &&
 430             (pdev->subsystem_vendor == 0x1682) &&
 431             (pdev->subsystem_device == 0x2452) &&
 432             (i2c_bus->valid == false) &&
 433             !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
 434                 struct radeon_device *rdev = dev->dev_private;
 435                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 436         }
 437
 438         /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
 439         if (((pdev->device == 0x9802) ||
 440              (pdev->device == 0x9805) ||
 441              (pdev->device == 0x9806)) &&
 442             (pdev->subsystem_vendor == 0x1734) &&
 443             (pdev->subsystem_device == 0x11bd)) {
 444                 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
 445                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 446                         *line_mux = 0x3103;
 447                 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
 448                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 449                 }
 450         }
 451
 452         return true;
 453 }
 454
 455 static const int supported_devices_connector_convert[] = {
 456         DRM_MODE_CONNECTOR_Unknown,
 457         DRM_MODE_CONNECTOR_VGA,
 458         DRM_MODE_CONNECTOR_DVII,
 459         DRM_MODE_CONNECTOR_DVID,
 460         DRM_MODE_CONNECTOR_DVIA,
 461         DRM_MODE_CONNECTOR_SVIDEO,
 462         DRM_MODE_CONNECTOR_Composite,
 463         DRM_MODE_CONNECTOR_LVDS,
 464         DRM_MODE_CONNECTOR_Unknown,
 465         DRM_MODE_CONNECTOR_Unknown,
 466         DRM_MODE_CONNECTOR_HDMIA,
 467         DRM_MODE_CONNECTOR_HDMIB,
 468         DRM_MODE_CONNECTOR_Unknown,
 469         DRM_MODE_CONNECTOR_Unknown,
 470         DRM_MODE_CONNECTOR_9PinDIN,
 471         DRM_MODE_CONNECTOR_DisplayPort
 472 };
 473
 474 static const uint16_t supported_devices_connector_object_id_convert[] = {
 475         CONNECTOR_OBJECT_ID_NONE,
 476         CONNECTOR_OBJECT_ID_VGA,
 477         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 478         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 479         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 480         CONNECTOR_OBJECT_ID_COMPOSITE,
 481         CONNECTOR_OBJECT_ID_SVIDEO,
 482         CONNECTOR_OBJECT_ID_LVDS,
 483         CONNECTOR_OBJECT_ID_9PIN_DIN,
 484         CONNECTOR_OBJECT_ID_9PIN_DIN,
 485         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 486         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 487         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 488         CONNECTOR_OBJECT_ID_SVIDEO
 489 };
 490
 491 static const int object_connector_convert[] = {
 492         DRM_MODE_CONNECTOR_Unknown,
 493         DRM_MODE_CONNECTOR_DVII,
 494         DRM_MODE_CONNECTOR_DVII,
 495         DRM_MODE_CONNECTOR_DVID,
 496         DRM_MODE_CONNECTOR_DVID,
 497         DRM_MODE_CONNECTOR_VGA,
 498         DRM_MODE_CONNECTOR_Composite,
 499         DRM_MODE_CONNECTOR_SVIDEO,
 500         DRM_MODE_CONNECTOR_Unknown,
 501         DRM_MODE_CONNECTOR_Unknown,
 502         DRM_MODE_CONNECTOR_9PinDIN,
 503         DRM_MODE_CONNECTOR_Unknown,
 504         DRM_MODE_CONNECTOR_HDMIA,
 505         DRM_MODE_CONNECTOR_HDMIB,
 506         DRM_MODE_CONNECTOR_LVDS,
 507         DRM_MODE_CONNECTOR_9PinDIN,
 508         DRM_MODE_CONNECTOR_Unknown,
 509         DRM_MODE_CONNECTOR_Unknown,
 510         DRM_MODE_CONNECTOR_Unknown,
 511         DRM_MODE_CONNECTOR_DisplayPort,
 512         DRM_MODE_CONNECTOR_eDP,
 513         DRM_MODE_CONNECTOR_Unknown
 514 };
 515
 516 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 517 {
 518         struct radeon_device *rdev = dev->dev_private;
 519         struct radeon_mode_info *mode_info = &rdev->mode_info;
 520         struct atom_context *ctx = mode_info->atom_context;
 521         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 522         u16 size, data_offset;
 523         u8 frev, crev;
 524         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 525         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 526         ATOM_OBJECT_TABLE *router_obj;
 527         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 528         ATOM_OBJECT_HEADER *obj_header;
 529         int i, j, k, path_size, device_support;
 530         int connector_type;
 531         u16 igp_lane_info, conn_id, connector_object_id;
 532         struct radeon_i2c_bus_rec ddc_bus;
 533         struct radeon_router router;
 534         struct radeon_gpio_rec gpio;
 535         struct radeon_hpd hpd;
 536
 537         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 538                 return false;
 539
 540         if (crev < 2)
 541                 return false;
 542
 543         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 544         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 545             (ctx->bios + data_offset +
 546              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 547         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 548             (ctx->bios + data_offset +
 549              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 550         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 551             (ctx->bios + data_offset +
 552              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 553         router_obj = (ATOM_OBJECT_TABLE *)
 554                 (ctx->bios + data_offset +
 555                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 556         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 557
 558         path_size = 0;
 559         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 560                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 561                 ATOM_DISPLAY_OBJECT_PATH *path;
 562                 addr += path_size;
 563                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 564                 path_size += le16_to_cpu(path->usSize);
 565
 566                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 567                         uint8_t con_obj_id, con_obj_num;
 568
 569                         con_obj_id =
 570                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 571                             >> OBJECT_ID_SHIFT;
 572                         con_obj_num =
 573                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 574                             >> ENUM_ID_SHIFT;
 575
 576                         /* TODO CV support */
 577                         if (le16_to_cpu(path->usDeviceTag) ==
 578                                 ATOM_DEVICE_CV_SUPPORT)
 579                                 continue;
 580
 581                         /* IGP chips */
 582                         if ((rdev->flags & RADEON_IS_IGP) &&
 583                             (con_obj_id ==
 584                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 585                                 uint16_t igp_offset = 0;
 586                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 587
 588                                 index =
 589                                     GetIndexIntoMasterTable(DATA,
 590                                                             IntegratedSystemInfo);
 591
 592                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 593                                                            &crev, &igp_offset)) {
 594
 595                                         if (crev >= 2) {
 596                                                 igp_obj =
 597                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 598                                                          *) (ctx->bios + igp_offset);
 599
 600                                                 if (igp_obj) {
 601                                                         uint32_t slot_config, ct;
 602
 603                                                         if (con_obj_num == 1)
 604                                                                 slot_config =
 605                                                                         igp_obj->
 606                                                                         ulDDISlot1Config;
 607                                                         else
 608                                                                 slot_config =
 609                                                                         igp_obj->
 610                                                                         ulDDISlot2Config;
 611
 612                                                         ct = (slot_config >> 16) & 0xff;
 613                                                         connector_type =
 614                                                                 object_connector_convert
 615                                                                 [ct];
 616                                                         connector_object_id = ct;
 617                                                         igp_lane_info =
 618                                                                 slot_config & 0xffff;
 619                                                 } else
 620                                                         continue;
 621                                         } else
 622                                                 continue;
 623                                 } else {
 624                                         igp_lane_info = 0;
 625                                         connector_type =
 626                                                 object_connector_convert[con_obj_id];
 627                                         connector_object_id = con_obj_id;
 628                                 }
 629                         } else {
 630                                 igp_lane_info = 0;
 631                                 connector_type =
 632                                     object_connector_convert[con_obj_id];
 633                                 connector_object_id = con_obj_id;
 634                         }
 635
 636                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 637                                 continue;
 638
 639                         router.ddc_valid = false;
 640                         router.cd_valid = false;
 641                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 642                                 uint8_t grph_obj_type =
 643                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 644                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 645
 646                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 647                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 648                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 649                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 650                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 651                                                                 (ctx->bios + data_offset +
 652                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 653                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 654                                                         u16 caps = 0;
 655
 656                                                         while (record->ucRecordSize > 0 &&
 657                                                                record->ucRecordType > 0 &&
 658                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 659                                                                 switch (record->ucRecordType) {
 660                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 661                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 662                                                                                 record;
 663                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 664                                                                         break;
 665                                                                 }
 666                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 667                                                                         ((char *)record + record->ucRecordSize);
 668                                                         }
 669                                                         radeon_add_atom_encoder(dev,
 670                                                                                 encoder_obj,
 671                                                                                 le16_to_cpu
 672                                                                                 (path->
 673                                                                                  usDeviceTag),
 674                                                                                 caps);
 675                                                 }
 676                                         }
 677                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 678                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 679                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 680                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 681                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 682                                                                 (ctx->bios + data_offset +
 683                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 684                                                         ATOM_I2C_RECORD *i2c_record;
 685                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 686                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 687                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 688                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 689                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 690                                                                 (ctx->bios + data_offset +
 691                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 692                                                         u8 *num_dst_objs = (u8 *)
 693                                                                 ((u8 *)router_src_dst_table + 1 +
 694                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 695                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 696                                                         int enum_id;
 697
 698                                                         router.router_id = router_obj_id;
 699                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 700                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 701                                                                     le16_to_cpu(dst_objs[enum_id]))
 702                                                                         break;
 703                                                         }
 704
 705                                                         while (record->ucRecordSize > 0 &&
 706                                                                record->ucRecordType > 0 &&
 707                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 708                                                                 switch (record->ucRecordType) {
 709                                                                 case ATOM_I2C_RECORD_TYPE:
 710                                                                         i2c_record =
 711                                                                                 (ATOM_I2C_RECORD *)
 712                                                                                 record;
 713                                                                         i2c_config =
 714                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 715                                                                                 &i2c_record->sucI2cId;
 716                                                                         router.i2c_info =
 717                                                                                 radeon_lookup_i2c_gpio(rdev,
 718                                                                                                        i2c_config->
 719                                                                                                        ucAccess);
 720                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 721                                                                         break;
 722                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 723                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 724                                                                                 record;
 725                                                                         router.ddc_valid = true;
 726                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 727                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 728                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 729                                                                         break;
 730                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 731                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 732                                                                                 record;
 733                                                                         router.cd_valid = true;
 734                                                                         router.cd_mux_type = cd_path->ucMuxType;
 735                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 736                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 737                                                                         break;
 738                                                                 }
 739                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 740                                                                         ((char *)record + record->ucRecordSize);
 741                                                         }
 742                                                 }
 743                                         }
 744                                 }
 745                         }
 746
 747                         /* look up gpio for ddc, hpd */
 748                         ddc_bus.valid = false;
 749                         hpd.hpd = RADEON_HPD_NONE;
 750                         if ((le16_to_cpu(path->usDeviceTag) &
 751                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 752                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 753                                         if (le16_to_cpu(path->usConnObjectId) ==
 754                                             le16_to_cpu(con_obj->asObjects[j].
 755                                                         usObjectID)) {
 756                                                 ATOM_COMMON_RECORD_HEADER
 757                                                     *record =
 758                                                     (ATOM_COMMON_RECORD_HEADER
 759                                                      *)
 760                                                     (ctx->bios + data_offset +
 761                                                      le16_to_cpu(con_obj->
 762                                                                  asObjects[j].
 763                                                                  usRecordOffset));
 764                                                 ATOM_I2C_RECORD *i2c_record;
 765                                                 ATOM_HPD_INT_RECORD *hpd_record;
 766                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 767
 768                                                 while (record->ucRecordSize > 0 &&
 769                                                        record->ucRecordType > 0 &&
 770                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 771                                                         switch (record->ucRecordType) {
 772                                                         case ATOM_I2C_RECORD_TYPE:
 773                                                                 i2c_record =
 774                                                                     (ATOM_I2C_RECORD *)
 775                                                                         record;
 776                                                                 i2c_config =
 777                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 778                                                                         &i2c_record->sucI2cId;
 779                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 780                                                                                                  i2c_config->
 781                                                                                                  ucAccess);
 782                                                                 break;
 783                                                         case ATOM_HPD_INT_RECORD_TYPE:
 784                                                                 hpd_record =
 785                                                                         (ATOM_HPD_INT_RECORD *)
 786                                                                         record;
 787                                                                 gpio = radeon_atombios_lookup_gpio(rdev,
 788                                                                                           hpd_record->ucHPDIntGPIOID);
 789                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 790                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 791                                                                 break;
 792                                                         }
 793                                                         record =
 794                                                             (ATOM_COMMON_RECORD_HEADER
 795                                                              *) ((char *)record
 796                                                                  +
 797                                                                  record->
 798                                                                  ucRecordSize);
 799                                                 }
 800                                                 break;
 801                                         }
 802                                 }
 803                         }
 804
 805                         /* needed for aux chan transactions */
 806                         ddc_bus.hpd = hpd.hpd;
 807
 808                         conn_id = le16_to_cpu(path->usConnObjectId);
 809
 810                         if (!radeon_atom_apply_quirks
 811                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 812                              &ddc_bus, &conn_id, &hpd))
 813                                 continue;
 814
 815                         radeon_add_atom_connector(dev,
 816                                                   conn_id,
 817                                                   le16_to_cpu(path->
 818                                                               usDeviceTag),
 819                                                   connector_type, &ddc_bus,
 820                                                   igp_lane_info,
 821                                                   connector_object_id,
 822                                                   &hpd,
 823                                                   &router);
 824
 825                 }
 826         }
 827
 828         radeon_link_encoder_connector(dev);
 829
 830         radeon_setup_mst_connector(dev);
 831         return true;
 832 }
 833
 834 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 835                                                  int connector_type,
 836                                                  uint16_t devices)
 837 {
 838         struct radeon_device *rdev = dev->dev_private;
 839
 840         if (rdev->flags & RADEON_IS_IGP) {
 841                 return supported_devices_connector_object_id_convert
 842                         [connector_type];
 843         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 844                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 845                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 846                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 847                 struct atom_context *ctx = mode_info->atom_context;
 848                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 849                 uint16_t size, data_offset;
 850                 uint8_t frev, crev;
 851                 ATOM_XTMDS_INFO *xtmds;
 852
 853                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 854                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 855
 856                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 857                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 858                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 859                                 else
 860                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 861                         } else {
 862                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 863                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 864                                 else
 865                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 866                         }
 867                 } else
 868                         return supported_devices_connector_object_id_convert
 869                                 [connector_type];
 870         } else {
 871                 return supported_devices_connector_object_id_convert
 872                         [connector_type];
 873         }
 874 }
 875
 876 struct bios_connector {
 877         bool valid;
 878         uint16_t line_mux;
 879         uint16_t devices;
 880         int connector_type;
 881         struct radeon_i2c_bus_rec ddc_bus;
 882         struct radeon_hpd hpd;
 883 };
 884
 885 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 886                                                                  drm_device
 887                                                                  *dev)
 888 {
 889         struct radeon_device *rdev = dev->dev_private;
 890         struct radeon_mode_info *mode_info = &rdev->mode_info;
 891         struct atom_context *ctx = mode_info->atom_context;
 892         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 893         uint16_t size, data_offset;
 894         uint8_t frev, crev;
 895         uint16_t device_support;
 896         uint8_t dac;
 897         union atom_supported_devices *supported_devices;
 898         int i, j, max_device;
 899         struct bios_connector *bios_connectors;
 900         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 901         struct radeon_router router;
 902
 903         router.ddc_valid = false;
 904         router.cd_valid = false;
 905
 906         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 907         if (!bios_connectors)
 908                 return false;
 909
 910         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 911                                     &data_offset)) {
 912                 kfree(bios_connectors);
 913                 return false;
 914         }
 915
 916         supported_devices =
 917             (union atom_supported_devices *)(ctx->bios + data_offset);
 918
 919         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 920
 921         if (frev > 1)
 922                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 923         else
 924                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 925
 926         for (i = 0; i < max_device; i++) {
 927                 ATOM_CONNECTOR_INFO_I2C ci =
 928                     supported_devices->info.asConnInfo[i];
 929
 930                 bios_connectors[i].valid = false;
 931
 932                 if (!(device_support & (1 << i))) {
 933                         continue;
 934                 }
 935
 936                 if (i == ATOM_DEVICE_CV_INDEX) {
 937                         DRM_DEBUG_KMS("Skipping Component Video\n");
 938                         continue;
 939                 }
 940
 941                 bios_connectors[i].connector_type =
 942                     supported_devices_connector_convert[ci.sucConnectorInfo.
 943                                                         sbfAccess.
 944                                                         bfConnectorType];
 945
 946                 if (bios_connectors[i].connector_type ==
 947                     DRM_MODE_CONNECTOR_Unknown)
 948                         continue;
 949
 950                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 951
 952                 bios_connectors[i].line_mux =
 953                         ci.sucI2cId.ucAccess;
 954
 955                 /* give tv unique connector ids */
 956                 if (i == ATOM_DEVICE_TV1_INDEX) {
 957                         bios_connectors[i].ddc_bus.valid = false;
 958                         bios_connectors[i].line_mux = 50;
 959                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 960                         bios_connectors[i].ddc_bus.valid = false;
 961                         bios_connectors[i].line_mux = 51;
 962                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 963                         bios_connectors[i].ddc_bus.valid = false;
 964                         bios_connectors[i].line_mux = 52;
 965                 } else
 966                         bios_connectors[i].ddc_bus =
 967                             radeon_lookup_i2c_gpio(rdev,
 968                                                    bios_connectors[i].line_mux);
 969
 970                 if ((crev > 1) && (frev > 1)) {
 971                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 972                         switch (isb) {
 973                         case 0x4:
 974                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 975                                 break;
 976                         case 0xa:
 977                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 978                                 break;
 979                         default:
 980                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 981                                 break;
 982                         }
 983                 } else {
 984                         if (i == ATOM_DEVICE_DFP1_INDEX)
 985                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 986                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 987                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 988                         else
 989                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 990                 }
 991
 992                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 993                  * shared with a DVI port, we'll pick up the DVI connector when we
 994                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 995                  */
 996                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 997                         bios_connectors[i].connector_type =
 998                             DRM_MODE_CONNECTOR_VGA;
 999
1000                 if (!radeon_atom_apply_quirks
1001                     (dev, (1 << i), &bios_connectors[i].connector_type,
1002                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1003                      &bios_connectors[i].hpd))
1004                         continue;
1005
1006                 bios_connectors[i].valid = true;
1007                 bios_connectors[i].devices = (1 << i);
1008
1009                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1010                         radeon_add_atom_encoder(dev,
1011                                                 radeon_get_encoder_enum(dev,
1012                                                                       (1 << i),
1013                                                                       dac),
1014                                                 (1 << i),
1015                                                 0);
1016                 else
1017                         radeon_add_legacy_encoder(dev,
1018                                                   radeon_get_encoder_enum(dev,
1019                                                                         (1 << i),
1020                                                                         dac),
1021                                                   (1 << i));
1022         }
1023
1024         /* combine shared connectors */
1025         for (i = 0; i < max_device; i++) {
1026                 if (bios_connectors[i].valid) {
1027                         for (j = 0; j < max_device; j++) {
1028                                 if (bios_connectors[j].valid && (i != j)) {
1029                                         if (bios_connectors[i].line_mux ==
1030                                             bios_connectors[j].line_mux) {
1031                                                 /* make sure not to combine LVDS */
1032                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1033                                                         bios_connectors[i].line_mux = 53;
1034                                                         bios_connectors[i].ddc_bus.valid = false;
1035                                                         continue;
1036                                                 }
1037                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1038                                                         bios_connectors[j].line_mux = 53;
1039                                                         bios_connectors[j].ddc_bus.valid = false;
1040                                                         continue;
1041                                                 }
1042                                                 /* combine analog and digital for DVI-I */
1043                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1044                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1045                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1046                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1047                                                         bios_connectors[i].devices |=
1048                                                                 bios_connectors[j].devices;
1049                                                         bios_connectors[i].connector_type =
1050                                                                 DRM_MODE_CONNECTOR_DVII;
1051                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1052                                                                 bios_connectors[i].hpd =
1053                                                                         bios_connectors[j].hpd;
1054                                                         bios_connectors[j].valid = false;
1055                                                 }
1056                                         }
1057                                 }
1058                         }
1059                 }
1060         }
1061
1062         /* add the connectors */
1063         for (i = 0; i < max_device; i++) {
1064                 if (bios_connectors[i].valid) {
1065                         uint16_t connector_object_id =
1066                                 atombios_get_connector_object_id(dev,
1067                                                       bios_connectors[i].connector_type,
1068                                                       bios_connectors[i].devices);
1069                         radeon_add_atom_connector(dev,
1070                                                   bios_connectors[i].line_mux,
1071                                                   bios_connectors[i].devices,
1072                                                   bios_connectors[i].
1073                                                   connector_type,
1074                                                   &bios_connectors[i].ddc_bus,
1075                                                   0,
1076                                                   connector_object_id,
1077                                                   &bios_connectors[i].hpd,
1078                                                   &router);
1079                 }
1080         }
1081
1082         radeon_link_encoder_connector(dev);
1083
1084         kfree(bios_connectors);
1085         return true;
1086 }
1087
1088 union firmware_info {
1089         ATOM_FIRMWARE_INFO info;
1090         ATOM_FIRMWARE_INFO_V1_2 info_12;
1091         ATOM_FIRMWARE_INFO_V1_3 info_13;
1092         ATOM_FIRMWARE_INFO_V1_4 info_14;
1093         ATOM_FIRMWARE_INFO_V2_1 info_21;
1094         ATOM_FIRMWARE_INFO_V2_2 info_22;
1095 };
1096
1097 union igp_info {
1098         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1099         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1100         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1101         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1102         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1103 };
1104
1105 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1106 {
1107         struct radeon_mode_info *mode_info = &rdev->mode_info;
1108         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1109         union igp_info *igp_info;
1110         u8 frev, crev;
1111         u16 data_offset;
1112
1113         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1114                         &frev, &crev, &data_offset)) {
1115                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1116                         data_offset);
1117                 rdev->clock.vco_freq =
1118                         le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1119         }
1120 }
1121
1122 bool radeon_atom_get_clock_info(struct drm_device *dev)
1123 {
1124         struct radeon_device *rdev = dev->dev_private;
1125         struct radeon_mode_info *mode_info = &rdev->mode_info;
1126         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1127         union firmware_info *firmware_info;
1128         uint8_t frev, crev;
1129         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1130         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1131         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1132         struct radeon_pll *spll = &rdev->clock.spll;
1133         struct radeon_pll *mpll = &rdev->clock.mpll;
1134         uint16_t data_offset;
1135
1136         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1137                                    &frev, &crev, &data_offset)) {
1138                 firmware_info =
1139                         (union firmware_info *)(mode_info->atom_context->bios +
1140                                                 data_offset);
1141                 /* pixel clocks */
1142                 p1pll->reference_freq =
1143                     le16_to_cpu(firmware_info->info.usReferenceClock);
1144                 p1pll->reference_div = 0;
1145
1146                 if ((frev < 2) && (crev < 2))
1147                         p1pll->pll_out_min =
1148                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1149                 else
1150                         p1pll->pll_out_min =
1151                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1152                 p1pll->pll_out_max =
1153                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1154
1155                 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1156                         p1pll->lcd_pll_out_min =
1157                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1158                         if (p1pll->lcd_pll_out_min == 0)
1159                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1160                         p1pll->lcd_pll_out_max =
1161                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1162                         if (p1pll->lcd_pll_out_max == 0)
1163                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1164                 } else {
1165                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1166                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1167                 }
1168
1169                 if (p1pll->pll_out_min == 0) {
1170                         if (ASIC_IS_AVIVO(rdev))
1171                                 p1pll->pll_out_min = 64800;
1172                         else
1173                                 p1pll->pll_out_min = 20000;
1174                 }
1175
1176                 p1pll->pll_in_min =
1177                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1178                 p1pll->pll_in_max =
1179                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1180
1181                 *p2pll = *p1pll;
1182
1183                 /* system clock */
1184                 if (ASIC_IS_DCE4(rdev))
1185                         spll->reference_freq =
1186                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1187                 else
1188                         spll->reference_freq =
1189                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1190                 spll->reference_div = 0;
1191
1192                 spll->pll_out_min =
1193                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1194                 spll->pll_out_max =
1195                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1196
1197                 /* ??? */
1198                 if (spll->pll_out_min == 0) {
1199                         if (ASIC_IS_AVIVO(rdev))
1200                                 spll->pll_out_min = 64800;
1201                         else
1202                                 spll->pll_out_min = 20000;
1203                 }
1204
1205                 spll->pll_in_min =
1206                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1207                 spll->pll_in_max =
1208                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1209
1210                 /* memory clock */
1211                 if (ASIC_IS_DCE4(rdev))
1212                         mpll->reference_freq =
1213                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1214                 else
1215                         mpll->reference_freq =
1216                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1217                 mpll->reference_div = 0;
1218
1219                 mpll->pll_out_min =
1220                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1221                 mpll->pll_out_max =
1222                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1223
1224                 /* ??? */
1225                 if (mpll->pll_out_min == 0) {
1226                         if (ASIC_IS_AVIVO(rdev))
1227                                 mpll->pll_out_min = 64800;
1228                         else
1229                                 mpll->pll_out_min = 20000;
1230                 }
1231
1232                 mpll->pll_in_min =
1233                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1234                 mpll->pll_in_max =
1235                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1236
1237                 rdev->clock.default_sclk =
1238                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1239                 rdev->clock.default_mclk =
1240                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1241
1242                 if (ASIC_IS_DCE4(rdev)) {
1243                         rdev->clock.default_dispclk =
1244                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1245                         if (rdev->clock.default_dispclk == 0) {
1246                                 if (ASIC_IS_DCE6(rdev))
1247                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1248                                 else if (ASIC_IS_DCE5(rdev))
1249                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1250                                 else
1251                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1252                         }
1253                         /* set a reasonable default for DP */
1254                         if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1255                                 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1256                                          rdev->clock.default_dispclk / 100);
1257                                 rdev->clock.default_dispclk = 60000;
1258                         }
1259                         rdev->clock.dp_extclk =
1260                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1261                         rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1262                 }
1263                 *dcpll = *p1pll;
1264
1265                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1266                 if (rdev->clock.max_pixel_clock == 0)
1267                         rdev->clock.max_pixel_clock = 40000;
1268
1269                 /* not technically a clock, but... */
1270                 rdev->mode_info.firmware_flags =
1271                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1272
1273                 if (ASIC_IS_DCE8(rdev))
1274                         rdev->clock.vco_freq =
1275                                 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1276                 else if (ASIC_IS_DCE5(rdev))
1277                         rdev->clock.vco_freq = rdev->clock.current_dispclk;
1278                 else if (ASIC_IS_DCE41(rdev))
1279                         radeon_atombios_get_dentist_vco_freq(rdev);
1280                 else
1281                         rdev->clock.vco_freq = rdev->clock.current_dispclk;
1282
1283                 if (rdev->clock.vco_freq == 0)
1284                         rdev->clock.vco_freq = 360000;  /* 3.6 GHz */
1285
1286                 return true;
1287         }
1288
1289         return false;
1290 }
1291
1292 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1293 {
1294         struct radeon_mode_info *mode_info = &rdev->mode_info;
1295         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1296         union igp_info *igp_info;
1297         u8 frev, crev;
1298         u16 data_offset;
1299
1300         /* sideport is AMD only */
1301         if (rdev->family == CHIP_RS600)
1302                 return false;
1303
1304         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1305                                    &frev, &crev, &data_offset)) {
1306                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1307                                       data_offset);
1308                 switch (crev) {
1309                 case 1:
1310                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1311                                 return true;
1312                         break;
1313                 case 2:
1314                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1315                                 return true;
1316                         break;
1317                 default:
1318                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1319                         break;
1320                 }
1321         }
1322         return false;
1323 }
1324
1325 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1326                                    struct radeon_encoder_int_tmds *tmds)
1327 {
1328         struct drm_device *dev = encoder->base.dev;
1329         struct radeon_device *rdev = dev->dev_private;
1330         struct radeon_mode_info *mode_info = &rdev->mode_info;
1331         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1332         uint16_t data_offset;
1333         struct _ATOM_TMDS_INFO *tmds_info;
1334         uint8_t frev, crev;
1335         uint16_t maxfreq;
1336         int i;
1337
1338         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1339                                    &frev, &crev, &data_offset)) {
1340                 tmds_info =
1341                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1342                                                    data_offset);
1343
1344                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1345                 for (i = 0; i < 4; i++) {
1346                         tmds->tmds_pll[i].freq =
1347                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1348                         tmds->tmds_pll[i].value =
1349                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1350                         tmds->tmds_pll[i].value |=
1351                             (tmds_info->asMiscInfo[i].
1352                              ucPLL_VCO_Gain & 0x3f) << 6;
1353                         tmds->tmds_pll[i].value |=
1354                             (tmds_info->asMiscInfo[i].
1355                              ucPLL_DutyCycle & 0xf) << 12;
1356                         tmds->tmds_pll[i].value |=
1357                             (tmds_info->asMiscInfo[i].
1358                              ucPLL_VoltageSwing & 0xf) << 16;
1359
1360                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1361                                   tmds->tmds_pll[i].freq,
1362                                   tmds->tmds_pll[i].value);
1363
1364                         if (maxfreq == tmds->tmds_pll[i].freq) {
1365                                 tmds->tmds_pll[i].freq = 0xffffffff;
1366                                 break;
1367                         }
1368                 }
1369                 return true;
1370         }
1371         return false;
1372 }
1373
1374 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1375                                       struct radeon_atom_ss *ss,
1376                                       int id)
1377 {
1378         struct radeon_mode_info *mode_info = &rdev->mode_info;
1379         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1380         uint16_t data_offset, size;
1381         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1382         struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1383         uint8_t frev, crev;
1384         int i, num_indices;
1385
1386         memset(ss, 0, sizeof(struct radeon_atom_ss));
1387         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1388                                    &frev, &crev, &data_offset)) {
1389                 ss_info =
1390                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1391
1392                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1393                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1394                 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1395                         ((u8 *)&ss_info->asSS_Info[0]);
1396                 for (i = 0; i < num_indices; i++) {
1397                         if (ss_assign->ucSS_Id == id) {
1398                                 ss->percentage =
1399                                         le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1400                                 ss->type = ss_assign->ucSpreadSpectrumType;
1401                                 ss->step = ss_assign->ucSS_Step;
1402                                 ss->delay = ss_assign->ucSS_Delay;
1403                                 ss->range = ss_assign->ucSS_Range;
1404                                 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1405                                 return true;
1406                         }
1407                         ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1408                                 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1409                 }
1410         }
1411         return false;
1412 }
1413
1414 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1415                                                  struct radeon_atom_ss *ss,
1416                                                  int id)
1417 {
1418         struct radeon_mode_info *mode_info = &rdev->mode_info;
1419         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1420         u16 data_offset, size;
1421         union igp_info *igp_info;
1422         u8 frev, crev;
1423         u16 percentage = 0, rate = 0;
1424
1425         /* get any igp specific overrides */
1426         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1427                                    &frev, &crev, &data_offset)) {
1428                 igp_info = (union igp_info *)
1429                         (mode_info->atom_context->bios + data_offset);
1430                 switch (crev) {
1431                 case 6:
1432                         switch (id) {
1433                         case ASIC_INTERNAL_SS_ON_TMDS:
1434                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1435                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1436                                 break;
1437                         case ASIC_INTERNAL_SS_ON_HDMI:
1438                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1439                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1440                                 break;
1441                         case ASIC_INTERNAL_SS_ON_LVDS:
1442                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1443                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1444                                 break;
1445                         }
1446                         break;
1447                 case 7:
1448                         switch (id) {
1449                         case ASIC_INTERNAL_SS_ON_TMDS:
1450                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1451                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1452                                 break;
1453                         case ASIC_INTERNAL_SS_ON_HDMI:
1454                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1455                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1456                                 break;
1457                         case ASIC_INTERNAL_SS_ON_LVDS:
1458                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1459                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1460                                 break;
1461                         }
1462                         break;
1463                 case 8:
1464                         switch (id) {
1465                         case ASIC_INTERNAL_SS_ON_TMDS:
1466                                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1467                                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1468                                 break;
1469                         case ASIC_INTERNAL_SS_ON_HDMI:
1470                                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1471                                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1472                                 break;
1473                         case ASIC_INTERNAL_SS_ON_LVDS:
1474                                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1475                                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1476                                 break;
1477                         }
1478                         break;
1479                 default:
1480                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1481                         break;
1482                 }
1483                 if (percentage)
1484                         ss->percentage = percentage;
1485                 if (rate)
1486                         ss->rate = rate;
1487         }
1488 }
1489
1490 union asic_ss_info {
1491         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1492         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1493         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1494 };
1495
1496 union asic_ss_assignment {
1497         struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1498         struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1499         struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1500 };
1501
1502 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1503                                       struct radeon_atom_ss *ss,
1504                                       int id, u32 clock)
1505 {
1506         struct radeon_mode_info *mode_info = &rdev->mode_info;
1507         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1508         uint16_t data_offset, size;
1509         union asic_ss_info *ss_info;
1510         union asic_ss_assignment *ss_assign;
1511         uint8_t frev, crev;
1512         int i, num_indices;
1513
1514         if (id == ASIC_INTERNAL_MEMORY_SS) {
1515                 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1516                         return false;
1517         }
1518         if (id == ASIC_INTERNAL_ENGINE_SS) {
1519                 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1520                         return false;
1521         }
1522
1523         memset(ss, 0, sizeof(struct radeon_atom_ss));
1524         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1525                                    &frev, &crev, &data_offset)) {
1526
1527                 ss_info =
1528                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1529
1530                 switch (frev) {
1531                 case 1:
1532                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1533                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1534
1535                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1536                         for (i = 0; i < num_indices; i++) {
1537                                 if ((ss_assign->v1.ucClockIndication == id) &&
1538                                     (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1539                                         ss->percentage =
1540                                                 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1541                                         ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1542                                         ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1543                                         ss->percentage_divider = 100;
1544                                         return true;
1545                                 }
1546                                 ss_assign = (union asic_ss_assignment *)
1547                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1548                         }
1549                         break;
1550                 case 2:
1551                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1552                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1553                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1554                         for (i = 0; i < num_indices; i++) {
1555                                 if ((ss_assign->v2.ucClockIndication == id) &&
1556                                     (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1557                                         ss->percentage =
1558                                                 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1559                                         ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1560                                         ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1561                                         ss->percentage_divider = 100;
1562                                         if ((crev == 2) &&
1563                                             ((id == ASIC_INTERNAL_ENGINE_SS) ||
1564                                              (id == ASIC_INTERNAL_MEMORY_SS)))
1565                                                 ss->rate /= 100;
1566                                         return true;
1567                                 }
1568                                 ss_assign = (union asic_ss_assignment *)
1569                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1570                         }
1571                         break;
1572                 case 3:
1573                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1574                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1575                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1576                         for (i = 0; i < num_indices; i++) {
1577                                 if ((ss_assign->v3.ucClockIndication == id) &&
1578                                     (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1579                                         ss->percentage =
1580                                                 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1581                                         ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1582                                         ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1583                                         if (ss_assign->v3.ucSpreadSpectrumMode &
1584                                             SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1585                                                 ss->percentage_divider = 1000;
1586                                         else
1587                                                 ss->percentage_divider = 100;
1588                                         if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1589                                             (id == ASIC_INTERNAL_MEMORY_SS))
1590                                                 ss->rate /= 100;
1591                                         if (rdev->flags & RADEON_IS_IGP)
1592                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1593                                         return true;
1594                                 }
1595                                 ss_assign = (union asic_ss_assignment *)
1596                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1597                         }
1598                         break;
1599                 default:
1600                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1601                         break;
1602                 }
1603
1604         }
1605         return false;
1606 }
1607
1608 union lvds_info {
1609         struct _ATOM_LVDS_INFO info;
1610         struct _ATOM_LVDS_INFO_V12 info_12;
1611 };
1612
1613 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1614                                                               radeon_encoder
1615                                                               *encoder)
1616 {
1617         struct drm_device *dev = encoder->base.dev;
1618         struct radeon_device *rdev = dev->dev_private;
1619         struct radeon_mode_info *mode_info = &rdev->mode_info;
1620         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1621         uint16_t data_offset, misc;
1622         union lvds_info *lvds_info;
1623         uint8_t frev, crev;
1624         struct radeon_encoder_atom_dig *lvds = NULL;
1625         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1626
1627         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1628                                    &frev, &crev, &data_offset)) {
1629                 lvds_info =
1630                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1631                 lvds =
1632                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1633
1634                 if (!lvds)
1635                         return NULL;
1636
1637                 lvds->native_mode.clock =
1638                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1639                 lvds->native_mode.hdisplay =
1640                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1641                 lvds->native_mode.vdisplay =
1642                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1643                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1644                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1645                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1646                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1647                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1648                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1649                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1650                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1651                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1652                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1653                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1654                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1655                 lvds->panel_pwr_delay =
1656                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1657                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1658
1659                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1660                 if (misc & ATOM_VSYNC_POLARITY)
1661                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1662                 if (misc & ATOM_HSYNC_POLARITY)
1663                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1664                 if (misc & ATOM_COMPOSITESYNC)
1665                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1666                 if (misc & ATOM_INTERLACE)
1667                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1668                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1669                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1670
1671                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1672                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1673
1674                 /* set crtc values */
1675                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1676
1677                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1678
1679                 encoder->native_mode = lvds->native_mode;
1680
1681                 if (encoder_enum == 2)
1682                         lvds->linkb = true;
1683                 else
1684                         lvds->linkb = false;
1685
1686                 /* parse the lcd record table */
1687                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1688                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1689                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1690                         bool bad_record = false;
1691                         u8 *record;
1692
1693                         if ((frev == 1) && (crev < 2))
1694                                 /* absolute */
1695                                 record = (u8 *)(mode_info->atom_context->bios +
1696                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1697                         else
1698                                 /* relative */
1699                                 record = (u8 *)(mode_info->atom_context->bios +
1700                                                 data_offset +
1701                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1702                         while (*record != ATOM_RECORD_END_TYPE) {
1703                                 switch (*record) {
1704                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1705                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1706                                         break;
1707                                 case LCD_RTS_RECORD_TYPE:
1708                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1709                                         break;
1710                                 case LCD_CAP_RECORD_TYPE:
1711                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1712                                         break;
1713                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1714                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1715                                         if (fake_edid_record->ucFakeEDIDLength) {
1716                                                 struct edid *edid;
1717                                                 int edid_size =
1718                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1719                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1720                                                 if (edid) {
1721                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1722                                                                fake_edid_record->ucFakeEDIDLength);
1723
1724                                                         if (drm_edid_is_valid(edid)) {
1725                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1726                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1727                                                         } else
1728                                                                 kfree(edid);
1729                                                 }
1730                                         }
1731                                         record += fake_edid_record->ucFakeEDIDLength ?
1732                                                 fake_edid_record->ucFakeEDIDLength + 2 :
1733                                                 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1734                                         break;
1735                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1736                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1737                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1738                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1739                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1740                                         break;
1741                                 default:
1742                                         DRM_ERROR("Bad LCD record %d\n", *record);
1743                                         bad_record = true;
1744                                         break;
1745                                 }
1746                                 if (bad_record)
1747                                         break;
1748                         }
1749                 }
1750         }
1751         return lvds;
1752 }
1753
1754 struct radeon_encoder_primary_dac *
1755 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1756 {
1757         struct drm_device *dev = encoder->base.dev;
1758         struct radeon_device *rdev = dev->dev_private;
1759         struct radeon_mode_info *mode_info = &rdev->mode_info;
1760         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1761         uint16_t data_offset;
1762         struct _COMPASSIONATE_DATA *dac_info;
1763         uint8_t frev, crev;
1764         uint8_t bg, dac;
1765         struct radeon_encoder_primary_dac *p_dac = NULL;
1766
1767         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1768                                    &frev, &crev, &data_offset)) {
1769                 dac_info = (struct _COMPASSIONATE_DATA *)
1770                         (mode_info->atom_context->bios + data_offset);
1771
1772                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1773
1774                 if (!p_dac)
1775                         return NULL;
1776
1777                 bg = dac_info->ucDAC1_BG_Adjustment;
1778                 dac = dac_info->ucDAC1_DAC_Adjustment;
1779                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1780
1781         }
1782         return p_dac;
1783 }
1784
1785 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1786                                 struct drm_display_mode *mode)
1787 {
1788         struct radeon_mode_info *mode_info = &rdev->mode_info;
1789         ATOM_ANALOG_TV_INFO *tv_info;
1790         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1791         ATOM_DTD_FORMAT *dtd_timings;
1792         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1793         u8 frev, crev;
1794         u16 data_offset, misc;
1795
1796         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1797                                     &frev, &crev, &data_offset))
1798                 return false;
1799
1800         switch (crev) {
1801         case 1:
1802                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1803                 if (index >= MAX_SUPPORTED_TV_TIMING)
1804                         return false;
1805
1806                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1807                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1808                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1809                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1810                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1811
1812                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1813                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1814                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1815                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1816                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1817
1818                 mode->flags = 0;
1819                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1820                 if (misc & ATOM_VSYNC_POLARITY)
1821                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1822                 if (misc & ATOM_HSYNC_POLARITY)
1823                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1824                 if (misc & ATOM_COMPOSITESYNC)
1825                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1826                 if (misc & ATOM_INTERLACE)
1827                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1828                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1829                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1830
1831                 mode->crtc_clock = mode->clock =
1832                         le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1833
1834                 if (index == 1) {
1835                         /* PAL timings appear to have wrong values for totals */
1836                         mode->crtc_htotal -= 1;
1837                         mode->crtc_vtotal -= 1;
1838                 }
1839                 break;
1840         case 2:
1841                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1842                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1843                         return false;
1844
1845                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1846                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1847                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1848                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1849                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1850                         le16_to_cpu(dtd_timings->usHSyncOffset);
1851                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1852                         le16_to_cpu(dtd_timings->usHSyncWidth);
1853
1854                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1855                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1856                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1857                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1858                         le16_to_cpu(dtd_timings->usVSyncOffset);
1859                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1860                         le16_to_cpu(dtd_timings->usVSyncWidth);
1861
1862                 mode->flags = 0;
1863                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1864                 if (misc & ATOM_VSYNC_POLARITY)
1865                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1866                 if (misc & ATOM_HSYNC_POLARITY)
1867                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1868                 if (misc & ATOM_COMPOSITESYNC)
1869                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1870                 if (misc & ATOM_INTERLACE)
1871                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1872                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1873                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1874
1875                 mode->crtc_clock = mode->clock =
1876                         le16_to_cpu(dtd_timings->usPixClk) * 10;
1877                 break;
1878         }
1879         return true;
1880 }
1881
1882 enum radeon_tv_std
1883 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1884 {
1885         struct radeon_mode_info *mode_info = &rdev->mode_info;
1886         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1887         uint16_t data_offset;
1888         uint8_t frev, crev;
1889         struct _ATOM_ANALOG_TV_INFO *tv_info;
1890         enum radeon_tv_std tv_std = TV_STD_NTSC;
1891
1892         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1893                                    &frev, &crev, &data_offset)) {
1894
1895                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1896                         (mode_info->atom_context->bios + data_offset);
1897
1898                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1899                 case ATOM_TV_NTSC:
1900                         tv_std = TV_STD_NTSC;
1901                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1902                         break;
1903                 case ATOM_TV_NTSCJ:
1904                         tv_std = TV_STD_NTSC_J;
1905                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1906                         break;
1907                 case ATOM_TV_PAL:
1908                         tv_std = TV_STD_PAL;
1909                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1910                         break;
1911                 case ATOM_TV_PALM:
1912                         tv_std = TV_STD_PAL_M;
1913                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1914                         break;
1915                 case ATOM_TV_PALN:
1916                         tv_std = TV_STD_PAL_N;
1917                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1918                         break;
1919                 case ATOM_TV_PALCN:
1920                         tv_std = TV_STD_PAL_CN;
1921                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1922                         break;
1923                 case ATOM_TV_PAL60:
1924                         tv_std = TV_STD_PAL_60;
1925                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1926                         break;
1927                 case ATOM_TV_SECAM:
1928                         tv_std = TV_STD_SECAM;
1929                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1930                         break;
1931                 default:
1932                         tv_std = TV_STD_NTSC;
1933                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1934                         break;
1935                 }
1936         }
1937         return tv_std;
1938 }
1939
1940 struct radeon_encoder_tv_dac *
1941 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1942 {
1943         struct drm_device *dev = encoder->base.dev;
1944         struct radeon_device *rdev = dev->dev_private;
1945         struct radeon_mode_info *mode_info = &rdev->mode_info;
1946         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1947         uint16_t data_offset;
1948         struct _COMPASSIONATE_DATA *dac_info;
1949         uint8_t frev, crev;
1950         uint8_t bg, dac;
1951         struct radeon_encoder_tv_dac *tv_dac = NULL;
1952
1953         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1954                                    &frev, &crev, &data_offset)) {
1955
1956                 dac_info = (struct _COMPASSIONATE_DATA *)
1957                         (mode_info->atom_context->bios + data_offset);
1958
1959                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1960
1961                 if (!tv_dac)
1962                         return NULL;
1963
1964                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1965                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1966                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1967
1968                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1969                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1970                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1971
1972                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1973                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1974                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1975
1976                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1977         }
1978         return tv_dac;
1979 }
1980
1981 static const char *thermal_controller_names[] = {
1982         "NONE",
1983         "lm63",
1984         "adm1032",
1985         "adm1030",
1986         "max6649",
1987         "lm63", /* lm64 */
1988         "f75375",
1989         "asc7xxx",
1990 };
1991
1992 static const char *pp_lib_thermal_controller_names[] = {
1993         "NONE",
1994         "lm63",
1995         "adm1032",
1996         "adm1030",
1997         "max6649",
1998         "lm63", /* lm64 */
1999         "f75375",
2000         "RV6xx",
2001         "RV770",
2002         "adt7473",
2003         "NONE",
2004         "External GPIO",
2005         "Evergreen",
2006         "emc2103",
2007         "Sumo",
2008         "Northern Islands",
2009         "Southern Islands",
2010         "lm96163",
2011         "Sea Islands",
2012 };
2013
2014 union power_info {
2015         struct _ATOM_POWERPLAY_INFO info;
2016         struct _ATOM_POWERPLAY_INFO_V2 info_2;
2017         struct _ATOM_POWERPLAY_INFO_V3 info_3;
2018         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2019         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2020         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2021 };
2022
2023 union pplib_clock_info {
2024         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2025         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2026         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2027         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2028         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2029         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2030 };
2031
2032 union pplib_power_state {
2033         struct _ATOM_PPLIB_STATE v1;
2034         struct _ATOM_PPLIB_STATE_V2 v2;
2035 };
2036
2037 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2038                                                  int state_index,
2039                                                  u32 misc, u32 misc2)
2040 {
2041         rdev->pm.power_state[state_index].misc = misc;
2042         rdev->pm.power_state[state_index].misc2 = misc2;
2043         /* order matters! */
2044         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2045                 rdev->pm.power_state[state_index].type =
2046                         POWER_STATE_TYPE_POWERSAVE;
2047         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2048                 rdev->pm.power_state[state_index].type =
2049                         POWER_STATE_TYPE_BATTERY;
2050         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2051                 rdev->pm.power_state[state_index].type =
2052                         POWER_STATE_TYPE_BATTERY;
2053         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2054                 rdev->pm.power_state[state_index].type =
2055                         POWER_STATE_TYPE_BALANCED;
2056         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2057                 rdev->pm.power_state[state_index].type =
2058                         POWER_STATE_TYPE_PERFORMANCE;
2059                 rdev->pm.power_state[state_index].flags &=
2060                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2061         }
2062         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2063                 rdev->pm.power_state[state_index].type =
2064                         POWER_STATE_TYPE_BALANCED;
2065         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2066                 rdev->pm.power_state[state_index].type =
2067                         POWER_STATE_TYPE_DEFAULT;
2068                 rdev->pm.default_power_state_index = state_index;
2069                 rdev->pm.power_state[state_index].default_clock_mode =
2070                         &rdev->pm.power_state[state_index].clock_info[0];
2071         } else if (state_index == 0) {
2072                 rdev->pm.power_state[state_index].clock_info[0].flags |=
2073                         RADEON_PM_MODE_NO_DISPLAY;
2074         }
2075 }
2076
2077 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2078 {
2079         struct radeon_mode_info *mode_info = &rdev->mode_info;
2080         u32 misc, misc2 = 0;
2081         int num_modes = 0, i;
2082         int state_index = 0;
2083         struct radeon_i2c_bus_rec i2c_bus;
2084         union power_info *power_info;
2085         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2086         u16 data_offset;
2087         u8 frev, crev;
2088
2089         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2090                                    &frev, &crev, &data_offset))
2091                 return state_index;
2092         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2093
2094         /* add the i2c bus for thermal/fan chip */
2095         if ((power_info->info.ucOverdriveThermalController > 0) &&
2096             (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2097                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2098                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
2099                          power_info->info.ucOverdriveControllerAddress >> 1);
2100                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2101                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2102                 if (rdev->pm.i2c_bus) {
2103                         struct i2c_board_info info = { };
2104                         const char *name = thermal_controller_names[power_info->info.
2105                                                                     ucOverdriveThermalController];
2106                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2107                         strlcpy(info.type, name, sizeof(info.type));
2108                         i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2109                 }
2110         }
2111         num_modes = power_info->info.ucNumOfPowerModeEntries;
2112         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2113                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2114         if (num_modes == 0)
2115                 return state_index;
2116         rdev->pm.power_state = kcalloc(num_modes,
2117                                        sizeof(struct radeon_power_state),
2118                                        GFP_KERNEL);
2119         if (!rdev->pm.power_state)
2120                 return state_index;
2121         /* last mode is usually default, array is low to high */
2122         for (i = 0; i < num_modes; i++) {
2123                 rdev->pm.power_state[state_index].clock_info =
2124                         kcalloc(1, sizeof(struct radeon_pm_clock_info),
2125                                 GFP_KERNEL);
2126                 if (!rdev->pm.power_state[state_index].clock_info)
2127                         return state_index;
2128                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2129                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2130                 switch (frev) {
2131                 case 1:
2132                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2133                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2134                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2135                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2136                         /* skip invalid modes */
2137                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2138                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2139                                 continue;
2140                         rdev->pm.power_state[state_index].pcie_lanes =
2141                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2142                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2143                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2144                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2145                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2146                                         VOLTAGE_GPIO;
2147                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2148                                         radeon_atombios_lookup_gpio(rdev,
2149                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2150                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2151                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2152                                                 true;
2153                                 else
2154                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2155                                                 false;
2156                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2157                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2158                                         VOLTAGE_VDDC;
2159                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2160                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2161                         }
2162                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2163                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2164                         state_index++;
2165                         break;
2166                 case 2:
2167                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2168                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2169                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2170                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2171                         /* skip invalid modes */
2172                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2173                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2174                                 continue;
2175                         rdev->pm.power_state[state_index].pcie_lanes =
2176                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2177                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2178                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2179                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2180                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2181                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2182                                         VOLTAGE_GPIO;
2183                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2184                                         radeon_atombios_lookup_gpio(rdev,
2185                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2186                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2187                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2188                                                 true;
2189                                 else
2190                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2191                                                 false;
2192                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2193                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2194                                         VOLTAGE_VDDC;
2195                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2196                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2197                         }
2198                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2199                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2200                         state_index++;
2201                         break;
2202                 case 3:
2203                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2204                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2205                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2206                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2207                         /* skip invalid modes */
2208                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2209                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2210                                 continue;
2211                         rdev->pm.power_state[state_index].pcie_lanes =
2212                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2213                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2214                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2215                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2216                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2217                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2218                                         VOLTAGE_GPIO;
2219                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2220                                         radeon_atombios_lookup_gpio(rdev,
2221                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2222                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2223                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2224                                                 true;
2225                                 else
2226                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2227                                                 false;
2228                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2229                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2230                                         VOLTAGE_VDDC;
2231                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2232                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2233                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2234                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2235                                                 true;
2236                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2237                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2238                                 }
2239                         }
2240                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2241                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2242                         state_index++;
2243                         break;
2244                 }
2245         }
2246         /* last mode is usually default */
2247         if (rdev->pm.default_power_state_index == -1) {
2248                 rdev->pm.power_state[state_index - 1].type =
2249                         POWER_STATE_TYPE_DEFAULT;
2250                 rdev->pm.default_power_state_index = state_index - 1;
2251                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2252                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2253                 rdev->pm.power_state[state_index].flags &=
2254                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2255                 rdev->pm.power_state[state_index].misc = 0;
2256                 rdev->pm.power_state[state_index].misc2 = 0;
2257         }
2258         return state_index;
2259 }
2260
2261 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2262                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2263 {
2264         struct radeon_i2c_bus_rec i2c_bus;
2265
2266         /* add the i2c bus for thermal/fan chip */
2267         if (controller->ucType > 0) {
2268                 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2269                         rdev->pm.no_fan = true;
2270                 rdev->pm.fan_pulses_per_revolution =
2271                         controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2272                 if (rdev->pm.fan_pulses_per_revolution) {
2273                         rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2274                         rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2275                 }
2276                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2277                         DRM_INFO("Internal thermal controller %s fan control\n",
2278                                  (controller->ucFanParameters &
2279                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2280                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2281                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2282                         DRM_INFO("Internal thermal controller %s fan control\n",
2283                                  (controller->ucFanParameters &
2284                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2285                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2286                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2287                         DRM_INFO("Internal thermal controller %s fan control\n",
2288                                  (controller->ucFanParameters &
2289                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2290                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2291                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2292                         DRM_INFO("Internal thermal controller %s fan control\n",
2293                                  (controller->ucFanParameters &
2294                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2295                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2296                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2297                         DRM_INFO("Internal thermal controller %s fan control\n",
2298                                  (controller->ucFanParameters &
2299                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2300                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2301                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2302                         DRM_INFO("Internal thermal controller %s fan control\n",
2303                                  (controller->ucFanParameters &
2304                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2305                         rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2306                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2307                         DRM_INFO("Internal thermal controller %s fan control\n",
2308                                  (controller->ucFanParameters &
2309                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2310                         rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2311                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2312                         DRM_INFO("Internal thermal controller %s fan control\n",
2313                                  (controller->ucFanParameters &
2314                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2315                         rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2316                 } else if (controller->ucType ==
2317                            ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2318                         DRM_INFO("External GPIO thermal controller %s fan control\n",
2319                                  (controller->ucFanParameters &
2320                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2321                         rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2322                 } else if (controller->ucType ==
2323                            ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2324                         DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2325                                  (controller->ucFanParameters &
2326                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2327                         rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2328                 } else if (controller->ucType ==
2329                            ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2330                         DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2331                                  (controller->ucFanParameters &
2332                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2333                         rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2334                 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2335                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2336                                  pp_lib_thermal_controller_names[controller->ucType],
2337                                  controller->ucI2cAddress >> 1,
2338                                  (controller->ucFanParameters &
2339                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2340                         rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2341                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2342                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2343                         if (rdev->pm.i2c_bus) {
2344                                 struct i2c_board_info info = { };
2345                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2346                                 info.addr = controller->ucI2cAddress >> 1;
2347                                 strlcpy(info.type, name, sizeof(info.type));
2348                                 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2349                         }
2350                 } else {
2351                         DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2352                                  controller->ucType,
2353                                  controller->ucI2cAddress >> 1,
2354                                  (controller->ucFanParameters &
2355                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2356                 }
2357         }
2358 }
2359
2360 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2361                                           u16 *vddc, u16 *vddci, u16 *mvdd)
2362 {
2363         struct radeon_mode_info *mode_info = &rdev->mode_info;
2364         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2365         u8 frev, crev;
2366         u16 data_offset;
2367         union firmware_info *firmware_info;
2368
2369         *vddc = 0;
2370         *vddci = 0;
2371         *mvdd = 0;
2372
2373         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2374                                    &frev, &crev, &data_offset)) {
2375                 firmware_info =
2376                         (union firmware_info *)(mode_info->atom_context->bios +
2377                                                 data_offset);
2378                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2379                 if ((frev == 2) && (crev >= 2)) {
2380                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2381                         *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2382                 }
2383         }
2384 }
2385
2386 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2387                                                        int state_index, int mode_index,
2388                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2389 {
2390         int j;
2391         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2392         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2393         u16 vddc, vddci, mvdd;
2394
2395         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2396
2397         rdev->pm.power_state[state_index].misc = misc;
2398         rdev->pm.power_state[state_index].misc2 = misc2;
2399         rdev->pm.power_state[state_index].pcie_lanes =
2400                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2401                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2402         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2403         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2404                 rdev->pm.power_state[state_index].type =
2405                         POWER_STATE_TYPE_BATTERY;
2406                 break;
2407         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2408                 rdev->pm.power_state[state_index].type =
2409                         POWER_STATE_TYPE_BALANCED;
2410                 break;
2411         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2412                 rdev->pm.power_state[state_index].type =
2413                         POWER_STATE_TYPE_PERFORMANCE;
2414                 break;
2415         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2416                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2417                         rdev->pm.power_state[state_index].type =
2418                                 POWER_STATE_TYPE_PERFORMANCE;
2419                 break;
2420         }
2421         rdev->pm.power_state[state_index].flags = 0;
2422         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2423                 rdev->pm.power_state[state_index].flags |=
2424                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2425         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2426                 rdev->pm.power_state[state_index].type =
2427                         POWER_STATE_TYPE_DEFAULT;
2428                 rdev->pm.default_power_state_index = state_index;
2429                 rdev->pm.power_state[state_index].default_clock_mode =
2430                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2431                 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2432                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2433                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2434                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2435                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2436                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2437                 } else {
2438                         u16 max_vddci = 0;
2439
2440                         if (ASIC_IS_DCE4(rdev))
2441                                 radeon_atom_get_max_voltage(rdev,
2442                                                             SET_VOLTAGE_TYPE_ASIC_VDDCI,
2443                                                             &max_vddci);
2444                         /* patch the table values with the default sclk/mclk from firmware info */
2445                         for (j = 0; j < mode_index; j++) {
2446                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2447                                         rdev->clock.default_mclk;
2448                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2449                                         rdev->clock.default_sclk;
2450                                 if (vddc)
2451                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2452                                                 vddc;
2453                                 if (max_vddci)
2454                                         rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2455                                                 max_vddci;
2456                         }
2457                 }
2458         }
2459 }
2460
2461 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2462                                                    int state_index, int mode_index,
2463                                                    union pplib_clock_info *clock_info)
2464 {
2465         u32 sclk, mclk;
2466         u16 vddc;
2467
2468         if (rdev->flags & RADEON_IS_IGP) {
2469                 if (rdev->family >= CHIP_PALM) {
2470                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2471                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2472                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2473                 } else {
2474                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2475                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2476                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2477                 }
2478         } else if (rdev->family >= CHIP_BONAIRE) {
2479                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2480                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2481                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2482                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2483                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2484                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2485                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2486                         VOLTAGE_NONE;
2487         } else if (rdev->family >= CHIP_TAHITI) {
2488                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2489                 sclk |= clock_info->si.ucEngineClockHigh << 16;
2490                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2491                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2492                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2493                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2494                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2495                         VOLTAGE_SW;
2496                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2497                         le16_to_cpu(clock_info->si.usVDDC);
2498                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2499                         le16_to_cpu(clock_info->si.usVDDCI);
2500         } else if (rdev->family >= CHIP_CEDAR) {
2501                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2502                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2503                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2504                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2505                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2506                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2507                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2508                         VOLTAGE_SW;
2509                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2510                         le16_to_cpu(clock_info->evergreen.usVDDC);
2511                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2512                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2513         } else {
2514                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2515                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2516                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2517                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2518                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2519                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2520                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2521                         VOLTAGE_SW;
2522                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2523                         le16_to_cpu(clock_info->r600.usVDDC);
2524         }
2525
2526         /* patch up vddc if necessary */
2527         switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2528         case ATOM_VIRTUAL_VOLTAGE_ID0:
2529         case ATOM_VIRTUAL_VOLTAGE_ID1:
2530         case ATOM_VIRTUAL_VOLTAGE_ID2:
2531         case ATOM_VIRTUAL_VOLTAGE_ID3:
2532         case ATOM_VIRTUAL_VOLTAGE_ID4:
2533         case ATOM_VIRTUAL_VOLTAGE_ID5:
2534         case ATOM_VIRTUAL_VOLTAGE_ID6:
2535         case ATOM_VIRTUAL_VOLTAGE_ID7:
2536                 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2537                                              rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2538                                              &vddc) == 0)
2539                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2540                 break;
2541         default:
2542                 break;
2543         }
2544
2545         if (rdev->flags & RADEON_IS_IGP) {
2546                 /* skip invalid modes */
2547                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2548                         return false;
2549         } else {
2550                 /* skip invalid modes */
2551                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2552                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2553                         return false;
2554         }
2555         return true;
2556 }
2557
2558 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2559 {
2560         struct radeon_mode_info *mode_info = &rdev->mode_info;
2561         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2562         union pplib_power_state *power_state;
2563         int i, j;
2564         int state_index = 0, mode_index = 0;
2565         union pplib_clock_info *clock_info;
2566         bool valid;
2567         union power_info *power_info;
2568         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2569         u16 data_offset;
2570         u8 frev, crev;
2571
2572         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2573                                    &frev, &crev, &data_offset))
2574                 return state_index;
2575         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2576
2577         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2578         if (power_info->pplib.ucNumStates == 0)
2579                 return state_index;
2580         rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2581                                        sizeof(struct radeon_power_state),
2582                                        GFP_KERNEL);
2583         if (!rdev->pm.power_state)
2584                 return state_index;
2585         /* first mode is usually default, followed by low to high */
2586         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2587                 mode_index = 0;
2588                 power_state = (union pplib_power_state *)
2589                         (mode_info->atom_context->bios + data_offset +
2590                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2591                          i * power_info->pplib.ucStateEntrySize);
2592                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2593                         (mode_info->atom_context->bios + data_offset +
2594                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2595                          (power_state->v1.ucNonClockStateIndex *
2596                           power_info->pplib.ucNonClockSize));
2597                 rdev->pm.power_state[i].clock_info =
2598                         kcalloc((power_info->pplib.ucStateEntrySize - 1) ?
2599                                 (power_info->pplib.ucStateEntrySize - 1) : 1,
2600                                 sizeof(struct radeon_pm_clock_info),
2601                                 GFP_KERNEL);
2602                 if (!rdev->pm.power_state[i].clock_info)
2603                         return state_index;
2604                 if (power_info->pplib.ucStateEntrySize - 1) {
2605                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2606                                 clock_info = (union pplib_clock_info *)
2607                                         (mode_info->atom_context->bios + data_offset +
2608                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2609                                          (power_state->v1.ucClockStateIndices[j] *
2610                                           power_info->pplib.ucClockInfoSize));
2611                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2612                                                                                state_index, mode_index,
2613                                                                                clock_info);
2614                                 if (valid)
2615                                         mode_index++;
2616                         }
2617                 } else {
2618                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2619                                 rdev->clock.default_mclk;
2620                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2621                                 rdev->clock.default_sclk;
2622                         mode_index++;
2623                 }
2624                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2625                 if (mode_index) {
2626                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2627                                                                    non_clock_info);
2628                         state_index++;
2629                 }
2630         }
2631         /* if multiple clock modes, mark the lowest as no display */
2632         for (i = 0; i < state_index; i++) {
2633                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2634                         rdev->pm.power_state[i].clock_info[0].flags |=
2635                                 RADEON_PM_MODE_NO_DISPLAY;
2636         }
2637         /* first mode is usually default */
2638         if (rdev->pm.default_power_state_index == -1) {
2639                 rdev->pm.power_state[0].type =
2640                         POWER_STATE_TYPE_DEFAULT;
2641                 rdev->pm.default_power_state_index = 0;
2642                 rdev->pm.power_state[0].default_clock_mode =
2643                         &rdev->pm.power_state[0].clock_info[0];
2644         }
2645         return state_index;
2646 }
2647
2648 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2649 {
2650         struct radeon_mode_info *mode_info = &rdev->mode_info;
2651         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2652         union pplib_power_state *power_state;
2653         int i, j, non_clock_array_index, clock_array_index;
2654         int state_index = 0, mode_index = 0;
2655         union pplib_clock_info *clock_info;
2656         struct _StateArray *state_array;
2657         struct _ClockInfoArray *clock_info_array;
2658         struct _NonClockInfoArray *non_clock_info_array;
2659         bool valid;
2660         union power_info *power_info;
2661         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2662         u16 data_offset;
2663         u8 frev, crev;
2664         u8 *power_state_offset;
2665
2666         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2667                                    &frev, &crev, &data_offset))
2668                 return state_index;
2669         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2670
2671         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2672         state_array = (struct _StateArray *)
2673                 (mode_info->atom_context->bios + data_offset +
2674                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2675         clock_info_array = (struct _ClockInfoArray *)
2676                 (mode_info->atom_context->bios + data_offset +
2677                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2678         non_clock_info_array = (struct _NonClockInfoArray *)
2679                 (mode_info->atom_context->bios + data_offset +
2680                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2681         if (state_array->ucNumEntries == 0)
2682                 return state_index;
2683         rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2684                                        sizeof(struct radeon_power_state),
2685                                        GFP_KERNEL);
2686         if (!rdev->pm.power_state)
2687                 return state_index;
2688         power_state_offset = (u8 *)state_array->states;
2689         for (i = 0; i < state_array->ucNumEntries; i++) {
2690                 mode_index = 0;
2691                 power_state = (union pplib_power_state *)power_state_offset;
2692                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2693                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2694                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2695                 rdev->pm.power_state[i].clock_info =
2696                         kcalloc(power_state->v2.ucNumDPMLevels ?
2697                                 power_state->v2.ucNumDPMLevels : 1,
2698                                 sizeof(struct radeon_pm_clock_info),
2699                                 GFP_KERNEL);
2700                 if (!rdev->pm.power_state[i].clock_info)
2701                         return state_index;
2702                 if (power_state->v2.ucNumDPMLevels) {
2703                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2704                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2705                                 clock_info = (union pplib_clock_info *)
2706                                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2707                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2708                                                                                state_index, mode_index,
2709                                                                                clock_info);
2710                                 if (valid)
2711                                         mode_index++;
2712                         }
2713                 } else {
2714                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2715                                 rdev->clock.default_mclk;
2716                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2717                                 rdev->clock.default_sclk;
2718                         mode_index++;
2719                 }
2720                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2721                 if (mode_index) {
2722                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2723                                                                    non_clock_info);
2724                         state_index++;
2725                 }
2726                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2727         }
2728         /* if multiple clock modes, mark the lowest as no display */
2729         for (i = 0; i < state_index; i++) {
2730                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2731                         rdev->pm.power_state[i].clock_info[0].flags |=
2732                                 RADEON_PM_MODE_NO_DISPLAY;
2733         }
2734         /* first mode is usually default */
2735         if (rdev->pm.default_power_state_index == -1) {
2736                 rdev->pm.power_state[0].type =
2737                         POWER_STATE_TYPE_DEFAULT;
2738                 rdev->pm.default_power_state_index = 0;
2739                 rdev->pm.power_state[0].default_clock_mode =
2740                         &rdev->pm.power_state[0].clock_info[0];
2741         }
2742         return state_index;
2743 }
2744
2745 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2746 {
2747         struct radeon_mode_info *mode_info = &rdev->mode_info;
2748         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2749         u16 data_offset;
2750         u8 frev, crev;
2751         int state_index = 0;
2752
2753         rdev->pm.default_power_state_index = -1;
2754
2755         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2756                                    &frev, &crev, &data_offset)) {
2757                 switch (frev) {
2758                 case 1:
2759                 case 2:
2760                 case 3:
2761                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2762                         break;
2763                 case 4:
2764                 case 5:
2765                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2766                         break;
2767                 case 6:
2768                         state_index = radeon_atombios_parse_power_table_6(rdev);
2769                         break;
2770                 default:
2771                         break;
2772                 }
2773         }
2774
2775         if (state_index == 0) {
2776                 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2777                 if (rdev->pm.power_state) {
2778                         rdev->pm.power_state[0].clock_info =
2779                                 kcalloc(1,
2780                                         sizeof(struct radeon_pm_clock_info),
2781                                         GFP_KERNEL);
2782                         if (rdev->pm.power_state[0].clock_info) {
2783                                 /* add the default mode */
2784                                 rdev->pm.power_state[state_index].type =
2785                                         POWER_STATE_TYPE_DEFAULT;
2786                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2787                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2788                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2789                                 rdev->pm.power_state[state_index].default_clock_mode =
2790                                         &rdev->pm.power_state[state_index].clock_info[0];
2791                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2792                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2793                                 rdev->pm.default_power_state_index = state_index;
2794                                 rdev->pm.power_state[state_index].flags = 0;
2795                                 state_index++;
2796                         }
2797                 }
2798         }
2799
2800         rdev->pm.num_power_states = state_index;
2801
2802         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2803         rdev->pm.current_clock_mode_index = 0;
2804         if (rdev->pm.default_power_state_index >= 0)
2805                 rdev->pm.current_vddc =
2806                         rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2807         else
2808                 rdev->pm.current_vddc = 0;
2809 }
2810
2811 union get_clock_dividers {
2812         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2813         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2814         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2815         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2816         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2817         struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2818         struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2819 };
2820
2821 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2822                                    u8 clock_type,
2823                                    u32 clock,
2824                                    bool strobe_mode,
2825                                    struct atom_clock_dividers *dividers)
2826 {
2827         union get_clock_dividers args;
2828         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2829         u8 frev, crev;
2830
2831         memset(&args, 0, sizeof(args));
2832         memset(dividers, 0, sizeof(struct atom_clock_dividers));
2833
2834         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2835                 return -EINVAL;
2836
2837         switch (crev) {
2838         case 1:
2839                 /* r4xx, r5xx */
2840                 args.v1.ucAction = clock_type;
2841                 args.v1.ulClock = cpu_to_le32(clock);   /* 10 khz */
2842
2843                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2844
2845                 dividers->post_div = args.v1.ucPostDiv;
2846                 dividers->fb_div = args.v1.ucFbDiv;
2847                 dividers->enable_post_div = true;
2848                 break;
2849         case 2:
2850         case 3:
2851         case 5:
2852                 /* r6xx, r7xx, evergreen, ni, si */
2853                 if (rdev->family <= CHIP_RV770) {
2854                         args.v2.ucAction = clock_type;
2855                         args.v2.ulClock = cpu_to_le32(clock);   /* 10 khz */
2856
2857                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2858
2859                         dividers->post_div = args.v2.ucPostDiv;
2860                         dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2861                         dividers->ref_div = args.v2.ucAction;
2862                         if (rdev->family == CHIP_RV770) {
2863                                 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2864                                         true : false;
2865                                 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2866                         } else
2867                                 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2868                 } else {
2869                         if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2870                                 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2871
2872                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2873
2874                                 dividers->post_div = args.v3.ucPostDiv;
2875                                 dividers->enable_post_div = (args.v3.ucCntlFlag &
2876                                                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2877                                 dividers->enable_dithen = (args.v3.ucCntlFlag &
2878                                                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2879                                 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2880                                 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2881                                 dividers->ref_div = args.v3.ucRefDiv;
2882                                 dividers->vco_mode = (args.v3.ucCntlFlag &
2883                                                       ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2884                         } else {
2885                                 /* for SI we use ComputeMemoryClockParam for memory plls */
2886                                 if (rdev->family >= CHIP_TAHITI)
2887                                         return -EINVAL;
2888                                 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2889                                 if (strobe_mode)
2890                                         args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2891
2892                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2893
2894                                 dividers->post_div = args.v5.ucPostDiv;
2895                                 dividers->enable_post_div = (args.v5.ucCntlFlag &
2896                                                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2897                                 dividers->enable_dithen = (args.v5.ucCntlFlag &
2898                                                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2899                                 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2900                                 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2901                                 dividers->ref_div = args.v5.ucRefDiv;
2902                                 dividers->vco_mode = (args.v5.ucCntlFlag &
2903                                                       ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2904                         }
2905                 }
2906                 break;
2907         case 4:
2908                 /* fusion */
2909                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
2910
2911                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2912
2913                 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2914                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2915                 break;
2916         case 6:
2917                 /* CI */
2918                 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2919                 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2920                 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
2921
2922                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2923
2924                 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2925                 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2926                 dividers->ref_div = args.v6_out.ucPllRefDiv;
2927                 dividers->post_div = args.v6_out.ucPllPostDiv;
2928                 dividers->flags = args.v6_out.ucPllCntlFlag;
2929                 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2930                 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2931                 break;
2932         default:
2933                 return -EINVAL;
2934         }
2935         return 0;
2936 }
2937
2938 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2939                                         u32 clock,
2940                                         bool strobe_mode,
2941                                         struct atom_mpll_param *mpll_param)
2942 {
2943         COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2944         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2945         u8 frev, crev;
2946
2947         memset(&args, 0, sizeof(args));
2948         memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2949
2950         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2951                 return -EINVAL;
2952
2953         switch (frev) {
2954         case 2:
2955                 switch (crev) {
2956                 case 1:
2957                         /* SI */
2958                         args.ulClock = cpu_to_le32(clock);      /* 10 khz */
2959                         args.ucInputFlag = 0;
2960                         if (strobe_mode)
2961                                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2962
2963                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2964
2965                         mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2966                         mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2967                         mpll_param->post_div = args.ucPostDiv;
2968                         mpll_param->dll_speed = args.ucDllSpeed;
2969                         mpll_param->bwcntl = args.ucBWCntl;
2970                         mpll_param->vco_mode =
2971                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2972                         mpll_param->yclk_sel =
2973                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2974                         mpll_param->qdr =
2975                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2976                         mpll_param->half_rate =
2977                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2978                         break;
2979                 default:
2980                         return -EINVAL;
2981                 }
2982                 break;
2983         default:
2984                 return -EINVAL;
2985         }
2986         return 0;
2987 }
2988
2989 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2990 {
2991         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2992         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2993
2994         args.ucEnable = enable;
2995
2996         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2997 }
2998
2999 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3000 {
3001         GET_ENGINE_CLOCK_PS_ALLOCATION args;
3002         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3003
3004         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3005         return le32_to_cpu(args.ulReturnEngineClock);
3006 }
3007
3008 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3009 {
3010         GET_MEMORY_CLOCK_PS_ALLOCATION args;
3011         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3012
3013         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3014         return le32_to_cpu(args.ulReturnMemoryClock);
3015 }
3016
3017 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3018                                   uint32_t eng_clock)
3019 {
3020         SET_ENGINE_CLOCK_PS_ALLOCATION args;
3021         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3022
3023         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
3024
3025         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3026 }
3027
3028 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3029                                   uint32_t mem_clock)
3030 {
3031         SET_MEMORY_CLOCK_PS_ALLOCATION args;
3032         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3033
3034         if (rdev->flags & RADEON_IS_IGP)
3035                 return;
3036
3037         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
3038
3039         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3040 }
3041
3042 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3043                                          u32 eng_clock, u32 mem_clock)
3044 {
3045         SET_ENGINE_CLOCK_PS_ALLOCATION args;
3046         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3047         u32 tmp;
3048
3049         memset(&args, 0, sizeof(args));
3050
3051         tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3052         tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3053
3054         args.ulTargetEngineClock = cpu_to_le32(tmp);
3055         if (mem_clock)
3056                 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3057
3058         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3059 }
3060
3061 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3062                                    u32 mem_clock)
3063 {
3064         u32 args;
3065         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3066
3067         args = cpu_to_le32(mem_clock);  /* 10 khz */
3068
3069         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3070 }
3071
3072 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3073                                u32 mem_clock)
3074 {
3075         SET_MEMORY_CLOCK_PS_ALLOCATION args;
3076         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3077         u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3078
3079         args.ulTargetMemoryClock = cpu_to_le32(tmp);    /* 10 khz */
3080
3081         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3082 }
3083
3084 union set_voltage {
3085         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3086         struct _SET_VOLTAGE_PARAMETERS v1;
3087         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3088         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3089 };
3090
3091 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3092 {
3093         union set_voltage args;
3094         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3095         u8 frev, crev, volt_index = voltage_level;
3096
3097         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3098                 return;
3099
3100         /* 0xff01 is a flag rather then an actual voltage */
3101         if (voltage_level == 0xff01)
3102                 return;
3103
3104         switch (crev) {
3105         case 1:
3106                 args.v1.ucVoltageType = voltage_type;
3107                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3108                 args.v1.ucVoltageIndex = volt_index;
3109                 break;
3110         case 2:
3111                 args.v2.ucVoltageType = voltage_type;
3112                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3113                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3114                 break;
3115         case 3:
3116                 args.v3.ucVoltageType = voltage_type;
3117                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3118                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3119                 break;
3120         default:
3121                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3122                 return;
3123         }
3124
3125         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3126 }
3127
3128 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3129                              u16 voltage_id, u16 *voltage)
3130 {
3131         union set_voltage args;
3132         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3133         u8 frev, crev;
3134
3135         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3136                 return -EINVAL;
3137
3138         switch (crev) {
3139         case 1:
3140                 return -EINVAL;
3141         case 2:
3142                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3143                 args.v2.ucVoltageMode = 0;
3144                 args.v2.usVoltageLevel = 0;
3145
3146                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3147
3148                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3149                 break;
3150         case 3:
3151                 args.v3.ucVoltageType = voltage_type;
3152                 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3153                 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3154
3155                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3156
3157                 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3158                 break;
3159         default:
3160                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3161                 return -EINVAL;
3162         }
3163
3164         return 0;
3165 }
3166
3167 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3168                                                       u16 *voltage,
3169                                                       u16 leakage_idx)
3170 {
3171         return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3172 }
3173
3174 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3175                                           u16 *leakage_id)
3176 {
3177         union set_voltage args;
3178         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3179         u8 frev, crev;
3180
3181         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3182                 return -EINVAL;
3183
3184         switch (crev) {
3185         case 3:
3186         case 4:
3187                 args.v3.ucVoltageType = 0;
3188                 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3189                 args.v3.usVoltageLevel = 0;
3190
3191                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3192
3193                 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3194                 break;
3195         default:
3196                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3197                 return -EINVAL;
3198         }
3199
3200         return 0;
3201 }
3202
3203 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3204                                                          u16 *vddc, u16 *vddci,
3205                                                          u16 virtual_voltage_id,
3206                                                          u16 vbios_voltage_id)
3207 {
3208         int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3209         u8 frev, crev;
3210         u16 data_offset, size;
3211         int i, j;
3212         ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3213         u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3214
3215         *vddc = 0;
3216         *vddci = 0;
3217
3218         if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3219                                     &frev, &crev, &data_offset))
3220                 return -EINVAL;
3221
3222         profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3223                 (rdev->mode_info.atom_context->bios + data_offset);
3224
3225         switch (frev) {
3226         case 1:
3227                 return -EINVAL;
3228         case 2:
3229                 switch (crev) {
3230                 case 1:
3231                         if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3232                                 return -EINVAL;
3233                         leakage_bin = (u16 *)
3234                                 (rdev->mode_info.atom_context->bios + data_offset +
3235                                  le16_to_cpu(profile->usLeakageBinArrayOffset));
3236                         vddc_id_buf = (u16 *)
3237                                 (rdev->mode_info.atom_context->bios + data_offset +
3238                                  le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3239                         vddc_buf = (u16 *)
3240                                 (rdev->mode_info.atom_context->bios + data_offset +
3241                                  le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3242                         vddci_id_buf = (u16 *)
3243                                 (rdev->mode_info.atom_context->bios + data_offset +
3244                                  le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3245                         vddci_buf = (u16 *)
3246                                 (rdev->mode_info.atom_context->bios + data_offset +
3247                                  le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3248
3249                         if (profile->ucElbVDDC_Num > 0) {
3250                                 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3251                                         if (vddc_id_buf[i] == virtual_voltage_id) {
3252                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3253                                                         if (vbios_voltage_id <= leakage_bin[j]) {
3254                                                                 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3255                                                                 break;
3256                                                         }
3257                                                 }
3258                                                 break;
3259                                         }
3260                                 }
3261                         }
3262                         if (profile->ucElbVDDCI_Num > 0) {
3263                                 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3264                                         if (vddci_id_buf[i] == virtual_voltage_id) {
3265                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3266                                                         if (vbios_voltage_id <= leakage_bin[j]) {
3267                                                                 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3268                                                                 break;
3269                                                         }
3270                                                 }
3271                                                 break;
3272                                         }
3273                                 }
3274                         }
3275                         break;
3276                 default:
3277                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3278                         return -EINVAL;
3279                 }
3280                 break;
3281         default:
3282                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3283                 return -EINVAL;
3284         }
3285
3286         return 0;
3287 }
3288
3289 union get_voltage_info {
3290         struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3291         struct  _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3292 };
3293
3294 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3295                                 u16 virtual_voltage_id,
3296                                 u16 *voltage)
3297 {
3298         int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3299         u32 entry_id;
3300         u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3301         union get_voltage_info args;
3302
3303         for (entry_id = 0; entry_id < count; entry_id++) {
3304                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3305                     virtual_voltage_id)
3306                         break;
3307         }
3308
3309         if (entry_id >= count)
3310                 return -EINVAL;
3311
3312         args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3313         args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3314         args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3315         args.in.ulSCLKFreq =
3316                 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3317
3318         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3319
3320         *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3321
3322         return 0;
3323 }
3324
3325 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3326                                           u16 voltage_level, u8 voltage_type,
3327                                           u32 *gpio_value, u32 *gpio_mask)
3328 {
3329         union set_voltage args;
3330         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3331         u8 frev, crev;
3332
3333         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3334                 return -EINVAL;
3335
3336         switch (crev) {
3337         case 1:
3338                 return -EINVAL;
3339         case 2:
3340                 args.v2.ucVoltageType = voltage_type;
3341                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3342                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3343
3344                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3345
3346                 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3347
3348                 args.v2.ucVoltageType = voltage_type;
3349                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3350                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3351
3352                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3353
3354                 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3355                 break;
3356         default:
3357                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3358                 return -EINVAL;
3359         }
3360
3361         return 0;
3362 }
3363
3364 union voltage_object_info {
3365         struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3366         struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3367         struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3368 };
3369
3370 union voltage_object {
3371         struct _ATOM_VOLTAGE_OBJECT v1;
3372         struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3373         union _ATOM_VOLTAGE_OBJECT_V3 v3;
3374 };
3375
3376 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3377                                                           u8 voltage_type)
3378 {
3379         u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3380         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3381         u8 *start = (u8 *)v1;
3382
3383         while (offset < size) {
3384                 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3385                 if (vo->ucVoltageType == voltage_type)
3386                         return vo;
3387                 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3388                         vo->asFormula.ucNumOfVoltageEntries;
3389         }
3390         return NULL;
3391 }
3392
3393 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3394                                                              u8 voltage_type)
3395 {
3396         u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3397         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3398         u8 *start = (u8*)v2;
3399
3400         while (offset < size) {
3401                 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3402                 if (vo->ucVoltageType == voltage_type)
3403                         return vo;
3404                 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3405                         (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3406         }
3407         return NULL;
3408 }
3409
3410 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3411                                                              u8 voltage_type, u8 voltage_mode)
3412 {
3413         u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3414         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3415         u8 *start = (u8*)v3;
3416
3417         while (offset < size) {
3418                 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3419                 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3420                     (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3421                         return vo;
3422                 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3423         }
3424         return NULL;
3425 }
3426
3427 bool
3428 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3429                             u8 voltage_type, u8 voltage_mode)
3430 {
3431         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3432         u8 frev, crev;
3433         u16 data_offset, size;
3434         union voltage_object_info *voltage_info;
3435         union voltage_object *voltage_object = NULL;
3436
3437         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3438                                    &frev, &crev, &data_offset)) {
3439                 voltage_info = (union voltage_object_info *)
3440                         (rdev->mode_info.atom_context->bios + data_offset);
3441
3442                 switch (frev) {
3443                 case 1:
3444                 case 2:
3445                         switch (crev) {
3446                         case 1:
3447                                 voltage_object = (union voltage_object *)
3448                                         atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3449                                 if (voltage_object &&
3450                                     (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3451                                         return true;
3452                                 break;
3453                         case 2:
3454                                 voltage_object = (union voltage_object *)
3455                                         atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3456                                 if (voltage_object &&
3457                                     (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3458                                         return true;
3459                                 break;
3460                         default:
3461                                 DRM_ERROR("unknown voltage object table\n");
3462                                 return false;
3463                         }
3464                         break;
3465                 case 3:
3466                         switch (crev) {
3467                         case 1:
3468                                 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3469                                                                   voltage_type, voltage_mode))
3470                                         return true;
3471                                 break;
3472                         default:
3473                                 DRM_ERROR("unknown voltage object table\n");
3474                                 return false;
3475                         }
3476                         break;
3477                 default:
3478                         DRM_ERROR("unknown voltage object table\n");
3479                         return false;
3480                 }
3481
3482         }
3483         return false;
3484 }
3485
3486 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3487                               u8 voltage_type,
3488                               u8 *svd_gpio_id, u8 *svc_gpio_id)
3489 {
3490         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3491         u8 frev, crev;
3492         u16 data_offset, size;
3493         union voltage_object_info *voltage_info;
3494         union voltage_object *voltage_object = NULL;
3495
3496         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3497                                    &frev, &crev, &data_offset)) {
3498                 voltage_info = (union voltage_object_info *)
3499                         (rdev->mode_info.atom_context->bios + data_offset);
3500
3501                 switch (frev) {
3502                 case 3:
3503                         switch (crev) {
3504                         case 1:
3505                                 voltage_object = (union voltage_object *)
3506                                         atom_lookup_voltage_object_v3(&voltage_info->v3,
3507                                                                       voltage_type,
3508                                                                       VOLTAGE_OBJ_SVID2);
3509                                 if (voltage_object) {
3510                                         *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3511                                         *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3512                                 } else {
3513                                         return -EINVAL;
3514                                 }
3515                                 break;
3516                         default:
3517                                 DRM_ERROR("unknown voltage object table\n");
3518                                 return -EINVAL;
3519                         }
3520                         break;
3521                 default:
3522                         DRM_ERROR("unknown voltage object table\n");
3523                         return -EINVAL;
3524                 }
3525
3526         }
3527         return 0;
3528 }
3529
3530 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3531                                 u8 voltage_type, u16 *max_voltage)
3532 {
3533         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3534         u8 frev, crev;
3535         u16 data_offset, size;
3536         union voltage_object_info *voltage_info;
3537         union voltage_object *voltage_object = NULL;
3538
3539         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3540                                    &frev, &crev, &data_offset)) {
3541                 voltage_info = (union voltage_object_info *)
3542                         (rdev->mode_info.atom_context->bios + data_offset);
3543
3544                 switch (crev) {
3545                 case 1:
3546                         voltage_object = (union voltage_object *)
3547                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3548                         if (voltage_object) {
3549                                 ATOM_VOLTAGE_FORMULA *formula =
3550                                         &voltage_object->v1.asFormula;
3551                                 if (formula->ucFlag & 1)
3552                                         *max_voltage =
3553                                                 le16_to_cpu(formula->usVoltageBaseLevel) +
3554                                                 formula->ucNumOfVoltageEntries / 2 *
3555                                                 le16_to_cpu(formula->usVoltageStep);
3556                                 else
3557                                         *max_voltage =
3558                                                 le16_to_cpu(formula->usVoltageBaseLevel) +
3559                                                 (formula->ucNumOfVoltageEntries - 1) *
3560                                                 le16_to_cpu(formula->usVoltageStep);
3561                                 return 0;
3562                         }
3563                         break;
3564                 case 2:
3565                         voltage_object = (union voltage_object *)
3566                                 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3567                         if (voltage_object) {
3568                                 ATOM_VOLTAGE_FORMULA_V2 *formula =
3569                                         &voltage_object->v2.asFormula;
3570                                 if (formula->ucNumOfVoltageEntries) {
3571                                         VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3572                                                 ((u8 *)&formula->asVIDAdjustEntries[0] +
3573                                                  (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3574                                         *max_voltage =
3575                                                 le16_to_cpu(lut->usVoltageValue);
3576                                         return 0;
3577                                 }
3578                         }
3579                         break;
3580                 default:
3581                         DRM_ERROR("unknown voltage object table\n");
3582                         return -EINVAL;
3583                 }
3584
3585         }
3586         return -EINVAL;
3587 }
3588
3589 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3590                                 u8 voltage_type, u16 *min_voltage)
3591 {
3592         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3593         u8 frev, crev;
3594         u16 data_offset, size;
3595         union voltage_object_info *voltage_info;
3596         union voltage_object *voltage_object = NULL;
3597
3598         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3599                                    &frev, &crev, &data_offset)) {
3600                 voltage_info = (union voltage_object_info *)
3601                         (rdev->mode_info.atom_context->bios + data_offset);
3602
3603                 switch (crev) {
3604                 case 1:
3605                         voltage_object = (union voltage_object *)
3606                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3607                         if (voltage_object) {
3608                                 ATOM_VOLTAGE_FORMULA *formula =
3609                                         &voltage_object->v1.asFormula;
3610                                 *min_voltage =
3611                                         le16_to_cpu(formula->usVoltageBaseLevel);
3612                                 return 0;
3613                         }
3614                         break;
3615                 case 2:
3616                         voltage_object = (union voltage_object *)
3617                                 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3618                         if (voltage_object) {
3619                                 ATOM_VOLTAGE_FORMULA_V2 *formula =
3620                                         &voltage_object->v2.asFormula;
3621                                 if (formula->ucNumOfVoltageEntries) {
3622                                         *min_voltage =
3623                                                 le16_to_cpu(formula->asVIDAdjustEntries[
3624                                                                     0
3625                                                                     ].usVoltageValue);
3626                                         return 0;
3627                                 }
3628                         }
3629                         break;
3630                 default:
3631                         DRM_ERROR("unknown voltage object table\n");
3632                         return -EINVAL;
3633                 }
3634
3635         }
3636         return -EINVAL;
3637 }
3638
3639 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3640                                  u8 voltage_type, u16 *voltage_step)
3641 {
3642         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3643         u8 frev, crev;
3644         u16 data_offset, size;
3645         union voltage_object_info *voltage_info;
3646         union voltage_object *voltage_object = NULL;
3647
3648         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3649                                    &frev, &crev, &data_offset)) {
3650                 voltage_info = (union voltage_object_info *)
3651                         (rdev->mode_info.atom_context->bios + data_offset);
3652
3653                 switch (crev) {
3654                 case 1:
3655                         voltage_object = (union voltage_object *)
3656                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3657                         if (voltage_object) {
3658                                 ATOM_VOLTAGE_FORMULA *formula =
3659                                         &voltage_object->v1.asFormula;
3660                                 if (formula->ucFlag & 1)
3661                                         *voltage_step =
3662                                                 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3663                                 else
3664                                         *voltage_step =
3665                                                 le16_to_cpu(formula->usVoltageStep);
3666                                 return 0;
3667                         }
3668                         break;
3669                 case 2:
3670                         return -EINVAL;
3671                 default:
3672                         DRM_ERROR("unknown voltage object table\n");
3673                         return -EINVAL;
3674                 }
3675
3676         }
3677         return -EINVAL;
3678 }
3679
3680 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3681                                       u8 voltage_type,
3682                                       u16 nominal_voltage,
3683                                       u16 *true_voltage)
3684 {
3685         u16 min_voltage, max_voltage, voltage_step;
3686
3687         if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3688                 return -EINVAL;
3689         if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3690                 return -EINVAL;
3691         if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3692                 return -EINVAL;
3693
3694         if (nominal_voltage <= min_voltage)
3695                 *true_voltage = min_voltage;
3696         else if (nominal_voltage >= max_voltage)
3697                 *true_voltage = max_voltage;
3698         else
3699                 *true_voltage = min_voltage +
3700                         ((nominal_voltage - min_voltage) / voltage_step) *
3701                         voltage_step;
3702
3703         return 0;
3704 }
3705
3706 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3707                                   u8 voltage_type, u8 voltage_mode,
3708                                   struct atom_voltage_table *voltage_table)
3709 {
3710         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3711         u8 frev, crev;
3712         u16 data_offset, size;
3713         int i, ret;
3714         union voltage_object_info *voltage_info;
3715         union voltage_object *voltage_object = NULL;
3716
3717         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3718                                    &frev, &crev, &data_offset)) {
3719                 voltage_info = (union voltage_object_info *)
3720                         (rdev->mode_info.atom_context->bios + data_offset);
3721
3722                 switch (frev) {
3723                 case 1:
3724                 case 2:
3725                         switch (crev) {
3726                         case 1:
3727                                 DRM_ERROR("old table version %d, %d\n", frev, crev);
3728                                 return -EINVAL;
3729                         case 2:
3730                                 voltage_object = (union voltage_object *)
3731                                         atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3732                                 if (voltage_object) {
3733                                         ATOM_VOLTAGE_FORMULA_V2 *formula =
3734                                                 &voltage_object->v2.asFormula;
3735                                         VOLTAGE_LUT_ENTRY *lut;
3736                                         if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3737                                                 return -EINVAL;
3738                                         lut = &formula->asVIDAdjustEntries[0];
3739                                         for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3740                                                 voltage_table->entries[i].value =
3741                                                         le16_to_cpu(lut->usVoltageValue);
3742                                                 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3743                                                                                             voltage_table->entries[i].value,
3744                                                                                             voltage_type,
3745                                                                                             &voltage_table->entries[i].smio_low,
3746                                                                                             &voltage_table->mask_low);
3747                                                 if (ret)
3748                                                         return ret;
3749                                                 lut = (VOLTAGE_LUT_ENTRY *)
3750                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3751                                         }
3752                                         voltage_table->count = formula->ucNumOfVoltageEntries;
3753                                         return 0;
3754                                 }
3755                                 break;
3756                         default:
3757                                 DRM_ERROR("unknown voltage object table\n");
3758                                 return -EINVAL;
3759                         }
3760                         break;
3761                 case 3:
3762                         switch (crev) {
3763                         case 1:
3764                                 voltage_object = (union voltage_object *)
3765                                         atom_lookup_voltage_object_v3(&voltage_info->v3,
3766                                                                       voltage_type, voltage_mode);
3767                                 if (voltage_object) {
3768                                         ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3769                                                 &voltage_object->v3.asGpioVoltageObj;
3770                                         VOLTAGE_LUT_ENTRY_V2 *lut;
3771                                         if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3772                                                 return -EINVAL;
3773                                         lut = &gpio->asVolGpioLut[0];
3774                                         for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3775                                                 voltage_table->entries[i].value =
3776                                                         le16_to_cpu(lut->usVoltageValue);
3777                                                 voltage_table->entries[i].smio_low =
3778                                                         le32_to_cpu(lut->ulVoltageId);
3779                                                 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3780                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3781                                         }
3782                                         voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3783                                         voltage_table->count = gpio->ucGpioEntryNum;
3784                                         voltage_table->phase_delay = gpio->ucPhaseDelay;
3785                                         return 0;
3786                                 }
3787                                 break;
3788                         default:
3789                                 DRM_ERROR("unknown voltage object table\n");
3790                                 return -EINVAL;
3791                         }
3792                         break;
3793                 default:
3794                         DRM_ERROR("unknown voltage object table\n");
3795                         return -EINVAL;
3796                 }
3797         }
3798         return -EINVAL;
3799 }
3800
3801 union vram_info {
3802         struct _ATOM_VRAM_INFO_V3 v1_3;
3803         struct _ATOM_VRAM_INFO_V4 v1_4;
3804         struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3805 };
3806
3807 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3808                                 u8 module_index, struct atom_memory_info *mem_info)
3809 {
3810         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3811         u8 frev, crev, i;
3812         u16 data_offset, size;
3813         union vram_info *vram_info;
3814
3815         memset(mem_info, 0, sizeof(struct atom_memory_info));
3816
3817         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3818                                    &frev, &crev, &data_offset)) {
3819                 vram_info = (union vram_info *)
3820                         (rdev->mode_info.atom_context->bios + data_offset);
3821                 switch (frev) {
3822                 case 1:
3823                         switch (crev) {
3824                         case 3:
3825                                 /* r6xx */
3826                                 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3827                                         ATOM_VRAM_MODULE_V3 *vram_module =
3828                                                 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3829
3830                                         for (i = 0; i < module_index; i++) {
3831                                                 if (le16_to_cpu(vram_module->usSize) == 0)
3832                                                         return -EINVAL;
3833                                                 vram_module = (ATOM_VRAM_MODULE_V3 *)
3834                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3835                                         }
3836                                         mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3837                                         mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3838                                 } else
3839                                         return -EINVAL;
3840                                 break;
3841                         case 4:
3842                                 /* r7xx, evergreen */
3843                                 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3844                                         ATOM_VRAM_MODULE_V4 *vram_module =
3845                                                 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3846
3847                                         for (i = 0; i < module_index; i++) {
3848                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3849                                                         return -EINVAL;
3850                                                 vram_module = (ATOM_VRAM_MODULE_V4 *)
3851                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3852                                         }
3853                                         mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3854                                         mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3855                                 } else
3856                                         return -EINVAL;
3857                                 break;
3858                         default:
3859                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3860                                 return -EINVAL;
3861                         }
3862                         break;
3863                 case 2:
3864                         switch (crev) {
3865                         case 1:
3866                                 /* ni */
3867                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3868                                         ATOM_VRAM_MODULE_V7 *vram_module =
3869                                                 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3870
3871                                         for (i = 0; i < module_index; i++) {
3872                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3873                                                         return -EINVAL;
3874                                                 vram_module = (ATOM_VRAM_MODULE_V7 *)
3875                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3876                                         }
3877                                         mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3878                                         mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3879                                 } else
3880                                         return -EINVAL;
3881                                 break;
3882                         default:
3883                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3884                                 return -EINVAL;
3885                         }
3886                         break;
3887                 default:
3888                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3889                         return -EINVAL;
3890                 }
3891                 return 0;
3892         }
3893         return -EINVAL;
3894 }
3895
3896 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3897                                      bool gddr5, u8 module_index,
3898                                      struct atom_memory_clock_range_table *mclk_range_table)
3899 {
3900         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3901         u8 frev, crev, i;
3902         u16 data_offset, size;
3903         union vram_info *vram_info;
3904         u32 mem_timing_size = gddr5 ?
3905                 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3906
3907         memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3908
3909         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3910                                    &frev, &crev, &data_offset)) {
3911                 vram_info = (union vram_info *)
3912                         (rdev->mode_info.atom_context->bios + data_offset);
3913                 switch (frev) {
3914                 case 1:
3915                         switch (crev) {
3916                         case 3:
3917                                 DRM_ERROR("old table version %d, %d\n", frev, crev);
3918                                 return -EINVAL;
3919                         case 4:
3920                                 /* r7xx, evergreen */
3921                                 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3922                                         ATOM_VRAM_MODULE_V4 *vram_module =
3923                                                 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3924                                         ATOM_MEMORY_TIMING_FORMAT *format;
3925
3926                                         for (i = 0; i < module_index; i++) {
3927                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3928                                                         return -EINVAL;
3929                                                 vram_module = (ATOM_VRAM_MODULE_V4 *)
3930                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3931                                         }
3932                                         mclk_range_table->num_entries = (u8)
3933                                                 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3934                                                  mem_timing_size);
3935                                         format = &vram_module->asMemTiming[0];
3936                                         for (i = 0; i < mclk_range_table->num_entries; i++) {
3937                                                 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3938                                                 format = (ATOM_MEMORY_TIMING_FORMAT *)
3939                                                         ((u8 *)format + mem_timing_size);
3940                                         }
3941                                 } else
3942                                         return -EINVAL;
3943                                 break;
3944                         default:
3945                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3946                                 return -EINVAL;
3947                         }
3948                         break;
3949                 case 2:
3950                         DRM_ERROR("new table version %d, %d\n", frev, crev);
3951                         return -EINVAL;
3952                 default:
3953                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3954                         return -EINVAL;
3955                 }
3956                 return 0;
3957         }
3958         return -EINVAL;
3959 }
3960
3961 #define MEM_ID_MASK           0xff000000
3962 #define MEM_ID_SHIFT          24
3963 #define CLOCK_RANGE_MASK      0x00ffffff
3964 #define CLOCK_RANGE_SHIFT     0
3965 #define LOW_NIBBLE_MASK       0xf
3966 #define DATA_EQU_PREV         0
3967 #define DATA_FROM_TABLE       4
3968
3969 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3970                                   u8 module_index,
3971                                   struct atom_mc_reg_table *reg_table)
3972 {
3973         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3974         u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3975         u32 i = 0, j;
3976         u16 data_offset, size;
3977         union vram_info *vram_info;
3978
3979         memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3980
3981         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3982                                    &frev, &crev, &data_offset)) {
3983                 vram_info = (union vram_info *)
3984                         (rdev->mode_info.atom_context->bios + data_offset);
3985                 switch (frev) {
3986                 case 1:
3987                         DRM_ERROR("old table version %d, %d\n", frev, crev);
3988                         return -EINVAL;
3989                 case 2:
3990                         switch (crev) {
3991                         case 1:
3992                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3993                                         ATOM_INIT_REG_BLOCK *reg_block =
3994                                                 (ATOM_INIT_REG_BLOCK *)
3995                                                 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
3996                                         ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
3997                                                 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3998                                                 ((u8 *)reg_block + (2 * sizeof(u16)) +
3999                                                  le16_to_cpu(reg_block->usRegIndexTblSize));
4000                                         ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
4001                                         num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4002                                                            sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4003                                         if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4004                                                 return -EINVAL;
4005                                         while (i < num_entries) {
4006                                                 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4007                                                         break;
4008                                                 reg_table->mc_reg_address[i].s1 =
4009                                                         (u16)(le16_to_cpu(format->usRegIndex));
4010                                                 reg_table->mc_reg_address[i].pre_reg_data =
4011                                                         (u8)(format->ucPreRegDataLength);
4012                                                 i++;
4013                                                 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4014                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4015                                         }
4016                                         reg_table->last = i;
4017                                         while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4018                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4019                                                 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4020                                                                 >> MEM_ID_SHIFT);
4021                                                 if (module_index == t_mem_id) {
4022                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4023                                                                 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4024                                                                       >> CLOCK_RANGE_SHIFT);
4025                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
4026                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4027                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4028                                                                                 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4029                                                                         j++;
4030                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4031                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4032                                                                                 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4033                                                                 }
4034                                                         }
4035                                                         num_ranges++;
4036                                                 }
4037                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4038                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4039                                         }
4040                                         if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4041                                                 return -EINVAL;
4042                                         reg_table->num_entries = num_ranges;
4043                                 } else
4044                                         return -EINVAL;
4045                                 break;
4046                         default:
4047                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4048                                 return -EINVAL;
4049                         }
4050                         break;
4051                 default:
4052                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4053                         return -EINVAL;
4054                 }
4055                 return 0;
4056         }
4057         return -EINVAL;
4058 }
4059
4060 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4061 {
4062         struct radeon_device *rdev = dev->dev_private;
4063         uint32_t bios_2_scratch, bios_6_scratch;
4064
4065         if (rdev->family >= CHIP_R600) {
4066                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4067                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4068         } else {
4069                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4070                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4071         }
4072
4073         /* let the bios control the backlight */
4074         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4075
4076         /* tell the bios not to handle mode switching */
4077         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4078
4079         /* clear the vbios dpms state */
4080         if (ASIC_IS_DCE4(rdev))
4081                 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4082
4083         if (rdev->family >= CHIP_R600) {
4084                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4085                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4086         } else {
4087                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4088                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4089         }
4090
4091 }
4092
4093 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4094 {
4095         uint32_t scratch_reg;
4096         int i;
4097
4098         if (rdev->family >= CHIP_R600)
4099                 scratch_reg = R600_BIOS_0_SCRATCH;
4100         else
4101                 scratch_reg = RADEON_BIOS_0_SCRATCH;
4102
4103         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4104                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4105 }
4106
4107 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4108 {
4109         uint32_t scratch_reg;
4110         int i;
4111
4112         if (rdev->family >= CHIP_R600)
4113                 scratch_reg = R600_BIOS_0_SCRATCH;
4114         else
4115                 scratch_reg = RADEON_BIOS_0_SCRATCH;
4116
4117         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4118                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4119 }
4120
4121 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4122 {
4123         struct drm_device *dev = encoder->dev;
4124         struct radeon_device *rdev = dev->dev_private;
4125         uint32_t bios_6_scratch;
4126
4127         if (rdev->family >= CHIP_R600)
4128                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4129         else
4130                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4131
4132         if (lock) {
4133                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4134                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4135         } else {
4136                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4137                 bios_6_scratch |= ATOM_S6_ACC_MODE;
4138         }
4139
4140         if (rdev->family >= CHIP_R600)
4141                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4142         else
4143                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4144 }
4145
4146 /* at some point we may want to break this out into individual functions */
4147 void
4148 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4149                                        struct drm_encoder *encoder,
4150                                        bool connected)
4151 {
4152         struct drm_device *dev = connector->dev;
4153         struct radeon_device *rdev = dev->dev_private;
4154         struct radeon_connector *radeon_connector =
4155             to_radeon_connector(connector);
4156         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4157         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4158
4159         if (rdev->family >= CHIP_R600) {
4160                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4161                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4162                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4163         } else {
4164                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4165                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4166                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4167         }
4168
4169         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4170             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4171                 if (connected) {
4172                         DRM_DEBUG_KMS("TV1 connected\n");
4173                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4174                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4175                 } else {
4176                         DRM_DEBUG_KMS("TV1 disconnected\n");
4177                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4178                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4179                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4180                 }
4181         }
4182         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4183             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4184                 if (connected) {
4185                         DRM_DEBUG_KMS("CV connected\n");
4186                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4187                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4188                 } else {
4189                         DRM_DEBUG_KMS("CV disconnected\n");
4190                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
4191                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4192                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4193                 }
4194         }
4195         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4196             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4197                 if (connected) {
4198                         DRM_DEBUG_KMS("LCD1 connected\n");
4199                         bios_0_scratch |= ATOM_S0_LCD1;
4200                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4201                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4202                 } else {
4203                         DRM_DEBUG_KMS("LCD1 disconnected\n");
4204                         bios_0_scratch &= ~ATOM_S0_LCD1;
4205                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4206                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4207                 }
4208         }
4209         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4210             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4211                 if (connected) {
4212                         DRM_DEBUG_KMS("CRT1 connected\n");
4213                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4214                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4215                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4216                 } else {
4217                         DRM_DEBUG_KMS("CRT1 disconnected\n");
4218                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4219                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4220                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4221                 }
4222         }
4223         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4224             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4225                 if (connected) {
4226                         DRM_DEBUG_KMS("CRT2 connected\n");
4227                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4228                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4229                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4230                 } else {
4231                         DRM_DEBUG_KMS("CRT2 disconnected\n");
4232                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4233                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4234                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4235                 }
4236         }
4237         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4238             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4239                 if (connected) {
4240                         DRM_DEBUG_KMS("DFP1 connected\n");
4241                         bios_0_scratch |= ATOM_S0_DFP1;
4242                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4243                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4244                 } else {
4245                         DRM_DEBUG_KMS("DFP1 disconnected\n");
4246                         bios_0_scratch &= ~ATOM_S0_DFP1;
4247                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4248                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4249                 }
4250         }
4251         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4252             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4253                 if (connected) {
4254                         DRM_DEBUG_KMS("DFP2 connected\n");
4255                         bios_0_scratch |= ATOM_S0_DFP2;
4256                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4257                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4258                 } else {
4259                         DRM_DEBUG_KMS("DFP2 disconnected\n");
4260                         bios_0_scratch &= ~ATOM_S0_DFP2;
4261                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4262                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4263                 }
4264         }
4265         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4266             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4267                 if (connected) {
4268                         DRM_DEBUG_KMS("DFP3 connected\n");
4269                         bios_0_scratch |= ATOM_S0_DFP3;
4270                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4271                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4272                 } else {
4273                         DRM_DEBUG_KMS("DFP3 disconnected\n");
4274                         bios_0_scratch &= ~ATOM_S0_DFP3;
4275                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4276                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4277                 }
4278         }
4279         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4280             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4281                 if (connected) {
4282                         DRM_DEBUG_KMS("DFP4 connected\n");
4283                         bios_0_scratch |= ATOM_S0_DFP4;
4284                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4285                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4286                 } else {
4287                         DRM_DEBUG_KMS("DFP4 disconnected\n");
4288                         bios_0_scratch &= ~ATOM_S0_DFP4;
4289                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4290                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4291                 }
4292         }
4293         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4294             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4295                 if (connected) {
4296                         DRM_DEBUG_KMS("DFP5 connected\n");
4297                         bios_0_scratch |= ATOM_S0_DFP5;
4298                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4299                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4300                 } else {
4301                         DRM_DEBUG_KMS("DFP5 disconnected\n");
4302                         bios_0_scratch &= ~ATOM_S0_DFP5;
4303                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4304                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4305                 }
4306         }
4307         if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4308             (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4309                 if (connected) {
4310                         DRM_DEBUG_KMS("DFP6 connected\n");
4311                         bios_0_scratch |= ATOM_S0_DFP6;
4312                         bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4313                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4314                 } else {
4315                         DRM_DEBUG_KMS("DFP6 disconnected\n");
4316                         bios_0_scratch &= ~ATOM_S0_DFP6;
4317                         bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4318                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4319                 }
4320         }
4321
4322         if (rdev->family >= CHIP_R600) {
4323                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4324                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4325                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4326         } else {
4327                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4328                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4329                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4330         }
4331 }
4332
4333 void
4334 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4335 {
4336         struct drm_device *dev = encoder->dev;
4337         struct radeon_device *rdev = dev->dev_private;
4338         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4339         uint32_t bios_3_scratch;
4340
4341         if (ASIC_IS_DCE4(rdev))
4342                 return;
4343
4344         if (rdev->family >= CHIP_R600)
4345                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4346         else
4347                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4348
4349         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4350                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4351                 bios_3_scratch |= (crtc << 18);
4352         }
4353         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4354                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4355                 bios_3_scratch |= (crtc << 24);
4356         }
4357         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4358                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4359                 bios_3_scratch |= (crtc << 16);
4360         }
4361         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4362                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4363                 bios_3_scratch |= (crtc << 20);
4364         }
4365         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4366                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4367                 bios_3_scratch |= (crtc << 17);
4368         }
4369         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4370                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4371                 bios_3_scratch |= (crtc << 19);
4372         }
4373         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4374                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4375                 bios_3_scratch |= (crtc << 23);
4376         }
4377         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4378                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4379                 bios_3_scratch |= (crtc << 25);
4380         }
4381
4382         if (rdev->family >= CHIP_R600)
4383                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4384         else
4385                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4386 }
4387
4388 void
4389 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4390 {
4391         struct drm_device *dev = encoder->dev;
4392         struct radeon_device *rdev = dev->dev_private;
4393         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4394         uint32_t bios_2_scratch;
4395
4396         if (ASIC_IS_DCE4(rdev))
4397                 return;
4398
4399         if (rdev->family >= CHIP_R600)
4400                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4401         else
4402                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4403
4404         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4405                 if (on)
4406                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4407                 else
4408                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4409         }
4410         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4411                 if (on)
4412                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4413                 else
4414                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4415         }
4416         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4417                 if (on)
4418                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4419                 else
4420                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4421         }
4422         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4423                 if (on)
4424                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4425                 else
4426                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4427         }
4428         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4429                 if (on)
4430                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4431                 else
4432                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4433         }
4434         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4435                 if (on)
4436                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4437                 else
4438                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4439         }
4440         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4441                 if (on)
4442                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4443                 else
4444                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4445         }
4446         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4447                 if (on)
4448                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4449                 else
4450                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4451         }
4452         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4453                 if (on)
4454                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4455                 else
4456                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4457         }
4458         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4459                 if (on)
4460                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4461                 else
4462                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4463         }
4464
4465         if (rdev->family >= CHIP_R600)
4466                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4467         else
4468                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4469 }