2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
32 #include <drm/drm_debugfs.h>
33 #include <drm/drm_device.h>
34 #include <drm/drm_file.h>
35 #include <drm/drm_pci.h>
39 #include "r420_reg_safe.h"
42 #include "radeon_asic.h"
43 #include "radeon_reg.h"
45 void r420_pm_init_profile(struct radeon_device *rdev)
48 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
49 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
50 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
51 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
53 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
54 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
55 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
56 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
58 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
59 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
60 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
61 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
63 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
64 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
65 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
66 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
68 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
69 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
70 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
71 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
73 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
74 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
75 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
76 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
78 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
79 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
80 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
81 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
84 static void r420_set_reg_safe(struct radeon_device *rdev)
86 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
87 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
90 void r420_pipes_init(struct radeon_device *rdev)
93 unsigned gb_pipe_select;
96 /* GA_ENHANCE workaround TCL deadlock issue */
97 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
99 /* add idle wait as per freedesktop.org bug 24041 */
100 if (r100_gui_wait_for_idle(rdev)) {
101 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
103 /* get max number of pipes */
104 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
105 num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
107 /* SE chips have 1 pipe */
108 if ((rdev->pdev->device == 0x5e4c) ||
109 (rdev->pdev->device == 0x5e4f))
112 rdev->num_gb_pipes = num_pipes;
116 /* force to 1 pipe */
132 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
133 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
134 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
135 WREG32(R300_GB_TILE_CONFIG, tmp);
136 if (r100_gui_wait_for_idle(rdev)) {
137 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
140 tmp = RREG32(R300_DST_PIPE_CONFIG);
141 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
143 WREG32(R300_RB2D_DSTCACHE_MODE,
144 RREG32(R300_RB2D_DSTCACHE_MODE) |
145 R300_DC_AUTOFLUSH_ENABLE |
146 R300_DC_DC_DISABLE_IGNORE_PE);
148 if (r100_gui_wait_for_idle(rdev)) {
149 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
152 if (rdev->family == CHIP_RV530) {
153 tmp = RREG32(RV530_GB_PIPE_SELECT2);
155 rdev->num_z_pipes = 2;
157 rdev->num_z_pipes = 1;
159 rdev->num_z_pipes = 1;
161 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
162 rdev->num_gb_pipes, rdev->num_z_pipes);
165 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
170 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
171 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
172 r = RREG32(R_0001FC_MC_IND_DATA);
173 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
177 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
181 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
182 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
183 S_0001F8_MC_IND_WR_EN(1));
184 WREG32(R_0001FC_MC_IND_DATA, v);
185 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
188 static void r420_debugfs(struct radeon_device *rdev)
190 if (r100_debugfs_rbbm_init(rdev)) {
191 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
193 if (r420_debugfs_pipes_info_init(rdev)) {
194 DRM_ERROR("Failed to register debugfs file for pipes !\n");
198 static void r420_clock_resume(struct radeon_device *rdev)
202 if (radeon_dynclks != -1 && radeon_dynclks)
203 radeon_atom_set_clock_gating(rdev, 1);
204 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
205 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
206 if (rdev->family == CHIP_R420)
207 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
208 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
211 static void r420_cp_errata_init(struct radeon_device *rdev)
214 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
216 /* RV410 and R420 can lock up if CP DMA to host memory happens
217 * while the 2D engine is busy.
219 * The proper workaround is to queue a RESYNC at the beginning
220 * of the CP init, apparently.
222 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
223 r = radeon_ring_lock(rdev, ring, 8);
225 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
226 radeon_ring_write(ring, rdev->config.r300.resync_scratch);
227 radeon_ring_write(ring, 0xDEADBEEF);
228 radeon_ring_unlock_commit(rdev, ring, false);
231 static void r420_cp_errata_fini(struct radeon_device *rdev)
234 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
236 /* Catch the RESYNC we dispatched all the way back,
237 * at the very beginning of the CP init.
239 r = radeon_ring_lock(rdev, ring, 8);
241 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
242 radeon_ring_write(ring, R300_RB3D_DC_FINISH);
243 radeon_ring_unlock_commit(rdev, ring, false);
244 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
247 static int r420_startup(struct radeon_device *rdev)
251 /* set common regs */
252 r100_set_common_regs(rdev);
254 r300_mc_program(rdev);
256 r420_clock_resume(rdev);
257 /* Initialize GART (initialize after TTM so we can allocate
258 * memory through TTM but finalize after TTM) */
259 if (rdev->flags & RADEON_IS_PCIE) {
260 r = rv370_pcie_gart_enable(rdev);
264 if (rdev->flags & RADEON_IS_PCI) {
265 r = r100_pci_gart_enable(rdev);
269 r420_pipes_init(rdev);
271 /* allocate wb buffer */
272 r = radeon_wb_init(rdev);
276 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
278 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
283 if (!rdev->irq.installed) {
284 r = radeon_irq_kms_init(rdev);
290 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
292 r = r100_cp_init(rdev, 1024 * 1024);
294 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
297 r420_cp_errata_init(rdev);
299 r = radeon_ib_pool_init(rdev);
301 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
308 int r420_resume(struct radeon_device *rdev)
312 /* Make sur GART are not working */
313 if (rdev->flags & RADEON_IS_PCIE)
314 rv370_pcie_gart_disable(rdev);
315 if (rdev->flags & RADEON_IS_PCI)
316 r100_pci_gart_disable(rdev);
317 /* Resume clock before doing reset */
318 r420_clock_resume(rdev);
319 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
320 if (radeon_asic_reset(rdev)) {
321 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
322 RREG32(R_000E40_RBBM_STATUS),
323 RREG32(R_0007C0_CP_STAT));
325 /* check if cards are posted or not */
326 if (rdev->is_atom_bios) {
327 atom_asic_init(rdev->mode_info.atom_context);
329 radeon_combios_asic_init(rdev->ddev);
331 /* Resume clock after posting */
332 r420_clock_resume(rdev);
333 /* Initialize surface registers */
334 radeon_surface_init(rdev);
336 rdev->accel_working = true;
337 r = r420_startup(rdev);
339 rdev->accel_working = false;
344 int r420_suspend(struct radeon_device *rdev)
346 radeon_pm_suspend(rdev);
347 r420_cp_errata_fini(rdev);
348 r100_cp_disable(rdev);
349 radeon_wb_disable(rdev);
350 r100_irq_disable(rdev);
351 if (rdev->flags & RADEON_IS_PCIE)
352 rv370_pcie_gart_disable(rdev);
353 if (rdev->flags & RADEON_IS_PCI)
354 r100_pci_gart_disable(rdev);
358 void r420_fini(struct radeon_device *rdev)
360 radeon_pm_fini(rdev);
362 radeon_wb_fini(rdev);
363 radeon_ib_pool_fini(rdev);
364 radeon_gem_fini(rdev);
365 if (rdev->flags & RADEON_IS_PCIE)
366 rv370_pcie_gart_fini(rdev);
367 if (rdev->flags & RADEON_IS_PCI)
368 r100_pci_gart_fini(rdev);
369 radeon_agp_fini(rdev);
370 radeon_irq_kms_fini(rdev);
371 radeon_fence_driver_fini(rdev);
372 radeon_bo_fini(rdev);
373 if (rdev->is_atom_bios) {
374 radeon_atombios_fini(rdev);
376 radeon_combios_fini(rdev);
382 int r420_init(struct radeon_device *rdev)
386 /* Initialize scratch registers */
387 radeon_scratch_init(rdev);
388 /* Initialize surface registers */
389 radeon_surface_init(rdev);
390 /* TODO: disable VGA need to use VGA request */
391 /* restore some register to sane defaults */
392 r100_restore_sanity(rdev);
394 if (!radeon_get_bios(rdev)) {
395 if (ASIC_IS_AVIVO(rdev))
398 if (rdev->is_atom_bios) {
399 r = radeon_atombios_init(rdev);
404 r = radeon_combios_init(rdev);
409 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
410 if (radeon_asic_reset(rdev)) {
412 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
413 RREG32(R_000E40_RBBM_STATUS),
414 RREG32(R_0007C0_CP_STAT));
416 /* check if cards are posted or not */
417 if (radeon_boot_test_post_card(rdev) == false)
420 /* Initialize clocks */
421 radeon_get_clock_info(rdev->ddev);
423 if (rdev->flags & RADEON_IS_AGP) {
424 r = radeon_agp_init(rdev);
426 radeon_agp_disable(rdev);
429 /* initialize memory controller */
433 r = radeon_fence_driver_init(rdev);
438 r = radeon_bo_init(rdev);
442 if (rdev->family == CHIP_R420)
443 r100_enable_bm(rdev);
445 if (rdev->flags & RADEON_IS_PCIE) {
446 r = rv370_pcie_gart_init(rdev);
450 if (rdev->flags & RADEON_IS_PCI) {
451 r = r100_pci_gart_init(rdev);
455 r420_set_reg_safe(rdev);
457 /* Initialize power management */
458 radeon_pm_init(rdev);
460 rdev->accel_working = true;
461 r = r420_startup(rdev);
463 /* Somethings want wront with the accel init stop accel */
464 dev_err(rdev->dev, "Disabling GPU acceleration\n");
466 radeon_wb_fini(rdev);
467 radeon_ib_pool_fini(rdev);
468 radeon_irq_kms_fini(rdev);
469 if (rdev->flags & RADEON_IS_PCIE)
470 rv370_pcie_gart_fini(rdev);
471 if (rdev->flags & RADEON_IS_PCI)
472 r100_pci_gart_fini(rdev);
473 radeon_agp_fini(rdev);
474 rdev->accel_working = false;
482 #if defined(CONFIG_DEBUG_FS)
483 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
485 struct drm_info_node *node = (struct drm_info_node *) m->private;
486 struct drm_device *dev = node->minor->dev;
487 struct radeon_device *rdev = dev->dev_private;
490 tmp = RREG32(R400_GB_PIPE_SELECT);
491 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
492 tmp = RREG32(R300_GB_TILE_CONFIG);
493 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
494 tmp = RREG32(R300_DST_PIPE_CONFIG);
495 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
499 static struct drm_info_list r420_pipes_info_list[] = {
500 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
504 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
506 #if defined(CONFIG_DEBUG_FS)
507 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);