drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/firmware.h>
  30 #include <linux/module.h>
  31 #include <linux/pci.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_device.h>
  36 #include <drm/drm_file.h>
  37 #include <drm/drm_fourcc.h>
  38 #include <drm/drm_vblank.h>
  39 #include <drm/radeon_drm.h>
  40
  41 #include "atom.h"
  42 #include "r100_reg_safe.h"
  43 #include "r100d.h"
  44 #include "radeon.h"
  45 #include "radeon_asic.h"
  46 #include "radeon_reg.h"
  47 #include "rn50_reg_safe.h"
  48 #include "rs100d.h"
  49 #include "rv200d.h"
  50 #include "rv250d.h"
  51
  52 /* Firmware Names */
  53 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  54 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  55 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  56 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  57 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  58 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  59 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  60
  61 MODULE_FIRMWARE(FIRMWARE_R100);
  62 MODULE_FIRMWARE(FIRMWARE_R200);
  63 MODULE_FIRMWARE(FIRMWARE_R300);
  64 MODULE_FIRMWARE(FIRMWARE_R420);
  65 MODULE_FIRMWARE(FIRMWARE_RS690);
  66 MODULE_FIRMWARE(FIRMWARE_RS600);
  67 MODULE_FIRMWARE(FIRMWARE_R520);
  68
  69 #include "r100_track.h"
  70
  71 /* This files gather functions specifics to:
  72  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  73  * and others in some cases.
  74  */
  75
  76 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
  77 {
  78         if (crtc == 0) {
  79                 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
  80                         return true;
  81                 else
  82                         return false;
  83         } else {
  84                 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
  85                         return true;
  86                 else
  87                         return false;
  88         }
  89 }
  90
  91 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
  92 {
  93         u32 vline1, vline2;
  94
  95         if (crtc == 0) {
  96                 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  97                 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  98         } else {
  99                 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
 100                 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
 101         }
 102         if (vline1 != vline2)
 103                 return true;
 104         else
 105                 return false;
 106 }
 107
 108 /**
 109  * r100_wait_for_vblank - vblank wait asic callback.
 110  *
 111  * @rdev: radeon_device pointer
 112  * @crtc: crtc to wait for vblank on
 113  *
 114  * Wait for vblank on the requested crtc (r1xx-r4xx).
 115  */
 116 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
 117 {
 118         unsigned i = 0;
 119
 120         if (crtc >= rdev->num_crtc)
 121                 return;
 122
 123         if (crtc == 0) {
 124                 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
 125                         return;
 126         } else {
 127                 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
 128                         return;
 129         }
 130
 131         /* depending on when we hit vblank, we may be close to active; if so,
 132          * wait for another frame.
 133          */
 134         while (r100_is_in_vblank(rdev, crtc)) {
 135                 if (i++ % 100 == 0) {
 136                         if (!r100_is_counter_moving(rdev, crtc))
 137                                 break;
 138                 }
 139         }
 140
 141         while (!r100_is_in_vblank(rdev, crtc)) {
 142                 if (i++ % 100 == 0) {
 143                         if (!r100_is_counter_moving(rdev, crtc))
 144                                 break;
 145                 }
 146         }
 147 }
 148
 149 /**
 150  * r100_page_flip - pageflip callback.
 151  *
 152  * @rdev: radeon_device pointer
 153  * @crtc_id: crtc to cleanup pageflip on
 154  * @crtc_base: new address of the crtc (GPU MC address)
 155  * @async: asynchronous flip
 156  *
 157  * Does the actual pageflip (r1xx-r4xx).
 158  * During vblank we take the crtc lock and wait for the update_pending
 159  * bit to go high, when it does, we release the lock, and allow the
 160  * double buffered update to take place.
 161  */
 162 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
 163 {
 164         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 165         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 166         int i;
 167
 168         /* Lock the graphics update lock */
 169         /* update the scanout addresses */
 170         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 171
 172         /* Wait for update_pending to go high. */
 173         for (i = 0; i < rdev->usec_timeout; i++) {
 174                 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
 175                         break;
 176                 udelay(1);
 177         }
 178         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 179
 180         /* Unlock the lock, so double-buffering can take place inside vblank */
 181         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 182         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 183
 184 }
 185
 186 /**
 187  * r100_page_flip_pending - check if page flip is still pending
 188  *
 189  * @rdev: radeon_device pointer
 190  * @crtc_id: crtc to check
 191  *
 192  * Check if the last pagefilp is still pending (r1xx-r4xx).
 193  * Returns the current update pending status.
 194  */
 195 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
 196 {
 197         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 198
 199         /* Return current update_pending status: */
 200         return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
 201                 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
 202 }
 203
 204 /**
 205  * r100_pm_get_dynpm_state - look up dynpm power state callback.
 206  *
 207  * @rdev: radeon_device pointer
 208  *
 209  * Look up the optimal power state based on the
 210  * current state of the GPU (r1xx-r5xx).
 211  * Used for dynpm only.
 212  */
 213 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 214 {
 215         int i;
 216         rdev->pm.dynpm_can_upclock = true;
 217         rdev->pm.dynpm_can_downclock = true;
 218
 219         switch (rdev->pm.dynpm_planned_action) {
 220         case DYNPM_ACTION_MINIMUM:
 221                 rdev->pm.requested_power_state_index = 0;
 222                 rdev->pm.dynpm_can_downclock = false;
 223                 break;
 224         case DYNPM_ACTION_DOWNCLOCK:
 225                 if (rdev->pm.current_power_state_index == 0) {
 226                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 227                         rdev->pm.dynpm_can_downclock = false;
 228                 } else {
 229                         if (rdev->pm.active_crtc_count > 1) {
 230                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 231                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 232                                                 continue;
 233                                         else if (i >= rdev->pm.current_power_state_index) {
 234                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 235                                                 break;
 236                                         } else {
 237                                                 rdev->pm.requested_power_state_index = i;
 238                                                 break;
 239                                         }
 240                                 }
 241                         } else
 242                                 rdev->pm.requested_power_state_index =
 243                                         rdev->pm.current_power_state_index - 1;
 244                 }
 245                 /* don't use the power state if crtcs are active and no display flag is set */
 246                 if ((rdev->pm.active_crtc_count > 0) &&
 247                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 248                      RADEON_PM_MODE_NO_DISPLAY)) {
 249                         rdev->pm.requested_power_state_index++;
 250                 }
 251                 break;
 252         case DYNPM_ACTION_UPCLOCK:
 253                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 254                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 255                         rdev->pm.dynpm_can_upclock = false;
 256                 } else {
 257                         if (rdev->pm.active_crtc_count > 1) {
 258                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 259                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 260                                                 continue;
 261                                         else if (i <= rdev->pm.current_power_state_index) {
 262                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 263                                                 break;
 264                                         } else {
 265                                                 rdev->pm.requested_power_state_index = i;
 266                                                 break;
 267                                         }
 268                                 }
 269                         } else
 270                                 rdev->pm.requested_power_state_index =
 271                                         rdev->pm.current_power_state_index + 1;
 272                 }
 273                 break;
 274         case DYNPM_ACTION_DEFAULT:
 275                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 276                 rdev->pm.dynpm_can_upclock = false;
 277                 break;
 278         case DYNPM_ACTION_NONE:
 279         default:
 280                 DRM_ERROR("Requested mode for not defined action\n");
 281                 return;
 282         }
 283         /* only one clock mode per power state */
 284         rdev->pm.requested_clock_mode_index = 0;
 285
 286         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 287                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 288                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 289                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 290                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 291                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 292                   pcie_lanes);
 293 }
 294
 295 /**
 296  * r100_pm_init_profile - Initialize power profiles callback.
 297  *
 298  * @rdev: radeon_device pointer
 299  *
 300  * Initialize the power states used in profile mode
 301  * (r1xx-r3xx).
 302  * Used for profile mode only.
 303  */
 304 void r100_pm_init_profile(struct radeon_device *rdev)
 305 {
 306         /* default */
 307         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 308         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 309         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 310         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 311         /* low sh */
 312         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 313         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 314         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 315         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 316         /* mid sh */
 317         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 318         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 319         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 320         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 321         /* high sh */
 322         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 323         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 324         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 325         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 326         /* low mh */
 327         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 328         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 329         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 330         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 331         /* mid mh */
 332         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 333         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 334         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 335         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 336         /* high mh */
 337         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 338         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 339         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 340         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 341 }
 342
 343 /**
 344  * r100_pm_misc - set additional pm hw parameters callback.
 345  *
 346  * @rdev: radeon_device pointer
 347  *
 348  * Set non-clock parameters associated with a power state
 349  * (voltage, pcie lanes, etc.) (r1xx-r4xx).
 350  */
 351 void r100_pm_misc(struct radeon_device *rdev)
 352 {
 353         int requested_index = rdev->pm.requested_power_state_index;
 354         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 355         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 356         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 357
 358         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 359                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 360                         tmp = RREG32(voltage->gpio.reg);
 361                         if (voltage->active_high)
 362                                 tmp |= voltage->gpio.mask;
 363                         else
 364                                 tmp &= ~(voltage->gpio.mask);
 365                         WREG32(voltage->gpio.reg, tmp);
 366                         if (voltage->delay)
 367                                 udelay(voltage->delay);
 368                 } else {
 369                         tmp = RREG32(voltage->gpio.reg);
 370                         if (voltage->active_high)
 371                                 tmp &= ~voltage->gpio.mask;
 372                         else
 373                                 tmp |= voltage->gpio.mask;
 374                         WREG32(voltage->gpio.reg, tmp);
 375                         if (voltage->delay)
 376                                 udelay(voltage->delay);
 377                 }
 378         }
 379
 380         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 381         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 382         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 383         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 384         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 385         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 386                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 387                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 388                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 389                 else
 390                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 391                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 392                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 393                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 394                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 395         } else
 396                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 397
 398         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 399                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 400                 if (voltage->delay) {
 401                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 402                         switch (voltage->delay) {
 403                         case 33:
 404                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 405                                 break;
 406                         case 66:
 407                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 408                                 break;
 409                         case 99:
 410                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 411                                 break;
 412                         case 132:
 413                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 414                                 break;
 415                         }
 416                 } else
 417                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 418         } else
 419                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 420
 421         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 422                 sclk_cntl &= ~FORCE_HDP;
 423         else
 424                 sclk_cntl |= FORCE_HDP;
 425
 426         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 427         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 428         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 429
 430         /* set pcie lanes */
 431         if ((rdev->flags & RADEON_IS_PCIE) &&
 432             !(rdev->flags & RADEON_IS_IGP) &&
 433             rdev->asic->pm.set_pcie_lanes &&
 434             (ps->pcie_lanes !=
 435              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 436                 radeon_set_pcie_lanes(rdev,
 437                                       ps->pcie_lanes);
 438                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 439         }
 440 }
 441
 442 /**
 443  * r100_pm_prepare - pre-power state change callback.
 444  *
 445  * @rdev: radeon_device pointer
 446  *
 447  * Prepare for a power state change (r1xx-r4xx).
 448  */
 449 void r100_pm_prepare(struct radeon_device *rdev)
 450 {
 451         struct drm_device *ddev = rdev->ddev;
 452         struct drm_crtc *crtc;
 453         struct radeon_crtc *radeon_crtc;
 454         u32 tmp;
 455
 456         /* disable any active CRTCs */
 457         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 458                 radeon_crtc = to_radeon_crtc(crtc);
 459                 if (radeon_crtc->enabled) {
 460                         if (radeon_crtc->crtc_id) {
 461                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 462                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 463                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 464                         } else {
 465                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 466                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 467                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 468                         }
 469                 }
 470         }
 471 }
 472
 473 /**
 474  * r100_pm_finish - post-power state change callback.
 475  *
 476  * @rdev: radeon_device pointer
 477  *
 478  * Clean up after a power state change (r1xx-r4xx).
 479  */
 480 void r100_pm_finish(struct radeon_device *rdev)
 481 {
 482         struct drm_device *ddev = rdev->ddev;
 483         struct drm_crtc *crtc;
 484         struct radeon_crtc *radeon_crtc;
 485         u32 tmp;
 486
 487         /* enable any active CRTCs */
 488         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 489                 radeon_crtc = to_radeon_crtc(crtc);
 490                 if (radeon_crtc->enabled) {
 491                         if (radeon_crtc->crtc_id) {
 492                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 493                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 494                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 495                         } else {
 496                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 497                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 498                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 499                         }
 500                 }
 501         }
 502 }
 503
 504 /**
 505  * r100_gui_idle - gui idle callback.
 506  *
 507  * @rdev: radeon_device pointer
 508  *
 509  * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
 510  * Returns true if idle, false if not.
 511  */
 512 bool r100_gui_idle(struct radeon_device *rdev)
 513 {
 514         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 515                 return false;
 516         else
 517                 return true;
 518 }
 519
 520 /* hpd for digital panel detect/disconnect */
 521 /**
 522  * r100_hpd_sense - hpd sense callback.
 523  *
 524  * @rdev: radeon_device pointer
 525  * @hpd: hpd (hotplug detect) pin
 526  *
 527  * Checks if a digital monitor is connected (r1xx-r4xx).
 528  * Returns true if connected, false if not connected.
 529  */
 530 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 531 {
 532         bool connected = false;
 533
 534         switch (hpd) {
 535         case RADEON_HPD_1:
 536                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 537                         connected = true;
 538                 break;
 539         case RADEON_HPD_2:
 540                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 541                         connected = true;
 542                 break;
 543         default:
 544                 break;
 545         }
 546         return connected;
 547 }
 548
 549 /**
 550  * r100_hpd_set_polarity - hpd set polarity callback.
 551  *
 552  * @rdev: radeon_device pointer
 553  * @hpd: hpd (hotplug detect) pin
 554  *
 555  * Set the polarity of the hpd pin (r1xx-r4xx).
 556  */
 557 void r100_hpd_set_polarity(struct radeon_device *rdev,
 558                            enum radeon_hpd_id hpd)
 559 {
 560         u32 tmp;
 561         bool connected = r100_hpd_sense(rdev, hpd);
 562
 563         switch (hpd) {
 564         case RADEON_HPD_1:
 565                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 566                 if (connected)
 567                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 568                 else
 569                         tmp |= RADEON_FP_DETECT_INT_POL;
 570                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 571                 break;
 572         case RADEON_HPD_2:
 573                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 574                 if (connected)
 575                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 576                 else
 577                         tmp |= RADEON_FP2_DETECT_INT_POL;
 578                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 579                 break;
 580         default:
 581                 break;
 582         }
 583 }
 584
 585 /**
 586  * r100_hpd_init - hpd setup callback.
 587  *
 588  * @rdev: radeon_device pointer
 589  *
 590  * Setup the hpd pins used by the card (r1xx-r4xx).
 591  * Set the polarity, and enable the hpd interrupts.
 592  */
 593 void r100_hpd_init(struct radeon_device *rdev)
 594 {
 595         struct drm_device *dev = rdev->ddev;
 596         struct drm_connector *connector;
 597         unsigned enable = 0;
 598
 599         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 600                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 601                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 602                         enable |= 1 << radeon_connector->hpd.hpd;
 603                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 604         }
 605         radeon_irq_kms_enable_hpd(rdev, enable);
 606 }
 607
 608 /**
 609  * r100_hpd_fini - hpd tear down callback.
 610  *
 611  * @rdev: radeon_device pointer
 612  *
 613  * Tear down the hpd pins used by the card (r1xx-r4xx).
 614  * Disable the hpd interrupts.
 615  */
 616 void r100_hpd_fini(struct radeon_device *rdev)
 617 {
 618         struct drm_device *dev = rdev->ddev;
 619         struct drm_connector *connector;
 620         unsigned disable = 0;
 621
 622         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 623                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 624                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 625                         disable |= 1 << radeon_connector->hpd.hpd;
 626         }
 627         radeon_irq_kms_disable_hpd(rdev, disable);
 628 }
 629
 630 /*
 631  * PCI GART
 632  */
 633 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 634 {
 635         /* TODO: can we do somethings here ? */
 636         /* It seems hw only cache one entry so we should discard this
 637          * entry otherwise if first GPU GART read hit this entry it
 638          * could end up in wrong address. */
 639 }
 640
 641 int r100_pci_gart_init(struct radeon_device *rdev)
 642 {
 643         int r;
 644
 645         if (rdev->gart.ptr) {
 646                 WARN(1, "R100 PCI GART already initialized\n");
 647                 return 0;
 648         }
 649         /* Initialize common gart structure */
 650         r = radeon_gart_init(rdev);
 651         if (r)
 652                 return r;
 653         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 654         rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 655         rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
 656         rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 657         return radeon_gart_table_ram_alloc(rdev);
 658 }
 659
 660 int r100_pci_gart_enable(struct radeon_device *rdev)
 661 {
 662         uint32_t tmp;
 663
 664         /* discard memory request outside of configured range */
 665         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 666         WREG32(RADEON_AIC_CNTL, tmp);
 667         /* set address range for PCI address translate */
 668         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 669         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 670         /* set PCI GART page-table base address */
 671         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 672         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 673         WREG32(RADEON_AIC_CNTL, tmp);
 674         r100_pci_gart_tlb_flush(rdev);
 675         DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
 676                  (unsigned)(rdev->mc.gtt_size >> 20),
 677                  (unsigned long long)rdev->gart.table_addr);
 678         rdev->gart.ready = true;
 679         return 0;
 680 }
 681
 682 void r100_pci_gart_disable(struct radeon_device *rdev)
 683 {
 684         uint32_t tmp;
 685
 686         /* discard memory request outside of configured range */
 687         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 688         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 689         WREG32(RADEON_AIC_LO_ADDR, 0);
 690         WREG32(RADEON_AIC_HI_ADDR, 0);
 691 }
 692
 693 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
 694 {
 695         return addr;
 696 }
 697
 698 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
 699                             uint64_t entry)
 700 {
 701         u32 *gtt = rdev->gart.ptr;
 702         gtt[i] = cpu_to_le32(lower_32_bits(entry));
 703 }
 704
 705 void r100_pci_gart_fini(struct radeon_device *rdev)
 706 {
 707         radeon_gart_fini(rdev);
 708         r100_pci_gart_disable(rdev);
 709         radeon_gart_table_ram_free(rdev);
 710 }
 711
 712 int r100_irq_set(struct radeon_device *rdev)
 713 {
 714         uint32_t tmp = 0;
 715
 716         if (!rdev->irq.installed) {
 717                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 718                 WREG32(R_000040_GEN_INT_CNTL, 0);
 719                 return -EINVAL;
 720         }
 721         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 722                 tmp |= RADEON_SW_INT_ENABLE;
 723         }
 724         if (rdev->irq.crtc_vblank_int[0] ||
 725             atomic_read(&rdev->irq.pflip[0])) {
 726                 tmp |= RADEON_CRTC_VBLANK_MASK;
 727         }
 728         if (rdev->irq.crtc_vblank_int[1] ||
 729             atomic_read(&rdev->irq.pflip[1])) {
 730                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 731         }
 732         if (rdev->irq.hpd[0]) {
 733                 tmp |= RADEON_FP_DETECT_MASK;
 734         }
 735         if (rdev->irq.hpd[1]) {
 736                 tmp |= RADEON_FP2_DETECT_MASK;
 737         }
 738         WREG32(RADEON_GEN_INT_CNTL, tmp);
 739
 740         /* read back to post the write */
 741         RREG32(RADEON_GEN_INT_CNTL);
 742
 743         return 0;
 744 }
 745
 746 void r100_irq_disable(struct radeon_device *rdev)
 747 {
 748         u32 tmp;
 749
 750         WREG32(R_000040_GEN_INT_CNTL, 0);
 751         /* Wait and acknowledge irq */
 752         mdelay(1);
 753         tmp = RREG32(R_000044_GEN_INT_STATUS);
 754         WREG32(R_000044_GEN_INT_STATUS, tmp);
 755 }
 756
 757 static uint32_t r100_irq_ack(struct radeon_device *rdev)
 758 {
 759         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 760         uint32_t irq_mask = RADEON_SW_INT_TEST |
 761                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 762                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 763
 764         if (irqs) {
 765                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 766         }
 767         return irqs & irq_mask;
 768 }
 769
 770 int r100_irq_process(struct radeon_device *rdev)
 771 {
 772         uint32_t status, msi_rearm;
 773         bool queue_hotplug = false;
 774
 775         status = r100_irq_ack(rdev);
 776         if (!status) {
 777                 return IRQ_NONE;
 778         }
 779         if (rdev->shutdown) {
 780                 return IRQ_NONE;
 781         }
 782         while (status) {
 783                 /* SW interrupt */
 784                 if (status & RADEON_SW_INT_TEST) {
 785                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 786                 }
 787                 /* Vertical blank interrupts */
 788                 if (status & RADEON_CRTC_VBLANK_STAT) {
 789                         if (rdev->irq.crtc_vblank_int[0]) {
 790                                 drm_handle_vblank(rdev->ddev, 0);
 791                                 rdev->pm.vblank_sync = true;
 792                                 wake_up(&rdev->irq.vblank_queue);
 793                         }
 794                         if (atomic_read(&rdev->irq.pflip[0]))
 795                                 radeon_crtc_handle_vblank(rdev, 0);
 796                 }
 797                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 798                         if (rdev->irq.crtc_vblank_int[1]) {
 799                                 drm_handle_vblank(rdev->ddev, 1);
 800                                 rdev->pm.vblank_sync = true;
 801                                 wake_up(&rdev->irq.vblank_queue);
 802                         }
 803                         if (atomic_read(&rdev->irq.pflip[1]))
 804                                 radeon_crtc_handle_vblank(rdev, 1);
 805                 }
 806                 if (status & RADEON_FP_DETECT_STAT) {
 807                         queue_hotplug = true;
 808                         DRM_DEBUG("HPD1\n");
 809                 }
 810                 if (status & RADEON_FP2_DETECT_STAT) {
 811                         queue_hotplug = true;
 812                         DRM_DEBUG("HPD2\n");
 813                 }
 814                 status = r100_irq_ack(rdev);
 815         }
 816         if (queue_hotplug)
 817                 schedule_delayed_work(&rdev->hotplug_work, 0);
 818         if (rdev->msi_enabled) {
 819                 switch (rdev->family) {
 820                 case CHIP_RS400:
 821                 case CHIP_RS480:
 822                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 823                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 824                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 825                         break;
 826                 default:
 827                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 828                         break;
 829                 }
 830         }
 831         return IRQ_HANDLED;
 832 }
 833
 834 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 835 {
 836         if (crtc == 0)
 837                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 838         else
 839                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 840 }
 841
 842 /**
 843  * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
 844  * @rdev: radeon device structure
 845  * @ring: ring buffer struct for emitting packets
 846  */
 847 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
 848 {
 849         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 850         radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
 851                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 852         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 853         radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
 854 }
 855
 856 /* Who ever call radeon_fence_emit should call ring_lock and ask
 857  * for enough space (today caller are ib schedule and buffer move) */
 858 void r100_fence_ring_emit(struct radeon_device *rdev,
 859                           struct radeon_fence *fence)
 860 {
 861         struct radeon_ring *ring = &rdev->ring[fence->ring];
 862
 863         /* We have to make sure that caches are flushed before
 864          * CPU might read something from VRAM. */
 865         radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 866         radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
 867         radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 868         radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
 869         /* Wait until IDLE & CLEAN */
 870         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 871         radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 872         r100_ring_hdp_flush(rdev, ring);
 873         /* Emit fence sequence & fire IRQ */
 874         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 875         radeon_ring_write(ring, fence->seq);
 876         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 877         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 878 }
 879
 880 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
 881                               struct radeon_ring *ring,
 882                               struct radeon_semaphore *semaphore,
 883                               bool emit_wait)
 884 {
 885         /* Unused on older asics, since we don't have semaphores or multiple rings */
 886         BUG();
 887         return false;
 888 }
 889
 890 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
 891                                     uint64_t src_offset,
 892                                     uint64_t dst_offset,
 893                                     unsigned num_gpu_pages,
 894                                     struct dma_resv *resv)
 895 {
 896         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 897         struct radeon_fence *fence;
 898         uint32_t cur_pages;
 899         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 900         uint32_t pitch;
 901         uint32_t stride_pixels;
 902         unsigned ndw;
 903         int num_loops;
 904         int r = 0;
 905
 906         /* radeon limited to 16k stride */
 907         stride_bytes &= 0x3fff;
 908         /* radeon pitch is /64 */
 909         pitch = stride_bytes / 64;
 910         stride_pixels = stride_bytes / 4;
 911         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 912
 913         /* Ask for enough room for blit + flush + fence */
 914         ndw = 64 + (10 * num_loops);
 915         r = radeon_ring_lock(rdev, ring, ndw);
 916         if (r) {
 917                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 918                 return ERR_PTR(-EINVAL);
 919         }
 920         while (num_gpu_pages > 0) {
 921                 cur_pages = num_gpu_pages;
 922                 if (cur_pages > 8191) {
 923                         cur_pages = 8191;
 924                 }
 925                 num_gpu_pages -= cur_pages;
 926
 927                 /* pages are in Y direction - height
 928                    page width in X direction - width */
 929                 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
 930                 radeon_ring_write(ring,
 931                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 932                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 933                                   RADEON_GMC_SRC_CLIPPING |
 934                                   RADEON_GMC_DST_CLIPPING |
 935                                   RADEON_GMC_BRUSH_NONE |
 936                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 937                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 938                                   RADEON_ROP3_S |
 939                                   RADEON_DP_SRC_SOURCE_MEMORY |
 940                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 941                                   RADEON_GMC_WR_MSK_DIS);
 942                 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
 943                 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
 944                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 945                 radeon_ring_write(ring, 0);
 946                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 947                 radeon_ring_write(ring, num_gpu_pages);
 948                 radeon_ring_write(ring, num_gpu_pages);
 949                 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
 950         }
 951         radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 952         radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
 953         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 954         radeon_ring_write(ring,
 955                           RADEON_WAIT_2D_IDLECLEAN |
 956                           RADEON_WAIT_HOST_IDLECLEAN |
 957                           RADEON_WAIT_DMA_GUI_IDLE);
 958         r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
 959         if (r) {
 960                 radeon_ring_unlock_undo(rdev, ring);
 961                 return ERR_PTR(r);
 962         }
 963         radeon_ring_unlock_commit(rdev, ring, false);
 964         return fence;
 965 }
 966
 967 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 968 {
 969         unsigned i;
 970         u32 tmp;
 971
 972         for (i = 0; i < rdev->usec_timeout; i++) {
 973                 tmp = RREG32(R_000E40_RBBM_STATUS);
 974                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 975                         return 0;
 976                 }
 977                 udelay(1);
 978         }
 979         return -1;
 980 }
 981
 982 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 983 {
 984         int r;
 985
 986         r = radeon_ring_lock(rdev, ring, 2);
 987         if (r) {
 988                 return;
 989         }
 990         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 991         radeon_ring_write(ring,
 992                           RADEON_ISYNC_ANY2D_IDLE3D |
 993                           RADEON_ISYNC_ANY3D_IDLE2D |
 994                           RADEON_ISYNC_WAIT_IDLEGUI |
 995                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 996         radeon_ring_unlock_commit(rdev, ring, false);
 997 }
 998
 999
1000 /* Load the microcode for the CP */
1001 static int r100_cp_init_microcode(struct radeon_device *rdev)
1002 {
1003         const char *fw_name = NULL;
1004         int err;
1005
1006         DRM_DEBUG_KMS("\n");
1007
1008         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1009             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1010             (rdev->family == CHIP_RS200)) {
1011                 DRM_INFO("Loading R100 Microcode\n");
1012                 fw_name = FIRMWARE_R100;
1013         } else if ((rdev->family == CHIP_R200) ||
1014                    (rdev->family == CHIP_RV250) ||
1015                    (rdev->family == CHIP_RV280) ||
1016                    (rdev->family == CHIP_RS300)) {
1017                 DRM_INFO("Loading R200 Microcode\n");
1018                 fw_name = FIRMWARE_R200;
1019         } else if ((rdev->family == CHIP_R300) ||
1020                    (rdev->family == CHIP_R350) ||
1021                    (rdev->family == CHIP_RV350) ||
1022                    (rdev->family == CHIP_RV380) ||
1023                    (rdev->family == CHIP_RS400) ||
1024                    (rdev->family == CHIP_RS480)) {
1025                 DRM_INFO("Loading R300 Microcode\n");
1026                 fw_name = FIRMWARE_R300;
1027         } else if ((rdev->family == CHIP_R420) ||
1028                    (rdev->family == CHIP_R423) ||
1029                    (rdev->family == CHIP_RV410)) {
1030                 DRM_INFO("Loading R400 Microcode\n");
1031                 fw_name = FIRMWARE_R420;
1032         } else if ((rdev->family == CHIP_RS690) ||
1033                    (rdev->family == CHIP_RS740)) {
1034                 DRM_INFO("Loading RS690/RS740 Microcode\n");
1035                 fw_name = FIRMWARE_RS690;
1036         } else if (rdev->family == CHIP_RS600) {
1037                 DRM_INFO("Loading RS600 Microcode\n");
1038                 fw_name = FIRMWARE_RS600;
1039         } else if ((rdev->family == CHIP_RV515) ||
1040                    (rdev->family == CHIP_R520) ||
1041                    (rdev->family == CHIP_RV530) ||
1042                    (rdev->family == CHIP_R580) ||
1043                    (rdev->family == CHIP_RV560) ||
1044                    (rdev->family == CHIP_RV570)) {
1045                 DRM_INFO("Loading R500 Microcode\n");
1046                 fw_name = FIRMWARE_R520;
1047         }
1048
1049         err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1050         if (err) {
1051                 pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name);
1052         } else if (rdev->me_fw->size % 8) {
1053                 pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1054                        rdev->me_fw->size, fw_name);
1055                 err = -EINVAL;
1056                 release_firmware(rdev->me_fw);
1057                 rdev->me_fw = NULL;
1058         }
1059         return err;
1060 }
1061
1062 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1063                       struct radeon_ring *ring)
1064 {
1065         u32 rptr;
1066
1067         if (rdev->wb.enabled)
1068                 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1069         else
1070                 rptr = RREG32(RADEON_CP_RB_RPTR);
1071
1072         return rptr;
1073 }
1074
1075 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1076                       struct radeon_ring *ring)
1077 {
1078         return RREG32(RADEON_CP_RB_WPTR);
1079 }
1080
1081 void r100_gfx_set_wptr(struct radeon_device *rdev,
1082                        struct radeon_ring *ring)
1083 {
1084         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1085         (void)RREG32(RADEON_CP_RB_WPTR);
1086 }
1087
1088 static void r100_cp_load_microcode(struct radeon_device *rdev)
1089 {
1090         const __be32 *fw_data;
1091         int i, size;
1092
1093         if (r100_gui_wait_for_idle(rdev)) {
1094                 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1095         }
1096
1097         if (rdev->me_fw) {
1098                 size = rdev->me_fw->size / 4;
1099                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1100                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1101                 for (i = 0; i < size; i += 2) {
1102                         WREG32(RADEON_CP_ME_RAM_DATAH,
1103                                be32_to_cpup(&fw_data[i]));
1104                         WREG32(RADEON_CP_ME_RAM_DATAL,
1105                                be32_to_cpup(&fw_data[i + 1]));
1106                 }
1107         }
1108 }
1109
1110 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1111 {
1112         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1113         unsigned rb_bufsz;
1114         unsigned rb_blksz;
1115         unsigned max_fetch;
1116         unsigned pre_write_timer;
1117         unsigned pre_write_limit;
1118         unsigned indirect2_start;
1119         unsigned indirect1_start;
1120         uint32_t tmp;
1121         int r;
1122
1123         r100_debugfs_cp_init(rdev);
1124         if (!rdev->me_fw) {
1125                 r = r100_cp_init_microcode(rdev);
1126                 if (r) {
1127                         DRM_ERROR("Failed to load firmware!\n");
1128                         return r;
1129                 }
1130         }
1131
1132         /* Align ring size */
1133         rb_bufsz = order_base_2(ring_size / 8);
1134         ring_size = (1 << (rb_bufsz + 1)) * 4;
1135         r100_cp_load_microcode(rdev);
1136         r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1137                              RADEON_CP_PACKET2);
1138         if (r) {
1139                 return r;
1140         }
1141         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1142          * the rptr copy in system ram */
1143         rb_blksz = 9;
1144         /* cp will read 128bytes at a time (4 dwords) */
1145         max_fetch = 1;
1146         ring->align_mask = 16 - 1;
1147         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1148         pre_write_timer = 64;
1149         /* Force CP_RB_WPTR write if written more than one time before the
1150          * delay expire
1151          */
1152         pre_write_limit = 0;
1153         /* Setup the cp cache like this (cache size is 96 dwords) :
1154          *      RING            0  to 15
1155          *      INDIRECT1       16 to 79
1156          *      INDIRECT2       80 to 95
1157          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1158          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1159          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1160          * Idea being that most of the gpu cmd will be through indirect1 buffer
1161          * so it gets the bigger cache.
1162          */
1163         indirect2_start = 80;
1164         indirect1_start = 16;
1165         /* cp setup */
1166         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1167         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1168                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1169                REG_SET(RADEON_MAX_FETCH, max_fetch));
1170 #ifdef __BIG_ENDIAN
1171         tmp |= RADEON_BUF_SWAP_32BIT;
1172 #endif
1173         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1174
1175         /* Set ring address */
1176         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1177         WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1178         /* Force read & write ptr to 0 */
1179         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1180         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1181         ring->wptr = 0;
1182         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1183
1184         /* set the wb address whether it's enabled or not */
1185         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1186                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1187         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1188
1189         if (rdev->wb.enabled)
1190                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1191         else {
1192                 tmp |= RADEON_RB_NO_UPDATE;
1193                 WREG32(R_000770_SCRATCH_UMSK, 0);
1194         }
1195
1196         WREG32(RADEON_CP_RB_CNTL, tmp);
1197         udelay(10);
1198         /* Set cp mode to bus mastering & enable cp*/
1199         WREG32(RADEON_CP_CSQ_MODE,
1200                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1201                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1202         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1203         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1204         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1205
1206         /* at this point everything should be setup correctly to enable master */
1207         pci_set_master(rdev->pdev);
1208
1209         radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1210         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1211         if (r) {
1212                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1213                 return r;
1214         }
1215         ring->ready = true;
1216         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1217
1218         if (!ring->rptr_save_reg /* not resuming from suspend */
1219             && radeon_ring_supports_scratch_reg(rdev, ring)) {
1220                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1221                 if (r) {
1222                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1223                         ring->rptr_save_reg = 0;
1224                 }
1225         }
1226         return 0;
1227 }
1228
1229 void r100_cp_fini(struct radeon_device *rdev)
1230 {
1231         if (r100_cp_wait_for_idle(rdev)) {
1232                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1233         }
1234         /* Disable ring */
1235         r100_cp_disable(rdev);
1236         radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1237         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1238         DRM_INFO("radeon: cp finalized\n");
1239 }
1240
1241 void r100_cp_disable(struct radeon_device *rdev)
1242 {
1243         /* Disable ring */
1244         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1245         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1246         WREG32(RADEON_CP_CSQ_MODE, 0);
1247         WREG32(RADEON_CP_CSQ_CNTL, 0);
1248         WREG32(R_000770_SCRATCH_UMSK, 0);
1249         if (r100_gui_wait_for_idle(rdev)) {
1250                 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1251         }
1252 }
1253
1254 /*
1255  * CS functions
1256  */
1257 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1258                             struct radeon_cs_packet *pkt,
1259                             unsigned idx,
1260                             unsigned reg)
1261 {
1262         int r;
1263         u32 tile_flags = 0;
1264         u32 tmp;
1265         struct radeon_bo_list *reloc;
1266         u32 value;
1267
1268         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1269         if (r) {
1270                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1271                           idx, reg);
1272                 radeon_cs_dump_packet(p, pkt);
1273                 return r;
1274         }
1275
1276         value = radeon_get_ib_value(p, idx);
1277         tmp = value & 0x003fffff;
1278         tmp += (((u32)reloc->gpu_offset) >> 10);
1279
1280         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1281                 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1282                         tile_flags |= RADEON_DST_TILE_MACRO;
1283                 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1284                         if (reg == RADEON_SRC_PITCH_OFFSET) {
1285                                 DRM_ERROR("Cannot src blit from microtiled surface\n");
1286                                 radeon_cs_dump_packet(p, pkt);
1287                                 return -EINVAL;
1288                         }
1289                         tile_flags |= RADEON_DST_TILE_MICRO;
1290                 }
1291
1292                 tmp |= tile_flags;
1293                 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1294         } else
1295                 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1296         return 0;
1297 }
1298
1299 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1300                              struct radeon_cs_packet *pkt,
1301                              int idx)
1302 {
1303         unsigned c, i;
1304         struct radeon_bo_list *reloc;
1305         struct r100_cs_track *track;
1306         int r = 0;
1307         volatile uint32_t *ib;
1308         u32 idx_value;
1309
1310         ib = p->ib.ptr;
1311         track = (struct r100_cs_track *)p->track;
1312         c = radeon_get_ib_value(p, idx++) & 0x1F;
1313         if (c > 16) {
1314             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1315                       pkt->opcode);
1316             radeon_cs_dump_packet(p, pkt);
1317             return -EINVAL;
1318         }
1319         track->num_arrays = c;
1320         for (i = 0; i < (c - 1); i+=2, idx+=3) {
1321                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1322                 if (r) {
1323                         DRM_ERROR("No reloc for packet3 %d\n",
1324                                   pkt->opcode);
1325                         radeon_cs_dump_packet(p, pkt);
1326                         return r;
1327                 }
1328                 idx_value = radeon_get_ib_value(p, idx);
1329                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1330
1331                 track->arrays[i + 0].esize = idx_value >> 8;
1332                 track->arrays[i + 0].robj = reloc->robj;
1333                 track->arrays[i + 0].esize &= 0x7F;
1334                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1335                 if (r) {
1336                         DRM_ERROR("No reloc for packet3 %d\n",
1337                                   pkt->opcode);
1338                         radeon_cs_dump_packet(p, pkt);
1339                         return r;
1340                 }
1341                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1342                 track->arrays[i + 1].robj = reloc->robj;
1343                 track->arrays[i + 1].esize = idx_value >> 24;
1344                 track->arrays[i + 1].esize &= 0x7F;
1345         }
1346         if (c & 1) {
1347                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1348                 if (r) {
1349                         DRM_ERROR("No reloc for packet3 %d\n",
1350                                           pkt->opcode);
1351                         radeon_cs_dump_packet(p, pkt);
1352                         return r;
1353                 }
1354                 idx_value = radeon_get_ib_value(p, idx);
1355                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1356                 track->arrays[i + 0].robj = reloc->robj;
1357                 track->arrays[i + 0].esize = idx_value >> 8;
1358                 track->arrays[i + 0].esize &= 0x7F;
1359         }
1360         return r;
1361 }
1362
1363 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1364                           struct radeon_cs_packet *pkt,
1365                           const unsigned *auth, unsigned n,
1366                           radeon_packet0_check_t check)
1367 {
1368         unsigned reg;
1369         unsigned i, j, m;
1370         unsigned idx;
1371         int r;
1372
1373         idx = pkt->idx + 1;
1374         reg = pkt->reg;
1375         /* Check that register fall into register range
1376          * determined by the number of entry (n) in the
1377          * safe register bitmap.
1378          */
1379         if (pkt->one_reg_wr) {
1380                 if ((reg >> 7) > n) {
1381                         return -EINVAL;
1382                 }
1383         } else {
1384                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1385                         return -EINVAL;
1386                 }
1387         }
1388         for (i = 0; i <= pkt->count; i++, idx++) {
1389                 j = (reg >> 7);
1390                 m = 1 << ((reg >> 2) & 31);
1391                 if (auth[j] & m) {
1392                         r = check(p, pkt, idx, reg);
1393                         if (r) {
1394                                 return r;
1395                         }
1396                 }
1397                 if (pkt->one_reg_wr) {
1398                         if (!(auth[j] & m)) {
1399                                 break;
1400                         }
1401                 } else {
1402                         reg += 4;
1403                 }
1404         }
1405         return 0;
1406 }
1407
1408 /**
1409  * r100_cs_packet_parse_vline() - parse userspace VLINE packet
1410  * @p:          parser structure holding parsing context.
1411  *
1412  * Userspace sends a special sequence for VLINE waits.
1413  * PACKET0 - VLINE_START_END + value
1414  * PACKET0 - WAIT_UNTIL +_value
1415  * RELOC (P3) - crtc_id in reloc.
1416  *
1417  * This function parses this and relocates the VLINE START END
1418  * and WAIT UNTIL packets to the correct crtc.
1419  * It also detects a switched off crtc and nulls out the
1420  * wait in that case.
1421  */
1422 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1423 {
1424         struct drm_crtc *crtc;
1425         struct radeon_crtc *radeon_crtc;
1426         struct radeon_cs_packet p3reloc, waitreloc;
1427         int crtc_id;
1428         int r;
1429         uint32_t header, h_idx, reg;
1430         volatile uint32_t *ib;
1431
1432         ib = p->ib.ptr;
1433
1434         /* parse the wait until */
1435         r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1436         if (r)
1437                 return r;
1438
1439         /* check its a wait until and only 1 count */
1440         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1441             waitreloc.count != 0) {
1442                 DRM_ERROR("vline wait had illegal wait until segment\n");
1443                 return -EINVAL;
1444         }
1445
1446         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1447                 DRM_ERROR("vline wait had illegal wait until\n");
1448                 return -EINVAL;
1449         }
1450
1451         /* jump over the NOP */
1452         r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1453         if (r)
1454                 return r;
1455
1456         h_idx = p->idx - 2;
1457         p->idx += waitreloc.count + 2;
1458         p->idx += p3reloc.count + 2;
1459
1460         header = radeon_get_ib_value(p, h_idx);
1461         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1462         reg = R100_CP_PACKET0_GET_REG(header);
1463         crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
1464         if (!crtc) {
1465                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1466                 return -ENOENT;
1467         }
1468         radeon_crtc = to_radeon_crtc(crtc);
1469         crtc_id = radeon_crtc->crtc_id;
1470
1471         if (!crtc->enabled) {
1472                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1473                 ib[h_idx + 2] = PACKET2(0);
1474                 ib[h_idx + 3] = PACKET2(0);
1475         } else if (crtc_id == 1) {
1476                 switch (reg) {
1477                 case AVIVO_D1MODE_VLINE_START_END:
1478                         header &= ~R300_CP_PACKET0_REG_MASK;
1479                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1480                         break;
1481                 case RADEON_CRTC_GUI_TRIG_VLINE:
1482                         header &= ~R300_CP_PACKET0_REG_MASK;
1483                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1484                         break;
1485                 default:
1486                         DRM_ERROR("unknown crtc reloc\n");
1487                         return -EINVAL;
1488                 }
1489                 ib[h_idx] = header;
1490                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1491         }
1492
1493         return 0;
1494 }
1495
1496 static int r100_get_vtx_size(uint32_t vtx_fmt)
1497 {
1498         int vtx_size;
1499         vtx_size = 2;
1500         /* ordered according to bits in spec */
1501         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1502                 vtx_size++;
1503         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1504                 vtx_size += 3;
1505         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1506                 vtx_size++;
1507         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1508                 vtx_size++;
1509         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1510                 vtx_size += 3;
1511         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1512                 vtx_size++;
1513         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1514                 vtx_size++;
1515         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1516                 vtx_size += 2;
1517         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1518                 vtx_size += 2;
1519         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1520                 vtx_size++;
1521         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1522                 vtx_size += 2;
1523         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1524                 vtx_size++;
1525         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1526                 vtx_size += 2;
1527         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1528                 vtx_size++;
1529         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1530                 vtx_size++;
1531         /* blend weight */
1532         if (vtx_fmt & (0x7 << 15))
1533                 vtx_size += (vtx_fmt >> 15) & 0x7;
1534         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1535                 vtx_size += 3;
1536         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1537                 vtx_size += 2;
1538         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1539                 vtx_size++;
1540         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1541                 vtx_size++;
1542         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1543                 vtx_size++;
1544         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1545                 vtx_size++;
1546         return vtx_size;
1547 }
1548
1549 static int r100_packet0_check(struct radeon_cs_parser *p,
1550                               struct radeon_cs_packet *pkt,
1551                               unsigned idx, unsigned reg)
1552 {
1553         struct radeon_bo_list *reloc;
1554         struct r100_cs_track *track;
1555         volatile uint32_t *ib;
1556         uint32_t tmp;
1557         int r;
1558         int i, face;
1559         u32 tile_flags = 0;
1560         u32 idx_value;
1561
1562         ib = p->ib.ptr;
1563         track = (struct r100_cs_track *)p->track;
1564
1565         idx_value = radeon_get_ib_value(p, idx);
1566
1567         switch (reg) {
1568         case RADEON_CRTC_GUI_TRIG_VLINE:
1569                 r = r100_cs_packet_parse_vline(p);
1570                 if (r) {
1571                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1572                                   idx, reg);
1573                         radeon_cs_dump_packet(p, pkt);
1574                         return r;
1575                 }
1576                 break;
1577                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1578                  * range access */
1579         case RADEON_DST_PITCH_OFFSET:
1580         case RADEON_SRC_PITCH_OFFSET:
1581                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1582                 if (r)
1583                         return r;
1584                 break;
1585         case RADEON_RB3D_DEPTHOFFSET:
1586                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1587                 if (r) {
1588                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1589                                   idx, reg);
1590                         radeon_cs_dump_packet(p, pkt);
1591                         return r;
1592                 }
1593                 track->zb.robj = reloc->robj;
1594                 track->zb.offset = idx_value;
1595                 track->zb_dirty = true;
1596                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1597                 break;
1598         case RADEON_RB3D_COLOROFFSET:
1599                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1600                 if (r) {
1601                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1602                                   idx, reg);
1603                         radeon_cs_dump_packet(p, pkt);
1604                         return r;
1605                 }
1606                 track->cb[0].robj = reloc->robj;
1607                 track->cb[0].offset = idx_value;
1608                 track->cb_dirty = true;
1609                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1610                 break;
1611         case RADEON_PP_TXOFFSET_0:
1612         case RADEON_PP_TXOFFSET_1:
1613         case RADEON_PP_TXOFFSET_2:
1614                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1615                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1616                 if (r) {
1617                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1618                                   idx, reg);
1619                         radeon_cs_dump_packet(p, pkt);
1620                         return r;
1621                 }
1622                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1623                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
1624                                 tile_flags |= RADEON_TXO_MACRO_TILE;
1625                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
1626                                 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1627
1628                         tmp = idx_value & ~(0x7 << 2);
1629                         tmp |= tile_flags;
1630                         ib[idx] = tmp + ((u32)reloc->gpu_offset);
1631                 } else
1632                         ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1633                 track->textures[i].robj = reloc->robj;
1634                 track->tex_dirty = true;
1635                 break;
1636         case RADEON_PP_CUBIC_OFFSET_T0_0:
1637         case RADEON_PP_CUBIC_OFFSET_T0_1:
1638         case RADEON_PP_CUBIC_OFFSET_T0_2:
1639         case RADEON_PP_CUBIC_OFFSET_T0_3:
1640         case RADEON_PP_CUBIC_OFFSET_T0_4:
1641                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1642                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1643                 if (r) {
1644                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1645                                   idx, reg);
1646                         radeon_cs_dump_packet(p, pkt);
1647                         return r;
1648                 }
1649                 track->textures[0].cube_info[i].offset = idx_value;
1650                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1651                 track->textures[0].cube_info[i].robj = reloc->robj;
1652                 track->tex_dirty = true;
1653                 break;
1654         case RADEON_PP_CUBIC_OFFSET_T1_0:
1655         case RADEON_PP_CUBIC_OFFSET_T1_1:
1656         case RADEON_PP_CUBIC_OFFSET_T1_2:
1657         case RADEON_PP_CUBIC_OFFSET_T1_3:
1658         case RADEON_PP_CUBIC_OFFSET_T1_4:
1659                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1660                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1661                 if (r) {
1662                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1663                                   idx, reg);
1664                         radeon_cs_dump_packet(p, pkt);
1665                         return r;
1666                 }
1667                 track->textures[1].cube_info[i].offset = idx_value;
1668                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1669                 track->textures[1].cube_info[i].robj = reloc->robj;
1670                 track->tex_dirty = true;
1671                 break;
1672         case RADEON_PP_CUBIC_OFFSET_T2_0:
1673         case RADEON_PP_CUBIC_OFFSET_T2_1:
1674         case RADEON_PP_CUBIC_OFFSET_T2_2:
1675         case RADEON_PP_CUBIC_OFFSET_T2_3:
1676         case RADEON_PP_CUBIC_OFFSET_T2_4:
1677                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1678                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1679                 if (r) {
1680                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1681                                   idx, reg);
1682                         radeon_cs_dump_packet(p, pkt);
1683                         return r;
1684                 }
1685                 track->textures[2].cube_info[i].offset = idx_value;
1686                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1687                 track->textures[2].cube_info[i].robj = reloc->robj;
1688                 track->tex_dirty = true;
1689                 break;
1690         case RADEON_RE_WIDTH_HEIGHT:
1691                 track->maxy = ((idx_value >> 16) & 0x7FF);
1692                 track->cb_dirty = true;
1693                 track->zb_dirty = true;
1694                 break;
1695         case RADEON_RB3D_COLORPITCH:
1696                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1697                 if (r) {
1698                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1699                                   idx, reg);
1700                         radeon_cs_dump_packet(p, pkt);
1701                         return r;
1702                 }
1703                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1704                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
1705                                 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1706                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
1707                                 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1708
1709                         tmp = idx_value & ~(0x7 << 16);
1710                         tmp |= tile_flags;
1711                         ib[idx] = tmp;
1712                 } else
1713                         ib[idx] = idx_value;
1714
1715                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1716                 track->cb_dirty = true;
1717                 break;
1718         case RADEON_RB3D_DEPTHPITCH:
1719                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1720                 track->zb_dirty = true;
1721                 break;
1722         case RADEON_RB3D_CNTL:
1723                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1724                 case 7:
1725                 case 8:
1726                 case 9:
1727                 case 11:
1728                 case 12:
1729                         track->cb[0].cpp = 1;
1730                         break;
1731                 case 3:
1732                 case 4:
1733                 case 15:
1734                         track->cb[0].cpp = 2;
1735                         break;
1736                 case 6:
1737                         track->cb[0].cpp = 4;
1738                         break;
1739                 default:
1740                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1741                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1742                         return -EINVAL;
1743                 }
1744                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1745                 track->cb_dirty = true;
1746                 track->zb_dirty = true;
1747                 break;
1748         case RADEON_RB3D_ZSTENCILCNTL:
1749                 switch (idx_value & 0xf) {
1750                 case 0:
1751                         track->zb.cpp = 2;
1752                         break;
1753                 case 2:
1754                 case 3:
1755                 case 4:
1756                 case 5:
1757                 case 9:
1758                 case 11:
1759                         track->zb.cpp = 4;
1760                         break;
1761                 default:
1762                         break;
1763                 }
1764                 track->zb_dirty = true;
1765                 break;
1766         case RADEON_RB3D_ZPASS_ADDR:
1767                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1768                 if (r) {
1769                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1770                                   idx, reg);
1771                         radeon_cs_dump_packet(p, pkt);
1772                         return r;
1773                 }
1774                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1775                 break;
1776         case RADEON_PP_CNTL:
1777                 {
1778                         uint32_t temp = idx_value >> 4;
1779                         for (i = 0; i < track->num_texture; i++)
1780                                 track->textures[i].enabled = !!(temp & (1 << i));
1781                         track->tex_dirty = true;
1782                 }
1783                 break;
1784         case RADEON_SE_VF_CNTL:
1785                 track->vap_vf_cntl = idx_value;
1786                 break;
1787         case RADEON_SE_VTX_FMT:
1788                 track->vtx_size = r100_get_vtx_size(idx_value);
1789                 break;
1790         case RADEON_PP_TEX_SIZE_0:
1791         case RADEON_PP_TEX_SIZE_1:
1792         case RADEON_PP_TEX_SIZE_2:
1793                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1794                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1795                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1796                 track->tex_dirty = true;
1797                 break;
1798         case RADEON_PP_TEX_PITCH_0:
1799         case RADEON_PP_TEX_PITCH_1:
1800         case RADEON_PP_TEX_PITCH_2:
1801                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1802                 track->textures[i].pitch = idx_value + 32;
1803                 track->tex_dirty = true;
1804                 break;
1805         case RADEON_PP_TXFILTER_0:
1806         case RADEON_PP_TXFILTER_1:
1807         case RADEON_PP_TXFILTER_2:
1808                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1809                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1810                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1811                 tmp = (idx_value >> 23) & 0x7;
1812                 if (tmp == 2 || tmp == 6)
1813                         track->textures[i].roundup_w = false;
1814                 tmp = (idx_value >> 27) & 0x7;
1815                 if (tmp == 2 || tmp == 6)
1816                         track->textures[i].roundup_h = false;
1817                 track->tex_dirty = true;
1818                 break;
1819         case RADEON_PP_TXFORMAT_0:
1820         case RADEON_PP_TXFORMAT_1:
1821         case RADEON_PP_TXFORMAT_2:
1822                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1823                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1824                         track->textures[i].use_pitch = true;
1825                 } else {
1826                         track->textures[i].use_pitch = false;
1827                         track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
1828                         track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
1829                 }
1830                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1831                         track->textures[i].tex_coord_type = 2;
1832                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1833                 case RADEON_TXFORMAT_I8:
1834                 case RADEON_TXFORMAT_RGB332:
1835                 case RADEON_TXFORMAT_Y8:
1836                         track->textures[i].cpp = 1;
1837                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1838                         break;
1839                 case RADEON_TXFORMAT_AI88:
1840                 case RADEON_TXFORMAT_ARGB1555:
1841                 case RADEON_TXFORMAT_RGB565:
1842                 case RADEON_TXFORMAT_ARGB4444:
1843                 case RADEON_TXFORMAT_VYUY422:
1844                 case RADEON_TXFORMAT_YVYU422:
1845                 case RADEON_TXFORMAT_SHADOW16:
1846                 case RADEON_TXFORMAT_LDUDV655:
1847                 case RADEON_TXFORMAT_DUDV88:
1848                         track->textures[i].cpp = 2;
1849                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1850                         break;
1851                 case RADEON_TXFORMAT_ARGB8888:
1852                 case RADEON_TXFORMAT_RGBA8888:
1853                 case RADEON_TXFORMAT_SHADOW32:
1854                 case RADEON_TXFORMAT_LDUDUV8888:
1855                         track->textures[i].cpp = 4;
1856                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1857                         break;
1858                 case RADEON_TXFORMAT_DXT1:
1859                         track->textures[i].cpp = 1;
1860                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1861                         break;
1862                 case RADEON_TXFORMAT_DXT23:
1863                 case RADEON_TXFORMAT_DXT45:
1864                         track->textures[i].cpp = 1;
1865                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1866                         break;
1867                 }
1868                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1869                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1870                 track->tex_dirty = true;
1871                 break;
1872         case RADEON_PP_CUBIC_FACES_0:
1873         case RADEON_PP_CUBIC_FACES_1:
1874         case RADEON_PP_CUBIC_FACES_2:
1875                 tmp = idx_value;
1876                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1877                 for (face = 0; face < 4; face++) {
1878                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1879                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1880                 }
1881                 track->tex_dirty = true;
1882                 break;
1883         default:
1884                 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
1885                 return -EINVAL;
1886         }
1887         return 0;
1888 }
1889
1890 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1891                                          struct radeon_cs_packet *pkt,
1892                                          struct radeon_bo *robj)
1893 {
1894         unsigned idx;
1895         u32 value;
1896         idx = pkt->idx + 1;
1897         value = radeon_get_ib_value(p, idx + 2);
1898         if ((value + 1) > radeon_bo_size(robj)) {
1899                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1900                           "(need %u have %lu) !\n",
1901                           value + 1,
1902                           radeon_bo_size(robj));
1903                 return -EINVAL;
1904         }
1905         return 0;
1906 }
1907
1908 static int r100_packet3_check(struct radeon_cs_parser *p,
1909                               struct radeon_cs_packet *pkt)
1910 {
1911         struct radeon_bo_list *reloc;
1912         struct r100_cs_track *track;
1913         unsigned idx;
1914         volatile uint32_t *ib;
1915         int r;
1916
1917         ib = p->ib.ptr;
1918         idx = pkt->idx + 1;
1919         track = (struct r100_cs_track *)p->track;
1920         switch (pkt->opcode) {
1921         case PACKET3_3D_LOAD_VBPNTR:
1922                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1923                 if (r)
1924                         return r;
1925                 break;
1926         case PACKET3_INDX_BUFFER:
1927                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1928                 if (r) {
1929                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1930                         radeon_cs_dump_packet(p, pkt);
1931                         return r;
1932                 }
1933                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1934                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1935                 if (r) {
1936                         return r;
1937                 }
1938                 break;
1939         case 0x23:
1940                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1941                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1942                 if (r) {
1943                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1944                         radeon_cs_dump_packet(p, pkt);
1945                         return r;
1946                 }
1947                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1948                 track->num_arrays = 1;
1949                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1950
1951                 track->arrays[0].robj = reloc->robj;
1952                 track->arrays[0].esize = track->vtx_size;
1953
1954                 track->max_indx = radeon_get_ib_value(p, idx+1);
1955
1956                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1957                 track->immd_dwords = pkt->count - 1;
1958                 r = r100_cs_track_check(p->rdev, track);
1959                 if (r)
1960                         return r;
1961                 break;
1962         case PACKET3_3D_DRAW_IMMD:
1963                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1964                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1965                         return -EINVAL;
1966                 }
1967                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1968                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1969                 track->immd_dwords = pkt->count - 1;
1970                 r = r100_cs_track_check(p->rdev, track);
1971                 if (r)
1972                         return r;
1973                 break;
1974                 /* triggers drawing using in-packet vertex data */
1975         case PACKET3_3D_DRAW_IMMD_2:
1976                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1977                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1978                         return -EINVAL;
1979                 }
1980                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1981                 track->immd_dwords = pkt->count;
1982                 r = r100_cs_track_check(p->rdev, track);
1983                 if (r)
1984                         return r;
1985                 break;
1986                 /* triggers drawing using in-packet vertex data */
1987         case PACKET3_3D_DRAW_VBUF_2:
1988                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1989                 r = r100_cs_track_check(p->rdev, track);
1990                 if (r)
1991                         return r;
1992                 break;
1993                 /* triggers drawing of vertex buffers setup elsewhere */
1994         case PACKET3_3D_DRAW_INDX_2:
1995                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1996                 r = r100_cs_track_check(p->rdev, track);
1997                 if (r)
1998                         return r;
1999                 break;
2000                 /* triggers drawing using indices to vertex buffer */
2001         case PACKET3_3D_DRAW_VBUF:
2002                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2003                 r = r100_cs_track_check(p->rdev, track);
2004                 if (r)
2005                         return r;
2006                 break;
2007                 /* triggers drawing of vertex buffers setup elsewhere */
2008         case PACKET3_3D_DRAW_INDX:
2009                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2010                 r = r100_cs_track_check(p->rdev, track);
2011                 if (r)
2012                         return r;
2013                 break;
2014                 /* triggers drawing using indices to vertex buffer */
2015         case PACKET3_3D_CLEAR_HIZ:
2016         case PACKET3_3D_CLEAR_ZMASK:
2017                 if (p->rdev->hyperz_filp != p->filp)
2018                         return -EINVAL;
2019                 break;
2020         case PACKET3_NOP:
2021                 break;
2022         default:
2023                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2024                 return -EINVAL;
2025         }
2026         return 0;
2027 }
2028
2029 int r100_cs_parse(struct radeon_cs_parser *p)
2030 {
2031         struct radeon_cs_packet pkt;
2032         struct r100_cs_track *track;
2033         int r;
2034
2035         track = kzalloc(sizeof(*track), GFP_KERNEL);
2036         if (!track)
2037                 return -ENOMEM;
2038         r100_cs_track_clear(p->rdev, track);
2039         p->track = track;
2040         do {
2041                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2042                 if (r) {
2043                         return r;
2044                 }
2045                 p->idx += pkt.count + 2;
2046                 switch (pkt.type) {
2047                 case RADEON_PACKET_TYPE0:
2048                         if (p->rdev->family >= CHIP_R200)
2049                                 r = r100_cs_parse_packet0(p, &pkt,
2050                                         p->rdev->config.r100.reg_safe_bm,
2051                                         p->rdev->config.r100.reg_safe_bm_size,
2052                                         &r200_packet0_check);
2053                         else
2054                                 r = r100_cs_parse_packet0(p, &pkt,
2055                                         p->rdev->config.r100.reg_safe_bm,
2056                                         p->rdev->config.r100.reg_safe_bm_size,
2057                                         &r100_packet0_check);
2058                         break;
2059                 case RADEON_PACKET_TYPE2:
2060                         break;
2061                 case RADEON_PACKET_TYPE3:
2062                         r = r100_packet3_check(p, &pkt);
2063                         break;
2064                 default:
2065                         DRM_ERROR("Unknown packet type %d !\n",
2066                                   pkt.type);
2067                         return -EINVAL;
2068                 }
2069                 if (r)
2070                         return r;
2071         } while (p->idx < p->chunk_ib->length_dw);
2072         return 0;
2073 }
2074
2075 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2076 {
2077         DRM_ERROR("pitch                      %d\n", t->pitch);
2078         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2079         DRM_ERROR("width                      %d\n", t->width);
2080         DRM_ERROR("width_11                   %d\n", t->width_11);
2081         DRM_ERROR("height                     %d\n", t->height);
2082         DRM_ERROR("height_11                  %d\n", t->height_11);
2083         DRM_ERROR("num levels                 %d\n", t->num_levels);
2084         DRM_ERROR("depth                      %d\n", t->txdepth);
2085         DRM_ERROR("bpp                        %d\n", t->cpp);
2086         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2087         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2088         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2089         DRM_ERROR("compress format            %d\n", t->compress_format);
2090 }
2091
2092 static int r100_track_compress_size(int compress_format, int w, int h)
2093 {
2094         int block_width, block_height, block_bytes;
2095         int wblocks, hblocks;
2096         int min_wblocks;
2097         int sz;
2098
2099         block_width = 4;
2100         block_height = 4;
2101
2102         switch (compress_format) {
2103         case R100_TRACK_COMP_DXT1:
2104                 block_bytes = 8;
2105                 min_wblocks = 4;
2106                 break;
2107         default:
2108         case R100_TRACK_COMP_DXT35:
2109                 block_bytes = 16;
2110                 min_wblocks = 2;
2111                 break;
2112         }
2113
2114         hblocks = (h + block_height - 1) / block_height;
2115         wblocks = (w + block_width - 1) / block_width;
2116         if (wblocks < min_wblocks)
2117                 wblocks = min_wblocks;
2118         sz = wblocks * hblocks * block_bytes;
2119         return sz;
2120 }
2121
2122 static int r100_cs_track_cube(struct radeon_device *rdev,
2123                               struct r100_cs_track *track, unsigned idx)
2124 {
2125         unsigned face, w, h;
2126         struct radeon_bo *cube_robj;
2127         unsigned long size;
2128         unsigned compress_format = track->textures[idx].compress_format;
2129
2130         for (face = 0; face < 5; face++) {
2131                 cube_robj = track->textures[idx].cube_info[face].robj;
2132                 w = track->textures[idx].cube_info[face].width;
2133                 h = track->textures[idx].cube_info[face].height;
2134
2135                 if (compress_format) {
2136                         size = r100_track_compress_size(compress_format, w, h);
2137                 } else
2138                         size = w * h;
2139                 size *= track->textures[idx].cpp;
2140
2141                 size += track->textures[idx].cube_info[face].offset;
2142
2143                 if (size > radeon_bo_size(cube_robj)) {
2144                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2145                                   size, radeon_bo_size(cube_robj));
2146                         r100_cs_track_texture_print(&track->textures[idx]);
2147                         return -1;
2148                 }
2149         }
2150         return 0;
2151 }
2152
2153 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2154                                        struct r100_cs_track *track)
2155 {
2156         struct radeon_bo *robj;
2157         unsigned long size;
2158         unsigned u, i, w, h, d;
2159         int ret;
2160
2161         for (u = 0; u < track->num_texture; u++) {
2162                 if (!track->textures[u].enabled)
2163                         continue;
2164                 if (track->textures[u].lookup_disable)
2165                         continue;
2166                 robj = track->textures[u].robj;
2167                 if (robj == NULL) {
2168                         DRM_ERROR("No texture bound to unit %u\n", u);
2169                         return -EINVAL;
2170                 }
2171                 size = 0;
2172                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2173                         if (track->textures[u].use_pitch) {
2174                                 if (rdev->family < CHIP_R300)
2175                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2176                                 else
2177                                         w = track->textures[u].pitch / (1 << i);
2178                         } else {
2179                                 w = track->textures[u].width;
2180                                 if (rdev->family >= CHIP_RV515)
2181                                         w |= track->textures[u].width_11;
2182                                 w = w / (1 << i);
2183                                 if (track->textures[u].roundup_w)
2184                                         w = roundup_pow_of_two(w);
2185                         }
2186                         h = track->textures[u].height;
2187                         if (rdev->family >= CHIP_RV515)
2188                                 h |= track->textures[u].height_11;
2189                         h = h / (1 << i);
2190                         if (track->textures[u].roundup_h)
2191                                 h = roundup_pow_of_two(h);
2192                         if (track->textures[u].tex_coord_type == 1) {
2193                                 d = (1 << track->textures[u].txdepth) / (1 << i);
2194                                 if (!d)
2195                                         d = 1;
2196                         } else {
2197                                 d = 1;
2198                         }
2199                         if (track->textures[u].compress_format) {
2200
2201                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2202                                 /* compressed textures are block based */
2203                         } else
2204                                 size += w * h * d;
2205                 }
2206                 size *= track->textures[u].cpp;
2207
2208                 switch (track->textures[u].tex_coord_type) {
2209                 case 0:
2210                 case 1:
2211                         break;
2212                 case 2:
2213                         if (track->separate_cube) {
2214                                 ret = r100_cs_track_cube(rdev, track, u);
2215                                 if (ret)
2216                                         return ret;
2217                         } else
2218                                 size *= 6;
2219                         break;
2220                 default:
2221                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2222                                   "%u\n", track->textures[u].tex_coord_type, u);
2223                         return -EINVAL;
2224                 }
2225                 if (size > radeon_bo_size(robj)) {
2226                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2227                                   "%lu\n", u, size, radeon_bo_size(robj));
2228                         r100_cs_track_texture_print(&track->textures[u]);
2229                         return -EINVAL;
2230                 }
2231         }
2232         return 0;
2233 }
2234
2235 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2236 {
2237         unsigned i;
2238         unsigned long size;
2239         unsigned prim_walk;
2240         unsigned nverts;
2241         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2242
2243         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2244             !track->blend_read_enable)
2245                 num_cb = 0;
2246
2247         for (i = 0; i < num_cb; i++) {
2248                 if (track->cb[i].robj == NULL) {
2249                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2250                         return -EINVAL;
2251                 }
2252                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2253                 size += track->cb[i].offset;
2254                 if (size > radeon_bo_size(track->cb[i].robj)) {
2255                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2256                                   "(need %lu have %lu) !\n", i, size,
2257                                   radeon_bo_size(track->cb[i].robj));
2258                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2259                                   i, track->cb[i].pitch, track->cb[i].cpp,
2260                                   track->cb[i].offset, track->maxy);
2261                         return -EINVAL;
2262                 }
2263         }
2264         track->cb_dirty = false;
2265
2266         if (track->zb_dirty && track->z_enabled) {
2267                 if (track->zb.robj == NULL) {
2268                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2269                         return -EINVAL;
2270                 }
2271                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2272                 size += track->zb.offset;
2273                 if (size > radeon_bo_size(track->zb.robj)) {
2274                         DRM_ERROR("[drm] Buffer too small for z buffer "
2275                                   "(need %lu have %lu) !\n", size,
2276                                   radeon_bo_size(track->zb.robj));
2277                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2278                                   track->zb.pitch, track->zb.cpp,
2279                                   track->zb.offset, track->maxy);
2280                         return -EINVAL;
2281                 }
2282         }
2283         track->zb_dirty = false;
2284
2285         if (track->aa_dirty && track->aaresolve) {
2286                 if (track->aa.robj == NULL) {
2287                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2288                         return -EINVAL;
2289                 }
2290                 /* I believe the format comes from colorbuffer0. */
2291                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2292                 size += track->aa.offset;
2293                 if (size > radeon_bo_size(track->aa.robj)) {
2294                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2295                                   "(need %lu have %lu) !\n", i, size,
2296                                   radeon_bo_size(track->aa.robj));
2297                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2298                                   i, track->aa.pitch, track->cb[0].cpp,
2299                                   track->aa.offset, track->maxy);
2300                         return -EINVAL;
2301                 }
2302         }
2303         track->aa_dirty = false;
2304
2305         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2306         if (track->vap_vf_cntl & (1 << 14)) {
2307                 nverts = track->vap_alt_nverts;
2308         } else {
2309                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2310         }
2311         switch (prim_walk) {
2312         case 1:
2313                 for (i = 0; i < track->num_arrays; i++) {
2314                         size = track->arrays[i].esize * track->max_indx * 4;
2315                         if (track->arrays[i].robj == NULL) {
2316                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2317                                           "bound\n", prim_walk, i);
2318                                 return -EINVAL;
2319                         }
2320                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2321                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2322                                         "need %lu dwords have %lu dwords\n",
2323                                         prim_walk, i, size >> 2,
2324                                         radeon_bo_size(track->arrays[i].robj)
2325                                         >> 2);
2326                                 DRM_ERROR("Max indices %u\n", track->max_indx);
2327                                 return -EINVAL;
2328                         }
2329                 }
2330                 break;
2331         case 2:
2332                 for (i = 0; i < track->num_arrays; i++) {
2333                         size = track->arrays[i].esize * (nverts - 1) * 4;
2334                         if (track->arrays[i].robj == NULL) {
2335                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2336                                           "bound\n", prim_walk, i);
2337                                 return -EINVAL;
2338                         }
2339                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2340                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2341                                         "need %lu dwords have %lu dwords\n",
2342                                         prim_walk, i, size >> 2,
2343                                         radeon_bo_size(track->arrays[i].robj)
2344                                         >> 2);
2345                                 return -EINVAL;
2346                         }
2347                 }
2348                 break;
2349         case 3:
2350                 size = track->vtx_size * nverts;
2351                 if (size != track->immd_dwords) {
2352                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2353                                   track->immd_dwords, size);
2354                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2355                                   nverts, track->vtx_size);
2356                         return -EINVAL;
2357                 }
2358                 break;
2359         default:
2360                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2361                           prim_walk);
2362                 return -EINVAL;
2363         }
2364
2365         if (track->tex_dirty) {
2366                 track->tex_dirty = false;
2367                 return r100_cs_track_texture_check(rdev, track);
2368         }
2369         return 0;
2370 }
2371
2372 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2373 {
2374         unsigned i, face;
2375
2376         track->cb_dirty = true;
2377         track->zb_dirty = true;
2378         track->tex_dirty = true;
2379         track->aa_dirty = true;
2380
2381         if (rdev->family < CHIP_R300) {
2382                 track->num_cb = 1;
2383                 if (rdev->family <= CHIP_RS200)
2384                         track->num_texture = 3;
2385                 else
2386                         track->num_texture = 6;
2387                 track->maxy = 2048;
2388                 track->separate_cube = true;
2389         } else {
2390                 track->num_cb = 4;
2391                 track->num_texture = 16;
2392                 track->maxy = 4096;
2393                 track->separate_cube = false;
2394                 track->aaresolve = false;
2395                 track->aa.robj = NULL;
2396         }
2397
2398         for (i = 0; i < track->num_cb; i++) {
2399                 track->cb[i].robj = NULL;
2400                 track->cb[i].pitch = 8192;
2401                 track->cb[i].cpp = 16;
2402                 track->cb[i].offset = 0;
2403         }
2404         track->z_enabled = true;
2405         track->zb.robj = NULL;
2406         track->zb.pitch = 8192;
2407         track->zb.cpp = 4;
2408         track->zb.offset = 0;
2409         track->vtx_size = 0x7F;
2410         track->immd_dwords = 0xFFFFFFFFUL;
2411         track->num_arrays = 11;
2412         track->max_indx = 0x00FFFFFFUL;
2413         for (i = 0; i < track->num_arrays; i++) {
2414                 track->arrays[i].robj = NULL;
2415                 track->arrays[i].esize = 0x7F;
2416         }
2417         for (i = 0; i < track->num_texture; i++) {
2418                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2419                 track->textures[i].pitch = 16536;
2420                 track->textures[i].width = 16536;
2421                 track->textures[i].height = 16536;
2422                 track->textures[i].width_11 = 1 << 11;
2423                 track->textures[i].height_11 = 1 << 11;
2424                 track->textures[i].num_levels = 12;
2425                 if (rdev->family <= CHIP_RS200) {
2426                         track->textures[i].tex_coord_type = 0;
2427                         track->textures[i].txdepth = 0;
2428                 } else {
2429                         track->textures[i].txdepth = 16;
2430                         track->textures[i].tex_coord_type = 1;
2431                 }
2432                 track->textures[i].cpp = 64;
2433                 track->textures[i].robj = NULL;
2434                 /* CS IB emission code makes sure texture unit are disabled */
2435                 track->textures[i].enabled = false;
2436                 track->textures[i].lookup_disable = false;
2437                 track->textures[i].roundup_w = true;
2438                 track->textures[i].roundup_h = true;
2439                 if (track->separate_cube)
2440                         for (face = 0; face < 5; face++) {
2441                                 track->textures[i].cube_info[face].robj = NULL;
2442                                 track->textures[i].cube_info[face].width = 16536;
2443                                 track->textures[i].cube_info[face].height = 16536;
2444                                 track->textures[i].cube_info[face].offset = 0;
2445                         }
2446         }
2447 }
2448
2449 /*
2450  * Global GPU functions
2451  */
2452 static void r100_errata(struct radeon_device *rdev)
2453 {
2454         rdev->pll_errata = 0;
2455
2456         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2457                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2458         }
2459
2460         if (rdev->family == CHIP_RV100 ||
2461             rdev->family == CHIP_RS100 ||
2462             rdev->family == CHIP_RS200) {
2463                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2464         }
2465 }
2466
2467 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2468 {
2469         unsigned i;
2470         uint32_t tmp;
2471
2472         for (i = 0; i < rdev->usec_timeout; i++) {
2473                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2474                 if (tmp >= n) {
2475                         return 0;
2476                 }
2477                 udelay(1);
2478         }
2479         return -1;
2480 }
2481
2482 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2483 {
2484         unsigned i;
2485         uint32_t tmp;
2486
2487         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2488                 pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n");
2489         }
2490         for (i = 0; i < rdev->usec_timeout; i++) {
2491                 tmp = RREG32(RADEON_RBBM_STATUS);
2492                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2493                         return 0;
2494                 }
2495                 udelay(1);
2496         }
2497         return -1;
2498 }
2499
2500 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2501 {
2502         unsigned i;
2503         uint32_t tmp;
2504
2505         for (i = 0; i < rdev->usec_timeout; i++) {
2506                 /* read MC_STATUS */
2507                 tmp = RREG32(RADEON_MC_STATUS);
2508                 if (tmp & RADEON_MC_IDLE) {
2509                         return 0;
2510                 }
2511                 udelay(1);
2512         }
2513         return -1;
2514 }
2515
2516 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2517 {
2518         u32 rbbm_status;
2519
2520         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2521         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2522                 radeon_ring_lockup_update(rdev, ring);
2523                 return false;
2524         }
2525         return radeon_ring_test_lockup(rdev, ring);
2526 }
2527
2528 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2529 void r100_enable_bm(struct radeon_device *rdev)
2530 {
2531         uint32_t tmp;
2532         /* Enable bus mastering */
2533         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2534         WREG32(RADEON_BUS_CNTL, tmp);
2535 }
2536
2537 void r100_bm_disable(struct radeon_device *rdev)
2538 {
2539         u32 tmp;
2540
2541         /* disable bus mastering */
2542         tmp = RREG32(R_000030_BUS_CNTL);
2543         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2544         mdelay(1);
2545         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2546         mdelay(1);
2547         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2548         tmp = RREG32(RADEON_BUS_CNTL);
2549         mdelay(1);
2550         pci_clear_master(rdev->pdev);
2551         mdelay(1);
2552 }
2553
2554 int r100_asic_reset(struct radeon_device *rdev, bool hard)
2555 {
2556         struct r100_mc_save save;
2557         u32 status, tmp;
2558         int ret = 0;
2559
2560         status = RREG32(R_000E40_RBBM_STATUS);
2561         if (!G_000E40_GUI_ACTIVE(status)) {
2562                 return 0;
2563         }
2564         r100_mc_stop(rdev, &save);
2565         status = RREG32(R_000E40_RBBM_STATUS);
2566         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2567         /* stop CP */
2568         WREG32(RADEON_CP_CSQ_CNTL, 0);
2569         tmp = RREG32(RADEON_CP_RB_CNTL);
2570         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2571         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2572         WREG32(RADEON_CP_RB_WPTR, 0);
2573         WREG32(RADEON_CP_RB_CNTL, tmp);
2574         /* save PCI state */
2575         pci_save_state(rdev->pdev);
2576         /* disable bus mastering */
2577         r100_bm_disable(rdev);
2578         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2579                                         S_0000F0_SOFT_RESET_RE(1) |
2580                                         S_0000F0_SOFT_RESET_PP(1) |
2581                                         S_0000F0_SOFT_RESET_RB(1));
2582         RREG32(R_0000F0_RBBM_SOFT_RESET);
2583         mdelay(500);
2584         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2585         mdelay(1);
2586         status = RREG32(R_000E40_RBBM_STATUS);
2587         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2588         /* reset CP */
2589         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2590         RREG32(R_0000F0_RBBM_SOFT_RESET);
2591         mdelay(500);
2592         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2593         mdelay(1);
2594         status = RREG32(R_000E40_RBBM_STATUS);
2595         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2596         /* restore PCI & busmastering */
2597         pci_restore_state(rdev->pdev);
2598         r100_enable_bm(rdev);
2599         /* Check if GPU is idle */
2600         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2601                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2602                 dev_err(rdev->dev, "failed to reset GPU\n");
2603                 ret = -1;
2604         } else
2605                 dev_info(rdev->dev, "GPU reset succeed\n");
2606         r100_mc_resume(rdev, &save);
2607         return ret;
2608 }
2609
2610 void r100_set_common_regs(struct radeon_device *rdev)
2611 {
2612         bool force_dac2 = false;
2613         u32 tmp;
2614
2615         /* set these so they don't interfere with anything */
2616         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2617         WREG32(RADEON_SUBPIC_CNTL, 0);
2618         WREG32(RADEON_VIPH_CONTROL, 0);
2619         WREG32(RADEON_I2C_CNTL_1, 0);
2620         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2621         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2622         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2623
2624         /* always set up dac2 on rn50 and some rv100 as lots
2625          * of servers seem to wire it up to a VGA port but
2626          * don't report it in the bios connector
2627          * table.
2628          */
2629         switch (rdev->pdev->device) {
2630                 /* RN50 */
2631         case 0x515e:
2632         case 0x5969:
2633                 force_dac2 = true;
2634                 break;
2635                 /* RV100*/
2636         case 0x5159:
2637         case 0x515a:
2638                 /* DELL triple head servers */
2639                 if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2640                     ((rdev->pdev->subsystem_device == 0x016c) ||
2641                      (rdev->pdev->subsystem_device == 0x016d) ||
2642                      (rdev->pdev->subsystem_device == 0x016e) ||
2643                      (rdev->pdev->subsystem_device == 0x016f) ||
2644                      (rdev->pdev->subsystem_device == 0x0170) ||
2645                      (rdev->pdev->subsystem_device == 0x017d) ||
2646                      (rdev->pdev->subsystem_device == 0x017e) ||
2647                      (rdev->pdev->subsystem_device == 0x0183) ||
2648                      (rdev->pdev->subsystem_device == 0x018a) ||
2649                      (rdev->pdev->subsystem_device == 0x019a)))
2650                         force_dac2 = true;
2651                 break;
2652         }
2653
2654         if (force_dac2) {
2655                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2656                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2657                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2658
2659                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2660                    enable it, even it's detected.
2661                 */
2662
2663                 /* force it to crtc0 */
2664                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2665                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2666                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2667
2668                 /* set up the TV DAC */
2669                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2670                                  RADEON_TV_DAC_STD_MASK |
2671                                  RADEON_TV_DAC_RDACPD |
2672                                  RADEON_TV_DAC_GDACPD |
2673                                  RADEON_TV_DAC_BDACPD |
2674                                  RADEON_TV_DAC_BGADJ_MASK |
2675                                  RADEON_TV_DAC_DACADJ_MASK);
2676                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2677                                 RADEON_TV_DAC_NHOLD |
2678                                 RADEON_TV_DAC_STD_PS2 |
2679                                 (0x58 << 16));
2680
2681                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2682                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2683                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2684         }
2685
2686         /* switch PM block to ACPI mode */
2687         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2688         tmp &= ~RADEON_PM_MODE_SEL;
2689         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2690
2691 }
2692
2693 /*
2694  * VRAM info
2695  */
2696 static void r100_vram_get_type(struct radeon_device *rdev)
2697 {
2698         uint32_t tmp;
2699
2700         rdev->mc.vram_is_ddr = false;
2701         if (rdev->flags & RADEON_IS_IGP)
2702                 rdev->mc.vram_is_ddr = true;
2703         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2704                 rdev->mc.vram_is_ddr = true;
2705         if ((rdev->family == CHIP_RV100) ||
2706             (rdev->family == CHIP_RS100) ||
2707             (rdev->family == CHIP_RS200)) {
2708                 tmp = RREG32(RADEON_MEM_CNTL);
2709                 if (tmp & RV100_HALF_MODE) {
2710                         rdev->mc.vram_width = 32;
2711                 } else {
2712                         rdev->mc.vram_width = 64;
2713                 }
2714                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2715                         rdev->mc.vram_width /= 4;
2716                         rdev->mc.vram_is_ddr = true;
2717                 }
2718         } else if (rdev->family <= CHIP_RV280) {
2719                 tmp = RREG32(RADEON_MEM_CNTL);
2720                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2721                         rdev->mc.vram_width = 128;
2722                 } else {
2723                         rdev->mc.vram_width = 64;
2724                 }
2725         } else {
2726                 /* newer IGPs */
2727                 rdev->mc.vram_width = 128;
2728         }
2729 }
2730
2731 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2732 {
2733         u32 aper_size;
2734         u8 byte;
2735
2736         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2737
2738         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2739          * that is has the 2nd generation multifunction PCI interface
2740          */
2741         if (rdev->family == CHIP_RV280 ||
2742             rdev->family >= CHIP_RV350) {
2743                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2744                        ~RADEON_HDP_APER_CNTL);
2745                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2746                 return aper_size * 2;
2747         }
2748
2749         /* Older cards have all sorts of funny issues to deal with. First
2750          * check if it's a multifunction card by reading the PCI config
2751          * header type... Limit those to one aperture size
2752          */
2753         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2754         if (byte & 0x80) {
2755                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2756                 DRM_INFO("Limiting VRAM to one aperture\n");
2757                 return aper_size;
2758         }
2759
2760         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2761          * have set it up. We don't write this as it's broken on some ASICs but
2762          * we expect the BIOS to have done the right thing (might be too optimistic...)
2763          */
2764         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2765                 return aper_size * 2;
2766         return aper_size;
2767 }
2768
2769 void r100_vram_init_sizes(struct radeon_device *rdev)
2770 {
2771         u64 config_aper_size;
2772
2773         /* work out accessible VRAM */
2774         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2775         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2776         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2777         /* FIXME we don't use the second aperture yet when we could use it */
2778         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2779                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2780         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2781         if (rdev->flags & RADEON_IS_IGP) {
2782                 uint32_t tom;
2783                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2784                 tom = RREG32(RADEON_NB_TOM);
2785                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2786                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2787                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2788         } else {
2789                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2790                 /* Some production boards of m6 will report 0
2791                  * if it's 8 MB
2792                  */
2793                 if (rdev->mc.real_vram_size == 0) {
2794                         rdev->mc.real_vram_size = 8192 * 1024;
2795                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2796                 }
2797                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2798                  * Novell bug 204882 + along with lots of ubuntu ones
2799                  */
2800                 if (rdev->mc.aper_size > config_aper_size)
2801                         config_aper_size = rdev->mc.aper_size;
2802
2803                 if (config_aper_size > rdev->mc.real_vram_size)
2804                         rdev->mc.mc_vram_size = config_aper_size;
2805                 else
2806                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2807         }
2808 }
2809
2810 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2811 {
2812         uint32_t temp;
2813
2814         temp = RREG32(RADEON_CONFIG_CNTL);
2815         if (!state) {
2816                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2817                 temp |= RADEON_CFG_VGA_IO_DIS;
2818         } else {
2819                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2820         }
2821         WREG32(RADEON_CONFIG_CNTL, temp);
2822 }
2823
2824 static void r100_mc_init(struct radeon_device *rdev)
2825 {
2826         u64 base;
2827
2828         r100_vram_get_type(rdev);
2829         r100_vram_init_sizes(rdev);
2830         base = rdev->mc.aper_base;
2831         if (rdev->flags & RADEON_IS_IGP)
2832                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2833         radeon_vram_location(rdev, &rdev->mc, base);
2834         rdev->mc.gtt_base_align = 0;
2835         if (!(rdev->flags & RADEON_IS_AGP))
2836                 radeon_gtt_location(rdev, &rdev->mc);
2837         radeon_update_bandwidth_info(rdev);
2838 }
2839
2840
2841 /*
2842  * Indirect registers accessor
2843  */
2844 void r100_pll_errata_after_index(struct radeon_device *rdev)
2845 {
2846         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2847                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2848                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2849         }
2850 }
2851
2852 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2853 {
2854         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2855          * or the chip could hang on a subsequent access
2856          */
2857         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2858                 mdelay(5);
2859         }
2860
2861         /* This function is required to workaround a hardware bug in some (all?)
2862          * revisions of the R300.  This workaround should be called after every
2863          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2864          * may not be correct.
2865          */
2866         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2867                 uint32_t save, tmp;
2868
2869                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2870                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2871                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2872                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2873                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2874         }
2875 }
2876
2877 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2878 {
2879         unsigned long flags;
2880         uint32_t data;
2881
2882         spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2883         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2884         r100_pll_errata_after_index(rdev);
2885         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2886         r100_pll_errata_after_data(rdev);
2887         spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2888         return data;
2889 }
2890
2891 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2892 {
2893         unsigned long flags;
2894
2895         spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2896         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2897         r100_pll_errata_after_index(rdev);
2898         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2899         r100_pll_errata_after_data(rdev);
2900         spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2901 }
2902
2903 static void r100_set_safe_registers(struct radeon_device *rdev)
2904 {
2905         if (ASIC_IS_RN50(rdev)) {
2906                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2907                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2908         } else if (rdev->family < CHIP_R200) {
2909                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2910                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2911         } else {
2912                 r200_set_safe_registers(rdev);
2913         }
2914 }
2915
2916 /*
2917  * Debugfs info
2918  */
2919 #if defined(CONFIG_DEBUG_FS)
2920 static int r100_debugfs_rbbm_info_show(struct seq_file *m, void *unused)
2921 {
2922         struct radeon_device *rdev = (struct radeon_device *)m->private;
2923         uint32_t reg, value;
2924         unsigned i;
2925
2926         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2927         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2928         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2929         for (i = 0; i < 64; i++) {
2930                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2931                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2932                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2933                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2934                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2935         }
2936         return 0;
2937 }
2938
2939 static int r100_debugfs_cp_ring_info_show(struct seq_file *m, void *unused)
2940 {
2941         struct radeon_device *rdev = (struct radeon_device *)m->private;
2942         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2943         uint32_t rdp, wdp;
2944         unsigned count, i, j;
2945
2946         radeon_ring_free_size(rdev, ring);
2947         rdp = RREG32(RADEON_CP_RB_RPTR);
2948         wdp = RREG32(RADEON_CP_RB_WPTR);
2949         count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2950         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2951         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2952         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2953         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2954         seq_printf(m, "%u dwords in ring\n", count);
2955         if (ring->ready) {
2956                 for (j = 0; j <= count; j++) {
2957                         i = (rdp + j) & ring->ptr_mask;
2958                         seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2959                 }
2960         }
2961         return 0;
2962 }
2963
2964
2965 static int r100_debugfs_cp_csq_fifo_show(struct seq_file *m, void *unused)
2966 {
2967         struct radeon_device *rdev = (struct radeon_device *)m->private;
2968         uint32_t csq_stat, csq2_stat, tmp;
2969         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2970         unsigned i;
2971
2972         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2973         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2974         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2975         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2976         r_rptr = (csq_stat >> 0) & 0x3ff;
2977         r_wptr = (csq_stat >> 10) & 0x3ff;
2978         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2979         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2980         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2981         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2982         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2983         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2984         seq_printf(m, "Ring rptr %u\n", r_rptr);
2985         seq_printf(m, "Ring wptr %u\n", r_wptr);
2986         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2987         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2988         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2989         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2990         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2991          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2992         seq_printf(m, "Ring fifo:\n");
2993         for (i = 0; i < 256; i++) {
2994                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2995                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2996                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2997         }
2998         seq_printf(m, "Indirect1 fifo:\n");
2999         for (i = 256; i <= 512; i++) {
3000                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3001                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3002                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3003         }
3004         seq_printf(m, "Indirect2 fifo:\n");
3005         for (i = 640; i < ib1_wptr; i++) {
3006                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3007                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3008                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3009         }
3010         return 0;
3011 }
3012
3013 static int r100_debugfs_mc_info_show(struct seq_file *m, void *unused)
3014 {
3015         struct radeon_device *rdev = (struct radeon_device *)m->private;
3016         uint32_t tmp;
3017
3018         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3019         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3020         tmp = RREG32(RADEON_MC_FB_LOCATION);
3021         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3022         tmp = RREG32(RADEON_BUS_CNTL);
3023         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3024         tmp = RREG32(RADEON_MC_AGP_LOCATION);
3025         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3026         tmp = RREG32(RADEON_AGP_BASE);
3027         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3028         tmp = RREG32(RADEON_HOST_PATH_CNTL);
3029         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3030         tmp = RREG32(0x01D0);
3031         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3032         tmp = RREG32(RADEON_AIC_LO_ADDR);
3033         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3034         tmp = RREG32(RADEON_AIC_HI_ADDR);
3035         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3036         tmp = RREG32(0x01E4);
3037         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3038         return 0;
3039 }
3040
3041 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_rbbm_info);
3042 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_ring_info);
3043 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_csq_fifo);
3044 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_mc_info);
3045
3046 #endif
3047
3048 void  r100_debugfs_rbbm_init(struct radeon_device *rdev)
3049 {
3050 #if defined(CONFIG_DEBUG_FS)
3051         struct dentry *root = rdev->ddev->primary->debugfs_root;
3052
3053         debugfs_create_file("r100_rbbm_info", 0444, root, rdev,
3054                             &r100_debugfs_rbbm_info_fops);
3055 #endif
3056 }
3057
3058 void r100_debugfs_cp_init(struct radeon_device *rdev)
3059 {
3060 #if defined(CONFIG_DEBUG_FS)
3061         struct dentry *root = rdev->ddev->primary->debugfs_root;
3062
3063         debugfs_create_file("r100_cp_ring_info", 0444, root, rdev,
3064                             &r100_debugfs_cp_ring_info_fops);
3065         debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev,
3066                             &r100_debugfs_cp_csq_fifo_fops);
3067 #endif
3068 }
3069
3070 void  r100_debugfs_mc_info_init(struct radeon_device *rdev)
3071 {
3072 #if defined(CONFIG_DEBUG_FS)
3073         struct dentry *root = rdev->ddev->primary->debugfs_root;
3074
3075         debugfs_create_file("r100_mc_info", 0444, root, rdev,
3076                             &r100_debugfs_mc_info_fops);
3077 #endif
3078 }
3079
3080 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3081                          uint32_t tiling_flags, uint32_t pitch,
3082                          uint32_t offset, uint32_t obj_size)
3083 {
3084         int surf_index = reg * 16;
3085         int flags = 0;
3086
3087         if (rdev->family <= CHIP_RS200) {
3088                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3089                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3090                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
3091                 if (tiling_flags & RADEON_TILING_MACRO)
3092                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
3093                 /* setting pitch to 0 disables tiling */
3094                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3095                                 == 0)
3096                         pitch = 0;
3097         } else if (rdev->family <= CHIP_RV280) {
3098                 if (tiling_flags & (RADEON_TILING_MACRO))
3099                         flags |= R200_SURF_TILE_COLOR_MACRO;
3100                 if (tiling_flags & RADEON_TILING_MICRO)
3101                         flags |= R200_SURF_TILE_COLOR_MICRO;
3102         } else {
3103                 if (tiling_flags & RADEON_TILING_MACRO)
3104                         flags |= R300_SURF_TILE_MACRO;
3105                 if (tiling_flags & RADEON_TILING_MICRO)
3106                         flags |= R300_SURF_TILE_MICRO;
3107         }
3108
3109         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3110                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3111         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3112                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3113
3114         /* r100/r200 divide by 16 */
3115         if (rdev->family < CHIP_R300)
3116                 flags |= pitch / 16;
3117         else
3118                 flags |= pitch / 8;
3119
3120
3121         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3122         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3123         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3124         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3125         return 0;
3126 }
3127
3128 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3129 {
3130         int surf_index = reg * 16;
3131         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3132 }
3133
3134 void r100_bandwidth_update(struct radeon_device *rdev)
3135 {
3136         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3137         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3138         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
3139         fixed20_12 crit_point_ff = {0};
3140         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3141         fixed20_12 memtcas_ff[8] = {
3142                 dfixed_init(1),
3143                 dfixed_init(2),
3144                 dfixed_init(3),
3145                 dfixed_init(0),
3146                 dfixed_init_half(1),
3147                 dfixed_init_half(2),
3148                 dfixed_init(0),
3149         };
3150         fixed20_12 memtcas_rs480_ff[8] = {
3151                 dfixed_init(0),
3152                 dfixed_init(1),
3153                 dfixed_init(2),
3154                 dfixed_init(3),
3155                 dfixed_init(0),
3156                 dfixed_init_half(1),
3157                 dfixed_init_half(2),
3158                 dfixed_init_half(3),
3159         };
3160         fixed20_12 memtcas2_ff[8] = {
3161                 dfixed_init(0),
3162                 dfixed_init(1),
3163                 dfixed_init(2),
3164                 dfixed_init(3),
3165                 dfixed_init(4),
3166                 dfixed_init(5),
3167                 dfixed_init(6),
3168                 dfixed_init(7),
3169         };
3170         fixed20_12 memtrbs[8] = {
3171                 dfixed_init(1),
3172                 dfixed_init_half(1),
3173                 dfixed_init(2),
3174                 dfixed_init_half(2),
3175                 dfixed_init(3),
3176                 dfixed_init_half(3),
3177                 dfixed_init(4),
3178                 dfixed_init_half(4)
3179         };
3180         fixed20_12 memtrbs_r4xx[8] = {
3181                 dfixed_init(4),
3182                 dfixed_init(5),
3183                 dfixed_init(6),
3184                 dfixed_init(7),
3185                 dfixed_init(8),
3186                 dfixed_init(9),
3187                 dfixed_init(10),
3188                 dfixed_init(11)
3189         };
3190         fixed20_12 min_mem_eff;
3191         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3192         fixed20_12 cur_latency_mclk, cur_latency_sclk;
3193         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0},
3194                 disp_drain_rate2, read_return_rate;
3195         fixed20_12 time_disp1_drop_priority;
3196         int c;
3197         int cur_size = 16;       /* in octawords */
3198         int critical_point = 0, critical_point2;
3199 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
3200         int stop_req, max_stop_req;
3201         struct drm_display_mode *mode1 = NULL;
3202         struct drm_display_mode *mode2 = NULL;
3203         uint32_t pixel_bytes1 = 0;
3204         uint32_t pixel_bytes2 = 0;
3205
3206         /* Guess line buffer size to be 8192 pixels */
3207         u32 lb_size = 8192;
3208
3209         if (!rdev->mode_info.mode_config_initialized)
3210                 return;
3211
3212         radeon_update_display_priority(rdev);
3213
3214         if (rdev->mode_info.crtcs[0]->base.enabled) {
3215                 const struct drm_framebuffer *fb =
3216                         rdev->mode_info.crtcs[0]->base.primary->fb;
3217
3218                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3219                 pixel_bytes1 = fb->format->cpp[0];
3220         }
3221         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3222                 if (rdev->mode_info.crtcs[1]->base.enabled) {
3223                         const struct drm_framebuffer *fb =
3224                                 rdev->mode_info.crtcs[1]->base.primary->fb;
3225
3226                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3227                         pixel_bytes2 = fb->format->cpp[0];
3228                 }
3229         }
3230
3231         min_mem_eff.full = dfixed_const_8(0);
3232         /* get modes */
3233         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3234                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3235                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3236                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3237                 /* check crtc enables */
3238                 if (mode2)
3239                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3240                 if (mode1)
3241                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3242                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3243         }
3244
3245         /*
3246          * determine is there is enough bw for current mode
3247          */
3248         sclk_ff = rdev->pm.sclk;
3249         mclk_ff = rdev->pm.mclk;
3250
3251         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3252         temp_ff.full = dfixed_const(temp);
3253         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3254
3255         pix_clk.full = 0;
3256         pix_clk2.full = 0;
3257         peak_disp_bw.full = 0;
3258         if (mode1) {
3259                 temp_ff.full = dfixed_const(1000);
3260                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3261                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3262                 temp_ff.full = dfixed_const(pixel_bytes1);
3263                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3264         }
3265         if (mode2) {
3266                 temp_ff.full = dfixed_const(1000);
3267                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3268                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3269                 temp_ff.full = dfixed_const(pixel_bytes2);
3270                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3271         }
3272
3273         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3274         if (peak_disp_bw.full >= mem_bw.full) {
3275                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3276                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3277         }
3278
3279         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
3280         temp = RREG32(RADEON_MEM_TIMING_CNTL);
3281         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3282                 mem_trcd = ((temp >> 2) & 0x3) + 1;
3283                 mem_trp  = ((temp & 0x3)) + 1;
3284                 mem_tras = ((temp & 0x70) >> 4) + 1;
3285         } else if (rdev->family == CHIP_R300 ||
3286                    rdev->family == CHIP_R350) { /* r300, r350 */
3287                 mem_trcd = (temp & 0x7) + 1;
3288                 mem_trp = ((temp >> 8) & 0x7) + 1;
3289                 mem_tras = ((temp >> 11) & 0xf) + 4;
3290         } else if (rdev->family == CHIP_RV350 ||
3291                    rdev->family == CHIP_RV380) {
3292                 /* rv3x0 */
3293                 mem_trcd = (temp & 0x7) + 3;
3294                 mem_trp = ((temp >> 8) & 0x7) + 3;
3295                 mem_tras = ((temp >> 11) & 0xf) + 6;
3296         } else if (rdev->family == CHIP_R420 ||
3297                    rdev->family == CHIP_R423 ||
3298                    rdev->family == CHIP_RV410) {
3299                 /* r4xx */
3300                 mem_trcd = (temp & 0xf) + 3;
3301                 if (mem_trcd > 15)
3302                         mem_trcd = 15;
3303                 mem_trp = ((temp >> 8) & 0xf) + 3;
3304                 if (mem_trp > 15)
3305                         mem_trp = 15;
3306                 mem_tras = ((temp >> 12) & 0x1f) + 6;
3307                 if (mem_tras > 31)
3308                         mem_tras = 31;
3309         } else { /* RV200, R200 */
3310                 mem_trcd = (temp & 0x7) + 1;
3311                 mem_trp = ((temp >> 8) & 0x7) + 1;
3312                 mem_tras = ((temp >> 12) & 0xf) + 4;
3313         }
3314         /* convert to FF */
3315         trcd_ff.full = dfixed_const(mem_trcd);
3316         trp_ff.full = dfixed_const(mem_trp);
3317         tras_ff.full = dfixed_const(mem_tras);
3318
3319         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3320         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3321         data = (temp & (7 << 20)) >> 20;
3322         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3323                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3324                         tcas_ff = memtcas_rs480_ff[data];
3325                 else
3326                         tcas_ff = memtcas_ff[data];
3327         } else
3328                 tcas_ff = memtcas2_ff[data];
3329
3330         if (rdev->family == CHIP_RS400 ||
3331             rdev->family == CHIP_RS480) {
3332                 /* extra cas latency stored in bits 23-25 0-4 clocks */
3333                 data = (temp >> 23) & 0x7;
3334                 if (data < 5)
3335                         tcas_ff.full += dfixed_const(data);
3336         }
3337
3338         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3339                 /* on the R300, Tcas is included in Trbs.
3340                  */
3341                 temp = RREG32(RADEON_MEM_CNTL);
3342                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3343                 if (data == 1) {
3344                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
3345                                 temp = RREG32(R300_MC_IND_INDEX);
3346                                 temp &= ~R300_MC_IND_ADDR_MASK;
3347                                 temp |= R300_MC_READ_CNTL_CD_mcind;
3348                                 WREG32(R300_MC_IND_INDEX, temp);
3349                                 temp = RREG32(R300_MC_IND_DATA);
3350                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3351                         } else {
3352                                 temp = RREG32(R300_MC_READ_CNTL_AB);
3353                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3354                         }
3355                 } else {
3356                         temp = RREG32(R300_MC_READ_CNTL_AB);
3357                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3358                 }
3359                 if (rdev->family == CHIP_RV410 ||
3360                     rdev->family == CHIP_R420 ||
3361                     rdev->family == CHIP_R423)
3362                         trbs_ff = memtrbs_r4xx[data];
3363                 else
3364                         trbs_ff = memtrbs[data];
3365                 tcas_ff.full += trbs_ff.full;
3366         }
3367
3368         sclk_eff_ff.full = sclk_ff.full;
3369
3370         if (rdev->flags & RADEON_IS_AGP) {
3371                 fixed20_12 agpmode_ff;
3372                 agpmode_ff.full = dfixed_const(radeon_agpmode);
3373                 temp_ff.full = dfixed_const_666(16);
3374                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3375         }
3376         /* TODO PCIE lanes may affect this - agpmode == 16?? */
3377
3378         if (ASIC_IS_R300(rdev)) {
3379                 sclk_delay_ff.full = dfixed_const(250);
3380         } else {
3381                 if ((rdev->family == CHIP_RV100) ||
3382                     rdev->flags & RADEON_IS_IGP) {
3383                         if (rdev->mc.vram_is_ddr)
3384                                 sclk_delay_ff.full = dfixed_const(41);
3385                         else
3386                                 sclk_delay_ff.full = dfixed_const(33);
3387                 } else {
3388                         if (rdev->mc.vram_width == 128)
3389                                 sclk_delay_ff.full = dfixed_const(57);
3390                         else
3391                                 sclk_delay_ff.full = dfixed_const(41);
3392                 }
3393         }
3394
3395         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3396
3397         if (rdev->mc.vram_is_ddr) {
3398                 if (rdev->mc.vram_width == 32) {
3399                         k1.full = dfixed_const(40);
3400                         c  = 3;
3401                 } else {
3402                         k1.full = dfixed_const(20);
3403                         c  = 1;
3404                 }
3405         } else {
3406                 k1.full = dfixed_const(40);
3407                 c  = 3;
3408         }
3409
3410         temp_ff.full = dfixed_const(2);
3411         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3412         temp_ff.full = dfixed_const(c);
3413         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3414         temp_ff.full = dfixed_const(4);
3415         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3416         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3417         mc_latency_mclk.full += k1.full;
3418
3419         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3420         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3421
3422         /*
3423           HW cursor time assuming worst case of full size colour cursor.
3424         */
3425         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3426         temp_ff.full += trcd_ff.full;
3427         if (temp_ff.full < tras_ff.full)
3428                 temp_ff.full = tras_ff.full;
3429         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3430
3431         temp_ff.full = dfixed_const(cur_size);
3432         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3433         /*
3434           Find the total latency for the display data.
3435         */
3436         disp_latency_overhead.full = dfixed_const(8);
3437         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3438         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3439         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3440
3441         if (mc_latency_mclk.full > mc_latency_sclk.full)
3442                 disp_latency.full = mc_latency_mclk.full;
3443         else
3444                 disp_latency.full = mc_latency_sclk.full;
3445
3446         /* setup Max GRPH_STOP_REQ default value */
3447         if (ASIC_IS_RV100(rdev))
3448                 max_stop_req = 0x5c;
3449         else
3450                 max_stop_req = 0x7c;
3451
3452         if (mode1) {
3453                 /*  CRTC1
3454                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3455                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3456                 */
3457                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3458
3459                 if (stop_req > max_stop_req)
3460                         stop_req = max_stop_req;
3461
3462                 /*
3463                   Find the drain rate of the display buffer.
3464                 */
3465                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3466                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3467
3468                 /*
3469                   Find the critical point of the display buffer.
3470                 */
3471                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3472                 crit_point_ff.full += dfixed_const_half(0);
3473
3474                 critical_point = dfixed_trunc(crit_point_ff);
3475
3476                 if (rdev->disp_priority == 2) {
3477                         critical_point = 0;
3478                 }
3479
3480                 /*
3481                   The critical point should never be above max_stop_req-4.  Setting
3482                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3483                 */
3484                 if (max_stop_req - critical_point < 4)
3485                         critical_point = 0;
3486
3487                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3488                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3489                         critical_point = 0x10;
3490                 }
3491
3492                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3493                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3494                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3495                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3496                 if ((rdev->family == CHIP_R350) &&
3497                     (stop_req > 0x15)) {
3498                         stop_req -= 0x10;
3499                 }
3500                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3501                 temp |= RADEON_GRPH_BUFFER_SIZE;
3502                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3503                           RADEON_GRPH_CRITICAL_AT_SOF |
3504                           RADEON_GRPH_STOP_CNTL);
3505                 /*
3506                   Write the result into the register.
3507                 */
3508                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3509                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3510
3511 #if 0
3512                 if ((rdev->family == CHIP_RS400) ||
3513                     (rdev->family == CHIP_RS480)) {
3514                         /* attempt to program RS400 disp regs correctly ??? */
3515                         temp = RREG32(RS400_DISP1_REG_CNTL);
3516                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3517                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3518                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3519                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3520                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3521                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3522                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3523                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3524                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3525                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3526                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3527                 }
3528 #endif
3529
3530                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3531                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3532                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3533         }
3534
3535         if (mode2) {
3536                 u32 grph2_cntl;
3537                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3538
3539                 if (stop_req > max_stop_req)
3540                         stop_req = max_stop_req;
3541
3542                 /*
3543                   Find the drain rate of the display buffer.
3544                 */
3545                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3546                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3547
3548                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3549                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3550                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3551                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3552                 if ((rdev->family == CHIP_R350) &&
3553                     (stop_req > 0x15)) {
3554                         stop_req -= 0x10;
3555                 }
3556                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3557                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3558                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3559                           RADEON_GRPH_CRITICAL_AT_SOF |
3560                           RADEON_GRPH_STOP_CNTL);
3561
3562                 if ((rdev->family == CHIP_RS100) ||
3563                     (rdev->family == CHIP_RS200))
3564                         critical_point2 = 0;
3565                 else {
3566                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3567                         temp_ff.full = dfixed_const(temp);
3568                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3569                         if (sclk_ff.full < temp_ff.full)
3570                                 temp_ff.full = sclk_ff.full;
3571
3572                         read_return_rate.full = temp_ff.full;
3573
3574                         if (mode1) {
3575                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3576                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3577                         } else {
3578                                 time_disp1_drop_priority.full = 0;
3579                         }
3580                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3581                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3582                         crit_point_ff.full += dfixed_const_half(0);
3583
3584                         critical_point2 = dfixed_trunc(crit_point_ff);
3585
3586                         if (rdev->disp_priority == 2) {
3587                                 critical_point2 = 0;
3588                         }
3589
3590                         if (max_stop_req - critical_point2 < 4)
3591                                 critical_point2 = 0;
3592
3593                 }
3594
3595                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3596                         /* some R300 cards have problem with this set to 0 */
3597                         critical_point2 = 0x10;
3598                 }
3599
3600                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3601                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3602
3603                 if ((rdev->family == CHIP_RS400) ||
3604                     (rdev->family == CHIP_RS480)) {
3605 #if 0
3606                         /* attempt to program RS400 disp2 regs correctly ??? */
3607                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3608                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3609                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3610                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3611                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3612                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3613                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3614                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3615                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3616                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3617                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3618                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3619 #endif
3620                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3621                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3622                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3623                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3624                 }
3625
3626                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3627                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3628         }
3629
3630         /* Save number of lines the linebuffer leads before the scanout */
3631         if (mode1)
3632             rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
3633
3634         if (mode2)
3635             rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3636 }
3637
3638 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3639 {
3640         uint32_t scratch;
3641         uint32_t tmp = 0;
3642         unsigned i;
3643         int r;
3644
3645         r = radeon_scratch_get(rdev, &scratch);
3646         if (r) {
3647                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3648                 return r;
3649         }
3650         WREG32(scratch, 0xCAFEDEAD);
3651         r = radeon_ring_lock(rdev, ring, 2);
3652         if (r) {
3653                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3654                 radeon_scratch_free(rdev, scratch);
3655                 return r;
3656         }
3657         radeon_ring_write(ring, PACKET0(scratch, 0));
3658         radeon_ring_write(ring, 0xDEADBEEF);
3659         radeon_ring_unlock_commit(rdev, ring, false);
3660         for (i = 0; i < rdev->usec_timeout; i++) {
3661                 tmp = RREG32(scratch);
3662                 if (tmp == 0xDEADBEEF) {
3663                         break;
3664                 }
3665                 udelay(1);
3666         }
3667         if (i < rdev->usec_timeout) {
3668                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3669         } else {
3670                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3671                           scratch, tmp);
3672                 r = -EINVAL;
3673         }
3674         radeon_scratch_free(rdev, scratch);
3675         return r;
3676 }
3677
3678 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3679 {
3680         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3681
3682         if (ring->rptr_save_reg) {
3683                 u32 next_rptr = ring->wptr + 2 + 3;
3684                 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3685                 radeon_ring_write(ring, next_rptr);
3686         }
3687
3688         radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3689         radeon_ring_write(ring, ib->gpu_addr);
3690         radeon_ring_write(ring, ib->length_dw);
3691 }
3692
3693 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3694 {
3695         struct radeon_ib ib;
3696         uint32_t scratch;
3697         uint32_t tmp = 0;
3698         unsigned i;
3699         int r;
3700
3701         r = radeon_scratch_get(rdev, &scratch);
3702         if (r) {
3703                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3704                 return r;
3705         }
3706         WREG32(scratch, 0xCAFEDEAD);
3707         r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3708         if (r) {
3709                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3710                 goto free_scratch;
3711         }
3712         ib.ptr[0] = PACKET0(scratch, 0);
3713         ib.ptr[1] = 0xDEADBEEF;
3714         ib.ptr[2] = PACKET2(0);
3715         ib.ptr[3] = PACKET2(0);
3716         ib.ptr[4] = PACKET2(0);
3717         ib.ptr[5] = PACKET2(0);
3718         ib.ptr[6] = PACKET2(0);
3719         ib.ptr[7] = PACKET2(0);
3720         ib.length_dw = 8;
3721         r = radeon_ib_schedule(rdev, &ib, NULL, false);
3722         if (r) {
3723                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3724                 goto free_ib;
3725         }
3726         r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3727                 RADEON_USEC_IB_TEST_TIMEOUT));
3728         if (r < 0) {
3729                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3730                 goto free_ib;
3731         } else if (r == 0) {
3732                 DRM_ERROR("radeon: fence wait timed out.\n");
3733                 r = -ETIMEDOUT;
3734                 goto free_ib;
3735         }
3736         r = 0;
3737         for (i = 0; i < rdev->usec_timeout; i++) {
3738                 tmp = RREG32(scratch);
3739                 if (tmp == 0xDEADBEEF) {
3740                         break;
3741                 }
3742                 udelay(1);
3743         }
3744         if (i < rdev->usec_timeout) {
3745                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3746         } else {
3747                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3748                           scratch, tmp);
3749                 r = -EINVAL;
3750         }
3751 free_ib:
3752         radeon_ib_free(rdev, &ib);
3753 free_scratch:
3754         radeon_scratch_free(rdev, scratch);
3755         return r;
3756 }
3757
3758 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3759 {
3760         /* Shutdown CP we shouldn't need to do that but better be safe than
3761          * sorry
3762          */
3763         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3764         WREG32(R_000740_CP_CSQ_CNTL, 0);
3765
3766         /* Save few CRTC registers */
3767         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3768         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3769         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3770         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3771         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3772                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3773                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3774         }
3775
3776         /* Disable VGA aperture access */
3777         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3778         /* Disable cursor, overlay, crtc */
3779         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3780         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3781                                         S_000054_CRTC_DISPLAY_DIS(1));
3782         WREG32(R_000050_CRTC_GEN_CNTL,
3783                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3784                         S_000050_CRTC_DISP_REQ_EN_B(1));
3785         WREG32(R_000420_OV0_SCALE_CNTL,
3786                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3787         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3788         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3789                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3790                                                 S_000360_CUR2_LOCK(1));
3791                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3792                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3793                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3794                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3795                 WREG32(R_000360_CUR2_OFFSET,
3796                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3797         }
3798 }
3799
3800 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3801 {
3802         /* Update base address for crtc */
3803         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3804         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3805                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3806         }
3807         /* Restore CRTC registers */
3808         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3809         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3810         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3811         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3812                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3813         }
3814 }
3815
3816 void r100_vga_render_disable(struct radeon_device *rdev)
3817 {
3818         u32 tmp;
3819
3820         tmp = RREG8(R_0003C2_GENMO_WT);
3821         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3822 }
3823
3824 static void r100_mc_program(struct radeon_device *rdev)
3825 {
3826         struct r100_mc_save save;
3827
3828         /* Stops all mc clients */
3829         r100_mc_stop(rdev, &save);
3830         if (rdev->flags & RADEON_IS_AGP) {
3831                 WREG32(R_00014C_MC_AGP_LOCATION,
3832                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3833                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3834                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3835                 if (rdev->family > CHIP_RV200)
3836                         WREG32(R_00015C_AGP_BASE_2,
3837                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3838         } else {
3839                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3840                 WREG32(R_000170_AGP_BASE, 0);
3841                 if (rdev->family > CHIP_RV200)
3842                         WREG32(R_00015C_AGP_BASE_2, 0);
3843         }
3844         /* Wait for mc idle */
3845         if (r100_mc_wait_for_idle(rdev))
3846                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3847         /* Program MC, should be a 32bits limited address space */
3848         WREG32(R_000148_MC_FB_LOCATION,
3849                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3850                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3851         r100_mc_resume(rdev, &save);
3852 }
3853
3854 static void r100_clock_startup(struct radeon_device *rdev)
3855 {
3856         u32 tmp;
3857
3858         if (radeon_dynclks != -1 && radeon_dynclks)
3859                 radeon_legacy_set_clock_gating(rdev, 1);
3860         /* We need to force on some of the block */
3861         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3862         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3863         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3864                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3865         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3866 }
3867
3868 static int r100_startup(struct radeon_device *rdev)
3869 {
3870         int r;
3871
3872         /* set common regs */
3873         r100_set_common_regs(rdev);
3874         /* program mc */
3875         r100_mc_program(rdev);
3876         /* Resume clock */
3877         r100_clock_startup(rdev);
3878         /* Initialize GART (initialize after TTM so we can allocate
3879          * memory through TTM but finalize after TTM) */
3880         r100_enable_bm(rdev);
3881         if (rdev->flags & RADEON_IS_PCI) {
3882                 r = r100_pci_gart_enable(rdev);
3883                 if (r)
3884                         return r;
3885         }
3886
3887         /* allocate wb buffer */
3888         r = radeon_wb_init(rdev);
3889         if (r)
3890                 return r;
3891
3892         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3893         if (r) {
3894                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3895                 return r;
3896         }
3897
3898         /* Enable IRQ */
3899         if (!rdev->irq.installed) {
3900                 r = radeon_irq_kms_init(rdev);
3901                 if (r)
3902                         return r;
3903         }
3904
3905         r100_irq_set(rdev);
3906         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3907         /* 1M ring buffer */
3908         r = r100_cp_init(rdev, 1024 * 1024);
3909         if (r) {
3910                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3911                 return r;
3912         }
3913
3914         r = radeon_ib_pool_init(rdev);
3915         if (r) {
3916                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3917                 return r;
3918         }
3919
3920         return 0;
3921 }
3922
3923 int r100_resume(struct radeon_device *rdev)
3924 {
3925         int r;
3926
3927         /* Make sur GART are not working */
3928         if (rdev->flags & RADEON_IS_PCI)
3929                 r100_pci_gart_disable(rdev);
3930         /* Resume clock before doing reset */
3931         r100_clock_startup(rdev);
3932         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3933         if (radeon_asic_reset(rdev)) {
3934                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3935                         RREG32(R_000E40_RBBM_STATUS),
3936                         RREG32(R_0007C0_CP_STAT));
3937         }
3938         /* post */
3939         radeon_combios_asic_init(rdev->ddev);
3940         /* Resume clock after posting */
3941         r100_clock_startup(rdev);
3942         /* Initialize surface registers */
3943         radeon_surface_init(rdev);
3944
3945         rdev->accel_working = true;
3946         r = r100_startup(rdev);
3947         if (r) {
3948                 rdev->accel_working = false;
3949         }
3950         return r;
3951 }
3952
3953 int r100_suspend(struct radeon_device *rdev)
3954 {
3955         radeon_pm_suspend(rdev);
3956         r100_cp_disable(rdev);
3957         radeon_wb_disable(rdev);
3958         r100_irq_disable(rdev);
3959         if (rdev->flags & RADEON_IS_PCI)
3960                 r100_pci_gart_disable(rdev);
3961         return 0;
3962 }
3963
3964 void r100_fini(struct radeon_device *rdev)
3965 {
3966         radeon_pm_fini(rdev);
3967         r100_cp_fini(rdev);
3968         radeon_wb_fini(rdev);
3969         radeon_ib_pool_fini(rdev);
3970         radeon_gem_fini(rdev);
3971         if (rdev->flags & RADEON_IS_PCI)
3972                 r100_pci_gart_fini(rdev);
3973         radeon_agp_fini(rdev);
3974         radeon_irq_kms_fini(rdev);
3975         radeon_fence_driver_fini(rdev);
3976         radeon_bo_fini(rdev);
3977         radeon_atombios_fini(rdev);
3978         kfree(rdev->bios);
3979         rdev->bios = NULL;
3980 }
3981
3982 /*
3983  * Due to how kexec works, it can leave the hw fully initialised when it
3984  * boots the new kernel. However doing our init sequence with the CP and
3985  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3986  * do some quick sanity checks and restore sane values to avoid this
3987  * problem.
3988  */
3989 void r100_restore_sanity(struct radeon_device *rdev)
3990 {
3991         u32 tmp;
3992
3993         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3994         if (tmp) {
3995                 WREG32(RADEON_CP_CSQ_CNTL, 0);
3996         }
3997         tmp = RREG32(RADEON_CP_RB_CNTL);
3998         if (tmp) {
3999                 WREG32(RADEON_CP_RB_CNTL, 0);
4000         }
4001         tmp = RREG32(RADEON_SCRATCH_UMSK);
4002         if (tmp) {
4003                 WREG32(RADEON_SCRATCH_UMSK, 0);
4004         }
4005 }
4006
4007 int r100_init(struct radeon_device *rdev)
4008 {
4009         int r;
4010
4011         /* Register debugfs file specific to this group of asics */
4012         r100_debugfs_mc_info_init(rdev);
4013         /* Disable VGA */
4014         r100_vga_render_disable(rdev);
4015         /* Initialize scratch registers */
4016         radeon_scratch_init(rdev);
4017         /* Initialize surface registers */
4018         radeon_surface_init(rdev);
4019         /* sanity check some register to avoid hangs like after kexec */
4020         r100_restore_sanity(rdev);
4021         /* TODO: disable VGA need to use VGA request */
4022         /* BIOS*/
4023         if (!radeon_get_bios(rdev)) {
4024                 if (ASIC_IS_AVIVO(rdev))
4025                         return -EINVAL;
4026         }
4027         if (rdev->is_atom_bios) {
4028                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4029                 return -EINVAL;
4030         } else {
4031                 r = radeon_combios_init(rdev);
4032                 if (r)
4033                         return r;
4034         }
4035         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4036         if (radeon_asic_reset(rdev)) {
4037                 dev_warn(rdev->dev,
4038                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4039                         RREG32(R_000E40_RBBM_STATUS),
4040                         RREG32(R_0007C0_CP_STAT));
4041         }
4042         /* check if cards are posted or not */
4043         if (radeon_boot_test_post_card(rdev) == false)
4044                 return -EINVAL;
4045         /* Set asic errata */
4046         r100_errata(rdev);
4047         /* Initialize clocks */
4048         radeon_get_clock_info(rdev->ddev);
4049         /* initialize AGP */
4050         if (rdev->flags & RADEON_IS_AGP) {
4051                 r = radeon_agp_init(rdev);
4052                 if (r) {
4053                         radeon_agp_disable(rdev);
4054                 }
4055         }
4056         /* initialize VRAM */
4057         r100_mc_init(rdev);
4058         /* Fence driver */
4059         radeon_fence_driver_init(rdev);
4060         /* Memory manager */
4061         r = radeon_bo_init(rdev);
4062         if (r)
4063                 return r;
4064         if (rdev->flags & RADEON_IS_PCI) {
4065                 r = r100_pci_gart_init(rdev);
4066                 if (r)
4067                         return r;
4068         }
4069         r100_set_safe_registers(rdev);
4070
4071         /* Initialize power management */
4072         radeon_pm_init(rdev);
4073
4074         rdev->accel_working = true;
4075         r = r100_startup(rdev);
4076         if (r) {
4077                 /* Somethings want wront with the accel init stop accel */
4078                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4079                 r100_cp_fini(rdev);
4080                 radeon_wb_fini(rdev);
4081                 radeon_ib_pool_fini(rdev);
4082                 radeon_irq_kms_fini(rdev);
4083                 if (rdev->flags & RADEON_IS_PCI)
4084                         r100_pci_gart_fini(rdev);
4085                 rdev->accel_working = false;
4086         }
4087         return 0;
4088 }
4089
4090 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4091 {
4092         unsigned long flags;
4093         uint32_t ret;
4094
4095         spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4096         writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4097         ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4098         spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4099         return ret;
4100 }
4101
4102 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4103 {
4104         unsigned long flags;
4105
4106         spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4107         writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4108         writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4109         spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4110 }
4111
4112 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4113 {
4114         if (reg < rdev->rio_mem_size)
4115                 return ioread32(rdev->rio_mem + reg);
4116         else {
4117                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4118                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4119         }
4120 }
4121
4122 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4123 {
4124         if (reg < rdev->rio_mem_size)
4125                 iowrite32(v, rdev->rio_mem + reg);
4126         else {
4127                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4128                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4129         }
4130 }