tipc: fix bug in link failover handling
[linux-2.6-microblaze.git] / drivers / gpu / drm / radeon / evergreen_hdmi.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Christian König.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Christian König
25  *          Rafał Miłecki
26  */
27 #include <linux/hdmi.h>
28 #include <drm/drmP.h>
29 #include <drm/radeon_drm.h>
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "radeon_audio.h"
33 #include "evergreend.h"
34 #include "atom.h"
35
36 /* enable the audio stream */
37 void dce4_audio_enable(struct radeon_device *rdev,
38                               struct r600_audio_pin *pin,
39                               u8 enable_mask)
40 {
41         u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
42
43         if (!pin)
44                 return;
45
46         if (enable_mask) {
47                 tmp |= AUDIO_ENABLED;
48                 if (enable_mask & 1)
49                         tmp |= PIN0_AUDIO_ENABLED;
50                 if (enable_mask & 2)
51                         tmp |= PIN1_AUDIO_ENABLED;
52                 if (enable_mask & 4)
53                         tmp |= PIN2_AUDIO_ENABLED;
54                 if (enable_mask & 8)
55                         tmp |= PIN3_AUDIO_ENABLED;
56         } else {
57                 tmp &= ~(AUDIO_ENABLED |
58                          PIN0_AUDIO_ENABLED |
59                          PIN1_AUDIO_ENABLED |
60                          PIN2_AUDIO_ENABLED |
61                          PIN3_AUDIO_ENABLED);
62         }
63
64         WREG32(AZ_HOT_PLUG_CONTROL, tmp);
65 }
66
67 void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
68         const struct radeon_hdmi_acr *acr)
69 {
70         struct drm_device *dev = encoder->dev;
71         struct radeon_device *rdev = dev->dev_private;
72         int bpc = 8;
73
74         if (encoder->crtc) {
75                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
76                 bpc = radeon_crtc->bpc;
77         }
78
79         if (bpc > 8)
80                 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
81                         HDMI_ACR_AUTO_SEND);    /* allow hw to sent ACR packets when required */
82         else
83                 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
84                         HDMI_ACR_SOURCE |               /* select SW CTS value */
85                         HDMI_ACR_AUTO_SEND);    /* allow hw to sent ACR packets when required */
86
87         WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
88         WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
89
90         WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
91         WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
92
93         WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
94         WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
95 }
96
97 void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
98                 struct drm_connector *connector, struct drm_display_mode *mode)
99 {
100         struct radeon_device *rdev = encoder->dev->dev_private;
101         u32 tmp = 0;
102
103         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
104                 if (connector->latency_present[1])
105                         tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
106                                 AUDIO_LIPSYNC(connector->audio_latency[1]);
107                 else
108                         tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
109         } else {
110                 if (connector->latency_present[0])
111                         tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
112                                 AUDIO_LIPSYNC(connector->audio_latency[0]);
113                 else
114                         tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
115         }
116         WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
117 }
118
119 void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
120         u8 *sadb, int sad_count)
121 {
122         struct radeon_device *rdev = encoder->dev->dev_private;
123         u32 tmp;
124
125         /* program the speaker allocation */
126         tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
127         tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
128         /* set HDMI mode */
129         tmp |= HDMI_CONNECTION;
130         if (sad_count)
131                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
132         else
133                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
134         WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
135 }
136
137 void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
138         u8 *sadb, int sad_count)
139 {
140         struct radeon_device *rdev = encoder->dev->dev_private;
141         u32 tmp;
142
143         /* program the speaker allocation */
144         tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
145         tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
146         /* set DP mode */
147         tmp |= DP_CONNECTION;
148         if (sad_count)
149                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
150         else
151                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
152         WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
153 }
154
155 void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
156         struct cea_sad *sads, int sad_count)
157 {
158         int i;
159         struct radeon_device *rdev = encoder->dev->dev_private;
160         static const u16 eld_reg_to_type[][2] = {
161                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
162                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
163                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
164                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
165                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
166                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
167                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
168                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
169                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
170                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
171                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
172                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
173         };
174
175         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
176                 u32 value = 0;
177                 u8 stereo_freqs = 0;
178                 int max_channels = -1;
179                 int j;
180
181                 for (j = 0; j < sad_count; j++) {
182                         struct cea_sad *sad = &sads[j];
183
184                         if (sad->format == eld_reg_to_type[i][1]) {
185                                 if (sad->channels > max_channels) {
186                                         value = MAX_CHANNELS(sad->channels) |
187                                                 DESCRIPTOR_BYTE_2(sad->byte2) |
188                                                 SUPPORTED_FREQUENCIES(sad->freq);
189                                         max_channels = sad->channels;
190                                 }
191
192                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
193                                         stereo_freqs |= sad->freq;
194                                 else
195                                         break;
196                         }
197                 }
198
199                 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
200
201                 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
202         }
203 }
204
205 /*
206  * build a AVI Info Frame
207  */
208 void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,
209     unsigned char *buffer, size_t size)
210 {
211         uint8_t *frame = buffer + 3;
212
213         WREG32(AFMT_AVI_INFO0 + offset,
214                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
215         WREG32(AFMT_AVI_INFO1 + offset,
216                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
217         WREG32(AFMT_AVI_INFO2 + offset,
218                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
219         WREG32(AFMT_AVI_INFO3 + offset,
220                 frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
221
222         WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
223                 HDMI_AVI_INFO_SEND |    /* enable AVI info frames */
224                 HDMI_AVI_INFO_CONT);    /* required for audio info values to be updated */
225
226         WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
227                 HDMI_AVI_INFO_LINE(2),  /* anything other than 0 */
228                 ~HDMI_AVI_INFO_LINE_MASK);
229 }
230
231 void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
232         struct radeon_crtc *crtc, unsigned int clock)
233 {
234         unsigned int max_ratio = clock / 24000;
235         u32 dto_phase;
236         u32 wallclock_ratio;
237         u32 value;
238
239         if (max_ratio >= 8) {
240                 dto_phase = 192 * 1000;
241                 wallclock_ratio = 3;
242         } else if (max_ratio >= 4) {
243                 dto_phase = 96 * 1000;
244                 wallclock_ratio = 2;
245         } else if (max_ratio >= 2) {
246                 dto_phase = 48 * 1000;
247                 wallclock_ratio = 1;
248         } else {
249                 dto_phase = 24 * 1000;
250                 wallclock_ratio = 0;
251         }
252
253         value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
254         value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
255         value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;
256         WREG32(DCCG_AUDIO_DTO0_CNTL, value);
257
258         /* Two dtos; generally use dto0 for HDMI */
259         value = 0;
260
261         if (crtc)
262                 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
263
264         WREG32(DCCG_AUDIO_DTO_SOURCE, value);
265
266         /* Express [24MHz / target pixel clock] as an exact rational
267          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
268          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
269          */
270         WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
271         WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
272 }
273
274 void dce4_dp_audio_set_dto(struct radeon_device *rdev,
275         struct radeon_crtc *crtc, unsigned int clock)
276 {
277         u32 value;
278
279         value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
280         value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO;
281         WREG32(DCCG_AUDIO_DTO1_CNTL, value);
282
283         /* Two dtos; generally use dto1 for DP */
284         value = 0;
285         value |= DCCG_AUDIO_DTO_SEL;
286
287         if (crtc)
288                 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
289
290         WREG32(DCCG_AUDIO_DTO_SOURCE, value);
291
292         /* Express [24MHz / target pixel clock] as an exact rational
293          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
294          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
295          */
296         WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
297         WREG32(DCCG_AUDIO_DTO1_MODULE, rdev->clock.max_pixel_clock * 10);
298 }
299
300 void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
301 {
302         struct drm_device *dev = encoder->dev;
303         struct radeon_device *rdev = dev->dev_private;
304
305         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
306                 HDMI_NULL_SEND |        /* send null packets when required */
307                 HDMI_GC_SEND |          /* send general control packets */
308                 HDMI_GC_CONT);          /* send general control packets every frame */
309 }
310
311 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)
312 {
313         struct drm_device *dev = encoder->dev;
314         struct radeon_device *rdev = dev->dev_private;
315         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
316         uint32_t val;
317
318         val = RREG32(HDMI_CONTROL + offset);
319         val &= ~HDMI_DEEP_COLOR_ENABLE;
320         val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
321
322         switch (bpc) {
323                 case 0:
324                 case 6:
325                 case 8:
326                 case 16:
327                 default:
328                         DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
329                                          connector->name, bpc);
330                         break;
331                 case 10:
332                         val |= HDMI_DEEP_COLOR_ENABLE;
333                         val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
334                         DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
335                                          connector->name);
336                         break;
337                 case 12:
338                         val |= HDMI_DEEP_COLOR_ENABLE;
339                         val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
340                         DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
341                                          connector->name);
342                         break;
343         }
344
345         WREG32(HDMI_CONTROL + offset, val);
346 }
347
348 void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)
349 {
350         struct drm_device *dev = encoder->dev;
351         struct radeon_device *rdev = dev->dev_private;
352
353         WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
354                 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
355                 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
356
357         WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
358                 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
359
360         WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
361                 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
362
363         WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
364                 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
365                 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
366
367         WREG32(AFMT_60958_0 + offset,
368                 AFMT_60958_CS_CHANNEL_NUMBER_L(1));
369
370         WREG32(AFMT_60958_1 + offset,
371                 AFMT_60958_CS_CHANNEL_NUMBER_R(2));
372
373         WREG32(AFMT_60958_2 + offset,
374                 AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
375                 AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
376                 AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
377                 AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
378                 AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
379                 AFMT_60958_CS_CHANNEL_NUMBER_7(8));
380
381         WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
382                 AFMT_AUDIO_CHANNEL_ENABLE(0xff));
383
384         /* allow 60958 channel status and send audio packets fields to be updated */
385         WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
386                 AFMT_AUDIO_SAMPLE_SEND | AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE);
387 }
388
389
390 void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
391 {
392         struct drm_device *dev = encoder->dev;
393         struct radeon_device *rdev = dev->dev_private;
394
395         if (mute)
396                 WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);
397         else
398                 WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);
399 }
400
401 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
402 {
403         struct drm_device *dev = encoder->dev;
404         struct radeon_device *rdev = dev->dev_private;
405         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
406         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
407
408         if (!dig || !dig->afmt)
409                 return;
410
411         /* Silent, r600_hdmi_enable will raise WARN for us */
412         if (enable && dig->afmt->enabled)
413                 return;
414         if (!enable && !dig->afmt->enabled)
415                 return;
416
417         if (!enable && dig->afmt->pin) {
418                 radeon_audio_enable(rdev, dig->afmt->pin, 0);
419                 dig->afmt->pin = NULL;
420         }
421
422         dig->afmt->enabled = enable;
423
424         DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
425                   enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
426 }
427
428 void evergreen_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable)
429 {
430         struct drm_device *dev = encoder->dev;
431         struct radeon_device *rdev = dev->dev_private;
432         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
433         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
434         uint32_t offset;
435
436         if (!dig || !dig->afmt)
437                 return;
438
439         offset = dig->afmt->offset;
440
441         if (enable) {
442                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
443                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
444                 struct radeon_connector_atom_dig *dig_connector;
445                 uint32_t val;
446
447                 if (dig->afmt->enabled)
448                         return;
449
450                 WREG32(EVERGREEN_DP_SEC_TIMESTAMP + offset, EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
451
452                 if (radeon_connector->con_priv) {
453                         dig_connector = radeon_connector->con_priv;
454                         val = RREG32(EVERGREEN_DP_SEC_AUD_N + offset);
455                         val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);
456
457                         if (dig_connector->dp_clock == 162000)
458                                 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3);
459                         else
460                                 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);
461
462                         WREG32(EVERGREEN_DP_SEC_AUD_N + offset, val);
463                 }
464
465                 WREG32(EVERGREEN_DP_SEC_CNTL + offset,
466                         EVERGREEN_DP_SEC_ASP_ENABLE |           /* Audio packet transmission */
467                         EVERGREEN_DP_SEC_ATP_ENABLE |           /* Audio timestamp packet transmission */
468                         EVERGREEN_DP_SEC_AIP_ENABLE |           /* Audio infoframe packet transmission */
469                         EVERGREEN_DP_SEC_STREAM_ENABLE);        /* Master enable for secondary stream engine */
470                 radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
471         } else {
472                 if (!dig->afmt->enabled)
473                         return;
474
475                 WREG32(EVERGREEN_DP_SEC_CNTL + offset, 0);
476                 radeon_audio_enable(rdev, dig->afmt->pin, 0);
477         }
478
479         dig->afmt->enabled = enable;
480 }