2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <linux/backlight.h>
28 #include <linux/dmi.h>
29 #include <linux/pci.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/drm_file.h>
33 #include <drm/radeon_drm.h>
36 #include "radeon_atombios.h"
38 #include "radeon_asic.h"
39 #include "radeon_audio.h"
41 extern int atom_debug;
44 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
49 if (rdev->family >= CHIP_R600)
50 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
52 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
54 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
55 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
57 return backlight_level;
61 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
66 if (rdev->family >= CHIP_R600)
67 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
69 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
71 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
72 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
73 ATOM_S2_CURRENT_BL_LEVEL_MASK);
75 if (rdev->family >= CHIP_R600)
76 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
78 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
82 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
84 struct drm_device *dev = radeon_encoder->base.dev;
85 struct radeon_device *rdev = dev->dev_private;
87 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
90 return radeon_atom_get_backlight_level_from_reg(rdev);
94 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
96 struct drm_encoder *encoder = &radeon_encoder->base;
97 struct drm_device *dev = radeon_encoder->base.dev;
98 struct radeon_device *rdev = dev->dev_private;
99 struct radeon_encoder_atom_dig *dig;
100 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
103 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
106 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
107 radeon_encoder->enc_priv) {
108 dig = radeon_encoder->enc_priv;
109 dig->backlight_level = level;
110 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
112 switch (radeon_encoder->encoder_id) {
113 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
114 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
115 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
116 if (dig->backlight_level == 0) {
117 args.ucAction = ATOM_LCD_BLOFF;
118 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
120 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
121 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
122 args.ucAction = ATOM_LCD_BLON;
123 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
127 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
128 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
129 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
131 if (dig->backlight_level == 0)
132 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
134 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
135 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
144 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
146 static u8 radeon_atom_bl_level(struct backlight_device *bd)
150 /* Convert brightness to hardware level */
151 if (bd->props.brightness < 0)
153 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
154 level = RADEON_MAX_BL_LEVEL;
156 level = bd->props.brightness;
161 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
163 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
164 struct radeon_encoder *radeon_encoder = pdata->encoder;
166 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
171 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
173 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
174 struct radeon_encoder *radeon_encoder = pdata->encoder;
175 struct drm_device *dev = radeon_encoder->base.dev;
176 struct radeon_device *rdev = dev->dev_private;
178 return radeon_atom_get_backlight_level_from_reg(rdev);
181 static const struct backlight_ops radeon_atom_backlight_ops = {
182 .get_brightness = radeon_atom_backlight_get_brightness,
183 .update_status = radeon_atom_backlight_update_status,
186 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
187 struct drm_connector *drm_connector)
189 struct drm_device *dev = radeon_encoder->base.dev;
190 struct radeon_device *rdev = dev->dev_private;
191 struct backlight_device *bd;
192 struct backlight_properties props;
193 struct radeon_backlight_privdata *pdata;
194 struct radeon_encoder_atom_dig *dig;
197 /* Mac laptops with multiple GPUs use the gmux driver for backlight
198 * so don't register a backlight device
200 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
201 (rdev->pdev->device == 0x6741))
204 if (!radeon_encoder->enc_priv)
207 if (!rdev->is_atom_bios)
210 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
213 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
215 DRM_ERROR("Memory allocation failed\n");
219 memset(&props, 0, sizeof(props));
220 props.max_brightness = RADEON_MAX_BL_LEVEL;
221 props.type = BACKLIGHT_RAW;
222 snprintf(bl_name, sizeof(bl_name),
223 "radeon_bl%d", dev->primary->index);
224 bd = backlight_device_register(bl_name, drm_connector->kdev,
225 pdata, &radeon_atom_backlight_ops, &props);
227 DRM_ERROR("Backlight registration failed\n");
231 pdata->encoder = radeon_encoder;
233 dig = radeon_encoder->enc_priv;
236 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
237 /* Set a reasonable default here if the level is 0 otherwise
238 * fbdev will attempt to turn the backlight on after console
239 * unblanking and it will try and restore 0 which turns the backlight
242 if (bd->props.brightness == 0)
243 bd->props.brightness = RADEON_MAX_BL_LEVEL;
244 bd->props.power = FB_BLANK_UNBLANK;
245 backlight_update_status(bd);
247 DRM_INFO("radeon atom DIG backlight initialized\n");
248 rdev->mode_info.bl_encoder = radeon_encoder;
257 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
259 struct drm_device *dev = radeon_encoder->base.dev;
260 struct radeon_device *rdev = dev->dev_private;
261 struct backlight_device *bd = NULL;
262 struct radeon_encoder_atom_dig *dig;
264 if (!radeon_encoder->enc_priv)
267 if (!rdev->is_atom_bios)
270 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
273 dig = radeon_encoder->enc_priv;
278 struct radeon_legacy_backlight_privdata *pdata;
280 pdata = bl_get_data(bd);
281 backlight_device_unregister(bd);
284 DRM_INFO("radeon atom LVDS backlight unloaded\n");
288 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
290 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
294 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
300 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
301 const struct drm_display_mode *mode,
302 struct drm_display_mode *adjusted_mode)
304 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
305 struct drm_device *dev = encoder->dev;
306 struct radeon_device *rdev = dev->dev_private;
308 /* set the active encoder to connector routing */
309 radeon_encoder_set_active_device(encoder);
310 drm_mode_set_crtcinfo(adjusted_mode, 0);
313 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
314 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
315 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
317 /* vertical FP must be at least 1 */
318 if (mode->crtc_vsync_start == mode->crtc_vdisplay)
319 adjusted_mode->crtc_vsync_start++;
321 /* get the native mode for scaling */
322 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
323 radeon_panel_mode_fixup(encoder, adjusted_mode);
324 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
325 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
327 if (tv_dac->tv_std == TV_STD_NTSC ||
328 tv_dac->tv_std == TV_STD_NTSC_J ||
329 tv_dac->tv_std == TV_STD_PAL_M)
330 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
332 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
334 } else if (radeon_encoder->rmx_type != RMX_OFF) {
335 radeon_panel_mode_fixup(encoder, adjusted_mode);
338 if (ASIC_IS_DCE3(rdev) &&
339 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
340 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
341 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
342 radeon_dp_set_link_config(connector, adjusted_mode);
349 atombios_dac_setup(struct drm_encoder *encoder, int action)
351 struct drm_device *dev = encoder->dev;
352 struct radeon_device *rdev = dev->dev_private;
353 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
354 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
356 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
358 memset(&args, 0, sizeof(args));
360 switch (radeon_encoder->encoder_id) {
361 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
362 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
363 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
365 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
366 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
367 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
371 args.ucAction = action;
373 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
374 args.ucDacStandard = ATOM_DAC1_PS2;
375 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
376 args.ucDacStandard = ATOM_DAC1_CV;
378 switch (dac_info->tv_std) {
381 case TV_STD_SCART_PAL:
384 args.ucDacStandard = ATOM_DAC1_PAL;
390 args.ucDacStandard = ATOM_DAC1_NTSC;
394 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
396 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
401 atombios_tv_setup(struct drm_encoder *encoder, int action)
403 struct drm_device *dev = encoder->dev;
404 struct radeon_device *rdev = dev->dev_private;
405 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
406 TV_ENCODER_CONTROL_PS_ALLOCATION args;
408 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
410 memset(&args, 0, sizeof(args));
412 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
414 args.sTVEncoder.ucAction = action;
416 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
417 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
419 switch (dac_info->tv_std) {
421 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
424 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
427 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
430 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
433 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
435 case TV_STD_SCART_PAL:
436 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
439 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
442 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
445 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
450 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
452 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
456 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
461 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
462 bpc = radeon_crtc->bpc;
467 return PANEL_BPC_UNDEFINE;
469 return PANEL_6BIT_PER_COLOR;
472 return PANEL_8BIT_PER_COLOR;
474 return PANEL_10BIT_PER_COLOR;
476 return PANEL_12BIT_PER_COLOR;
478 return PANEL_16BIT_PER_COLOR;
482 union dvo_encoder_control {
483 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
484 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
485 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
486 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
490 atombios_dvo_setup(struct drm_encoder *encoder, int action)
492 struct drm_device *dev = encoder->dev;
493 struct radeon_device *rdev = dev->dev_private;
494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
495 union dvo_encoder_control args;
496 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
499 memset(&args, 0, sizeof(args));
501 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
504 /* some R4xx chips have the wrong frev */
505 if (rdev->family <= CHIP_RV410)
513 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
515 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
516 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
518 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
522 args.dvo.sDVOEncoder.ucAction = action;
523 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
524 /* DFP1, CRT1, TV1 depending on the type of port */
525 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
527 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
528 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
532 args.dvo_v3.ucAction = action;
533 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
534 args.dvo_v3.ucDVOConfig = 0; /* XXX */
538 args.dvo_v4.ucAction = action;
539 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
540 args.dvo_v4.ucDVOConfig = 0; /* XXX */
541 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
544 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
549 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
553 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
556 union lvds_encoder_control {
557 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
558 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
562 atombios_digital_setup(struct drm_encoder *encoder, int action)
564 struct drm_device *dev = encoder->dev;
565 struct radeon_device *rdev = dev->dev_private;
566 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
567 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
568 union lvds_encoder_control args;
570 int hdmi_detected = 0;
576 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
579 memset(&args, 0, sizeof(args));
581 switch (radeon_encoder->encoder_id) {
582 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
583 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
585 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
586 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
587 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
589 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
590 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
591 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
593 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
597 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
606 args.v1.ucAction = action;
608 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
609 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
610 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
611 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
612 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
613 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
614 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
617 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
618 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
619 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
620 /*if (pScrn->rgbBits == 8) */
621 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
627 args.v2.ucAction = action;
629 if (dig->coherent_mode)
630 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
633 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
634 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
635 args.v2.ucTruncate = 0;
636 args.v2.ucSpatial = 0;
637 args.v2.ucTemporal = 0;
639 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
640 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
641 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
642 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
643 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
644 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
645 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
647 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
648 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
649 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
650 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
651 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
652 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
656 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
657 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
658 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
662 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
667 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
671 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
675 atombios_get_encoder_mode(struct drm_encoder *encoder)
677 struct drm_device *dev = encoder->dev;
678 struct radeon_device *rdev = dev->dev_private;
679 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
680 struct drm_connector *connector;
681 struct radeon_connector *radeon_connector;
682 struct radeon_connector_atom_dig *dig_connector;
683 struct radeon_encoder_atom_dig *dig_enc;
685 if (radeon_encoder_is_digital(encoder)) {
686 dig_enc = radeon_encoder->enc_priv;
687 if (dig_enc->active_mst_links)
688 return ATOM_ENCODER_MODE_DP_MST;
690 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
691 return ATOM_ENCODER_MODE_DP_MST;
692 /* dp bridges are always DP */
693 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
694 return ATOM_ENCODER_MODE_DP;
696 /* DVO is always DVO */
697 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
698 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
699 return ATOM_ENCODER_MODE_DVO;
701 connector = radeon_get_connector_for_encoder(encoder);
702 /* if we don't have an active device yet, just use one of
703 * the connectors tied to the encoder.
706 connector = radeon_get_connector_for_encoder_init(encoder);
707 radeon_connector = to_radeon_connector(connector);
709 switch (connector->connector_type) {
710 case DRM_MODE_CONNECTOR_DVII:
711 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
712 if (radeon_audio != 0) {
713 if (radeon_connector->use_digital &&
714 (radeon_connector->audio == RADEON_AUDIO_ENABLE))
715 return ATOM_ENCODER_MODE_HDMI;
716 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
717 (radeon_connector->audio == RADEON_AUDIO_AUTO))
718 return ATOM_ENCODER_MODE_HDMI;
719 else if (radeon_connector->use_digital)
720 return ATOM_ENCODER_MODE_DVI;
722 return ATOM_ENCODER_MODE_CRT;
723 } else if (radeon_connector->use_digital) {
724 return ATOM_ENCODER_MODE_DVI;
726 return ATOM_ENCODER_MODE_CRT;
729 case DRM_MODE_CONNECTOR_DVID:
730 case DRM_MODE_CONNECTOR_HDMIA:
732 if (radeon_audio != 0) {
733 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
734 return ATOM_ENCODER_MODE_HDMI;
735 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
736 (radeon_connector->audio == RADEON_AUDIO_AUTO))
737 return ATOM_ENCODER_MODE_HDMI;
739 return ATOM_ENCODER_MODE_DVI;
741 return ATOM_ENCODER_MODE_DVI;
744 case DRM_MODE_CONNECTOR_LVDS:
745 return ATOM_ENCODER_MODE_LVDS;
747 case DRM_MODE_CONNECTOR_DisplayPort:
748 dig_connector = radeon_connector->con_priv;
749 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
750 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
751 if (radeon_audio != 0 &&
752 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
753 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
754 return ATOM_ENCODER_MODE_DP_AUDIO;
755 return ATOM_ENCODER_MODE_DP;
756 } else if (radeon_audio != 0) {
757 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
758 return ATOM_ENCODER_MODE_HDMI;
759 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
760 (radeon_connector->audio == RADEON_AUDIO_AUTO))
761 return ATOM_ENCODER_MODE_HDMI;
763 return ATOM_ENCODER_MODE_DVI;
765 return ATOM_ENCODER_MODE_DVI;
768 case DRM_MODE_CONNECTOR_eDP:
769 if (radeon_audio != 0 &&
770 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
771 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
772 return ATOM_ENCODER_MODE_DP_AUDIO;
773 return ATOM_ENCODER_MODE_DP;
774 case DRM_MODE_CONNECTOR_DVIA:
775 case DRM_MODE_CONNECTOR_VGA:
776 return ATOM_ENCODER_MODE_CRT;
778 case DRM_MODE_CONNECTOR_Composite:
779 case DRM_MODE_CONNECTOR_SVIDEO:
780 case DRM_MODE_CONNECTOR_9PinDIN:
782 return ATOM_ENCODER_MODE_TV;
783 /*return ATOM_ENCODER_MODE_CV;*/
789 * DIG Encoder/Transmitter Setup
792 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
793 * Supports up to 3 digital outputs
794 * - 2 DIG encoder blocks.
795 * DIG1 can drive UNIPHY link A or link B
796 * DIG2 can drive UNIPHY link B or LVTMA
799 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
800 * Supports up to 5 digital outputs
801 * - 2 DIG encoder blocks.
802 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
805 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
806 * Supports up to 6 digital outputs
807 * - 6 DIG encoder blocks.
808 * - DIG to PHY mapping is hardcoded
809 * DIG1 drives UNIPHY0 link A, A+B
810 * DIG2 drives UNIPHY0 link B
811 * DIG3 drives UNIPHY1 link A, A+B
812 * DIG4 drives UNIPHY1 link B
813 * DIG5 drives UNIPHY2 link A, A+B
814 * DIG6 drives UNIPHY2 link B
817 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
818 * Supports up to 6 digital outputs
819 * - 2 DIG encoder blocks.
821 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
823 * DIG1 drives UNIPHY0/1/2 link A
824 * DIG2 drives UNIPHY0/1/2 link B
827 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
829 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
830 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
831 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
832 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
835 union dig_encoder_control {
836 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
837 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
838 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
839 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
843 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
845 struct drm_device *dev = encoder->dev;
846 struct radeon_device *rdev = dev->dev_private;
847 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
848 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
849 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
850 union dig_encoder_control args;
854 int dp_lane_count = 0;
855 int hpd_id = RADEON_HPD_NONE;
858 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
859 struct radeon_connector_atom_dig *dig_connector =
860 radeon_connector->con_priv;
862 dp_clock = dig_connector->dp_clock;
863 dp_lane_count = dig_connector->dp_lane_count;
864 hpd_id = radeon_connector->hpd.hpd;
867 /* no dig encoder assigned */
868 if (dig->dig_encoder == -1)
871 memset(&args, 0, sizeof(args));
873 if (ASIC_IS_DCE4(rdev))
874 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
876 if (dig->dig_encoder)
877 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
879 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
882 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
889 args.v1.ucAction = action;
890 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
891 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
892 args.v3.ucPanelMode = panel_mode;
894 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
896 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
897 args.v1.ucLaneNum = dp_lane_count;
898 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
899 args.v1.ucLaneNum = 8;
901 args.v1.ucLaneNum = 4;
903 switch (radeon_encoder->encoder_id) {
904 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
905 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
907 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
908 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
909 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
911 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
912 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
916 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
918 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
920 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
921 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
926 args.v3.ucAction = action;
927 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
928 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
929 args.v3.ucPanelMode = panel_mode;
931 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
933 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
934 args.v3.ucLaneNum = dp_lane_count;
935 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
936 args.v3.ucLaneNum = 8;
938 args.v3.ucLaneNum = 4;
940 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
941 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
942 if (enc_override != -1)
943 args.v3.acConfig.ucDigSel = enc_override;
945 args.v3.acConfig.ucDigSel = dig->dig_encoder;
946 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
949 args.v4.ucAction = action;
950 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
951 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
952 args.v4.ucPanelMode = panel_mode;
954 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
956 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
957 args.v4.ucLaneNum = dp_lane_count;
958 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
959 args.v4.ucLaneNum = 8;
961 args.v4.ucLaneNum = 4;
963 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
964 if (dp_clock == 540000)
965 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
966 else if (dp_clock == 324000)
967 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
968 else if (dp_clock == 270000)
969 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
971 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
974 if (enc_override != -1)
975 args.v4.acConfig.ucDigSel = enc_override;
977 args.v4.acConfig.ucDigSel = dig->dig_encoder;
978 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
979 if (hpd_id == RADEON_HPD_NONE)
980 args.v4.ucHPD_ID = 0;
982 args.v4.ucHPD_ID = hpd_id + 1;
985 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
990 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
994 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
999 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
1001 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
1004 union dig_transmitter_control {
1005 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
1006 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
1007 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1008 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1009 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1013 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1015 struct drm_device *dev = encoder->dev;
1016 struct radeon_device *rdev = dev->dev_private;
1017 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1018 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1019 struct drm_connector *connector;
1020 union dig_transmitter_control args;
1026 int dp_lane_count = 0;
1027 int connector_object_id = 0;
1028 int igp_lane_info = 0;
1029 int dig_encoder = dig->dig_encoder;
1030 int hpd_id = RADEON_HPD_NONE;
1032 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1033 connector = radeon_get_connector_for_encoder_init(encoder);
1034 /* just needed to avoid bailing in the encoder check. the encoder
1035 * isn't used for init
1039 connector = radeon_get_connector_for_encoder(encoder);
1042 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1043 struct radeon_connector_atom_dig *dig_connector =
1044 radeon_connector->con_priv;
1046 hpd_id = radeon_connector->hpd.hpd;
1047 dp_clock = dig_connector->dp_clock;
1048 dp_lane_count = dig_connector->dp_lane_count;
1049 connector_object_id =
1050 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1051 igp_lane_info = dig_connector->igp_lane_info;
1054 if (encoder->crtc) {
1055 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1056 pll_id = radeon_crtc->pll_id;
1059 /* no dig encoder assigned */
1060 if (dig_encoder == -1)
1063 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1066 memset(&args, 0, sizeof(args));
1068 switch (radeon_encoder->encoder_id) {
1069 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1070 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1072 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1073 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1074 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1075 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1076 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1078 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1079 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1083 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1090 args.v1.ucAction = action;
1091 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1092 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1093 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1094 args.v1.asMode.ucLaneSel = lane_num;
1095 args.v1.asMode.ucLaneSet = lane_set;
1098 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1099 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1100 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1102 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1105 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1108 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1110 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1112 if ((rdev->flags & RADEON_IS_IGP) &&
1113 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1115 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1116 if (igp_lane_info & 0x1)
1117 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1118 else if (igp_lane_info & 0x2)
1119 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1120 else if (igp_lane_info & 0x4)
1121 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1122 else if (igp_lane_info & 0x8)
1123 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1125 if (igp_lane_info & 0x3)
1126 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1127 else if (igp_lane_info & 0xc)
1128 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1133 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1135 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1138 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1139 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1140 if (dig->coherent_mode)
1141 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1142 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1143 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1147 args.v2.ucAction = action;
1148 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1149 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1150 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1151 args.v2.asMode.ucLaneSel = lane_num;
1152 args.v2.asMode.ucLaneSet = lane_set;
1155 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1156 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1157 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1159 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1162 args.v2.acConfig.ucEncoderSel = dig_encoder;
1164 args.v2.acConfig.ucLinkSel = 1;
1166 switch (radeon_encoder->encoder_id) {
1167 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1168 args.v2.acConfig.ucTransmitterSel = 0;
1170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1171 args.v2.acConfig.ucTransmitterSel = 1;
1173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1174 args.v2.acConfig.ucTransmitterSel = 2;
1179 args.v2.acConfig.fCoherentMode = 1;
1180 args.v2.acConfig.fDPConnector = 1;
1181 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1182 if (dig->coherent_mode)
1183 args.v2.acConfig.fCoherentMode = 1;
1184 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1185 args.v2.acConfig.fDualLinkConnector = 1;
1189 args.v3.ucAction = action;
1190 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1191 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1192 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1193 args.v3.asMode.ucLaneSel = lane_num;
1194 args.v3.asMode.ucLaneSet = lane_set;
1197 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1198 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1199 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1201 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1205 args.v3.ucLaneNum = dp_lane_count;
1206 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1207 args.v3.ucLaneNum = 8;
1209 args.v3.ucLaneNum = 4;
1212 args.v3.acConfig.ucLinkSel = 1;
1213 if (dig_encoder & 1)
1214 args.v3.acConfig.ucEncoderSel = 1;
1216 /* Select the PLL for the PHY
1217 * DP PHY should be clocked from external src if there is
1220 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1221 if (is_dp && rdev->clock.dp_extclk)
1222 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1224 args.v3.acConfig.ucRefClkSource = pll_id;
1226 switch (radeon_encoder->encoder_id) {
1227 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1228 args.v3.acConfig.ucTransmitterSel = 0;
1230 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1231 args.v3.acConfig.ucTransmitterSel = 1;
1233 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1234 args.v3.acConfig.ucTransmitterSel = 2;
1239 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1240 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1241 if (dig->coherent_mode)
1242 args.v3.acConfig.fCoherentMode = 1;
1243 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1244 args.v3.acConfig.fDualLinkConnector = 1;
1248 args.v4.ucAction = action;
1249 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1250 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1251 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1252 args.v4.asMode.ucLaneSel = lane_num;
1253 args.v4.asMode.ucLaneSet = lane_set;
1256 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1257 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1258 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1260 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1264 args.v4.ucLaneNum = dp_lane_count;
1265 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1266 args.v4.ucLaneNum = 8;
1268 args.v4.ucLaneNum = 4;
1271 args.v4.acConfig.ucLinkSel = 1;
1272 if (dig_encoder & 1)
1273 args.v4.acConfig.ucEncoderSel = 1;
1275 /* Select the PLL for the PHY
1276 * DP PHY should be clocked from external src if there is
1279 /* On DCE5 DCPLL usually generates the DP ref clock */
1281 if (rdev->clock.dp_extclk)
1282 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1284 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1286 args.v4.acConfig.ucRefClkSource = pll_id;
1288 switch (radeon_encoder->encoder_id) {
1289 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1290 args.v4.acConfig.ucTransmitterSel = 0;
1292 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1293 args.v4.acConfig.ucTransmitterSel = 1;
1295 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1296 args.v4.acConfig.ucTransmitterSel = 2;
1301 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1302 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1303 if (dig->coherent_mode)
1304 args.v4.acConfig.fCoherentMode = 1;
1305 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1306 args.v4.acConfig.fDualLinkConnector = 1;
1310 args.v5.ucAction = action;
1312 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1314 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1316 switch (radeon_encoder->encoder_id) {
1317 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1319 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1321 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1323 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1325 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1327 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1329 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1331 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1333 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1335 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1336 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1340 args.v5.ucLaneNum = dp_lane_count;
1341 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1342 args.v5.ucLaneNum = 8;
1344 args.v5.ucLaneNum = 4;
1345 args.v5.ucConnObjId = connector_object_id;
1346 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1348 if (is_dp && rdev->clock.dp_extclk)
1349 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1351 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1354 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1355 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1356 if (dig->coherent_mode)
1357 args.v5.asConfig.ucCoherentMode = 1;
1359 if (hpd_id == RADEON_HPD_NONE)
1360 args.v5.asConfig.ucHPDSel = 0;
1362 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1363 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1364 args.v5.ucDPLaneSet = lane_set;
1367 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1372 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1376 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1380 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1382 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1386 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1388 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1389 struct drm_device *dev = radeon_connector->base.dev;
1390 struct radeon_device *rdev = dev->dev_private;
1391 union dig_transmitter_control args;
1392 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1395 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1398 if (!ASIC_IS_DCE4(rdev))
1401 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1402 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1405 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1408 memset(&args, 0, sizeof(args));
1410 args.v1.ucAction = action;
1412 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1414 /* wait for the panel to power up */
1415 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1418 for (i = 0; i < 300; i++) {
1419 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1429 union external_encoder_control {
1430 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1431 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1435 atombios_external_encoder_setup(struct drm_encoder *encoder,
1436 struct drm_encoder *ext_encoder,
1439 struct drm_device *dev = encoder->dev;
1440 struct radeon_device *rdev = dev->dev_private;
1441 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1442 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1443 union external_encoder_control args;
1444 struct drm_connector *connector;
1445 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1448 int dp_lane_count = 0;
1449 int connector_object_id = 0;
1450 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1452 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1453 connector = radeon_get_connector_for_encoder_init(encoder);
1455 connector = radeon_get_connector_for_encoder(encoder);
1458 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1459 struct radeon_connector_atom_dig *dig_connector =
1460 radeon_connector->con_priv;
1462 dp_clock = dig_connector->dp_clock;
1463 dp_lane_count = dig_connector->dp_lane_count;
1464 connector_object_id =
1465 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1468 memset(&args, 0, sizeof(args));
1470 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1475 /* no params on frev 1 */
1481 args.v1.sDigEncoder.ucAction = action;
1482 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1483 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1485 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1486 if (dp_clock == 270000)
1487 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1488 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1489 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1490 args.v1.sDigEncoder.ucLaneNum = 8;
1492 args.v1.sDigEncoder.ucLaneNum = 4;
1495 args.v3.sExtEncoder.ucAction = action;
1496 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1497 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1499 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1500 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1502 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1503 if (dp_clock == 270000)
1504 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1505 else if (dp_clock == 540000)
1506 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1507 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1508 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1509 args.v3.sExtEncoder.ucLaneNum = 8;
1511 args.v3.sExtEncoder.ucLaneNum = 4;
1513 case GRAPH_OBJECT_ENUM_ID1:
1514 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1516 case GRAPH_OBJECT_ENUM_ID2:
1517 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1519 case GRAPH_OBJECT_ENUM_ID3:
1520 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1523 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1526 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1531 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1534 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1538 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1540 struct drm_device *dev = encoder->dev;
1541 struct radeon_device *rdev = dev->dev_private;
1542 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1543 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1544 ENABLE_YUV_PS_ALLOCATION args;
1545 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1548 memset(&args, 0, sizeof(args));
1550 if (rdev->family >= CHIP_R600)
1551 reg = R600_BIOS_3_SCRATCH;
1553 reg = RADEON_BIOS_3_SCRATCH;
1555 /* XXX: fix up scratch reg handling */
1557 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1558 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1559 (radeon_crtc->crtc_id << 18)));
1560 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1561 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1566 args.ucEnable = ATOM_ENABLE;
1567 args.ucCRTC = radeon_crtc->crtc_id;
1569 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1575 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1577 struct drm_device *dev = encoder->dev;
1578 struct radeon_device *rdev = dev->dev_private;
1579 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1580 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1583 memset(&args, 0, sizeof(args));
1585 switch (radeon_encoder->encoder_id) {
1586 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1587 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1588 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1590 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1591 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1592 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1593 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1595 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1596 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1598 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1599 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1600 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1602 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1604 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1605 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1606 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1607 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1608 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1609 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1611 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1613 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1614 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1615 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1616 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1617 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1618 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1620 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1627 case DRM_MODE_DPMS_ON:
1628 args.ucAction = ATOM_ENABLE;
1629 /* workaround for DVOOutputControl on some RS690 systems */
1630 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1631 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1632 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1633 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1634 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1636 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1637 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1638 if (rdev->mode_info.bl_encoder) {
1639 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1641 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1643 args.ucAction = ATOM_LCD_BLON;
1644 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1648 case DRM_MODE_DPMS_STANDBY:
1649 case DRM_MODE_DPMS_SUSPEND:
1650 case DRM_MODE_DPMS_OFF:
1651 args.ucAction = ATOM_DISABLE;
1652 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1653 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1654 args.ucAction = ATOM_LCD_BLOFF;
1655 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1662 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1664 struct drm_device *dev = encoder->dev;
1665 struct radeon_device *rdev = dev->dev_private;
1666 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1667 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1668 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1669 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1670 struct radeon_connector *radeon_connector = NULL;
1671 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1672 bool travis_quirk = false;
1675 radeon_connector = to_radeon_connector(connector);
1676 radeon_dig_connector = radeon_connector->con_priv;
1677 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1678 ENCODER_OBJECT_ID_TRAVIS) &&
1679 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1680 !ASIC_IS_DCE5(rdev))
1681 travis_quirk = true;
1685 case DRM_MODE_DPMS_ON:
1686 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1688 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1690 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1692 /* setup and enable the encoder */
1693 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1694 atombios_dig_encoder_setup(encoder,
1695 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1698 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1699 atombios_external_encoder_setup(encoder, ext_encoder,
1700 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1702 } else if (ASIC_IS_DCE4(rdev)) {
1703 /* setup and enable the encoder */
1704 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1706 /* setup and enable the encoder and transmitter */
1707 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1708 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1710 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1711 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1712 atombios_set_edp_panel_power(connector,
1713 ATOM_TRANSMITTER_ACTION_POWER_ON);
1714 radeon_dig_connector->edp_on = true;
1717 /* enable the transmitter */
1718 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1719 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1720 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1721 radeon_dp_link_train(encoder, connector);
1722 if (ASIC_IS_DCE4(rdev))
1723 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1725 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1726 if (rdev->mode_info.bl_encoder)
1727 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1729 atombios_dig_transmitter_setup(encoder,
1730 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1733 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1735 case DRM_MODE_DPMS_STANDBY:
1736 case DRM_MODE_DPMS_SUSPEND:
1737 case DRM_MODE_DPMS_OFF:
1739 /* don't power off encoders with active MST links */
1740 if (dig->active_mst_links)
1743 if (ASIC_IS_DCE4(rdev)) {
1744 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1745 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1748 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1749 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1750 atombios_dig_transmitter_setup(encoder,
1751 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1753 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1754 connector && !travis_quirk)
1755 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1756 if (ASIC_IS_DCE4(rdev)) {
1757 /* disable the transmitter */
1758 atombios_dig_transmitter_setup(encoder,
1759 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1761 /* disable the encoder and transmitter */
1762 atombios_dig_transmitter_setup(encoder,
1763 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1764 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1766 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1768 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1769 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1770 atombios_set_edp_panel_power(connector,
1771 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1772 radeon_dig_connector->edp_on = false;
1780 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1782 struct drm_device *dev = encoder->dev;
1783 struct radeon_device *rdev = dev->dev_private;
1784 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1785 int encoder_mode = atombios_get_encoder_mode(encoder);
1787 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1788 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1789 radeon_encoder->active_device);
1791 if ((radeon_audio != 0) &&
1792 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1793 ENCODER_MODE_IS_DP(encoder_mode)))
1794 radeon_audio_dpms(encoder, mode);
1796 switch (radeon_encoder->encoder_id) {
1797 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1798 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1799 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1800 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1801 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1802 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1803 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1804 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1805 radeon_atom_encoder_dpms_avivo(encoder, mode);
1807 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1808 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1809 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1810 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1811 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1812 radeon_atom_encoder_dpms_dig(encoder, mode);
1814 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1815 if (ASIC_IS_DCE5(rdev)) {
1817 case DRM_MODE_DPMS_ON:
1818 atombios_dvo_setup(encoder, ATOM_ENABLE);
1820 case DRM_MODE_DPMS_STANDBY:
1821 case DRM_MODE_DPMS_SUSPEND:
1822 case DRM_MODE_DPMS_OFF:
1823 atombios_dvo_setup(encoder, ATOM_DISABLE);
1826 } else if (ASIC_IS_DCE3(rdev))
1827 radeon_atom_encoder_dpms_dig(encoder, mode);
1829 radeon_atom_encoder_dpms_avivo(encoder, mode);
1831 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1832 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1833 if (ASIC_IS_DCE5(rdev)) {
1835 case DRM_MODE_DPMS_ON:
1836 atombios_dac_setup(encoder, ATOM_ENABLE);
1838 case DRM_MODE_DPMS_STANDBY:
1839 case DRM_MODE_DPMS_SUSPEND:
1840 case DRM_MODE_DPMS_OFF:
1841 atombios_dac_setup(encoder, ATOM_DISABLE);
1845 radeon_atom_encoder_dpms_avivo(encoder, mode);
1851 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1855 union crtc_source_param {
1856 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1857 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1861 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1863 struct drm_device *dev = encoder->dev;
1864 struct radeon_device *rdev = dev->dev_private;
1865 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1866 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1867 union crtc_source_param args;
1868 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1870 struct radeon_encoder_atom_dig *dig;
1872 memset(&args, 0, sizeof(args));
1874 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1882 if (ASIC_IS_AVIVO(rdev))
1883 args.v1.ucCRTC = radeon_crtc->crtc_id;
1885 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)
1886 args.v1.ucCRTC = radeon_crtc->crtc_id;
1888 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1890 switch (radeon_encoder->encoder_id) {
1891 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1892 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1893 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1895 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1896 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1897 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1898 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1900 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1902 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1903 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1904 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1905 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1907 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1908 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1909 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1910 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1911 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1912 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1914 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1916 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1917 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1918 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1919 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1920 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1921 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1923 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1928 args.v2.ucCRTC = radeon_crtc->crtc_id;
1929 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1930 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1932 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1933 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1934 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1935 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1937 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1938 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1939 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1941 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1943 switch (radeon_encoder->encoder_id) {
1944 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1945 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1946 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1947 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1948 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1949 dig = radeon_encoder->enc_priv;
1950 switch (dig->dig_encoder) {
1952 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1955 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1958 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1961 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1964 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1967 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1970 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1974 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1975 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1977 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1978 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1979 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1980 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1981 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1983 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1985 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1986 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1987 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1988 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1989 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1991 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1998 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
2002 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2004 /* update scratch regs with new routing */
2005 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
2009 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
2011 struct drm_device *dev = encoder->dev;
2012 struct radeon_device *rdev = dev->dev_private;
2013 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2014 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
2016 union crtc_source_param args;
2018 memset(&args, 0, sizeof(args));
2020 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2023 if (frev != 1 && crev != 2)
2024 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2026 args.v2.ucCRTC = radeon_crtc->crtc_id;
2027 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2031 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2034 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2037 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2040 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2043 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2046 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2049 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2052 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2056 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2057 struct drm_display_mode *mode)
2059 struct drm_device *dev = encoder->dev;
2060 struct radeon_device *rdev = dev->dev_private;
2061 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2062 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2064 /* Funky macbooks */
2065 if ((rdev->pdev->device == 0x71C5) &&
2066 (rdev->pdev->subsystem_vendor == 0x106b) &&
2067 (rdev->pdev->subsystem_device == 0x0080)) {
2068 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2069 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2071 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2072 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2074 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2078 /* set scaler clears this on some chips */
2079 if (ASIC_IS_AVIVO(rdev) &&
2080 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2081 if (ASIC_IS_DCE8(rdev)) {
2082 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2083 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2086 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2087 } else if (ASIC_IS_DCE4(rdev)) {
2088 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2089 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2090 EVERGREEN_INTERLEAVE_EN);
2092 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2094 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2095 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2096 AVIVO_D1MODE_INTERLEAVE_EN);
2098 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2103 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2107 rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2110 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2112 struct drm_device *dev = encoder->dev;
2113 struct radeon_device *rdev = dev->dev_private;
2114 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2115 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2116 struct drm_encoder *test_encoder;
2117 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2118 uint32_t dig_enc_in_use = 0;
2125 if (ASIC_IS_DCE6(rdev)) {
2127 switch (radeon_encoder->encoder_id) {
2128 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2134 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2140 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2146 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2151 } else if (ASIC_IS_DCE4(rdev)) {
2153 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2154 /* ontario follows DCE4 */
2155 if (rdev->family == CHIP_PALM) {
2161 /* llano follows DCE3.2 */
2162 enc_idx = radeon_crtc->crtc_id;
2164 switch (radeon_encoder->encoder_id) {
2165 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2171 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2177 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2189 * On DCE32 any encoder can drive any block so usually just use crtc id,
2190 * but Apple thinks different at least on iMac10,1, so there use linkb,
2191 * otherwise the internal eDP panel will stay dark.
2193 if (ASIC_IS_DCE32(rdev)) {
2194 if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1"))
2195 enc_idx = (dig->linkb) ? 1 : 0;
2197 enc_idx = radeon_crtc->crtc_id;
2202 /* on DCE3 - LVTMA can only be driven by DIGB */
2203 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2204 struct radeon_encoder *radeon_test_encoder;
2206 if (encoder == test_encoder)
2209 if (!radeon_encoder_is_digital(test_encoder))
2212 radeon_test_encoder = to_radeon_encoder(test_encoder);
2213 dig = radeon_test_encoder->enc_priv;
2215 if (dig->dig_encoder >= 0)
2216 dig_enc_in_use |= (1 << dig->dig_encoder);
2219 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2220 if (dig_enc_in_use & 0x2)
2221 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2224 if (!(dig_enc_in_use & 1))
2229 if (enc_idx == -1) {
2230 DRM_ERROR("Got encoder index incorrect - returning 0\n");
2233 if (rdev->mode_info.active_encoders & (1 << enc_idx))
2234 DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2236 rdev->mode_info.active_encoders |= (1 << enc_idx);
2240 /* This only needs to be called once at startup */
2242 radeon_atom_encoder_init(struct radeon_device *rdev)
2244 struct drm_device *dev = rdev->ddev;
2245 struct drm_encoder *encoder;
2247 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2248 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2249 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2251 switch (radeon_encoder->encoder_id) {
2252 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2253 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2254 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2255 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2256 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2257 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2263 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2264 atombios_external_encoder_setup(encoder, ext_encoder,
2265 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2270 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2271 struct drm_display_mode *mode,
2272 struct drm_display_mode *adjusted_mode)
2274 struct drm_device *dev = encoder->dev;
2275 struct radeon_device *rdev = dev->dev_private;
2276 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2277 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2280 radeon_encoder->pixel_clock = adjusted_mode->clock;
2282 /* need to call this here rather than in prepare() since we need some crtc info */
2283 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2285 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2286 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2287 atombios_yuv_setup(encoder, true);
2289 atombios_yuv_setup(encoder, false);
2292 switch (radeon_encoder->encoder_id) {
2293 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2294 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2295 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2296 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2297 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2299 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2300 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2301 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2304 /* handled in dpms */
2306 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2307 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2308 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2309 atombios_dvo_setup(encoder, ATOM_ENABLE);
2311 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2312 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2313 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2314 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2315 atombios_dac_setup(encoder, ATOM_ENABLE);
2316 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2317 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2318 atombios_tv_setup(encoder, ATOM_ENABLE);
2320 atombios_tv_setup(encoder, ATOM_DISABLE);
2325 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2327 encoder_mode = atombios_get_encoder_mode(encoder);
2328 if (connector && (radeon_audio != 0) &&
2329 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2330 ENCODER_MODE_IS_DP(encoder_mode)))
2331 radeon_audio_mode_set(encoder, adjusted_mode);
2335 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2337 struct drm_device *dev = encoder->dev;
2338 struct radeon_device *rdev = dev->dev_private;
2339 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2340 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2342 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2343 ATOM_DEVICE_CV_SUPPORT |
2344 ATOM_DEVICE_CRT_SUPPORT)) {
2345 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2346 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2349 memset(&args, 0, sizeof(args));
2351 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2354 args.sDacload.ucMisc = 0;
2356 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2357 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2358 args.sDacload.ucDacType = ATOM_DAC_A;
2360 args.sDacload.ucDacType = ATOM_DAC_B;
2362 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2363 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2364 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2365 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2366 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2367 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2369 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2370 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2371 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2373 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2376 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2383 static enum drm_connector_status
2384 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2386 struct drm_device *dev = encoder->dev;
2387 struct radeon_device *rdev = dev->dev_private;
2388 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2389 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2390 uint32_t bios_0_scratch;
2392 if (!atombios_dac_load_detect(encoder, connector)) {
2393 DRM_DEBUG_KMS("detect returned false \n");
2394 return connector_status_unknown;
2397 if (rdev->family >= CHIP_R600)
2398 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2400 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2402 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2403 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2404 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2405 return connector_status_connected;
2407 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2408 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2409 return connector_status_connected;
2411 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2412 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2413 return connector_status_connected;
2415 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2416 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2417 return connector_status_connected; /* CTV */
2418 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2419 return connector_status_connected; /* STV */
2421 return connector_status_disconnected;
2424 static enum drm_connector_status
2425 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2427 struct drm_device *dev = encoder->dev;
2428 struct radeon_device *rdev = dev->dev_private;
2429 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2430 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2431 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2434 if (!ASIC_IS_DCE4(rdev))
2435 return connector_status_unknown;
2438 return connector_status_unknown;
2440 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2441 return connector_status_unknown;
2443 /* load detect on the dp bridge */
2444 atombios_external_encoder_setup(encoder, ext_encoder,
2445 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2447 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2449 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2450 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2451 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2452 return connector_status_connected;
2454 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2455 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2456 return connector_status_connected;
2458 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2459 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2460 return connector_status_connected;
2462 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2463 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2464 return connector_status_connected; /* CTV */
2465 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2466 return connector_status_connected; /* STV */
2468 return connector_status_disconnected;
2472 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2474 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2477 /* ddc_setup on the dp bridge */
2478 atombios_external_encoder_setup(encoder, ext_encoder,
2479 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2483 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2485 struct radeon_device *rdev = encoder->dev->dev_private;
2486 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2487 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2489 if ((radeon_encoder->active_device &
2490 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2491 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2492 ENCODER_OBJECT_ID_NONE)) {
2493 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2495 if (dig->dig_encoder >= 0)
2496 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2497 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2498 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2499 if (rdev->family >= CHIP_R600)
2500 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2502 /* RS600/690/740 have only 1 afmt block */
2503 dig->afmt = rdev->mode_info.afmt[0];
2508 radeon_atom_output_lock(encoder, true);
2511 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2513 /* select the clock/data port if it uses a router */
2514 if (radeon_connector->router.cd_valid)
2515 radeon_router_select_cd_port(radeon_connector);
2517 /* turn eDP panel on for mode set */
2518 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2519 atombios_set_edp_panel_power(connector,
2520 ATOM_TRANSMITTER_ACTION_POWER_ON);
2523 /* this is needed for the pll/ss setup to work correctly in some cases */
2524 atombios_set_encoder_crtc_source(encoder);
2525 /* set up the FMT blocks */
2526 if (ASIC_IS_DCE8(rdev))
2527 dce8_program_fmt(encoder);
2528 else if (ASIC_IS_DCE4(rdev))
2529 dce4_program_fmt(encoder);
2530 else if (ASIC_IS_DCE3(rdev))
2531 dce3_program_fmt(encoder);
2532 else if (ASIC_IS_AVIVO(rdev))
2533 avivo_program_fmt(encoder);
2536 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2538 /* need to call this here as we need the crtc set up */
2539 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2540 radeon_atom_output_lock(encoder, false);
2543 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2545 struct drm_device *dev = encoder->dev;
2546 struct radeon_device *rdev = dev->dev_private;
2547 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2548 struct radeon_encoder_atom_dig *dig;
2550 /* check for pre-DCE3 cards with shared encoders;
2551 * can't really use the links individually, so don't disable
2552 * the encoder if it's in use by another connector
2554 if (!ASIC_IS_DCE3(rdev)) {
2555 struct drm_encoder *other_encoder;
2556 struct radeon_encoder *other_radeon_encoder;
2558 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2559 other_radeon_encoder = to_radeon_encoder(other_encoder);
2560 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2561 drm_helper_encoder_in_use(other_encoder))
2566 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2568 switch (radeon_encoder->encoder_id) {
2569 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2570 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2571 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2572 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2573 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2575 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2576 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2577 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2578 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2579 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2580 /* handled in dpms */
2582 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2583 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2584 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2585 atombios_dvo_setup(encoder, ATOM_DISABLE);
2587 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2588 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2589 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2590 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2591 atombios_dac_setup(encoder, ATOM_DISABLE);
2592 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2593 atombios_tv_setup(encoder, ATOM_DISABLE);
2598 if (radeon_encoder_is_digital(encoder)) {
2599 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2600 if (rdev->asic->display.hdmi_enable)
2601 radeon_hdmi_enable(rdev, encoder, false);
2603 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2604 dig = radeon_encoder->enc_priv;
2605 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2606 dig->dig_encoder = -1;
2607 radeon_encoder->active_device = 0;
2610 radeon_encoder->active_device = 0;
2613 /* these are handled by the primary encoders */
2614 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2619 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2625 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2626 struct drm_display_mode *mode,
2627 struct drm_display_mode *adjusted_mode)
2632 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2638 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2643 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2644 .dpms = radeon_atom_ext_dpms,
2645 .prepare = radeon_atom_ext_prepare,
2646 .mode_set = radeon_atom_ext_mode_set,
2647 .commit = radeon_atom_ext_commit,
2648 .disable = radeon_atom_ext_disable,
2649 /* no detect for TMDS/LVDS yet */
2652 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2653 .dpms = radeon_atom_encoder_dpms,
2654 .mode_fixup = radeon_atom_mode_fixup,
2655 .prepare = radeon_atom_encoder_prepare,
2656 .mode_set = radeon_atom_encoder_mode_set,
2657 .commit = radeon_atom_encoder_commit,
2658 .disable = radeon_atom_encoder_disable,
2659 .detect = radeon_atom_dig_detect,
2662 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2663 .dpms = radeon_atom_encoder_dpms,
2664 .mode_fixup = radeon_atom_mode_fixup,
2665 .prepare = radeon_atom_encoder_prepare,
2666 .mode_set = radeon_atom_encoder_mode_set,
2667 .commit = radeon_atom_encoder_commit,
2668 .detect = radeon_atom_dac_detect,
2671 void radeon_enc_destroy(struct drm_encoder *encoder)
2673 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2674 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2675 radeon_atom_backlight_exit(radeon_encoder);
2676 kfree(radeon_encoder->enc_priv);
2677 drm_encoder_cleanup(encoder);
2678 kfree(radeon_encoder);
2681 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2682 .destroy = radeon_enc_destroy,
2685 static struct radeon_encoder_atom_dac *
2686 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2688 struct drm_device *dev = radeon_encoder->base.dev;
2689 struct radeon_device *rdev = dev->dev_private;
2690 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2695 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2699 static struct radeon_encoder_atom_dig *
2700 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2702 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2703 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2708 /* coherent mode by default */
2709 dig->coherent_mode = true;
2710 dig->dig_encoder = -1;
2712 if (encoder_enum == 2)
2721 radeon_add_atom_encoder(struct drm_device *dev,
2722 uint32_t encoder_enum,
2723 uint32_t supported_device,
2726 struct radeon_device *rdev = dev->dev_private;
2727 struct drm_encoder *encoder;
2728 struct radeon_encoder *radeon_encoder;
2730 /* see if we already added it */
2731 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2732 radeon_encoder = to_radeon_encoder(encoder);
2733 if (radeon_encoder->encoder_enum == encoder_enum) {
2734 radeon_encoder->devices |= supported_device;
2741 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2742 if (!radeon_encoder)
2745 encoder = &radeon_encoder->base;
2746 switch (rdev->num_crtc) {
2748 encoder->possible_crtcs = 0x1;
2752 encoder->possible_crtcs = 0x3;
2755 encoder->possible_crtcs = 0xf;
2758 encoder->possible_crtcs = 0x3f;
2762 radeon_encoder->enc_priv = NULL;
2764 radeon_encoder->encoder_enum = encoder_enum;
2765 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2766 radeon_encoder->devices = supported_device;
2767 radeon_encoder->rmx_type = RMX_OFF;
2768 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2769 radeon_encoder->is_ext_encoder = false;
2770 radeon_encoder->caps = caps;
2772 switch (radeon_encoder->encoder_id) {
2773 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2774 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2775 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2776 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2777 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2778 radeon_encoder->rmx_type = RMX_FULL;
2779 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2780 DRM_MODE_ENCODER_LVDS, NULL);
2781 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2783 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2784 DRM_MODE_ENCODER_TMDS, NULL);
2785 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2787 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2789 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2790 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2791 DRM_MODE_ENCODER_DAC, NULL);
2792 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2793 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2795 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2796 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2797 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2798 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2799 DRM_MODE_ENCODER_TVDAC, NULL);
2800 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2801 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2803 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2804 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2805 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2806 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2807 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2808 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2809 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2810 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2811 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2812 radeon_encoder->rmx_type = RMX_FULL;
2813 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2814 DRM_MODE_ENCODER_LVDS, NULL);
2815 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2816 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2817 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2818 DRM_MODE_ENCODER_DAC, NULL);
2819 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2821 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2822 DRM_MODE_ENCODER_TMDS, NULL);
2823 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2825 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2827 case ENCODER_OBJECT_ID_SI170B:
2828 case ENCODER_OBJECT_ID_CH7303:
2829 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2830 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2831 case ENCODER_OBJECT_ID_TITFP513:
2832 case ENCODER_OBJECT_ID_VT1623:
2833 case ENCODER_OBJECT_ID_HDMI_SI1930:
2834 case ENCODER_OBJECT_ID_TRAVIS:
2835 case ENCODER_OBJECT_ID_NUTMEG:
2836 /* these are handled by the primary encoders */
2837 radeon_encoder->is_ext_encoder = true;
2838 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2839 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2840 DRM_MODE_ENCODER_LVDS, NULL);
2841 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2842 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2843 DRM_MODE_ENCODER_DAC, NULL);
2845 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2846 DRM_MODE_ENCODER_TMDS, NULL);
2847 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);