drivers/gpu/drm/pl111/pl111_display.c

   1 /*
   2  * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
   3  *
   4  * Parts of this file were based on sources as follows:
   5  *
   6  * Copyright (c) 2006-2008 Intel Corporation
   7  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
   8  * Copyright (C) 2011 Texas Instruments
   9  *
  10  * This program is free software and is provided to you under the terms of the
  11  * GNU General Public License version 2 as published by the Free Software
  12  * Foundation, and any use by you of this program is subject to the terms of
  13  * such GNU licence.
  14  *
  15  */
  16
  17 #include <linux/amba/clcd-regs.h>
  18 #include <linux/clk.h>
  19 #include <linux/version.h>
  20 #include <linux/dma-buf.h>
  21 #include <linux/of_graph.h>
  22
  23 #include <drm/drmP.h>
  24 #include <drm/drm_gem_cma_helper.h>
  25 #include <drm/drm_gem_framebuffer_helper.h>
  26 #include <drm/drm_fb_cma_helper.h>
  27
  28 #include "pl111_drm.h"
  29
  30 irqreturn_t pl111_irq(int irq, void *data)
  31 {
  32         struct pl111_drm_dev_private *priv = data;
  33         u32 irq_stat;
  34         irqreturn_t status = IRQ_NONE;
  35
  36         irq_stat = readl(priv->regs + CLCD_PL111_MIS);
  37
  38         if (!irq_stat)
  39                 return IRQ_NONE;
  40
  41         if (irq_stat & CLCD_IRQ_NEXTBASE_UPDATE) {
  42                 drm_crtc_handle_vblank(&priv->pipe.crtc);
  43
  44                 status = IRQ_HANDLED;
  45         }
  46
  47         /* Clear the interrupt once done */
  48         writel(irq_stat, priv->regs + CLCD_PL111_ICR);
  49
  50         return status;
  51 }
  52
  53 static enum drm_mode_status
  54 pl111_mode_valid(struct drm_crtc *crtc,
  55                  const struct drm_display_mode *mode)
  56 {
  57         struct drm_device *drm = crtc->dev;
  58         struct pl111_drm_dev_private *priv = drm->dev_private;
  59         u32 cpp = priv->variant->fb_bpp / 8;
  60         u64 bw;
  61
  62         /*
  63          * We use the pixelclock to also account for interlaced modes, the
  64          * resulting bandwidth is in bytes per second.
  65          */
  66         bw = mode->clock * 1000; /* In Hz */
  67         bw = bw * mode->hdisplay * mode->vdisplay * cpp;
  68         bw = div_u64(bw, mode->htotal * mode->vtotal);
  69
  70         /*
  71          * If no bandwidth constraints, anything goes, else
  72          * check if we are too fast.
  73          */
  74         if (priv->memory_bw && (bw > priv->memory_bw)) {
  75                 DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu too fast\n",
  76                               mode->hdisplay, mode->vdisplay,
  77                               mode->clock * 1000, cpp, bw);
  78
  79                 return MODE_BAD;
  80         }
  81         DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu bytes/s OK\n",
  82                       mode->hdisplay, mode->vdisplay,
  83                       mode->clock * 1000, cpp, bw);
  84
  85         return MODE_OK;
  86 }
  87
  88 static int pl111_display_check(struct drm_simple_display_pipe *pipe,
  89                                struct drm_plane_state *pstate,
  90                                struct drm_crtc_state *cstate)
  91 {
  92         const struct drm_display_mode *mode = &cstate->mode;
  93         struct drm_framebuffer *old_fb = pipe->plane.state->fb;
  94         struct drm_framebuffer *fb = pstate->fb;
  95
  96         if (mode->hdisplay % 16)
  97                 return -EINVAL;
  98
  99         if (fb) {
 100                 u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0);
 101
 102                 /* FB base address must be dword aligned. */
 103                 if (offset & 3)
 104                         return -EINVAL;
 105
 106                 /* There's no pitch register -- the mode's hdisplay
 107                  * controls it.
 108                  */
 109                 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0])
 110                         return -EINVAL;
 111
 112                 /* We can't change the FB format in a flicker-free
 113                  * manner (and only update it during CRTC enable).
 114                  */
 115                 if (old_fb && old_fb->format != fb->format)
 116                         cstate->mode_changed = true;
 117         }
 118
 119         return 0;
 120 }
 121
 122 static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
 123                                  struct drm_crtc_state *cstate)
 124 {
 125         struct drm_crtc *crtc = &pipe->crtc;
 126         struct drm_plane *plane = &pipe->plane;
 127         struct drm_device *drm = crtc->dev;
 128         struct pl111_drm_dev_private *priv = drm->dev_private;
 129         const struct drm_display_mode *mode = &cstate->mode;
 130         struct drm_framebuffer *fb = plane->state->fb;
 131         struct drm_connector *connector = priv->connector;
 132         struct drm_bridge *bridge = priv->bridge;
 133         u32 cntl;
 134         u32 ppl, hsw, hfp, hbp;
 135         u32 lpp, vsw, vfp, vbp;
 136         u32 cpl, tim2;
 137         int ret;
 138
 139         ret = clk_set_rate(priv->clk, mode->clock * 1000);
 140         if (ret) {
 141                 dev_err(drm->dev,
 142                         "Failed to set pixel clock rate to %d: %d\n",
 143                         mode->clock * 1000, ret);
 144         }
 145
 146         clk_prepare_enable(priv->clk);
 147
 148         ppl = (mode->hdisplay / 16) - 1;
 149         hsw = mode->hsync_end - mode->hsync_start - 1;
 150         hfp = mode->hsync_start - mode->hdisplay - 1;
 151         hbp = mode->htotal - mode->hsync_end - 1;
 152
 153         lpp = mode->vdisplay - 1;
 154         vsw = mode->vsync_end - mode->vsync_start - 1;
 155         vfp = mode->vsync_start - mode->vdisplay;
 156         vbp = mode->vtotal - mode->vsync_end;
 157
 158         cpl = mode->hdisplay - 1;
 159
 160         writel((ppl << 2) |
 161                (hsw << 8) |
 162                (hfp << 16) |
 163                (hbp << 24),
 164                priv->regs + CLCD_TIM0);
 165         writel(lpp |
 166                (vsw << 10) |
 167                (vfp << 16) |
 168                (vbp << 24),
 169                priv->regs + CLCD_TIM1);
 170
 171         spin_lock(&priv->tim2_lock);
 172
 173         tim2 = readl(priv->regs + CLCD_TIM2);
 174         tim2 &= (TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
 175
 176         if (priv->variant->broken_clockdivider)
 177                 tim2 |= TIM2_BCD;
 178
 179         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 180                 tim2 |= TIM2_IHS;
 181
 182         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 183                 tim2 |= TIM2_IVS;
 184
 185         if (connector) {
 186                 if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
 187                         tim2 |= TIM2_IOE;
 188
 189                 if (connector->display_info.bus_flags &
 190                     DRM_BUS_FLAG_PIXDATA_NEGEDGE)
 191                         tim2 |= TIM2_IPC;
 192         }
 193
 194         if (bridge) {
 195                 const struct drm_bridge_timings *btimings = bridge->timings;
 196
 197                 /*
 198                  * Here is when things get really fun. Sometimes the bridge
 199                  * timings are such that the signal out from PL11x is not
 200                  * stable before the receiving bridge (such as a dumb VGA DAC
 201                  * or similar) samples it. If that happens, we compensate by
 202                  * the only method we have: output the data on the opposite
 203                  * edge of the clock so it is for sure stable when it gets
 204                  * sampled.
 205                  *
 206                  * The PL111 manual does not contain proper timining diagrams
 207                  * or data for these details, but we know from experiments
 208                  * that the setup time is more than 3000 picoseconds (3 ns).
 209                  * If we have a bridge that requires the signal to be stable
 210                  * earlier than 3000 ps before the clock pulse, we have to
 211                  * output the data on the opposite edge to avoid flicker.
 212                  */
 213                 if (btimings && btimings->setup_time_ps >= 3000)
 214                         tim2 ^= TIM2_IPC;
 215         }
 216
 217         tim2 |= cpl << 16;
 218         writel(tim2, priv->regs + CLCD_TIM2);
 219         spin_unlock(&priv->tim2_lock);
 220
 221         writel(0, priv->regs + CLCD_TIM3);
 222
 223         /* Hard-code TFT panel */
 224         cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1);
 225
 226         /* Note that the the hardware's format reader takes 'r' from
 227          * the low bit, while DRM formats list channels from high bit
 228          * to low bit as you read left to right.
 229          */
 230         switch (fb->format->format) {
 231         case DRM_FORMAT_ABGR8888:
 232         case DRM_FORMAT_XBGR8888:
 233                 cntl |= CNTL_LCDBPP24;
 234                 break;
 235         case DRM_FORMAT_ARGB8888:
 236         case DRM_FORMAT_XRGB8888:
 237                 cntl |= CNTL_LCDBPP24 | CNTL_BGR;
 238                 break;
 239         case DRM_FORMAT_BGR565:
 240                 if (priv->variant->is_pl110)
 241                         cntl |= CNTL_LCDBPP16;
 242                 else
 243                         cntl |= CNTL_LCDBPP16_565;
 244                 break;
 245         case DRM_FORMAT_RGB565:
 246                 if (priv->variant->is_pl110)
 247                         cntl |= CNTL_LCDBPP16;
 248                 else
 249                         cntl |= CNTL_LCDBPP16_565;
 250                 cntl |= CNTL_BGR;
 251                 break;
 252         case DRM_FORMAT_ABGR1555:
 253         case DRM_FORMAT_XBGR1555:
 254                 cntl |= CNTL_LCDBPP16;
 255                 break;
 256         case DRM_FORMAT_ARGB1555:
 257         case DRM_FORMAT_XRGB1555:
 258                 cntl |= CNTL_LCDBPP16 | CNTL_BGR;
 259                 break;
 260         case DRM_FORMAT_ABGR4444:
 261         case DRM_FORMAT_XBGR4444:
 262                 cntl |= CNTL_LCDBPP16_444;
 263                 break;
 264         case DRM_FORMAT_ARGB4444:
 265         case DRM_FORMAT_XRGB4444:
 266                 cntl |= CNTL_LCDBPP16_444 | CNTL_BGR;
 267                 break;
 268         default:
 269                 WARN_ONCE(true, "Unknown FB format 0x%08x\n",
 270                           fb->format->format);
 271                 break;
 272         }
 273
 274         /* The PL110 in Integrator/Versatile does the BGR routing externally */
 275         if (priv->variant->external_bgr)
 276                 cntl &= ~CNTL_BGR;
 277
 278         /* Power sequence: first enable and chill */
 279         writel(cntl, priv->regs + priv->ctrl);
 280
 281         /*
 282          * We expect this delay to stabilize the contrast
 283          * voltage Vee as stipulated by the manual
 284          */
 285         msleep(20);
 286
 287         if (priv->variant_display_enable)
 288                 priv->variant_display_enable(drm, fb->format->format);
 289
 290         /* Power Up */
 291         cntl |= CNTL_LCDPWR;
 292         writel(cntl, priv->regs + priv->ctrl);
 293
 294         if (!priv->variant->broken_vblank)
 295                 drm_crtc_vblank_on(crtc);
 296 }
 297
 298 void pl111_display_disable(struct drm_simple_display_pipe *pipe)
 299 {
 300         struct drm_crtc *crtc = &pipe->crtc;
 301         struct drm_device *drm = crtc->dev;
 302         struct pl111_drm_dev_private *priv = drm->dev_private;
 303         u32 cntl;
 304
 305         if (!priv->variant->broken_vblank)
 306                 drm_crtc_vblank_off(crtc);
 307
 308         /* Power Down */
 309         cntl = readl(priv->regs + priv->ctrl);
 310         if (cntl & CNTL_LCDPWR) {
 311                 cntl &= ~CNTL_LCDPWR;
 312                 writel(cntl, priv->regs + priv->ctrl);
 313         }
 314
 315         /*
 316          * We expect this delay to stabilize the contrast voltage Vee as
 317          * stipulated by the manual
 318          */
 319         msleep(20);
 320
 321         if (priv->variant_display_disable)
 322                 priv->variant_display_disable(drm);
 323
 324         /* Disable */
 325         writel(0, priv->regs + priv->ctrl);
 326
 327         clk_disable_unprepare(priv->clk);
 328 }
 329
 330 static void pl111_display_update(struct drm_simple_display_pipe *pipe,
 331                                  struct drm_plane_state *old_pstate)
 332 {
 333         struct drm_crtc *crtc = &pipe->crtc;
 334         struct drm_device *drm = crtc->dev;
 335         struct pl111_drm_dev_private *priv = drm->dev_private;
 336         struct drm_pending_vblank_event *event = crtc->state->event;
 337         struct drm_plane *plane = &pipe->plane;
 338         struct drm_plane_state *pstate = plane->state;
 339         struct drm_framebuffer *fb = pstate->fb;
 340
 341         if (fb) {
 342                 u32 addr = drm_fb_cma_get_gem_addr(fb, pstate, 0);
 343
 344                 writel(addr, priv->regs + CLCD_UBAS);
 345         }
 346
 347         if (event) {
 348                 crtc->state->event = NULL;
 349
 350                 spin_lock_irq(&crtc->dev->event_lock);
 351                 if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0)
 352                         drm_crtc_arm_vblank_event(crtc, event);
 353                 else
 354                         drm_crtc_send_vblank_event(crtc, event);
 355                 spin_unlock_irq(&crtc->dev->event_lock);
 356         }
 357 }
 358
 359 static int pl111_display_enable_vblank(struct drm_simple_display_pipe *pipe)
 360 {
 361         struct drm_crtc *crtc = &pipe->crtc;
 362         struct drm_device *drm = crtc->dev;
 363         struct pl111_drm_dev_private *priv = drm->dev_private;
 364
 365         writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + priv->ienb);
 366
 367         return 0;
 368 }
 369
 370 static void pl111_display_disable_vblank(struct drm_simple_display_pipe *pipe)
 371 {
 372         struct drm_crtc *crtc = &pipe->crtc;
 373         struct drm_device *drm = crtc->dev;
 374         struct pl111_drm_dev_private *priv = drm->dev_private;
 375
 376         writel(0, priv->regs + priv->ienb);
 377 }
 378
 379 static int pl111_display_prepare_fb(struct drm_simple_display_pipe *pipe,
 380                                     struct drm_plane_state *plane_state)
 381 {
 382         return drm_gem_fb_prepare_fb(&pipe->plane, plane_state);
 383 }
 384
 385 static struct drm_simple_display_pipe_funcs pl111_display_funcs = {
 386         .mode_valid = pl111_mode_valid,
 387         .check = pl111_display_check,
 388         .enable = pl111_display_enable,
 389         .disable = pl111_display_disable,
 390         .update = pl111_display_update,
 391         .prepare_fb = pl111_display_prepare_fb,
 392 };
 393
 394 static int pl111_clk_div_choose_div(struct clk_hw *hw, unsigned long rate,
 395                                     unsigned long *prate, bool set_parent)
 396 {
 397         int best_div = 1, div;
 398         struct clk_hw *parent = clk_hw_get_parent(hw);
 399         unsigned long best_prate = 0;
 400         unsigned long best_diff = ~0ul;
 401         int max_div = (1 << (TIM2_PCD_LO_BITS + TIM2_PCD_HI_BITS)) - 1;
 402
 403         for (div = 1; div < max_div; div++) {
 404                 unsigned long this_prate, div_rate, diff;
 405
 406                 if (set_parent)
 407                         this_prate = clk_hw_round_rate(parent, rate * div);
 408                 else
 409                         this_prate = *prate;
 410                 div_rate = DIV_ROUND_UP_ULL(this_prate, div);
 411                 diff = abs(rate - div_rate);
 412
 413                 if (diff < best_diff) {
 414                         best_div = div;
 415                         best_diff = diff;
 416                         best_prate = this_prate;
 417                 }
 418         }
 419
 420         *prate = best_prate;
 421         return best_div;
 422 }
 423
 424 static long pl111_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
 425                                      unsigned long *prate)
 426 {
 427         int div = pl111_clk_div_choose_div(hw, rate, prate, true);
 428
 429         return DIV_ROUND_UP_ULL(*prate, div);
 430 }
 431
 432 static unsigned long pl111_clk_div_recalc_rate(struct clk_hw *hw,
 433                                                unsigned long prate)
 434 {
 435         struct pl111_drm_dev_private *priv =
 436                 container_of(hw, struct pl111_drm_dev_private, clk_div);
 437         u32 tim2 = readl(priv->regs + CLCD_TIM2);
 438         int div;
 439
 440         if (tim2 & TIM2_BCD)
 441                 return prate;
 442
 443         div = tim2 & TIM2_PCD_LO_MASK;
 444         div |= (tim2 & TIM2_PCD_HI_MASK) >>
 445                 (TIM2_PCD_HI_SHIFT - TIM2_PCD_LO_BITS);
 446         div += 2;
 447
 448         return DIV_ROUND_UP_ULL(prate, div);
 449 }
 450
 451 static int pl111_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
 452                                   unsigned long prate)
 453 {
 454         struct pl111_drm_dev_private *priv =
 455                 container_of(hw, struct pl111_drm_dev_private, clk_div);
 456         int div = pl111_clk_div_choose_div(hw, rate, &prate, false);
 457         u32 tim2;
 458
 459         spin_lock(&priv->tim2_lock);
 460         tim2 = readl(priv->regs + CLCD_TIM2);
 461         tim2 &= ~(TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
 462
 463         if (div == 1) {
 464                 tim2 |= TIM2_BCD;
 465         } else {
 466                 div -= 2;
 467                 tim2 |= div & TIM2_PCD_LO_MASK;
 468                 tim2 |= (div >> TIM2_PCD_LO_BITS) << TIM2_PCD_HI_SHIFT;
 469         }
 470
 471         writel(tim2, priv->regs + CLCD_TIM2);
 472         spin_unlock(&priv->tim2_lock);
 473
 474         return 0;
 475 }
 476
 477 static const struct clk_ops pl111_clk_div_ops = {
 478         .recalc_rate = pl111_clk_div_recalc_rate,
 479         .round_rate = pl111_clk_div_round_rate,
 480         .set_rate = pl111_clk_div_set_rate,
 481 };
 482
 483 static int
 484 pl111_init_clock_divider(struct drm_device *drm)
 485 {
 486         struct pl111_drm_dev_private *priv = drm->dev_private;
 487         struct clk *parent = devm_clk_get(drm->dev, "clcdclk");
 488         struct clk_hw *div = &priv->clk_div;
 489         const char *parent_name;
 490         struct clk_init_data init = {
 491                 .name = "pl111_div",
 492                 .ops = &pl111_clk_div_ops,
 493                 .parent_names = &parent_name,
 494                 .num_parents = 1,
 495                 .flags = CLK_SET_RATE_PARENT,
 496         };
 497         int ret;
 498
 499         if (IS_ERR(parent)) {
 500                 dev_err(drm->dev, "CLCD: unable to get clcdclk.\n");
 501                 return PTR_ERR(parent);
 502         }
 503         /* If the clock divider is broken, use the parent directly */
 504         if (priv->variant->broken_clockdivider) {
 505                 priv->clk = parent;
 506                 return 0;
 507         }
 508         parent_name = __clk_get_name(parent);
 509
 510         spin_lock_init(&priv->tim2_lock);
 511         div->init = &init;
 512
 513         ret = devm_clk_hw_register(drm->dev, div);
 514
 515         priv->clk = div->clk;
 516         return ret;
 517 }
 518
 519 int pl111_display_init(struct drm_device *drm)
 520 {
 521         struct pl111_drm_dev_private *priv = drm->dev_private;
 522         struct device *dev = drm->dev;
 523         struct device_node *endpoint;
 524         u32 tft_r0b0g0[3];
 525         int ret;
 526
 527         endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
 528         if (!endpoint)
 529                 return -ENODEV;
 530
 531         if (of_property_read_u32_array(endpoint,
 532                                        "arm,pl11x,tft-r0g0b0-pads",
 533                                        tft_r0b0g0,
 534                                        ARRAY_SIZE(tft_r0b0g0)) != 0) {
 535                 dev_err(dev, "arm,pl11x,tft-r0g0b0-pads should be 3 ints\n");
 536                 of_node_put(endpoint);
 537                 return -ENOENT;
 538         }
 539         of_node_put(endpoint);
 540
 541         ret = pl111_init_clock_divider(drm);
 542         if (ret)
 543                 return ret;
 544
 545         if (!priv->variant->broken_vblank) {
 546                 pl111_display_funcs.enable_vblank = pl111_display_enable_vblank;
 547                 pl111_display_funcs.disable_vblank = pl111_display_disable_vblank;
 548         }
 549
 550         ret = drm_simple_display_pipe_init(drm, &priv->pipe,
 551                                            &pl111_display_funcs,
 552                                            priv->variant->formats,
 553                                            priv->variant->nformats,
 554                                            NULL,
 555                                            priv->connector);
 556         if (ret)
 557                 return ret;
 558
 559         return 0;
 560 }