drivers/gpu/drm/panfrost/panfrost_mmu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
   3
   4 #include <drm/panfrost_drm.h>
   5
   6 #include <linux/atomic.h>
   7 #include <linux/bitfield.h>
   8 #include <linux/delay.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/io-pgtable.h>
  14 #include <linux/iommu.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/shmem_fs.h>
  18 #include <linux/sizes.h>
  19
  20 #include "panfrost_device.h"
  21 #include "panfrost_mmu.h"
  22 #include "panfrost_gem.h"
  23 #include "panfrost_features.h"
  24 #include "panfrost_regs.h"
  25
  26 #define mmu_write(dev, reg, data) writel(data, dev->iomem + reg)
  27 #define mmu_read(dev, reg) readl(dev->iomem + reg)
  28
  29 static int wait_ready(struct panfrost_device *pfdev, u32 as_nr)
  30 {
  31         int ret;
  32         u32 val;
  33
  34         /* Wait for the MMU status to indicate there is no active command, in
  35          * case one is pending. */
  36         ret = readl_relaxed_poll_timeout_atomic(pfdev->iomem + AS_STATUS(as_nr),
  37                 val, !(val & AS_STATUS_AS_ACTIVE), 10, 100000);
  38
  39         if (ret) {
  40                 /* The GPU hung, let's trigger a reset */
  41                 panfrost_device_schedule_reset(pfdev);
  42                 dev_err(pfdev->dev, "AS_ACTIVE bit stuck\n");
  43         }
  44
  45         return ret;
  46 }
  47
  48 static int write_cmd(struct panfrost_device *pfdev, u32 as_nr, u32 cmd)
  49 {
  50         int status;
  51
  52         /* write AS_COMMAND when MMU is ready to accept another command */
  53         status = wait_ready(pfdev, as_nr);
  54         if (!status)
  55                 mmu_write(pfdev, AS_COMMAND(as_nr), cmd);
  56
  57         return status;
  58 }
  59
  60 static void lock_region(struct panfrost_device *pfdev, u32 as_nr,
  61                         u64 region_start, u64 size)
  62 {
  63         u8 region_width;
  64         u64 region;
  65         u64 region_end = region_start + size;
  66
  67         if (!size)
  68                 return;
  69
  70         /*
  71          * The locked region is a naturally aligned power of 2 block encoded as
  72          * log2 minus(1).
  73          * Calculate the desired start/end and look for the highest bit which
  74          * differs. The smallest naturally aligned block must include this bit
  75          * change, the desired region starts with this bit (and subsequent bits)
  76          * zeroed and ends with the bit (and subsequent bits) set to one.
  77          */
  78         region_width = max(fls64(region_start ^ (region_end - 1)),
  79                            const_ilog2(AS_LOCK_REGION_MIN_SIZE)) - 1;
  80
  81         /*
  82          * Mask off the low bits of region_start (which would be ignored by
  83          * the hardware anyway)
  84          */
  85         region_start &= GENMASK_ULL(63, region_width);
  86
  87         region = region_width | region_start;
  88
  89         /* Lock the region that needs to be updated */
  90         mmu_write(pfdev, AS_LOCKADDR_LO(as_nr), lower_32_bits(region));
  91         mmu_write(pfdev, AS_LOCKADDR_HI(as_nr), upper_32_bits(region));
  92         write_cmd(pfdev, as_nr, AS_COMMAND_LOCK);
  93 }
  94
  95
  96 static int mmu_hw_do_operation_locked(struct panfrost_device *pfdev, int as_nr,
  97                                       u64 iova, u64 size, u32 op)
  98 {
  99         if (as_nr < 0)
 100                 return 0;
 101
 102         if (op != AS_COMMAND_UNLOCK)
 103                 lock_region(pfdev, as_nr, iova, size);
 104
 105         /* Run the MMU operation */
 106         write_cmd(pfdev, as_nr, op);
 107
 108         /* Wait for the flush to complete */
 109         return wait_ready(pfdev, as_nr);
 110 }
 111
 112 static int mmu_hw_do_operation(struct panfrost_device *pfdev,
 113                                struct panfrost_mmu *mmu,
 114                                u64 iova, u64 size, u32 op)
 115 {
 116         int ret;
 117
 118         spin_lock(&pfdev->as_lock);
 119         ret = mmu_hw_do_operation_locked(pfdev, mmu->as, iova, size, op);
 120         spin_unlock(&pfdev->as_lock);
 121         return ret;
 122 }
 123
 124 static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
 125 {
 126         int as_nr = mmu->as;
 127         struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg;
 128         u64 transtab = cfg->arm_mali_lpae_cfg.transtab;
 129         u64 memattr = cfg->arm_mali_lpae_cfg.memattr;
 130
 131         mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
 132
 133         mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), lower_32_bits(transtab));
 134         mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), upper_32_bits(transtab));
 135
 136         /* Need to revisit mem attrs.
 137          * NC is the default, Mali driver is inner WT.
 138          */
 139         mmu_write(pfdev, AS_MEMATTR_LO(as_nr), lower_32_bits(memattr));
 140         mmu_write(pfdev, AS_MEMATTR_HI(as_nr), upper_32_bits(memattr));
 141
 142         write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
 143 }
 144
 145 static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr)
 146 {
 147         mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
 148
 149         mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0);
 150         mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0);
 151
 152         mmu_write(pfdev, AS_MEMATTR_LO(as_nr), 0);
 153         mmu_write(pfdev, AS_MEMATTR_HI(as_nr), 0);
 154
 155         write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
 156 }
 157
 158 u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
 159 {
 160         int as;
 161
 162         spin_lock(&pfdev->as_lock);
 163
 164         as = mmu->as;
 165         if (as >= 0) {
 166                 int en = atomic_inc_return(&mmu->as_count);
 167                 u32 mask = BIT(as) | BIT(16 + as);
 168
 169                 /*
 170                  * AS can be retained by active jobs or a perfcnt context,
 171                  * hence the '+ 1' here.
 172                  */
 173                 WARN_ON(en >= (NUM_JOB_SLOTS + 1));
 174
 175                 list_move(&mmu->list, &pfdev->as_lru_list);
 176
 177                 if (pfdev->as_faulty_mask & mask) {
 178                         /* Unhandled pagefault on this AS, the MMU was
 179                          * disabled. We need to re-enable the MMU after
 180                          * clearing+unmasking the AS interrupts.
 181                          */
 182                         mmu_write(pfdev, MMU_INT_CLEAR, mask);
 183                         mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask);
 184                         pfdev->as_faulty_mask &= ~mask;
 185                         panfrost_mmu_enable(pfdev, mmu);
 186                 }
 187
 188                 goto out;
 189         }
 190
 191         /* Check for a free AS */
 192         as = ffz(pfdev->as_alloc_mask);
 193         if (!(BIT(as) & pfdev->features.as_present)) {
 194                 struct panfrost_mmu *lru_mmu;
 195
 196                 list_for_each_entry_reverse(lru_mmu, &pfdev->as_lru_list, list) {
 197                         if (!atomic_read(&lru_mmu->as_count))
 198                                 break;
 199                 }
 200                 WARN_ON(&lru_mmu->list == &pfdev->as_lru_list);
 201
 202                 list_del_init(&lru_mmu->list);
 203                 as = lru_mmu->as;
 204
 205                 WARN_ON(as < 0);
 206                 lru_mmu->as = -1;
 207         }
 208
 209         /* Assign the free or reclaimed AS to the FD */
 210         mmu->as = as;
 211         set_bit(as, &pfdev->as_alloc_mask);
 212         atomic_set(&mmu->as_count, 1);
 213         list_add(&mmu->list, &pfdev->as_lru_list);
 214
 215         dev_dbg(pfdev->dev, "Assigned AS%d to mmu %p, alloc_mask=%lx", as, mmu, pfdev->as_alloc_mask);
 216
 217         panfrost_mmu_enable(pfdev, mmu);
 218
 219 out:
 220         spin_unlock(&pfdev->as_lock);
 221         return as;
 222 }
 223
 224 void panfrost_mmu_as_put(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
 225 {
 226         atomic_dec(&mmu->as_count);
 227         WARN_ON(atomic_read(&mmu->as_count) < 0);
 228 }
 229
 230 void panfrost_mmu_reset(struct panfrost_device *pfdev)
 231 {
 232         struct panfrost_mmu *mmu, *mmu_tmp;
 233
 234         spin_lock(&pfdev->as_lock);
 235
 236         pfdev->as_alloc_mask = 0;
 237         pfdev->as_faulty_mask = 0;
 238
 239         list_for_each_entry_safe(mmu, mmu_tmp, &pfdev->as_lru_list, list) {
 240                 mmu->as = -1;
 241                 atomic_set(&mmu->as_count, 0);
 242                 list_del_init(&mmu->list);
 243         }
 244
 245         spin_unlock(&pfdev->as_lock);
 246
 247         mmu_write(pfdev, MMU_INT_CLEAR, ~0);
 248         mmu_write(pfdev, MMU_INT_MASK, ~0);
 249 }
 250
 251 static size_t get_pgsize(u64 addr, size_t size)
 252 {
 253         if (addr & (SZ_2M - 1) || size < SZ_2M)
 254                 return SZ_4K;
 255
 256         return SZ_2M;
 257 }
 258
 259 static void panfrost_mmu_flush_range(struct panfrost_device *pfdev,
 260                                      struct panfrost_mmu *mmu,
 261                                      u64 iova, u64 size)
 262 {
 263         if (mmu->as < 0)
 264                 return;
 265
 266         pm_runtime_get_noresume(pfdev->dev);
 267
 268         /* Flush the PTs only if we're already awake */
 269         if (pm_runtime_active(pfdev->dev))
 270                 mmu_hw_do_operation(pfdev, mmu, iova, size, AS_COMMAND_FLUSH_PT);
 271
 272         pm_runtime_put_sync_autosuspend(pfdev->dev);
 273 }
 274
 275 static int mmu_map_sg(struct panfrost_device *pfdev, struct panfrost_mmu *mmu,
 276                       u64 iova, int prot, struct sg_table *sgt)
 277 {
 278         unsigned int count;
 279         struct scatterlist *sgl;
 280         struct io_pgtable_ops *ops = mmu->pgtbl_ops;
 281         u64 start_iova = iova;
 282
 283         for_each_sgtable_dma_sg(sgt, sgl, count) {
 284                 unsigned long paddr = sg_dma_address(sgl);
 285                 size_t len = sg_dma_len(sgl);
 286
 287                 dev_dbg(pfdev->dev, "map: as=%d, iova=%llx, paddr=%lx, len=%zx", mmu->as, iova, paddr, len);
 288
 289                 while (len) {
 290                         size_t pgsize = get_pgsize(iova | paddr, len);
 291
 292                         ops->map(ops, iova, paddr, pgsize, prot, GFP_KERNEL);
 293                         iova += pgsize;
 294                         paddr += pgsize;
 295                         len -= pgsize;
 296                 }
 297         }
 298
 299         panfrost_mmu_flush_range(pfdev, mmu, start_iova, iova - start_iova);
 300
 301         return 0;
 302 }
 303
 304 int panfrost_mmu_map(struct panfrost_gem_mapping *mapping)
 305 {
 306         struct panfrost_gem_object *bo = mapping->obj;
 307         struct drm_gem_shmem_object *shmem = &bo->base;
 308         struct drm_gem_object *obj = &shmem->base;
 309         struct panfrost_device *pfdev = to_panfrost_device(obj->dev);
 310         struct sg_table *sgt;
 311         int prot = IOMMU_READ | IOMMU_WRITE;
 312
 313         if (WARN_ON(mapping->active))
 314                 return 0;
 315
 316         if (bo->noexec)
 317                 prot |= IOMMU_NOEXEC;
 318
 319         sgt = drm_gem_shmem_get_pages_sgt(shmem);
 320         if (WARN_ON(IS_ERR(sgt)))
 321                 return PTR_ERR(sgt);
 322
 323         mmu_map_sg(pfdev, mapping->mmu, mapping->mmnode.start << PAGE_SHIFT,
 324                    prot, sgt);
 325         mapping->active = true;
 326
 327         return 0;
 328 }
 329
 330 void panfrost_mmu_unmap(struct panfrost_gem_mapping *mapping)
 331 {
 332         struct panfrost_gem_object *bo = mapping->obj;
 333         struct drm_gem_object *obj = &bo->base.base;
 334         struct panfrost_device *pfdev = to_panfrost_device(obj->dev);
 335         struct io_pgtable_ops *ops = mapping->mmu->pgtbl_ops;
 336         u64 iova = mapping->mmnode.start << PAGE_SHIFT;
 337         size_t len = mapping->mmnode.size << PAGE_SHIFT;
 338         size_t unmapped_len = 0;
 339
 340         if (WARN_ON(!mapping->active))
 341                 return;
 342
 343         dev_dbg(pfdev->dev, "unmap: as=%d, iova=%llx, len=%zx",
 344                 mapping->mmu->as, iova, len);
 345
 346         while (unmapped_len < len) {
 347                 size_t unmapped_page;
 348                 size_t pgsize = get_pgsize(iova, len - unmapped_len);
 349
 350                 if (ops->iova_to_phys(ops, iova)) {
 351                         unmapped_page = ops->unmap(ops, iova, pgsize, NULL);
 352                         WARN_ON(unmapped_page != pgsize);
 353                 }
 354                 iova += pgsize;
 355                 unmapped_len += pgsize;
 356         }
 357
 358         panfrost_mmu_flush_range(pfdev, mapping->mmu,
 359                                  mapping->mmnode.start << PAGE_SHIFT, len);
 360         mapping->active = false;
 361 }
 362
 363 static void mmu_tlb_inv_context_s1(void *cookie)
 364 {}
 365
 366 static void mmu_tlb_sync_context(void *cookie)
 367 {
 368         //struct panfrost_mmu *mmu = cookie;
 369         // TODO: Wait 1000 GPU cycles for HW_ISSUE_6367/T60X
 370 }
 371
 372 static void mmu_tlb_flush_walk(unsigned long iova, size_t size, size_t granule,
 373                                void *cookie)
 374 {
 375         mmu_tlb_sync_context(cookie);
 376 }
 377
 378 static const struct iommu_flush_ops mmu_tlb_ops = {
 379         .tlb_flush_all  = mmu_tlb_inv_context_s1,
 380         .tlb_flush_walk = mmu_tlb_flush_walk,
 381 };
 382
 383 static struct panfrost_gem_mapping *
 384 addr_to_mapping(struct panfrost_device *pfdev, int as, u64 addr)
 385 {
 386         struct panfrost_gem_mapping *mapping = NULL;
 387         struct drm_mm_node *node;
 388         u64 offset = addr >> PAGE_SHIFT;
 389         struct panfrost_mmu *mmu;
 390
 391         spin_lock(&pfdev->as_lock);
 392         list_for_each_entry(mmu, &pfdev->as_lru_list, list) {
 393                 if (as == mmu->as)
 394                         goto found_mmu;
 395         }
 396         goto out;
 397
 398 found_mmu:
 399
 400         spin_lock(&mmu->mm_lock);
 401
 402         drm_mm_for_each_node(node, &mmu->mm) {
 403                 if (offset >= node->start &&
 404                     offset < (node->start + node->size)) {
 405                         mapping = drm_mm_node_to_panfrost_mapping(node);
 406
 407                         kref_get(&mapping->refcount);
 408                         break;
 409                 }
 410         }
 411
 412         spin_unlock(&mmu->mm_lock);
 413 out:
 414         spin_unlock(&pfdev->as_lock);
 415         return mapping;
 416 }
 417
 418 #define NUM_FAULT_PAGES (SZ_2M / PAGE_SIZE)
 419
 420 static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as,
 421                                        u64 addr)
 422 {
 423         int ret, i;
 424         struct panfrost_gem_mapping *bomapping;
 425         struct panfrost_gem_object *bo;
 426         struct address_space *mapping;
 427         pgoff_t page_offset;
 428         struct sg_table *sgt;
 429         struct page **pages;
 430
 431         bomapping = addr_to_mapping(pfdev, as, addr);
 432         if (!bomapping)
 433                 return -ENOENT;
 434
 435         bo = bomapping->obj;
 436         if (!bo->is_heap) {
 437                 dev_WARN(pfdev->dev, "matching BO is not heap type (GPU VA = %llx)",
 438                          bomapping->mmnode.start << PAGE_SHIFT);
 439                 ret = -EINVAL;
 440                 goto err_bo;
 441         }
 442         WARN_ON(bomapping->mmu->as != as);
 443
 444         /* Assume 2MB alignment and size multiple */
 445         addr &= ~((u64)SZ_2M - 1);
 446         page_offset = addr >> PAGE_SHIFT;
 447         page_offset -= bomapping->mmnode.start;
 448
 449         mutex_lock(&bo->base.pages_lock);
 450
 451         if (!bo->base.pages) {
 452                 bo->sgts = kvmalloc_array(bo->base.base.size / SZ_2M,
 453                                      sizeof(struct sg_table), GFP_KERNEL | __GFP_ZERO);
 454                 if (!bo->sgts) {
 455                         mutex_unlock(&bo->base.pages_lock);
 456                         ret = -ENOMEM;
 457                         goto err_bo;
 458                 }
 459
 460                 pages = kvmalloc_array(bo->base.base.size >> PAGE_SHIFT,
 461                                        sizeof(struct page *), GFP_KERNEL | __GFP_ZERO);
 462                 if (!pages) {
 463                         kvfree(bo->sgts);
 464                         bo->sgts = NULL;
 465                         mutex_unlock(&bo->base.pages_lock);
 466                         ret = -ENOMEM;
 467                         goto err_bo;
 468                 }
 469                 bo->base.pages = pages;
 470                 bo->base.pages_use_count = 1;
 471         } else {
 472                 pages = bo->base.pages;
 473                 if (pages[page_offset]) {
 474                         /* Pages are already mapped, bail out. */
 475                         mutex_unlock(&bo->base.pages_lock);
 476                         goto out;
 477                 }
 478         }
 479
 480         mapping = bo->base.base.filp->f_mapping;
 481         mapping_set_unevictable(mapping);
 482
 483         for (i = page_offset; i < page_offset + NUM_FAULT_PAGES; i++) {
 484                 pages[i] = shmem_read_mapping_page(mapping, i);
 485                 if (IS_ERR(pages[i])) {
 486                         mutex_unlock(&bo->base.pages_lock);
 487                         ret = PTR_ERR(pages[i]);
 488                         goto err_pages;
 489                 }
 490         }
 491
 492         mutex_unlock(&bo->base.pages_lock);
 493
 494         sgt = &bo->sgts[page_offset / (SZ_2M / PAGE_SIZE)];
 495         ret = sg_alloc_table_from_pages(sgt, pages + page_offset,
 496                                         NUM_FAULT_PAGES, 0, SZ_2M, GFP_KERNEL);
 497         if (ret)
 498                 goto err_pages;
 499
 500         ret = dma_map_sgtable(pfdev->dev, sgt, DMA_BIDIRECTIONAL, 0);
 501         if (ret)
 502                 goto err_map;
 503
 504         mmu_map_sg(pfdev, bomapping->mmu, addr,
 505                    IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt);
 506
 507         bomapping->active = true;
 508
 509         dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr);
 510
 511 out:
 512         panfrost_gem_mapping_put(bomapping);
 513
 514         return 0;
 515
 516 err_map:
 517         sg_free_table(sgt);
 518 err_pages:
 519         drm_gem_shmem_put_pages(&bo->base);
 520 err_bo:
 521         panfrost_gem_mapping_put(bomapping);
 522         return ret;
 523 }
 524
 525 static void panfrost_mmu_release_ctx(struct kref *kref)
 526 {
 527         struct panfrost_mmu *mmu = container_of(kref, struct panfrost_mmu,
 528                                                 refcount);
 529         struct panfrost_device *pfdev = mmu->pfdev;
 530
 531         spin_lock(&pfdev->as_lock);
 532         if (mmu->as >= 0) {
 533                 pm_runtime_get_noresume(pfdev->dev);
 534                 if (pm_runtime_active(pfdev->dev))
 535                         panfrost_mmu_disable(pfdev, mmu->as);
 536                 pm_runtime_put_autosuspend(pfdev->dev);
 537
 538                 clear_bit(mmu->as, &pfdev->as_alloc_mask);
 539                 clear_bit(mmu->as, &pfdev->as_in_use_mask);
 540                 list_del(&mmu->list);
 541         }
 542         spin_unlock(&pfdev->as_lock);
 543
 544         free_io_pgtable_ops(mmu->pgtbl_ops);
 545         drm_mm_takedown(&mmu->mm);
 546         kfree(mmu);
 547 }
 548
 549 void panfrost_mmu_ctx_put(struct panfrost_mmu *mmu)
 550 {
 551         kref_put(&mmu->refcount, panfrost_mmu_release_ctx);
 552 }
 553
 554 struct panfrost_mmu *panfrost_mmu_ctx_get(struct panfrost_mmu *mmu)
 555 {
 556         kref_get(&mmu->refcount);
 557
 558         return mmu;
 559 }
 560
 561 #define PFN_4G          (SZ_4G >> PAGE_SHIFT)
 562 #define PFN_4G_MASK     (PFN_4G - 1)
 563 #define PFN_16M         (SZ_16M >> PAGE_SHIFT)
 564
 565 static void panfrost_drm_mm_color_adjust(const struct drm_mm_node *node,
 566                                          unsigned long color,
 567                                          u64 *start, u64 *end)
 568 {
 569         /* Executable buffers can't start or end on a 4GB boundary */
 570         if (!(color & PANFROST_BO_NOEXEC)) {
 571                 u64 next_seg;
 572
 573                 if ((*start & PFN_4G_MASK) == 0)
 574                         (*start)++;
 575
 576                 if ((*end & PFN_4G_MASK) == 0)
 577                         (*end)--;
 578
 579                 next_seg = ALIGN(*start, PFN_4G);
 580                 if (next_seg - *start <= PFN_16M)
 581                         *start = next_seg + 1;
 582
 583                 *end = min(*end, ALIGN(*start, PFN_4G) - 1);
 584         }
 585 }
 586
 587 struct panfrost_mmu *panfrost_mmu_ctx_create(struct panfrost_device *pfdev)
 588 {
 589         struct panfrost_mmu *mmu;
 590
 591         mmu = kzalloc(sizeof(*mmu), GFP_KERNEL);
 592         if (!mmu)
 593                 return ERR_PTR(-ENOMEM);
 594
 595         mmu->pfdev = pfdev;
 596         spin_lock_init(&mmu->mm_lock);
 597
 598         /* 4G enough for now. can be 48-bit */
 599         drm_mm_init(&mmu->mm, SZ_32M >> PAGE_SHIFT, (SZ_4G - SZ_32M) >> PAGE_SHIFT);
 600         mmu->mm.color_adjust = panfrost_drm_mm_color_adjust;
 601
 602         INIT_LIST_HEAD(&mmu->list);
 603         mmu->as = -1;
 604
 605         mmu->pgtbl_cfg = (struct io_pgtable_cfg) {
 606                 .pgsize_bitmap  = SZ_4K | SZ_2M,
 607                 .ias            = FIELD_GET(0xff, pfdev->features.mmu_features),
 608                 .oas            = FIELD_GET(0xff00, pfdev->features.mmu_features),
 609                 .coherent_walk  = pfdev->coherent,
 610                 .tlb            = &mmu_tlb_ops,
 611                 .iommu_dev      = pfdev->dev,
 612         };
 613
 614         mmu->pgtbl_ops = alloc_io_pgtable_ops(ARM_MALI_LPAE, &mmu->pgtbl_cfg,
 615                                               mmu);
 616         if (!mmu->pgtbl_ops) {
 617                 kfree(mmu);
 618                 return ERR_PTR(-EINVAL);
 619         }
 620
 621         kref_init(&mmu->refcount);
 622
 623         return mmu;
 624 }
 625
 626 static const char *access_type_name(struct panfrost_device *pfdev,
 627                 u32 fault_status)
 628 {
 629         switch (fault_status & AS_FAULTSTATUS_ACCESS_TYPE_MASK) {
 630         case AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC:
 631                 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_AARCH64_MMU))
 632                         return "ATOMIC";
 633                 else
 634                         return "UNKNOWN";
 635         case AS_FAULTSTATUS_ACCESS_TYPE_READ:
 636                 return "READ";
 637         case AS_FAULTSTATUS_ACCESS_TYPE_WRITE:
 638                 return "WRITE";
 639         case AS_FAULTSTATUS_ACCESS_TYPE_EX:
 640                 return "EXECUTE";
 641         default:
 642                 WARN_ON(1);
 643                 return NULL;
 644         }
 645 }
 646
 647 static irqreturn_t panfrost_mmu_irq_handler(int irq, void *data)
 648 {
 649         struct panfrost_device *pfdev = data;
 650
 651         if (!mmu_read(pfdev, MMU_INT_STAT))
 652                 return IRQ_NONE;
 653
 654         mmu_write(pfdev, MMU_INT_MASK, 0);
 655         return IRQ_WAKE_THREAD;
 656 }
 657
 658 static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data)
 659 {
 660         struct panfrost_device *pfdev = data;
 661         u32 status = mmu_read(pfdev, MMU_INT_RAWSTAT);
 662         int ret;
 663
 664         while (status) {
 665                 u32 as = ffs(status | (status >> 16)) - 1;
 666                 u32 mask = BIT(as) | BIT(as + 16);
 667                 u64 addr;
 668                 u32 fault_status;
 669                 u32 exception_type;
 670                 u32 access_type;
 671                 u32 source_id;
 672
 673                 fault_status = mmu_read(pfdev, AS_FAULTSTATUS(as));
 674                 addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(as));
 675                 addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(as)) << 32;
 676
 677                 /* decode the fault status */
 678                 exception_type = fault_status & 0xFF;
 679                 access_type = (fault_status >> 8) & 0x3;
 680                 source_id = (fault_status >> 16);
 681
 682                 mmu_write(pfdev, MMU_INT_CLEAR, mask);
 683
 684                 /* Page fault only */
 685                 ret = -1;
 686                 if ((status & mask) == BIT(as) && (exception_type & 0xF8) == 0xC0)
 687                         ret = panfrost_mmu_map_fault_addr(pfdev, as, addr);
 688
 689                 if (ret) {
 690                         /* terminal fault, print info about the fault */
 691                         dev_err(pfdev->dev,
 692                                 "Unhandled Page fault in AS%d at VA 0x%016llX\n"
 693                                 "Reason: %s\n"
 694                                 "raw fault status: 0x%X\n"
 695                                 "decoded fault status: %s\n"
 696                                 "exception type 0x%X: %s\n"
 697                                 "access type 0x%X: %s\n"
 698                                 "source id 0x%X\n",
 699                                 as, addr,
 700                                 "TODO",
 701                                 fault_status,
 702                                 (fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"),
 703                                 exception_type, panfrost_exception_name(exception_type),
 704                                 access_type, access_type_name(pfdev, fault_status),
 705                                 source_id);
 706
 707                         spin_lock(&pfdev->as_lock);
 708                         /* Ignore MMU interrupts on this AS until it's been
 709                          * re-enabled.
 710                          */
 711                         pfdev->as_faulty_mask |= mask;
 712
 713                         /* Disable the MMU to kill jobs on this AS. */
 714                         panfrost_mmu_disable(pfdev, as);
 715                         spin_unlock(&pfdev->as_lock);
 716                 }
 717
 718                 status &= ~mask;
 719
 720                 /* If we received new MMU interrupts, process them before returning. */
 721                 if (!status)
 722                         status = mmu_read(pfdev, MMU_INT_RAWSTAT) & ~pfdev->as_faulty_mask;
 723         }
 724
 725         spin_lock(&pfdev->as_lock);
 726         mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask);
 727         spin_unlock(&pfdev->as_lock);
 728
 729         return IRQ_HANDLED;
 730 };
 731
 732 int panfrost_mmu_init(struct panfrost_device *pfdev)
 733 {
 734         int err, irq;
 735
 736         irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "mmu");
 737         if (irq <= 0)
 738                 return -ENODEV;
 739
 740         err = devm_request_threaded_irq(pfdev->dev, irq,
 741                                         panfrost_mmu_irq_handler,
 742                                         panfrost_mmu_irq_handler_thread,
 743                                         IRQF_SHARED, KBUILD_MODNAME "-mmu",
 744                                         pfdev);
 745
 746         if (err) {
 747                 dev_err(pfdev->dev, "failed to request mmu irq");
 748                 return err;
 749         }
 750
 751         return 0;
 752 }
 753
 754 void panfrost_mmu_fini(struct panfrost_device *pfdev)
 755 {
 756         mmu_write(pfdev, MMU_INT_MASK, 0);
 757 }