1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
3 /* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */
4 /* Copyright 2019 Collabora ltd. */
5 #include <linux/bitfield.h>
6 #include <linux/bitmap.h>
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/interrupt.h>
11 #include <linux/iopoll.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
15 #include "panfrost_device.h"
16 #include "panfrost_features.h"
17 #include "panfrost_issues.h"
18 #include "panfrost_gpu.h"
19 #include "panfrost_perfcnt.h"
20 #include "panfrost_regs.h"
22 static irqreturn_t panfrost_gpu_irq_handler(int irq, void *data)
24 struct panfrost_device *pfdev = data;
25 u32 state = gpu_read(pfdev, GPU_INT_STAT);
26 u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS);
31 if (state & GPU_IRQ_MASK_ERROR) {
32 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32;
33 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO);
35 dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n",
36 fault_status & 0xFF, panfrost_exception_name(pfdev, fault_status),
39 if (state & GPU_IRQ_MULTIPLE_FAULT)
40 dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n");
42 gpu_write(pfdev, GPU_INT_MASK, 0);
45 if (state & GPU_IRQ_PERFCNT_SAMPLE_COMPLETED)
46 panfrost_perfcnt_sample_done(pfdev);
48 if (state & GPU_IRQ_CLEAN_CACHES_COMPLETED)
49 panfrost_perfcnt_clean_cache_done(pfdev);
51 gpu_write(pfdev, GPU_INT_CLEAR, state);
56 int panfrost_gpu_soft_reset(struct panfrost_device *pfdev)
61 gpu_write(pfdev, GPU_INT_MASK, 0);
62 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
63 gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET);
65 ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT,
66 val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000);
69 dev_err(pfdev->dev, "gpu soft reset timed out\n");
73 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL);
74 gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL);
79 static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)
83 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_8443) ||
84 panfrost_has_hw_issue(pfdev, HW_ISSUE_11035))
85 quirks |= SC_LS_PAUSEBUFFER_DISABLE;
87 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10327))
88 quirks |= SC_SDC_DISABLE_OQ_DISCARD;
90 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10797))
91 quirks |= SC_ENABLE_TEXGRD_FLAGS;
93 if (!panfrost_has_hw_issue(pfdev, GPUCORE_1619)) {
94 if (panfrost_model_cmp(pfdev, 0x750) < 0) /* T60x, T62x, T72x */
95 quirks |= SC_LS_ATTR_CHECK_DISABLE;
96 else if (panfrost_model_cmp(pfdev, 0x880) <= 0) /* T76x, T8xx */
97 quirks |= SC_LS_ALLOW_ATTR_TYPES;
100 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_TLS_HASHING))
101 quirks |= SC_TLS_HASH_ENABLE;
104 gpu_write(pfdev, GPU_SHADER_CONFIG, quirks);
107 quirks = gpu_read(pfdev, GPU_TILER_CONFIG);
109 /* Set tiler clock gate override if required */
110 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_T76X_3953))
111 quirks |= TC_CLOCK_GATE_OVERRIDE;
113 gpu_write(pfdev, GPU_TILER_CONFIG, quirks);
116 quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG);
118 /* Limit read & write ID width for AXI */
119 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG))
120 quirks &= ~(L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS |
121 L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES);
123 quirks &= ~(L2_MMU_CONFIG_LIMIT_EXTERNAL_READS |
124 L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES);
126 gpu_write(pfdev, GPU_L2_MMU_CONFIG, quirks);
129 if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) &&
130 pfdev->features.revision >= 0x2000)
131 quirks |= JM_MAX_JOB_THROTTLE_LIMIT << JM_JOB_THROTTLE_LIMIT_SHIFT;
132 else if (panfrost_model_eq(pfdev, 0x6000) &&
133 pfdev->features.coherency_features == COHERENCY_ACE)
134 quirks |= (COHERENCY_ACE_LITE | COHERENCY_ACE) <<
135 JM_FORCE_COHERENCY_FEATURES_SHIFT;
138 gpu_write(pfdev, GPU_JM_CONFIG, quirks);
140 /* Here goes platform specific quirks */
141 if (pfdev->comp->vendor_quirk)
142 pfdev->comp->vendor_quirk(pfdev);
145 #define MAX_HW_REVS 6
147 struct panfrost_model {
159 #define GPU_MODEL(_name, _id, ...) \
161 .name = __stringify(_name), \
163 .features = hw_features_##_name, \
164 .issues = hw_issues_##_name, \
165 .revs = { __VA_ARGS__ }, \
168 #define GPU_REV_EXT(name, _rev, _p, _s, stat) \
170 .revision = (_rev) << 12 | (_p) << 4 | (_s), \
171 .issues = hw_issues_##name##_r##_rev##p##_p##stat, \
173 #define GPU_REV(name, r, p) GPU_REV_EXT(name, r, p, 0, )
175 static const struct panfrost_model gpu_models[] = {
176 /* T60x has an oddball version */
177 GPU_MODEL(t600, 0x600,
178 GPU_REV_EXT(t600, 0, 0, 1, _15dev0)),
179 GPU_MODEL(t620, 0x620,
180 GPU_REV(t620, 0, 1), GPU_REV(t620, 1, 0)),
181 GPU_MODEL(t720, 0x720),
182 GPU_MODEL(t760, 0x750,
183 GPU_REV(t760, 0, 0), GPU_REV(t760, 0, 1),
184 GPU_REV_EXT(t760, 0, 1, 0, _50rel0),
185 GPU_REV(t760, 0, 2), GPU_REV(t760, 0, 3)),
186 GPU_MODEL(t820, 0x820),
187 GPU_MODEL(t830, 0x830),
188 GPU_MODEL(t860, 0x860),
189 GPU_MODEL(t880, 0x880),
191 GPU_MODEL(g71, 0x6000,
192 GPU_REV_EXT(g71, 0, 0, 1, _05dev0)),
193 GPU_MODEL(g72, 0x6001),
194 GPU_MODEL(g51, 0x7000),
195 GPU_MODEL(g76, 0x7001),
196 GPU_MODEL(g52, 0x7002),
197 GPU_MODEL(g31, 0x7003,
201 static void panfrost_gpu_init_features(struct panfrost_device *pfdev)
203 u32 gpu_id, num_js, major, minor, status, rev;
204 const char *name = "unknown";
206 u64 hw_issues = hw_issues_all;
207 const struct panfrost_model *model;
210 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES);
211 pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES);
212 pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES);
213 pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES);
214 pfdev->features.mmu_features = gpu_read(pfdev, GPU_MMU_FEATURES);
215 pfdev->features.thread_features = gpu_read(pfdev, GPU_THREAD_FEATURES);
216 pfdev->features.max_threads = gpu_read(pfdev, GPU_THREAD_MAX_THREADS);
217 pfdev->features.thread_max_workgroup_sz = gpu_read(pfdev, GPU_THREAD_MAX_WORKGROUP_SIZE);
218 pfdev->features.thread_max_barrier_sz = gpu_read(pfdev, GPU_THREAD_MAX_BARRIER_SIZE);
219 pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES);
220 for (i = 0; i < 4; i++)
221 pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i));
223 pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT);
225 pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT);
226 num_js = hweight32(pfdev->features.js_present);
227 for (i = 0; i < num_js; i++)
228 pfdev->features.js_features[i] = gpu_read(pfdev, GPU_JS_FEATURES(i));
230 pfdev->features.shader_present = gpu_read(pfdev, GPU_SHADER_PRESENT_LO);
231 pfdev->features.shader_present |= (u64)gpu_read(pfdev, GPU_SHADER_PRESENT_HI) << 32;
233 pfdev->features.tiler_present = gpu_read(pfdev, GPU_TILER_PRESENT_LO);
234 pfdev->features.tiler_present |= (u64)gpu_read(pfdev, GPU_TILER_PRESENT_HI) << 32;
236 pfdev->features.l2_present = gpu_read(pfdev, GPU_L2_PRESENT_LO);
237 pfdev->features.l2_present |= (u64)gpu_read(pfdev, GPU_L2_PRESENT_HI) << 32;
238 pfdev->features.nr_core_groups = hweight64(pfdev->features.l2_present);
240 pfdev->features.stack_present = gpu_read(pfdev, GPU_STACK_PRESENT_LO);
241 pfdev->features.stack_present |= (u64)gpu_read(pfdev, GPU_STACK_PRESENT_HI) << 32;
243 pfdev->features.thread_tls_alloc = gpu_read(pfdev, GPU_THREAD_TLS_ALLOC);
245 gpu_id = gpu_read(pfdev, GPU_ID);
246 pfdev->features.revision = gpu_id & 0xffff;
247 pfdev->features.id = gpu_id >> 16;
249 /* The T60x has an oddball ID value. Fix it up to the standard Midgard
250 * format so we (and userspace) don't have to special case it.
252 if (pfdev->features.id == 0x6956)
253 pfdev->features.id = 0x0600;
255 major = (pfdev->features.revision >> 12) & 0xf;
256 minor = (pfdev->features.revision >> 4) & 0xff;
257 status = pfdev->features.revision & 0xf;
258 rev = pfdev->features.revision;
260 gpu_id = pfdev->features.id;
262 for (model = gpu_models; model->name; model++) {
265 if (!panfrost_model_eq(pfdev, model->id))
269 hw_feat = model->features;
270 hw_issues |= model->issues;
271 for (i = 0; i < MAX_HW_REVS; i++) {
272 if (model->revs[i].revision == rev) {
275 } else if (model->revs[i].revision == (rev & ~0xf))
280 hw_issues |= model->revs[best].issues;
285 bitmap_from_u64(pfdev->features.hw_features, hw_feat);
286 bitmap_from_u64(pfdev->features.hw_issues, hw_issues);
288 dev_info(pfdev->dev, "mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x",
289 name, gpu_id, major, minor, status);
290 dev_info(pfdev->dev, "features: %64pb, issues: %64pb",
291 pfdev->features.hw_features,
292 pfdev->features.hw_issues);
294 dev_info(pfdev->dev, "Features: L2:0x%08x Shader:0x%08x Tiler:0x%08x Mem:0x%0x MMU:0x%08x AS:0x%x JS:0x%x",
295 pfdev->features.l2_features,
296 pfdev->features.core_features,
297 pfdev->features.tiler_features,
298 pfdev->features.mem_features,
299 pfdev->features.mmu_features,
300 pfdev->features.as_present,
301 pfdev->features.js_present);
303 dev_info(pfdev->dev, "shader_present=0x%0llx l2_present=0x%0llx",
304 pfdev->features.shader_present, pfdev->features.l2_present);
307 void panfrost_gpu_power_on(struct panfrost_device *pfdev)
312 panfrost_gpu_init_quirks(pfdev);
314 /* Just turn on everything for now */
315 gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present);
316 ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
317 val, val == pfdev->features.l2_present, 100, 1000);
319 dev_err(pfdev->dev, "error powering up gpu L2");
321 gpu_write(pfdev, SHADER_PWRON_LO, pfdev->features.shader_present);
322 ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
323 val, val == pfdev->features.shader_present, 100, 1000);
325 dev_err(pfdev->dev, "error powering up gpu shader");
327 gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present);
328 ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO,
329 val, val == pfdev->features.tiler_present, 100, 1000);
331 dev_err(pfdev->dev, "error powering up gpu tiler");
334 void panfrost_gpu_power_off(struct panfrost_device *pfdev)
336 gpu_write(pfdev, TILER_PWROFF_LO, 0);
337 gpu_write(pfdev, SHADER_PWROFF_LO, 0);
338 gpu_write(pfdev, L2_PWROFF_LO, 0);
341 int panfrost_gpu_init(struct panfrost_device *pfdev)
345 err = panfrost_gpu_soft_reset(pfdev);
349 panfrost_gpu_init_features(pfdev);
351 dma_set_mask_and_coherent(pfdev->dev,
352 DMA_BIT_MASK(FIELD_GET(0xff00, pfdev->features.mmu_features)));
353 dma_set_max_seg_size(pfdev->dev, UINT_MAX);
355 irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "gpu");
359 err = devm_request_irq(pfdev->dev, irq, panfrost_gpu_irq_handler,
360 IRQF_SHARED, KBUILD_MODNAME "-gpu", pfdev);
362 dev_err(pfdev->dev, "failed to request gpu irq");
366 panfrost_gpu_power_on(pfdev);
371 void panfrost_gpu_fini(struct panfrost_device *pfdev)
373 panfrost_gpu_power_off(pfdev);
376 u32 panfrost_gpu_get_latest_flush_id(struct panfrost_device *pfdev)
380 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_FLUSH_REDUCTION)) {
381 /* Flush reduction only makes sense when the GPU is kept powered on between jobs */
382 if (pm_runtime_get_if_in_use(pfdev->dev)) {
383 flush_id = gpu_read(pfdev, GPU_LATEST_FLUSH_ID);
384 pm_runtime_put(pfdev->dev);