2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
60 const struct display_timing *timings;
61 unsigned int num_timings;
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
89 unsigned int hpd_absent_delay;
92 unsigned int unprepare;
100 struct panel_simple {
101 struct drm_panel base;
106 const struct panel_desc *desc;
108 struct regulator *supply;
109 struct i2c_adapter *ddc;
111 struct gpio_desc *enable_gpio;
112 struct gpio_desc *hpd_gpio;
114 struct drm_display_mode override_mode;
117 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
119 return container_of(panel, struct panel_simple, base);
122 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
123 struct drm_connector *connector)
125 struct drm_display_mode *mode;
126 unsigned int i, num = 0;
128 for (i = 0; i < panel->desc->num_timings; i++) {
129 const struct display_timing *dt = &panel->desc->timings[i];
132 videomode_from_timing(dt, &vm);
133 mode = drm_mode_create(connector->dev);
135 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
136 dt->hactive.typ, dt->vactive.typ);
140 drm_display_mode_from_videomode(&vm, mode);
142 mode->type |= DRM_MODE_TYPE_DRIVER;
144 if (panel->desc->num_timings == 1)
145 mode->type |= DRM_MODE_TYPE_PREFERRED;
147 drm_mode_probed_add(connector, mode);
154 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
155 struct drm_connector *connector)
157 struct drm_display_mode *mode;
158 unsigned int i, num = 0;
160 for (i = 0; i < panel->desc->num_modes; i++) {
161 const struct drm_display_mode *m = &panel->desc->modes[i];
163 mode = drm_mode_duplicate(connector->dev, m);
165 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
166 m->hdisplay, m->vdisplay,
167 drm_mode_vrefresh(m));
171 mode->type |= DRM_MODE_TYPE_DRIVER;
173 if (panel->desc->num_modes == 1)
174 mode->type |= DRM_MODE_TYPE_PREFERRED;
176 drm_mode_set_name(mode);
178 drm_mode_probed_add(connector, mode);
185 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
186 struct drm_connector *connector)
188 struct drm_display_mode *mode;
189 bool has_override = panel->override_mode.type;
190 unsigned int num = 0;
196 mode = drm_mode_duplicate(connector->dev,
197 &panel->override_mode);
199 drm_mode_probed_add(connector, mode);
202 dev_err(panel->base.dev, "failed to add override mode\n");
206 /* Only add timings if override was not there or failed to validate */
207 if (num == 0 && panel->desc->num_timings)
208 num = panel_simple_get_timings_modes(panel, connector);
211 * Only add fixed modes if timings/override added no mode.
213 * We should only ever have either the display timings specified
214 * or a fixed mode. Anything else is rather bogus.
216 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
218 num = panel_simple_get_display_modes(panel, connector);
220 connector->display_info.bpc = panel->desc->bpc;
221 connector->display_info.width_mm = panel->desc->size.width;
222 connector->display_info.height_mm = panel->desc->size.height;
223 if (panel->desc->bus_format)
224 drm_display_info_set_bus_formats(&connector->display_info,
225 &panel->desc->bus_format, 1);
226 connector->display_info.bus_flags = panel->desc->bus_flags;
231 static int panel_simple_disable(struct drm_panel *panel)
233 struct panel_simple *p = to_panel_simple(panel);
238 if (p->desc->delay.disable)
239 msleep(p->desc->delay.disable);
246 static int panel_simple_unprepare(struct drm_panel *panel)
248 struct panel_simple *p = to_panel_simple(panel);
253 gpiod_set_value_cansleep(p->enable_gpio, 0);
255 regulator_disable(p->supply);
257 if (p->desc->delay.unprepare)
258 msleep(p->desc->delay.unprepare);
265 static int panel_simple_get_hpd_gpio(struct device *dev,
266 struct panel_simple *p, bool from_probe)
270 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
271 if (IS_ERR(p->hpd_gpio)) {
272 err = PTR_ERR(p->hpd_gpio);
275 * If we're called from probe we won't consider '-EPROBE_DEFER'
276 * to be an error--we'll leave the error code in "hpd_gpio".
277 * When we try to use it we'll try again. This allows for
278 * circular dependencies where the component providing the
279 * hpd gpio needs the panel to init before probing.
281 if (err != -EPROBE_DEFER || !from_probe) {
282 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
290 static int panel_simple_prepare(struct drm_panel *panel)
292 struct panel_simple *p = to_panel_simple(panel);
300 err = regulator_enable(p->supply);
302 dev_err(panel->dev, "failed to enable supply: %d\n", err);
306 gpiod_set_value_cansleep(p->enable_gpio, 1);
308 delay = p->desc->delay.prepare;
310 delay += p->desc->delay.hpd_absent_delay;
315 if (IS_ERR(p->hpd_gpio)) {
316 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
321 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
322 hpd_asserted, hpd_asserted,
324 if (hpd_asserted < 0)
329 "error waiting for hpd GPIO: %d\n", err);
339 static int panel_simple_enable(struct drm_panel *panel)
341 struct panel_simple *p = to_panel_simple(panel);
346 if (p->desc->delay.enable)
347 msleep(p->desc->delay.enable);
354 static int panel_simple_get_modes(struct drm_panel *panel,
355 struct drm_connector *connector)
357 struct panel_simple *p = to_panel_simple(panel);
360 /* probe EDID if a DDC bus is available */
362 struct edid *edid = drm_get_edid(connector, p->ddc);
364 drm_connector_update_edid_property(connector, edid);
366 num += drm_add_edid_modes(connector, edid);
371 /* add hard-coded panel modes */
372 num += panel_simple_get_non_edid_modes(p, connector);
377 static int panel_simple_get_timings(struct drm_panel *panel,
378 unsigned int num_timings,
379 struct display_timing *timings)
381 struct panel_simple *p = to_panel_simple(panel);
384 if (p->desc->num_timings < num_timings)
385 num_timings = p->desc->num_timings;
388 for (i = 0; i < num_timings; i++)
389 timings[i] = p->desc->timings[i];
391 return p->desc->num_timings;
394 static const struct drm_panel_funcs panel_simple_funcs = {
395 .disable = panel_simple_disable,
396 .unprepare = panel_simple_unprepare,
397 .prepare = panel_simple_prepare,
398 .enable = panel_simple_enable,
399 .get_modes = panel_simple_get_modes,
400 .get_timings = panel_simple_get_timings,
403 static struct panel_desc panel_dpi;
405 static int panel_dpi_probe(struct device *dev,
406 struct panel_simple *panel)
408 struct display_timing *timing;
409 const struct device_node *np;
410 struct panel_desc *desc;
411 unsigned int bus_flags;
416 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
420 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
424 ret = of_get_display_timing(np, "panel-timing", timing);
426 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
431 desc->timings = timing;
432 desc->num_timings = 1;
434 of_property_read_u32(np, "width-mm", &desc->size.width);
435 of_property_read_u32(np, "height-mm", &desc->size.height);
437 /* Extract bus_flags from display_timing */
439 vm.flags = timing->flags;
440 drm_bus_flags_from_videomode(&vm, &bus_flags);
441 desc->bus_flags = bus_flags;
443 /* We do not know the connector for the DT node, so guess it */
444 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
451 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
452 (to_check->field.typ >= bounds->field.min && \
453 to_check->field.typ <= bounds->field.max)
454 static void panel_simple_parse_panel_timing_node(struct device *dev,
455 struct panel_simple *panel,
456 const struct display_timing *ot)
458 const struct panel_desc *desc = panel->desc;
462 if (WARN_ON(desc->num_modes)) {
463 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
466 if (WARN_ON(!desc->num_timings)) {
467 dev_err(dev, "Reject override mode: no timings specified\n");
471 for (i = 0; i < panel->desc->num_timings; i++) {
472 const struct display_timing *dt = &panel->desc->timings[i];
474 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
475 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
476 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
477 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
478 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
479 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
484 if (ot->flags != dt->flags)
487 videomode_from_timing(ot, &vm);
488 drm_display_mode_from_videomode(&vm, &panel->override_mode);
489 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
490 DRM_MODE_TYPE_PREFERRED;
494 if (WARN_ON(!panel->override_mode.type))
495 dev_err(dev, "Reject override mode: No display_timing found\n");
498 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
500 struct panel_simple *panel;
501 struct display_timing dt;
502 struct device_node *ddc;
507 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
511 panel->enabled = false;
512 panel->prepared = false;
515 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
516 if (!panel->no_hpd) {
517 err = panel_simple_get_hpd_gpio(dev, panel, true);
522 panel->supply = devm_regulator_get(dev, "power");
523 if (IS_ERR(panel->supply))
524 return PTR_ERR(panel->supply);
526 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
528 if (IS_ERR(panel->enable_gpio)) {
529 err = PTR_ERR(panel->enable_gpio);
530 if (err != -EPROBE_DEFER)
531 dev_err(dev, "failed to request GPIO: %d\n", err);
535 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
537 panel->ddc = of_find_i2c_adapter_by_node(ddc);
541 return -EPROBE_DEFER;
544 if (desc == &panel_dpi) {
545 /* Handle the generic panel-dpi binding */
546 err = panel_dpi_probe(dev, panel);
550 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
551 panel_simple_parse_panel_timing_node(dev, panel, &dt);
554 connector_type = desc->connector_type;
555 /* Catch common mistakes for panels. */
556 switch (connector_type) {
558 dev_warn(dev, "Specify missing connector_type\n");
559 connector_type = DRM_MODE_CONNECTOR_DPI;
561 case DRM_MODE_CONNECTOR_LVDS:
562 WARN_ON(desc->bus_flags &
563 ~(DRM_BUS_FLAG_DE_LOW |
564 DRM_BUS_FLAG_DE_HIGH |
565 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
566 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
567 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
568 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
569 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
570 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
572 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
573 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
576 case DRM_MODE_CONNECTOR_eDP:
577 if (desc->bus_format == 0)
578 dev_warn(dev, "Specify missing bus_format\n");
579 if (desc->bpc != 6 && desc->bpc != 8)
580 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
582 case DRM_MODE_CONNECTOR_DSI:
583 if (desc->bpc != 6 && desc->bpc != 8)
584 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
586 case DRM_MODE_CONNECTOR_DPI:
587 bus_flags = DRM_BUS_FLAG_DE_LOW |
588 DRM_BUS_FLAG_DE_HIGH |
589 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
590 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
591 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
592 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
593 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
594 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
595 if (desc->bus_flags & ~bus_flags)
596 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
597 if (!(desc->bus_flags & bus_flags))
598 dev_warn(dev, "Specify missing bus_flags\n");
599 if (desc->bus_format == 0)
600 dev_warn(dev, "Specify missing bus_format\n");
601 if (desc->bpc != 6 && desc->bpc != 8)
602 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
605 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
606 connector_type = DRM_MODE_CONNECTOR_DPI;
610 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
612 err = drm_panel_of_backlight(&panel->base);
616 drm_panel_add(&panel->base);
618 dev_set_drvdata(dev, panel);
624 put_device(&panel->ddc->dev);
629 static int panel_simple_remove(struct device *dev)
631 struct panel_simple *panel = dev_get_drvdata(dev);
633 drm_panel_remove(&panel->base);
634 drm_panel_disable(&panel->base);
635 drm_panel_unprepare(&panel->base);
638 put_device(&panel->ddc->dev);
643 static void panel_simple_shutdown(struct device *dev)
645 struct panel_simple *panel = dev_get_drvdata(dev);
647 drm_panel_disable(&panel->base);
648 drm_panel_unprepare(&panel->base);
651 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
654 .hsync_start = 480 + 2,
655 .hsync_end = 480 + 2 + 41,
656 .htotal = 480 + 2 + 41 + 2,
658 .vsync_start = 272 + 2,
659 .vsync_end = 272 + 2 + 10,
660 .vtotal = 272 + 2 + 10 + 2,
661 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
664 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
665 .modes = &ire_am_480272h3tmqw_t01h_mode,
672 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
675 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
678 .hsync_start = 800 + 0,
679 .hsync_end = 800 + 0 + 255,
680 .htotal = 800 + 0 + 255 + 0,
682 .vsync_start = 480 + 2,
683 .vsync_end = 480 + 2 + 45,
684 .vtotal = 480 + 2 + 45 + 0,
685 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
688 static const struct panel_desc ampire_am800480r3tmqwa1h = {
689 .modes = &ire_am800480r3tmqwa1h_mode,
696 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
699 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
700 .pixelclock = { 26400000, 33300000, 46800000 },
701 .hactive = { 800, 800, 800 },
702 .hfront_porch = { 16, 210, 354 },
703 .hback_porch = { 45, 36, 6 },
704 .hsync_len = { 1, 10, 40 },
705 .vactive = { 480, 480, 480 },
706 .vfront_porch = { 7, 22, 147 },
707 .vback_porch = { 22, 13, 3 },
708 .vsync_len = { 1, 10, 20 },
709 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
710 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
713 static const struct panel_desc armadeus_st0700_adapt = {
714 .timings = &santek_st0700i5y_rbslw_f_timing,
721 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
722 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
725 static const struct drm_display_mode auo_b101aw03_mode = {
728 .hsync_start = 1024 + 156,
729 .hsync_end = 1024 + 156 + 8,
730 .htotal = 1024 + 156 + 8 + 156,
732 .vsync_start = 600 + 16,
733 .vsync_end = 600 + 16 + 6,
734 .vtotal = 600 + 16 + 6 + 16,
737 static const struct panel_desc auo_b101aw03 = {
738 .modes = &auo_b101aw03_mode,
745 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
746 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
747 .connector_type = DRM_MODE_CONNECTOR_LVDS,
750 static const struct display_timing auo_b101ean01_timing = {
751 .pixelclock = { 65300000, 72500000, 75000000 },
752 .hactive = { 1280, 1280, 1280 },
753 .hfront_porch = { 18, 119, 119 },
754 .hback_porch = { 21, 21, 21 },
755 .hsync_len = { 32, 32, 32 },
756 .vactive = { 800, 800, 800 },
757 .vfront_porch = { 4, 4, 4 },
758 .vback_porch = { 8, 8, 8 },
759 .vsync_len = { 18, 20, 20 },
762 static const struct panel_desc auo_b101ean01 = {
763 .timings = &auo_b101ean01_timing,
772 static const struct drm_display_mode auo_b101xtn01_mode = {
775 .hsync_start = 1366 + 20,
776 .hsync_end = 1366 + 20 + 70,
777 .htotal = 1366 + 20 + 70,
779 .vsync_start = 768 + 14,
780 .vsync_end = 768 + 14 + 42,
781 .vtotal = 768 + 14 + 42,
782 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
785 static const struct panel_desc auo_b101xtn01 = {
786 .modes = &auo_b101xtn01_mode,
795 static const struct drm_display_mode auo_b116xak01_mode = {
798 .hsync_start = 1366 + 48,
799 .hsync_end = 1366 + 48 + 32,
800 .htotal = 1366 + 48 + 32 + 10,
802 .vsync_start = 768 + 4,
803 .vsync_end = 768 + 4 + 6,
804 .vtotal = 768 + 4 + 6 + 15,
805 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
808 static const struct panel_desc auo_b116xak01 = {
809 .modes = &auo_b116xak01_mode,
817 .hpd_absent_delay = 200,
819 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
820 .connector_type = DRM_MODE_CONNECTOR_eDP,
823 static const struct drm_display_mode auo_b116xw03_mode = {
826 .hsync_start = 1366 + 40,
827 .hsync_end = 1366 + 40 + 40,
828 .htotal = 1366 + 40 + 40 + 32,
830 .vsync_start = 768 + 10,
831 .vsync_end = 768 + 10 + 12,
832 .vtotal = 768 + 10 + 12 + 6,
833 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
836 static const struct panel_desc auo_b116xw03 = {
837 .modes = &auo_b116xw03_mode,
847 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
848 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
849 .connector_type = DRM_MODE_CONNECTOR_eDP,
852 static const struct drm_display_mode auo_b133xtn01_mode = {
855 .hsync_start = 1366 + 48,
856 .hsync_end = 1366 + 48 + 32,
857 .htotal = 1366 + 48 + 32 + 20,
859 .vsync_start = 768 + 3,
860 .vsync_end = 768 + 3 + 6,
861 .vtotal = 768 + 3 + 6 + 13,
864 static const struct panel_desc auo_b133xtn01 = {
865 .modes = &auo_b133xtn01_mode,
874 static const struct drm_display_mode auo_b133htn01_mode = {
877 .hsync_start = 1920 + 172,
878 .hsync_end = 1920 + 172 + 80,
879 .htotal = 1920 + 172 + 80 + 60,
881 .vsync_start = 1080 + 25,
882 .vsync_end = 1080 + 25 + 10,
883 .vtotal = 1080 + 25 + 10 + 10,
886 static const struct panel_desc auo_b133htn01 = {
887 .modes = &auo_b133htn01_mode,
901 static const struct display_timing auo_g070vvn01_timings = {
902 .pixelclock = { 33300000, 34209000, 45000000 },
903 .hactive = { 800, 800, 800 },
904 .hfront_porch = { 20, 40, 200 },
905 .hback_porch = { 87, 40, 1 },
906 .hsync_len = { 1, 48, 87 },
907 .vactive = { 480, 480, 480 },
908 .vfront_porch = { 5, 13, 200 },
909 .vback_porch = { 31, 31, 29 },
910 .vsync_len = { 1, 1, 3 },
913 static const struct panel_desc auo_g070vvn01 = {
914 .timings = &auo_g070vvn01_timings,
929 static const struct drm_display_mode auo_g101evn010_mode = {
932 .hsync_start = 1280 + 82,
933 .hsync_end = 1280 + 82 + 2,
934 .htotal = 1280 + 82 + 2 + 84,
936 .vsync_start = 800 + 8,
937 .vsync_end = 800 + 8 + 2,
938 .vtotal = 800 + 8 + 2 + 6,
941 static const struct panel_desc auo_g101evn010 = {
942 .modes = &auo_g101evn010_mode,
949 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
950 .connector_type = DRM_MODE_CONNECTOR_LVDS,
953 static const struct drm_display_mode auo_g104sn02_mode = {
956 .hsync_start = 800 + 40,
957 .hsync_end = 800 + 40 + 216,
958 .htotal = 800 + 40 + 216 + 128,
960 .vsync_start = 600 + 10,
961 .vsync_end = 600 + 10 + 35,
962 .vtotal = 600 + 10 + 35 + 2,
965 static const struct panel_desc auo_g104sn02 = {
966 .modes = &auo_g104sn02_mode,
975 static const struct drm_display_mode auo_g121ean01_mode = {
978 .hsync_start = 1280 + 58,
979 .hsync_end = 1280 + 58 + 8,
980 .htotal = 1280 + 58 + 8 + 70,
982 .vsync_start = 800 + 6,
983 .vsync_end = 800 + 6 + 4,
984 .vtotal = 800 + 6 + 4 + 10,
987 static const struct panel_desc auo_g121ean01 = {
988 .modes = &auo_g121ean01_mode,
995 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
996 .connector_type = DRM_MODE_CONNECTOR_LVDS,
999 static const struct display_timing auo_g133han01_timings = {
1000 .pixelclock = { 134000000, 141200000, 149000000 },
1001 .hactive = { 1920, 1920, 1920 },
1002 .hfront_porch = { 39, 58, 77 },
1003 .hback_porch = { 59, 88, 117 },
1004 .hsync_len = { 28, 42, 56 },
1005 .vactive = { 1080, 1080, 1080 },
1006 .vfront_porch = { 3, 8, 11 },
1007 .vback_porch = { 5, 14, 19 },
1008 .vsync_len = { 4, 14, 19 },
1011 static const struct panel_desc auo_g133han01 = {
1012 .timings = &auo_g133han01_timings,
1025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1026 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1029 static const struct drm_display_mode auo_g156xtn01_mode = {
1032 .hsync_start = 1366 + 33,
1033 .hsync_end = 1366 + 33 + 67,
1036 .vsync_start = 768 + 4,
1037 .vsync_end = 768 + 4 + 4,
1041 static const struct panel_desc auo_g156xtn01 = {
1042 .modes = &auo_g156xtn01_mode,
1049 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1050 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1053 static const struct display_timing auo_g185han01_timings = {
1054 .pixelclock = { 120000000, 144000000, 175000000 },
1055 .hactive = { 1920, 1920, 1920 },
1056 .hfront_porch = { 36, 120, 148 },
1057 .hback_porch = { 24, 88, 108 },
1058 .hsync_len = { 20, 48, 64 },
1059 .vactive = { 1080, 1080, 1080 },
1060 .vfront_porch = { 6, 10, 40 },
1061 .vback_porch = { 2, 5, 20 },
1062 .vsync_len = { 2, 5, 20 },
1065 static const struct panel_desc auo_g185han01 = {
1066 .timings = &auo_g185han01_timings,
1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1080 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1083 static const struct display_timing auo_g190ean01_timings = {
1084 .pixelclock = { 90000000, 108000000, 135000000 },
1085 .hactive = { 1280, 1280, 1280 },
1086 .hfront_porch = { 126, 184, 1266 },
1087 .hback_porch = { 84, 122, 844 },
1088 .hsync_len = { 70, 102, 704 },
1089 .vactive = { 1024, 1024, 1024 },
1090 .vfront_porch = { 4, 26, 76 },
1091 .vback_porch = { 2, 8, 25 },
1092 .vsync_len = { 2, 8, 25 },
1095 static const struct panel_desc auo_g190ean01 = {
1096 .timings = &auo_g190ean01_timings,
1109 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1110 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1113 static const struct display_timing auo_p320hvn03_timings = {
1114 .pixelclock = { 106000000, 148500000, 164000000 },
1115 .hactive = { 1920, 1920, 1920 },
1116 .hfront_porch = { 25, 50, 130 },
1117 .hback_porch = { 25, 50, 130 },
1118 .hsync_len = { 20, 40, 105 },
1119 .vactive = { 1080, 1080, 1080 },
1120 .vfront_porch = { 8, 17, 150 },
1121 .vback_porch = { 8, 17, 150 },
1122 .vsync_len = { 4, 11, 100 },
1125 static const struct panel_desc auo_p320hvn03 = {
1126 .timings = &auo_p320hvn03_timings,
1138 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1139 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1142 static const struct drm_display_mode auo_t215hvn01_mode = {
1145 .hsync_start = 1920 + 88,
1146 .hsync_end = 1920 + 88 + 44,
1147 .htotal = 1920 + 88 + 44 + 148,
1149 .vsync_start = 1080 + 4,
1150 .vsync_end = 1080 + 4 + 5,
1151 .vtotal = 1080 + 4 + 5 + 36,
1154 static const struct panel_desc auo_t215hvn01 = {
1155 .modes = &auo_t215hvn01_mode,
1168 static const struct drm_display_mode avic_tm070ddh03_mode = {
1171 .hsync_start = 1024 + 160,
1172 .hsync_end = 1024 + 160 + 4,
1173 .htotal = 1024 + 160 + 4 + 156,
1175 .vsync_start = 600 + 17,
1176 .vsync_end = 600 + 17 + 1,
1177 .vtotal = 600 + 17 + 1 + 17,
1180 static const struct panel_desc avic_tm070ddh03 = {
1181 .modes = &avic_tm070ddh03_mode,
1195 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1198 .hsync_start = 800 + 40,
1199 .hsync_end = 800 + 40 + 48,
1200 .htotal = 800 + 40 + 48 + 40,
1202 .vsync_start = 480 + 13,
1203 .vsync_end = 480 + 13 + 3,
1204 .vtotal = 480 + 13 + 3 + 29,
1207 static const struct panel_desc bananapi_s070wv20_ct16 = {
1208 .modes = &bananapi_s070wv20_ct16_mode,
1217 static const struct drm_display_mode boe_hv070wsa_mode = {
1220 .hsync_start = 1024 + 30,
1221 .hsync_end = 1024 + 30 + 30,
1222 .htotal = 1024 + 30 + 30 + 30,
1224 .vsync_start = 600 + 10,
1225 .vsync_end = 600 + 10 + 10,
1226 .vtotal = 600 + 10 + 10 + 10,
1229 static const struct panel_desc boe_hv070wsa = {
1230 .modes = &boe_hv070wsa_mode,
1237 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1238 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1239 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1242 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1246 .hsync_start = 1280 + 48,
1247 .hsync_end = 1280 + 48 + 32,
1248 .htotal = 1280 + 48 + 32 + 80,
1250 .vsync_start = 800 + 3,
1251 .vsync_end = 800 + 3 + 5,
1252 .vtotal = 800 + 3 + 5 + 24,
1257 .hsync_start = 1280 + 48,
1258 .hsync_end = 1280 + 48 + 32,
1259 .htotal = 1280 + 48 + 32 + 80,
1261 .vsync_start = 800 + 3,
1262 .vsync_end = 800 + 3 + 5,
1263 .vtotal = 800 + 3 + 5 + 24,
1267 static const struct panel_desc boe_nv101wxmn51 = {
1268 .modes = boe_nv101wxmn51_modes,
1269 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1282 /* Also used for boe_nv133fhm_n62 */
1283 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1286 .hsync_start = 1920 + 48,
1287 .hsync_end = 1920 + 48 + 32,
1288 .htotal = 1920 + 48 + 32 + 200,
1290 .vsync_start = 1080 + 3,
1291 .vsync_end = 1080 + 3 + 6,
1292 .vtotal = 1080 + 3 + 6 + 31,
1295 /* Also used for boe_nv133fhm_n62 */
1296 static const struct panel_desc boe_nv133fhm_n61 = {
1297 .modes = &boe_nv133fhm_n61_modes,
1306 * When power is first given to the panel there's a short
1307 * spike on the HPD line. It was explained that this spike
1308 * was until the TCON data download was complete. On
1309 * one system this was measured at 8 ms. We'll put 15 ms
1310 * in the prepare delay just to be safe and take it away
1311 * from the hpd_absent_delay (which would otherwise be 200 ms)
1312 * to handle this. That means:
1313 * - If HPD isn't hooked up you still have 200 ms delay.
1314 * - If HPD is hooked up we won't try to look at it for the
1318 .hpd_absent_delay = 185,
1322 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1323 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1324 .connector_type = DRM_MODE_CONNECTOR_eDP,
1327 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1331 .hsync_start = 1920 + 48,
1332 .hsync_end = 1920 + 48 + 32,
1335 .vsync_start = 1080 + 3,
1336 .vsync_end = 1080 + 3 + 5,
1341 static const struct panel_desc boe_nv140fhmn49 = {
1342 .modes = boe_nv140fhmn49_modes,
1343 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1354 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1355 .connector_type = DRM_MODE_CONNECTOR_eDP,
1358 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1361 .hsync_start = 480 + 5,
1362 .hsync_end = 480 + 5 + 5,
1363 .htotal = 480 + 5 + 5 + 40,
1365 .vsync_start = 272 + 8,
1366 .vsync_end = 272 + 8 + 8,
1367 .vtotal = 272 + 8 + 8 + 8,
1368 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1371 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1372 .modes = &cdtech_s043wq26h_ct7_mode,
1379 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1382 /* S070PWS19HP-FC21 2017/04/22 */
1383 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1386 .hsync_start = 1024 + 160,
1387 .hsync_end = 1024 + 160 + 20,
1388 .htotal = 1024 + 160 + 20 + 140,
1390 .vsync_start = 600 + 12,
1391 .vsync_end = 600 + 12 + 3,
1392 .vtotal = 600 + 12 + 3 + 20,
1393 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1396 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1397 .modes = &cdtech_s070pws19hp_fc21_mode,
1404 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1405 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1406 .connector_type = DRM_MODE_CONNECTOR_DPI,
1409 /* S070SWV29HG-DC44 2017/09/21 */
1410 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1413 .hsync_start = 800 + 210,
1414 .hsync_end = 800 + 210 + 2,
1415 .htotal = 800 + 210 + 2 + 44,
1417 .vsync_start = 480 + 22,
1418 .vsync_end = 480 + 22 + 2,
1419 .vtotal = 480 + 22 + 2 + 21,
1420 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1423 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1424 .modes = &cdtech_s070swv29hg_dc44_mode,
1431 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1432 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1433 .connector_type = DRM_MODE_CONNECTOR_DPI,
1436 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1439 .hsync_start = 800 + 40,
1440 .hsync_end = 800 + 40 + 40,
1441 .htotal = 800 + 40 + 40 + 48,
1443 .vsync_start = 480 + 29,
1444 .vsync_end = 480 + 29 + 13,
1445 .vtotal = 480 + 29 + 13 + 3,
1446 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1449 static const struct panel_desc cdtech_s070wv95_ct16 = {
1450 .modes = &cdtech_s070wv95_ct16_mode,
1459 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1460 .pixelclock = { 68900000, 71100000, 73400000 },
1461 .hactive = { 1280, 1280, 1280 },
1462 .hfront_porch = { 65, 80, 95 },
1463 .hback_porch = { 64, 79, 94 },
1464 .hsync_len = { 1, 1, 1 },
1465 .vactive = { 800, 800, 800 },
1466 .vfront_porch = { 7, 11, 14 },
1467 .vback_porch = { 7, 11, 14 },
1468 .vsync_len = { 1, 1, 1 },
1469 .flags = DISPLAY_FLAGS_DE_HIGH,
1472 static const struct panel_desc chefree_ch101olhlwh_002 = {
1473 .timings = &chefree_ch101olhlwh_002_timing,
1484 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1485 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1486 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1489 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1492 .hsync_start = 800 + 49,
1493 .hsync_end = 800 + 49 + 33,
1494 .htotal = 800 + 49 + 33 + 17,
1496 .vsync_start = 1280 + 1,
1497 .vsync_end = 1280 + 1 + 7,
1498 .vtotal = 1280 + 1 + 7 + 15,
1499 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1502 static const struct panel_desc chunghwa_claa070wp03xg = {
1503 .modes = &chunghwa_claa070wp03xg_mode,
1510 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1511 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1512 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1515 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1518 .hsync_start = 1366 + 58,
1519 .hsync_end = 1366 + 58 + 58,
1520 .htotal = 1366 + 58 + 58 + 58,
1522 .vsync_start = 768 + 4,
1523 .vsync_end = 768 + 4 + 4,
1524 .vtotal = 768 + 4 + 4 + 4,
1527 static const struct panel_desc chunghwa_claa101wa01a = {
1528 .modes = &chunghwa_claa101wa01a_mode,
1535 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1536 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1537 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1540 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1543 .hsync_start = 1366 + 48,
1544 .hsync_end = 1366 + 48 + 32,
1545 .htotal = 1366 + 48 + 32 + 20,
1547 .vsync_start = 768 + 16,
1548 .vsync_end = 768 + 16 + 8,
1549 .vtotal = 768 + 16 + 8 + 16,
1552 static const struct panel_desc chunghwa_claa101wb01 = {
1553 .modes = &chunghwa_claa101wb01_mode,
1560 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1561 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1562 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1565 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1568 .hsync_start = 800 + 40,
1569 .hsync_end = 800 + 40 + 128,
1570 .htotal = 800 + 40 + 128 + 88,
1572 .vsync_start = 480 + 10,
1573 .vsync_end = 480 + 10 + 2,
1574 .vtotal = 480 + 10 + 2 + 33,
1575 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1578 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1579 .modes = &dataimage_scf0700c48ggu18_mode,
1586 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1587 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1590 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1591 .pixelclock = { 45000000, 51200000, 57000000 },
1592 .hactive = { 1024, 1024, 1024 },
1593 .hfront_porch = { 100, 106, 113 },
1594 .hback_porch = { 100, 106, 113 },
1595 .hsync_len = { 100, 108, 114 },
1596 .vactive = { 600, 600, 600 },
1597 .vfront_porch = { 8, 11, 15 },
1598 .vback_porch = { 8, 11, 15 },
1599 .vsync_len = { 9, 13, 15 },
1600 .flags = DISPLAY_FLAGS_DE_HIGH,
1603 static const struct panel_desc dlc_dlc0700yzg_1 = {
1604 .timings = &dlc_dlc0700yzg_1_timing,
1616 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1617 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1620 static const struct display_timing dlc_dlc1010gig_timing = {
1621 .pixelclock = { 68900000, 71100000, 73400000 },
1622 .hactive = { 1280, 1280, 1280 },
1623 .hfront_porch = { 43, 53, 63 },
1624 .hback_porch = { 43, 53, 63 },
1625 .hsync_len = { 44, 54, 64 },
1626 .vactive = { 800, 800, 800 },
1627 .vfront_porch = { 5, 8, 11 },
1628 .vback_porch = { 5, 8, 11 },
1629 .vsync_len = { 5, 7, 11 },
1630 .flags = DISPLAY_FLAGS_DE_HIGH,
1633 static const struct panel_desc dlc_dlc1010gig = {
1634 .timings = &dlc_dlc1010gig_timing,
1647 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1648 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1651 static const struct drm_display_mode edt_et035012dm6_mode = {
1654 .hsync_start = 320 + 20,
1655 .hsync_end = 320 + 20 + 30,
1656 .htotal = 320 + 20 + 68,
1658 .vsync_start = 240 + 4,
1659 .vsync_end = 240 + 4 + 4,
1660 .vtotal = 240 + 4 + 4 + 14,
1661 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1664 static const struct panel_desc edt_et035012dm6 = {
1665 .modes = &edt_et035012dm6_mode,
1672 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1673 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1676 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1679 .hsync_start = 480 + 8,
1680 .hsync_end = 480 + 8 + 4,
1681 .htotal = 480 + 8 + 4 + 41,
1684 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1689 .vsync_start = 288 + 2,
1690 .vsync_end = 288 + 2 + 4,
1691 .vtotal = 288 + 2 + 4 + 10,
1694 static const struct panel_desc edt_etm043080dh6gp = {
1695 .modes = &edt_etm043080dh6gp_mode,
1702 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1703 .connector_type = DRM_MODE_CONNECTOR_DPI,
1706 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1709 .hsync_start = 480 + 2,
1710 .hsync_end = 480 + 2 + 41,
1711 .htotal = 480 + 2 + 41 + 2,
1713 .vsync_start = 272 + 2,
1714 .vsync_end = 272 + 2 + 10,
1715 .vtotal = 272 + 2 + 10 + 2,
1716 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1719 static const struct panel_desc edt_etm0430g0dh6 = {
1720 .modes = &edt_etm0430g0dh6_mode,
1729 static const struct drm_display_mode edt_et057090dhu_mode = {
1732 .hsync_start = 640 + 16,
1733 .hsync_end = 640 + 16 + 30,
1734 .htotal = 640 + 16 + 30 + 114,
1736 .vsync_start = 480 + 10,
1737 .vsync_end = 480 + 10 + 3,
1738 .vtotal = 480 + 10 + 3 + 32,
1739 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1742 static const struct panel_desc edt_et057090dhu = {
1743 .modes = &edt_et057090dhu_mode,
1750 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1751 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1752 .connector_type = DRM_MODE_CONNECTOR_DPI,
1755 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1758 .hsync_start = 800 + 40,
1759 .hsync_end = 800 + 40 + 128,
1760 .htotal = 800 + 40 + 128 + 88,
1762 .vsync_start = 480 + 10,
1763 .vsync_end = 480 + 10 + 2,
1764 .vtotal = 480 + 10 + 2 + 33,
1765 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1768 static const struct panel_desc edt_etm0700g0dh6 = {
1769 .modes = &edt_etm0700g0dh6_mode,
1776 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1777 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1780 static const struct panel_desc edt_etm0700g0bdh6 = {
1781 .modes = &edt_etm0700g0dh6_mode,
1788 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1789 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1792 static const struct display_timing evervision_vgg804821_timing = {
1793 .pixelclock = { 27600000, 33300000, 50000000 },
1794 .hactive = { 800, 800, 800 },
1795 .hfront_porch = { 40, 66, 70 },
1796 .hback_porch = { 40, 67, 70 },
1797 .hsync_len = { 40, 67, 70 },
1798 .vactive = { 480, 480, 480 },
1799 .vfront_porch = { 6, 10, 10 },
1800 .vback_porch = { 7, 11, 11 },
1801 .vsync_len = { 7, 11, 11 },
1802 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1803 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1804 DISPLAY_FLAGS_SYNC_NEGEDGE,
1807 static const struct panel_desc evervision_vgg804821 = {
1808 .timings = &evervision_vgg804821_timing,
1815 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1816 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1819 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1822 .hsync_start = 800 + 168,
1823 .hsync_end = 800 + 168 + 64,
1824 .htotal = 800 + 168 + 64 + 88,
1826 .vsync_start = 480 + 37,
1827 .vsync_end = 480 + 37 + 2,
1828 .vtotal = 480 + 37 + 2 + 8,
1831 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1832 .modes = &foxlink_fl500wvr00_a0t_mode,
1839 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1842 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1846 .hsync_start = 320 + 44,
1847 .hsync_end = 320 + 44 + 16,
1848 .htotal = 320 + 44 + 16 + 20,
1850 .vsync_start = 240 + 2,
1851 .vsync_end = 240 + 2 + 6,
1852 .vtotal = 240 + 2 + 6 + 2,
1853 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1858 .hsync_start = 320 + 56,
1859 .hsync_end = 320 + 56 + 16,
1860 .htotal = 320 + 56 + 16 + 40,
1862 .vsync_start = 240 + 2,
1863 .vsync_end = 240 + 2 + 6,
1864 .vtotal = 240 + 2 + 6 + 2,
1865 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1869 static const struct panel_desc frida_frd350h54004 = {
1870 .modes = frida_frd350h54004_modes,
1871 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1877 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1878 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1879 .connector_type = DRM_MODE_CONNECTOR_DPI,
1882 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1885 .hsync_start = 800 + 20,
1886 .hsync_end = 800 + 20 + 24,
1887 .htotal = 800 + 20 + 24 + 20,
1889 .vsync_start = 1280 + 4,
1890 .vsync_end = 1280 + 4 + 8,
1891 .vtotal = 1280 + 4 + 8 + 4,
1892 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1895 static const struct panel_desc friendlyarm_hd702e = {
1896 .modes = &friendlyarm_hd702e_mode,
1904 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1907 .hsync_start = 480 + 5,
1908 .hsync_end = 480 + 5 + 1,
1909 .htotal = 480 + 5 + 1 + 40,
1911 .vsync_start = 272 + 8,
1912 .vsync_end = 272 + 8 + 1,
1913 .vtotal = 272 + 8 + 1 + 8,
1916 static const struct panel_desc giantplus_gpg482739qs5 = {
1917 .modes = &giantplus_gpg482739qs5_mode,
1924 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1927 static const struct display_timing giantplus_gpm940b0_timing = {
1928 .pixelclock = { 13500000, 27000000, 27500000 },
1929 .hactive = { 320, 320, 320 },
1930 .hfront_porch = { 14, 686, 718 },
1931 .hback_porch = { 50, 70, 255 },
1932 .hsync_len = { 1, 1, 1 },
1933 .vactive = { 240, 240, 240 },
1934 .vfront_porch = { 1, 1, 179 },
1935 .vback_porch = { 1, 21, 31 },
1936 .vsync_len = { 1, 1, 6 },
1937 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1940 static const struct panel_desc giantplus_gpm940b0 = {
1941 .timings = &giantplus_gpm940b0_timing,
1948 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1949 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1952 static const struct display_timing hannstar_hsd070pww1_timing = {
1953 .pixelclock = { 64300000, 71100000, 82000000 },
1954 .hactive = { 1280, 1280, 1280 },
1955 .hfront_porch = { 1, 1, 10 },
1956 .hback_porch = { 1, 1, 10 },
1958 * According to the data sheet, the minimum horizontal blanking interval
1959 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1960 * minimum working horizontal blanking interval to be 60 clocks.
1962 .hsync_len = { 58, 158, 661 },
1963 .vactive = { 800, 800, 800 },
1964 .vfront_porch = { 1, 1, 10 },
1965 .vback_porch = { 1, 1, 10 },
1966 .vsync_len = { 1, 21, 203 },
1967 .flags = DISPLAY_FLAGS_DE_HIGH,
1970 static const struct panel_desc hannstar_hsd070pww1 = {
1971 .timings = &hannstar_hsd070pww1_timing,
1978 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1979 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1982 static const struct display_timing hannstar_hsd100pxn1_timing = {
1983 .pixelclock = { 55000000, 65000000, 75000000 },
1984 .hactive = { 1024, 1024, 1024 },
1985 .hfront_porch = { 40, 40, 40 },
1986 .hback_porch = { 220, 220, 220 },
1987 .hsync_len = { 20, 60, 100 },
1988 .vactive = { 768, 768, 768 },
1989 .vfront_porch = { 7, 7, 7 },
1990 .vback_porch = { 21, 21, 21 },
1991 .vsync_len = { 10, 10, 10 },
1992 .flags = DISPLAY_FLAGS_DE_HIGH,
1995 static const struct panel_desc hannstar_hsd100pxn1 = {
1996 .timings = &hannstar_hsd100pxn1_timing,
2003 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2004 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2007 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2010 .hsync_start = 800 + 85,
2011 .hsync_end = 800 + 85 + 86,
2012 .htotal = 800 + 85 + 86 + 85,
2014 .vsync_start = 480 + 16,
2015 .vsync_end = 480 + 16 + 13,
2016 .vtotal = 480 + 16 + 13 + 16,
2019 static const struct panel_desc hitachi_tx23d38vm0caa = {
2020 .modes = &hitachi_tx23d38vm0caa_mode,
2033 static const struct drm_display_mode innolux_at043tn24_mode = {
2036 .hsync_start = 480 + 2,
2037 .hsync_end = 480 + 2 + 41,
2038 .htotal = 480 + 2 + 41 + 2,
2040 .vsync_start = 272 + 2,
2041 .vsync_end = 272 + 2 + 10,
2042 .vtotal = 272 + 2 + 10 + 2,
2043 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2046 static const struct panel_desc innolux_at043tn24 = {
2047 .modes = &innolux_at043tn24_mode,
2054 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2055 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2058 static const struct drm_display_mode innolux_at070tn92_mode = {
2061 .hsync_start = 800 + 210,
2062 .hsync_end = 800 + 210 + 20,
2063 .htotal = 800 + 210 + 20 + 46,
2065 .vsync_start = 480 + 22,
2066 .vsync_end = 480 + 22 + 10,
2067 .vtotal = 480 + 22 + 23 + 10,
2070 static const struct panel_desc innolux_at070tn92 = {
2071 .modes = &innolux_at070tn92_mode,
2077 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2080 static const struct display_timing innolux_g070y2_l01_timing = {
2081 .pixelclock = { 28000000, 29500000, 32000000 },
2082 .hactive = { 800, 800, 800 },
2083 .hfront_porch = { 61, 91, 141 },
2084 .hback_porch = { 60, 90, 140 },
2085 .hsync_len = { 12, 12, 12 },
2086 .vactive = { 480, 480, 480 },
2087 .vfront_porch = { 4, 9, 30 },
2088 .vback_porch = { 4, 8, 28 },
2089 .vsync_len = { 2, 2, 2 },
2090 .flags = DISPLAY_FLAGS_DE_HIGH,
2093 static const struct panel_desc innolux_g070y2_l01 = {
2094 .timings = &innolux_g070y2_l01_timing,
2107 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2108 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2111 static const struct display_timing innolux_g101ice_l01_timing = {
2112 .pixelclock = { 60400000, 71100000, 74700000 },
2113 .hactive = { 1280, 1280, 1280 },
2114 .hfront_porch = { 41, 80, 100 },
2115 .hback_porch = { 40, 79, 99 },
2116 .hsync_len = { 1, 1, 1 },
2117 .vactive = { 800, 800, 800 },
2118 .vfront_porch = { 5, 11, 14 },
2119 .vback_porch = { 4, 11, 14 },
2120 .vsync_len = { 1, 1, 1 },
2121 .flags = DISPLAY_FLAGS_DE_HIGH,
2124 static const struct panel_desc innolux_g101ice_l01 = {
2125 .timings = &innolux_g101ice_l01_timing,
2136 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2137 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2140 static const struct display_timing innolux_g121i1_l01_timing = {
2141 .pixelclock = { 67450000, 71000000, 74550000 },
2142 .hactive = { 1280, 1280, 1280 },
2143 .hfront_porch = { 40, 80, 160 },
2144 .hback_porch = { 39, 79, 159 },
2145 .hsync_len = { 1, 1, 1 },
2146 .vactive = { 800, 800, 800 },
2147 .vfront_porch = { 5, 11, 100 },
2148 .vback_porch = { 4, 11, 99 },
2149 .vsync_len = { 1, 1, 1 },
2152 static const struct panel_desc innolux_g121i1_l01 = {
2153 .timings = &innolux_g121i1_l01_timing,
2164 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2165 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2168 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2171 .hsync_start = 1024 + 0,
2172 .hsync_end = 1024 + 1,
2173 .htotal = 1024 + 0 + 1 + 320,
2175 .vsync_start = 768 + 38,
2176 .vsync_end = 768 + 38 + 1,
2177 .vtotal = 768 + 38 + 1 + 0,
2178 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2181 static const struct panel_desc innolux_g121x1_l03 = {
2182 .modes = &innolux_g121x1_l03_mode,
2197 * Datasheet specifies that at 60 Hz refresh rate:
2198 * - total horizontal time: { 1506, 1592, 1716 }
2199 * - total vertical time: { 788, 800, 868 }
2201 * ...but doesn't go into exactly how that should be split into a front
2202 * porch, back porch, or sync length. For now we'll leave a single setting
2203 * here which allows a bit of tweaking of the pixel clock at the expense of
2206 static const struct display_timing innolux_n116bge_timing = {
2207 .pixelclock = { 72600000, 76420000, 80240000 },
2208 .hactive = { 1366, 1366, 1366 },
2209 .hfront_porch = { 136, 136, 136 },
2210 .hback_porch = { 60, 60, 60 },
2211 .hsync_len = { 30, 30, 30 },
2212 .vactive = { 768, 768, 768 },
2213 .vfront_porch = { 8, 8, 8 },
2214 .vback_porch = { 12, 12, 12 },
2215 .vsync_len = { 12, 12, 12 },
2216 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2219 static const struct panel_desc innolux_n116bge = {
2220 .timings = &innolux_n116bge_timing,
2229 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2232 .hsync_start = 1366 + 16,
2233 .hsync_end = 1366 + 16 + 34,
2234 .htotal = 1366 + 16 + 34 + 50,
2236 .vsync_start = 768 + 2,
2237 .vsync_end = 768 + 2 + 6,
2238 .vtotal = 768 + 2 + 6 + 12,
2241 static const struct panel_desc innolux_n156bge_l21 = {
2242 .modes = &innolux_n156bge_l21_mode,
2249 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2250 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2251 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2254 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2257 .hsync_start = 2160 + 48,
2258 .hsync_end = 2160 + 48 + 32,
2259 .htotal = 2160 + 48 + 32 + 80,
2261 .vsync_start = 1440 + 3,
2262 .vsync_end = 1440 + 3 + 10,
2263 .vtotal = 1440 + 3 + 10 + 27,
2264 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2267 static const struct panel_desc innolux_p120zdg_bf1 = {
2268 .modes = &innolux_p120zdg_bf1_mode,
2276 .hpd_absent_delay = 200,
2281 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2284 .hsync_start = 1024 + 128,
2285 .hsync_end = 1024 + 128 + 64,
2286 .htotal = 1024 + 128 + 64 + 128,
2288 .vsync_start = 600 + 16,
2289 .vsync_end = 600 + 16 + 4,
2290 .vtotal = 600 + 16 + 4 + 16,
2293 static const struct panel_desc innolux_zj070na_01p = {
2294 .modes = &innolux_zj070na_01p_mode,
2303 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2306 .hsync_start = 1920 + 24,
2307 .hsync_end = 1920 + 24 + 48,
2308 .htotal = 1920 + 24 + 48 + 88,
2310 .vsync_start = 1080 + 3,
2311 .vsync_end = 1080 + 3 + 12,
2312 .vtotal = 1080 + 3 + 12 + 17,
2313 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2316 static const struct panel_desc ivo_m133nwf4_r0 = {
2317 .modes = &ivo_m133nwf4_r0_mode,
2325 .hpd_absent_delay = 200,
2328 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2329 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2330 .connector_type = DRM_MODE_CONNECTOR_eDP,
2333 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2334 .pixelclock = { 5580000, 5850000, 6200000 },
2335 .hactive = { 320, 320, 320 },
2336 .hfront_porch = { 30, 30, 30 },
2337 .hback_porch = { 30, 30, 30 },
2338 .hsync_len = { 1, 5, 17 },
2339 .vactive = { 240, 240, 240 },
2340 .vfront_porch = { 6, 6, 6 },
2341 .vback_porch = { 5, 5, 5 },
2342 .vsync_len = { 1, 2, 11 },
2343 .flags = DISPLAY_FLAGS_DE_HIGH,
2346 static const struct panel_desc koe_tx14d24vm1bpa = {
2347 .timings = &koe_tx14d24vm1bpa_timing,
2356 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2357 .pixelclock = { 151820000, 156720000, 159780000 },
2358 .hactive = { 1920, 1920, 1920 },
2359 .hfront_porch = { 105, 130, 142 },
2360 .hback_porch = { 45, 70, 82 },
2361 .hsync_len = { 30, 30, 30 },
2362 .vactive = { 1200, 1200, 1200},
2363 .vfront_porch = { 3, 5, 10 },
2364 .vback_porch = { 2, 5, 10 },
2365 .vsync_len = { 5, 5, 5 },
2368 static const struct panel_desc koe_tx26d202vm0bwa = {
2369 .timings = &koe_tx26d202vm0bwa_timing,
2382 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2383 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2384 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2387 static const struct display_timing koe_tx31d200vm0baa_timing = {
2388 .pixelclock = { 39600000, 43200000, 48000000 },
2389 .hactive = { 1280, 1280, 1280 },
2390 .hfront_porch = { 16, 36, 56 },
2391 .hback_porch = { 16, 36, 56 },
2392 .hsync_len = { 8, 8, 8 },
2393 .vactive = { 480, 480, 480 },
2394 .vfront_porch = { 6, 21, 33 },
2395 .vback_porch = { 6, 21, 33 },
2396 .vsync_len = { 8, 8, 8 },
2397 .flags = DISPLAY_FLAGS_DE_HIGH,
2400 static const struct panel_desc koe_tx31d200vm0baa = {
2401 .timings = &koe_tx31d200vm0baa_timing,
2408 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2409 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2412 static const struct display_timing kyo_tcg121xglp_timing = {
2413 .pixelclock = { 52000000, 65000000, 71000000 },
2414 .hactive = { 1024, 1024, 1024 },
2415 .hfront_porch = { 2, 2, 2 },
2416 .hback_porch = { 2, 2, 2 },
2417 .hsync_len = { 86, 124, 244 },
2418 .vactive = { 768, 768, 768 },
2419 .vfront_porch = { 2, 2, 2 },
2420 .vback_porch = { 2, 2, 2 },
2421 .vsync_len = { 6, 34, 73 },
2422 .flags = DISPLAY_FLAGS_DE_HIGH,
2425 static const struct panel_desc kyo_tcg121xglp = {
2426 .timings = &kyo_tcg121xglp_timing,
2433 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2434 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2437 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2440 .hsync_start = 320 + 20,
2441 .hsync_end = 320 + 20 + 30,
2442 .htotal = 320 + 20 + 30 + 38,
2444 .vsync_start = 240 + 4,
2445 .vsync_end = 240 + 4 + 3,
2446 .vtotal = 240 + 4 + 3 + 15,
2449 static const struct panel_desc lemaker_bl035_rgb_002 = {
2450 .modes = &lemaker_bl035_rgb_002_mode,
2456 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2457 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2460 static const struct drm_display_mode lg_lb070wv8_mode = {
2463 .hsync_start = 800 + 88,
2464 .hsync_end = 800 + 88 + 80,
2465 .htotal = 800 + 88 + 80 + 88,
2467 .vsync_start = 480 + 10,
2468 .vsync_end = 480 + 10 + 25,
2469 .vtotal = 480 + 10 + 25 + 10,
2472 static const struct panel_desc lg_lb070wv8 = {
2473 .modes = &lg_lb070wv8_mode,
2480 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2481 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2484 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2487 .hsync_start = 1536 + 12,
2488 .hsync_end = 1536 + 12 + 16,
2489 .htotal = 1536 + 12 + 16 + 48,
2491 .vsync_start = 2048 + 8,
2492 .vsync_end = 2048 + 8 + 4,
2493 .vtotal = 2048 + 8 + 4 + 8,
2494 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2497 static const struct panel_desc lg_lp079qx1_sp0v = {
2498 .modes = &lg_lp079qx1_sp0v_mode,
2506 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2509 .hsync_start = 2048 + 150,
2510 .hsync_end = 2048 + 150 + 5,
2511 .htotal = 2048 + 150 + 5 + 5,
2513 .vsync_start = 1536 + 3,
2514 .vsync_end = 1536 + 3 + 1,
2515 .vtotal = 1536 + 3 + 1 + 9,
2518 static const struct panel_desc lg_lp097qx1_spa1 = {
2519 .modes = &lg_lp097qx1_spa1_mode,
2527 static const struct drm_display_mode lg_lp120up1_mode = {
2530 .hsync_start = 1920 + 40,
2531 .hsync_end = 1920 + 40 + 40,
2532 .htotal = 1920 + 40 + 40+ 80,
2534 .vsync_start = 1280 + 4,
2535 .vsync_end = 1280 + 4 + 4,
2536 .vtotal = 1280 + 4 + 4 + 12,
2539 static const struct panel_desc lg_lp120up1 = {
2540 .modes = &lg_lp120up1_mode,
2547 .connector_type = DRM_MODE_CONNECTOR_eDP,
2550 static const struct drm_display_mode lg_lp129qe_mode = {
2553 .hsync_start = 2560 + 48,
2554 .hsync_end = 2560 + 48 + 32,
2555 .htotal = 2560 + 48 + 32 + 80,
2557 .vsync_start = 1700 + 3,
2558 .vsync_end = 1700 + 3 + 10,
2559 .vtotal = 1700 + 3 + 10 + 36,
2562 static const struct panel_desc lg_lp129qe = {
2563 .modes = &lg_lp129qe_mode,
2572 static const struct display_timing logictechno_lt161010_2nh_timing = {
2573 .pixelclock = { 26400000, 33300000, 46800000 },
2574 .hactive = { 800, 800, 800 },
2575 .hfront_porch = { 16, 210, 354 },
2576 .hback_porch = { 46, 46, 46 },
2577 .hsync_len = { 1, 20, 40 },
2578 .vactive = { 480, 480, 480 },
2579 .vfront_porch = { 7, 22, 147 },
2580 .vback_porch = { 23, 23, 23 },
2581 .vsync_len = { 1, 10, 20 },
2582 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2583 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2584 DISPLAY_FLAGS_SYNC_POSEDGE,
2587 static const struct panel_desc logictechno_lt161010_2nh = {
2588 .timings = &logictechno_lt161010_2nh_timing,
2594 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2595 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2596 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2597 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2598 .connector_type = DRM_MODE_CONNECTOR_DPI,
2601 static const struct display_timing logictechno_lt170410_2whc_timing = {
2602 .pixelclock = { 68900000, 71100000, 73400000 },
2603 .hactive = { 1280, 1280, 1280 },
2604 .hfront_porch = { 23, 60, 71 },
2605 .hback_porch = { 23, 60, 71 },
2606 .hsync_len = { 15, 40, 47 },
2607 .vactive = { 800, 800, 800 },
2608 .vfront_porch = { 5, 7, 10 },
2609 .vback_porch = { 5, 7, 10 },
2610 .vsync_len = { 6, 9, 12 },
2611 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2612 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2613 DISPLAY_FLAGS_SYNC_POSEDGE,
2616 static const struct panel_desc logictechno_lt170410_2whc = {
2617 .timings = &logictechno_lt170410_2whc_timing,
2623 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2624 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2625 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2628 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2631 .hsync_start = 800 + 0,
2632 .hsync_end = 800 + 1,
2633 .htotal = 800 + 0 + 1 + 160,
2635 .vsync_start = 480 + 0,
2636 .vsync_end = 480 + 48 + 1,
2637 .vtotal = 480 + 48 + 1 + 0,
2638 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2641 static const struct drm_display_mode logicpd_type_28_mode = {
2644 .hsync_start = 480 + 3,
2645 .hsync_end = 480 + 3 + 42,
2646 .htotal = 480 + 3 + 42 + 2,
2649 .vsync_start = 272 + 2,
2650 .vsync_end = 272 + 2 + 11,
2651 .vtotal = 272 + 2 + 11 + 3,
2652 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2655 static const struct panel_desc logicpd_type_28 = {
2656 .modes = &logicpd_type_28_mode,
2669 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2670 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2671 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2672 .connector_type = DRM_MODE_CONNECTOR_DPI,
2675 static const struct panel_desc mitsubishi_aa070mc01 = {
2676 .modes = &mitsubishi_aa070mc01_mode,
2689 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2690 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2691 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2694 static const struct display_timing nec_nl12880bc20_05_timing = {
2695 .pixelclock = { 67000000, 71000000, 75000000 },
2696 .hactive = { 1280, 1280, 1280 },
2697 .hfront_porch = { 2, 30, 30 },
2698 .hback_porch = { 6, 100, 100 },
2699 .hsync_len = { 2, 30, 30 },
2700 .vactive = { 800, 800, 800 },
2701 .vfront_porch = { 5, 5, 5 },
2702 .vback_porch = { 11, 11, 11 },
2703 .vsync_len = { 7, 7, 7 },
2706 static const struct panel_desc nec_nl12880bc20_05 = {
2707 .timings = &nec_nl12880bc20_05_timing,
2718 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2719 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2722 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2725 .hsync_start = 480 + 2,
2726 .hsync_end = 480 + 2 + 41,
2727 .htotal = 480 + 2 + 41 + 2,
2729 .vsync_start = 272 + 2,
2730 .vsync_end = 272 + 2 + 4,
2731 .vtotal = 272 + 2 + 4 + 2,
2732 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2735 static const struct panel_desc nec_nl4827hc19_05b = {
2736 .modes = &nec_nl4827hc19_05b_mode,
2743 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2744 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2747 static const struct drm_display_mode netron_dy_e231732_mode = {
2750 .hsync_start = 1024 + 160,
2751 .hsync_end = 1024 + 160 + 70,
2752 .htotal = 1024 + 160 + 70 + 90,
2754 .vsync_start = 600 + 127,
2755 .vsync_end = 600 + 127 + 20,
2756 .vtotal = 600 + 127 + 20 + 3,
2759 static const struct panel_desc netron_dy_e231732 = {
2760 .modes = &netron_dy_e231732_mode,
2766 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2769 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2773 .hsync_start = 1920 + 48,
2774 .hsync_end = 1920 + 48 + 32,
2775 .htotal = 1920 + 48 + 32 + 80,
2777 .vsync_start = 1080 + 3,
2778 .vsync_end = 1080 + 3 + 5,
2779 .vtotal = 1080 + 3 + 5 + 23,
2780 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2784 .hsync_start = 1920 + 48,
2785 .hsync_end = 1920 + 48 + 32,
2786 .htotal = 1920 + 48 + 32 + 80,
2788 .vsync_start = 1080 + 3,
2789 .vsync_end = 1080 + 3 + 5,
2790 .vtotal = 1080 + 3 + 5 + 23,
2791 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2795 static const struct panel_desc neweast_wjfh116008a = {
2796 .modes = neweast_wjfh116008a_modes,
2808 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2809 .connector_type = DRM_MODE_CONNECTOR_eDP,
2812 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2815 .hsync_start = 480 + 2,
2816 .hsync_end = 480 + 2 + 41,
2817 .htotal = 480 + 2 + 41 + 2,
2819 .vsync_start = 272 + 2,
2820 .vsync_end = 272 + 2 + 10,
2821 .vtotal = 272 + 2 + 10 + 2,
2822 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2825 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2826 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2833 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2834 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2835 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2836 .connector_type = DRM_MODE_CONNECTOR_DPI,
2839 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2840 .pixelclock = { 130000000, 148350000, 163000000 },
2841 .hactive = { 1920, 1920, 1920 },
2842 .hfront_porch = { 80, 100, 100 },
2843 .hback_porch = { 100, 120, 120 },
2844 .hsync_len = { 50, 60, 60 },
2845 .vactive = { 1080, 1080, 1080 },
2846 .vfront_porch = { 12, 30, 30 },
2847 .vback_porch = { 4, 10, 10 },
2848 .vsync_len = { 4, 5, 5 },
2851 static const struct panel_desc nlt_nl192108ac18_02d = {
2852 .timings = &nlt_nl192108ac18_02d_timing,
2862 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2863 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2866 static const struct drm_display_mode nvd_9128_mode = {
2869 .hsync_start = 800 + 130,
2870 .hsync_end = 800 + 130 + 98,
2871 .htotal = 800 + 0 + 130 + 98,
2873 .vsync_start = 480 + 10,
2874 .vsync_end = 480 + 10 + 50,
2875 .vtotal = 480 + 0 + 10 + 50,
2878 static const struct panel_desc nvd_9128 = {
2879 .modes = &nvd_9128_mode,
2886 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2887 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2890 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2891 .pixelclock = { 30000000, 30000000, 40000000 },
2892 .hactive = { 800, 800, 800 },
2893 .hfront_porch = { 40, 40, 40 },
2894 .hback_porch = { 40, 40, 40 },
2895 .hsync_len = { 1, 48, 48 },
2896 .vactive = { 480, 480, 480 },
2897 .vfront_porch = { 13, 13, 13 },
2898 .vback_porch = { 29, 29, 29 },
2899 .vsync_len = { 3, 3, 3 },
2900 .flags = DISPLAY_FLAGS_DE_HIGH,
2903 static const struct panel_desc okaya_rs800480t_7x0gp = {
2904 .timings = &okaya_rs800480t_7x0gp_timing,
2917 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2920 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2923 .hsync_start = 480 + 5,
2924 .hsync_end = 480 + 5 + 30,
2925 .htotal = 480 + 5 + 30 + 10,
2927 .vsync_start = 272 + 8,
2928 .vsync_end = 272 + 8 + 5,
2929 .vtotal = 272 + 8 + 5 + 3,
2932 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2933 .modes = &olimex_lcd_olinuxino_43ts_mode,
2939 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2943 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2944 * pixel clocks, but this is the timing that was being used in the Adafruit
2945 * installation instructions.
2947 static const struct drm_display_mode ontat_yx700wv03_mode = {
2957 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2962 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2964 static const struct panel_desc ontat_yx700wv03 = {
2965 .modes = &ontat_yx700wv03_mode,
2972 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2975 static const struct drm_display_mode ortustech_com37h3m_mode = {
2978 .hsync_start = 480 + 40,
2979 .hsync_end = 480 + 40 + 10,
2980 .htotal = 480 + 40 + 10 + 40,
2982 .vsync_start = 640 + 4,
2983 .vsync_end = 640 + 4 + 2,
2984 .vtotal = 640 + 4 + 2 + 4,
2985 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2988 static const struct panel_desc ortustech_com37h3m = {
2989 .modes = &ortustech_com37h3m_mode,
2993 .width = 56, /* 56.16mm */
2994 .height = 75, /* 74.88mm */
2996 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2997 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2998 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3001 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3004 .hsync_start = 480 + 10,
3005 .hsync_end = 480 + 10 + 10,
3006 .htotal = 480 + 10 + 10 + 15,
3008 .vsync_start = 800 + 3,
3009 .vsync_end = 800 + 3 + 3,
3010 .vtotal = 800 + 3 + 3 + 3,
3013 static const struct panel_desc ortustech_com43h4m85ulc = {
3014 .modes = &ortustech_com43h4m85ulc_mode,
3021 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3022 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3023 .connector_type = DRM_MODE_CONNECTOR_DPI,
3026 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3029 .hsync_start = 800 + 210,
3030 .hsync_end = 800 + 210 + 30,
3031 .htotal = 800 + 210 + 30 + 16,
3033 .vsync_start = 480 + 22,
3034 .vsync_end = 480 + 22 + 13,
3035 .vtotal = 480 + 22 + 13 + 10,
3036 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3039 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3040 .modes = &osddisplays_osd070t1718_19ts_mode,
3047 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3048 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3049 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3050 .connector_type = DRM_MODE_CONNECTOR_DPI,
3053 static const struct drm_display_mode pda_91_00156_a0_mode = {
3056 .hsync_start = 800 + 1,
3057 .hsync_end = 800 + 1 + 64,
3058 .htotal = 800 + 1 + 64 + 64,
3060 .vsync_start = 480 + 1,
3061 .vsync_end = 480 + 1 + 23,
3062 .vtotal = 480 + 1 + 23 + 22,
3065 static const struct panel_desc pda_91_00156_a0 = {
3066 .modes = &pda_91_00156_a0_mode,
3072 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3075 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3078 .hsync_start = 800 + 54,
3079 .hsync_end = 800 + 54 + 2,
3080 .htotal = 800 + 54 + 2 + 44,
3082 .vsync_start = 480 + 49,
3083 .vsync_end = 480 + 49 + 2,
3084 .vtotal = 480 + 49 + 2 + 22,
3087 static const struct panel_desc powertip_ph800480t013_idf02 = {
3088 .modes = &powertip_ph800480t013_idf02_mode,
3094 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3095 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3096 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3097 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3098 .connector_type = DRM_MODE_CONNECTOR_DPI,
3101 static const struct drm_display_mode qd43003c0_40_mode = {
3104 .hsync_start = 480 + 8,
3105 .hsync_end = 480 + 8 + 4,
3106 .htotal = 480 + 8 + 4 + 39,
3108 .vsync_start = 272 + 4,
3109 .vsync_end = 272 + 4 + 10,
3110 .vtotal = 272 + 4 + 10 + 2,
3113 static const struct panel_desc qd43003c0_40 = {
3114 .modes = &qd43003c0_40_mode,
3121 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3124 static const struct display_timing rocktech_rk070er9427_timing = {
3125 .pixelclock = { 26400000, 33300000, 46800000 },
3126 .hactive = { 800, 800, 800 },
3127 .hfront_porch = { 16, 210, 354 },
3128 .hback_porch = { 46, 46, 46 },
3129 .hsync_len = { 1, 1, 1 },
3130 .vactive = { 480, 480, 480 },
3131 .vfront_porch = { 7, 22, 147 },
3132 .vback_porch = { 23, 23, 23 },
3133 .vsync_len = { 1, 1, 1 },
3134 .flags = DISPLAY_FLAGS_DE_HIGH,
3137 static const struct panel_desc rocktech_rk070er9427 = {
3138 .timings = &rocktech_rk070er9427_timing,
3151 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3154 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3157 .hsync_start = 1280 + 48,
3158 .hsync_end = 1280 + 48 + 32,
3159 .htotal = 1280 + 48 + 32 + 80,
3161 .vsync_start = 800 + 2,
3162 .vsync_end = 800 + 2 + 5,
3163 .vtotal = 800 + 2 + 5 + 16,
3166 static const struct panel_desc rocktech_rk101ii01d_ct = {
3167 .modes = &rocktech_rk101ii01d_ct_mode,
3177 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3178 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3179 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3182 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3185 .hsync_start = 2560 + 48,
3186 .hsync_end = 2560 + 48 + 32,
3187 .htotal = 2560 + 48 + 32 + 80,
3189 .vsync_start = 1600 + 2,
3190 .vsync_end = 1600 + 2 + 5,
3191 .vtotal = 1600 + 2 + 5 + 57,
3194 static const struct panel_desc samsung_lsn122dl01_c01 = {
3195 .modes = &samsung_lsn122dl01_c01_mode,
3203 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3206 .hsync_start = 1024 + 24,
3207 .hsync_end = 1024 + 24 + 136,
3208 .htotal = 1024 + 24 + 136 + 160,
3210 .vsync_start = 600 + 3,
3211 .vsync_end = 600 + 3 + 6,
3212 .vtotal = 600 + 3 + 6 + 61,
3215 static const struct panel_desc samsung_ltn101nt05 = {
3216 .modes = &samsung_ltn101nt05_mode,
3223 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3224 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3225 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3228 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3231 .hsync_start = 1366 + 64,
3232 .hsync_end = 1366 + 64 + 48,
3233 .htotal = 1366 + 64 + 48 + 128,
3235 .vsync_start = 768 + 2,
3236 .vsync_end = 768 + 2 + 5,
3237 .vtotal = 768 + 2 + 5 + 17,
3240 static const struct panel_desc samsung_ltn140at29_301 = {
3241 .modes = &samsung_ltn140at29_301_mode,
3250 static const struct display_timing satoz_sat050at40h12r2_timing = {
3251 .pixelclock = {33300000, 33300000, 50000000},
3252 .hactive = {800, 800, 800},
3253 .hfront_porch = {16, 210, 354},
3254 .hback_porch = {46, 46, 46},
3255 .hsync_len = {1, 1, 40},
3256 .vactive = {480, 480, 480},
3257 .vfront_porch = {7, 22, 147},
3258 .vback_porch = {23, 23, 23},
3259 .vsync_len = {1, 1, 20},
3262 static const struct panel_desc satoz_sat050at40h12r2 = {
3263 .timings = &satoz_sat050at40h12r2_timing,
3270 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3271 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3274 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3277 .hsync_start = 1920 + 48,
3278 .hsync_end = 1920 + 48 + 32,
3279 .htotal = 1920 + 48 + 32 + 80,
3281 .vsync_start = 1280 + 3,
3282 .vsync_end = 1280 + 3 + 10,
3283 .vtotal = 1280 + 3 + 10 + 57,
3284 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3287 static const struct panel_desc sharp_ld_d5116z01b = {
3288 .modes = &sharp_ld_d5116z01b_mode,
3295 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3296 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3299 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3302 .hsync_start = 800 + 64,
3303 .hsync_end = 800 + 64 + 128,
3304 .htotal = 800 + 64 + 128 + 64,
3306 .vsync_start = 480 + 8,
3307 .vsync_end = 480 + 8 + 2,
3308 .vtotal = 480 + 8 + 2 + 35,
3309 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3312 static const struct panel_desc sharp_lq070y3dg3b = {
3313 .modes = &sharp_lq070y3dg3b_mode,
3317 .width = 152, /* 152.4mm */
3318 .height = 91, /* 91.4mm */
3320 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3321 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3322 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3325 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3328 .hsync_start = 240 + 16,
3329 .hsync_end = 240 + 16 + 7,
3330 .htotal = 240 + 16 + 7 + 5,
3332 .vsync_start = 320 + 9,
3333 .vsync_end = 320 + 9 + 1,
3334 .vtotal = 320 + 9 + 1 + 7,
3337 static const struct panel_desc sharp_lq035q7db03 = {
3338 .modes = &sharp_lq035q7db03_mode,
3345 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3348 static const struct display_timing sharp_lq101k1ly04_timing = {
3349 .pixelclock = { 60000000, 65000000, 80000000 },
3350 .hactive = { 1280, 1280, 1280 },
3351 .hfront_porch = { 20, 20, 20 },
3352 .hback_porch = { 20, 20, 20 },
3353 .hsync_len = { 10, 10, 10 },
3354 .vactive = { 800, 800, 800 },
3355 .vfront_porch = { 4, 4, 4 },
3356 .vback_porch = { 4, 4, 4 },
3357 .vsync_len = { 4, 4, 4 },
3358 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3361 static const struct panel_desc sharp_lq101k1ly04 = {
3362 .timings = &sharp_lq101k1ly04_timing,
3369 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3370 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3373 static const struct display_timing sharp_lq123p1jx31_timing = {
3374 .pixelclock = { 252750000, 252750000, 266604720 },
3375 .hactive = { 2400, 2400, 2400 },
3376 .hfront_porch = { 48, 48, 48 },
3377 .hback_porch = { 80, 80, 84 },
3378 .hsync_len = { 32, 32, 32 },
3379 .vactive = { 1600, 1600, 1600 },
3380 .vfront_porch = { 3, 3, 3 },
3381 .vback_porch = { 33, 33, 120 },
3382 .vsync_len = { 10, 10, 10 },
3383 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3386 static const struct panel_desc sharp_lq123p1jx31 = {
3387 .timings = &sharp_lq123p1jx31_timing,
3401 static const struct display_timing sharp_ls020b1dd01d_timing = {
3402 .pixelclock = { 2000000, 4200000, 5000000 },
3403 .hactive = { 240, 240, 240 },
3404 .hfront_porch = { 66, 66, 66 },
3405 .hback_porch = { 1, 1, 1 },
3406 .hsync_len = { 1, 1, 1 },
3407 .vactive = { 160, 160, 160 },
3408 .vfront_porch = { 52, 52, 52 },
3409 .vback_porch = { 6, 6, 6 },
3410 .vsync_len = { 10, 10, 10 },
3411 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
3414 static const struct panel_desc sharp_ls020b1dd01d = {
3415 .timings = &sharp_ls020b1dd01d_timing,
3422 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3423 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3424 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3425 | DRM_BUS_FLAG_SHARP_SIGNALS,
3428 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3431 .hsync_start = 800 + 1,
3432 .hsync_end = 800 + 1 + 64,
3433 .htotal = 800 + 1 + 64 + 64,
3435 .vsync_start = 480 + 1,
3436 .vsync_end = 480 + 1 + 23,
3437 .vtotal = 480 + 1 + 23 + 22,
3440 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3441 .modes = &shelly_sca07010_bfn_lnn_mode,
3447 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3450 static const struct drm_display_mode starry_kr070pe2t_mode = {
3453 .hsync_start = 800 + 209,
3454 .hsync_end = 800 + 209 + 1,
3455 .htotal = 800 + 209 + 1 + 45,
3457 .vsync_start = 480 + 22,
3458 .vsync_end = 480 + 22 + 1,
3459 .vtotal = 480 + 22 + 1 + 22,
3462 static const struct panel_desc starry_kr070pe2t = {
3463 .modes = &starry_kr070pe2t_mode,
3470 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3471 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3472 .connector_type = DRM_MODE_CONNECTOR_DPI,
3475 static const struct drm_display_mode starry_kr122ea0sra_mode = {
3478 .hsync_start = 1920 + 16,
3479 .hsync_end = 1920 + 16 + 16,
3480 .htotal = 1920 + 16 + 16 + 32,
3482 .vsync_start = 1200 + 15,
3483 .vsync_end = 1200 + 15 + 2,
3484 .vtotal = 1200 + 15 + 2 + 18,
3485 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3488 static const struct panel_desc starry_kr122ea0sra = {
3489 .modes = &starry_kr122ea0sra_mode,
3496 .prepare = 10 + 200,
3498 .unprepare = 10 + 500,
3502 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3505 .hsync_start = 800 + 39,
3506 .hsync_end = 800 + 39 + 47,
3507 .htotal = 800 + 39 + 47 + 39,
3509 .vsync_start = 480 + 13,
3510 .vsync_end = 480 + 13 + 2,
3511 .vtotal = 480 + 13 + 2 + 29,
3514 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3515 .modes = &tfc_s9700rtwv43tr_01b_mode,
3522 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3523 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3526 static const struct display_timing tianma_tm070jdhg30_timing = {
3527 .pixelclock = { 62600000, 68200000, 78100000 },
3528 .hactive = { 1280, 1280, 1280 },
3529 .hfront_porch = { 15, 64, 159 },
3530 .hback_porch = { 5, 5, 5 },
3531 .hsync_len = { 1, 1, 256 },
3532 .vactive = { 800, 800, 800 },
3533 .vfront_porch = { 3, 40, 99 },
3534 .vback_porch = { 2, 2, 2 },
3535 .vsync_len = { 1, 1, 128 },
3536 .flags = DISPLAY_FLAGS_DE_HIGH,
3539 static const struct panel_desc tianma_tm070jdhg30 = {
3540 .timings = &tianma_tm070jdhg30_timing,
3547 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3548 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3551 static const struct panel_desc tianma_tm070jvhg33 = {
3552 .timings = &tianma_tm070jdhg30_timing,
3559 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3560 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3563 static const struct display_timing tianma_tm070rvhg71_timing = {
3564 .pixelclock = { 27700000, 29200000, 39600000 },
3565 .hactive = { 800, 800, 800 },
3566 .hfront_porch = { 12, 40, 212 },
3567 .hback_porch = { 88, 88, 88 },
3568 .hsync_len = { 1, 1, 40 },
3569 .vactive = { 480, 480, 480 },
3570 .vfront_porch = { 1, 13, 88 },
3571 .vback_porch = { 32, 32, 32 },
3572 .vsync_len = { 1, 1, 3 },
3573 .flags = DISPLAY_FLAGS_DE_HIGH,
3576 static const struct panel_desc tianma_tm070rvhg71 = {
3577 .timings = &tianma_tm070rvhg71_timing,
3584 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3585 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3588 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3592 .hsync_start = 320 + 50,
3593 .hsync_end = 320 + 50 + 6,
3594 .htotal = 320 + 50 + 6 + 38,
3596 .vsync_start = 240 + 3,
3597 .vsync_end = 240 + 3 + 1,
3598 .vtotal = 240 + 3 + 1 + 17,
3599 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3603 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3604 .modes = ti_nspire_cx_lcd_mode,
3611 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3612 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3615 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3619 .hsync_start = 320 + 6,
3620 .hsync_end = 320 + 6 + 6,
3621 .htotal = 320 + 6 + 6 + 6,
3623 .vsync_start = 240 + 0,
3624 .vsync_end = 240 + 0 + 1,
3625 .vtotal = 240 + 0 + 1 + 0,
3626 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3630 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3631 .modes = ti_nspire_classic_lcd_mode,
3633 /* The grayscale panel has 8 bit for the color .. Y (black) */
3639 /* This is the grayscale bus format */
3640 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3641 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3644 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3647 .hsync_start = 1280 + 192,
3648 .hsync_end = 1280 + 192 + 128,
3649 .htotal = 1280 + 192 + 128 + 64,
3651 .vsync_start = 768 + 20,
3652 .vsync_end = 768 + 20 + 7,
3653 .vtotal = 768 + 20 + 7 + 3,
3656 static const struct panel_desc toshiba_lt089ac29000 = {
3657 .modes = &toshiba_lt089ac29000_mode,
3663 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3664 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3665 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3668 static const struct drm_display_mode tpk_f07a_0102_mode = {
3671 .hsync_start = 800 + 40,
3672 .hsync_end = 800 + 40 + 128,
3673 .htotal = 800 + 40 + 128 + 88,
3675 .vsync_start = 480 + 10,
3676 .vsync_end = 480 + 10 + 2,
3677 .vtotal = 480 + 10 + 2 + 33,
3680 static const struct panel_desc tpk_f07a_0102 = {
3681 .modes = &tpk_f07a_0102_mode,
3687 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3690 static const struct drm_display_mode tpk_f10a_0102_mode = {
3693 .hsync_start = 1024 + 176,
3694 .hsync_end = 1024 + 176 + 5,
3695 .htotal = 1024 + 176 + 5 + 88,
3697 .vsync_start = 600 + 20,
3698 .vsync_end = 600 + 20 + 5,
3699 .vtotal = 600 + 20 + 5 + 25,
3702 static const struct panel_desc tpk_f10a_0102 = {
3703 .modes = &tpk_f10a_0102_mode,
3711 static const struct display_timing urt_umsh_8596md_timing = {
3712 .pixelclock = { 33260000, 33260000, 33260000 },
3713 .hactive = { 800, 800, 800 },
3714 .hfront_porch = { 41, 41, 41 },
3715 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3716 .hsync_len = { 71, 128, 128 },
3717 .vactive = { 480, 480, 480 },
3718 .vfront_porch = { 10, 10, 10 },
3719 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3720 .vsync_len = { 2, 2, 2 },
3721 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3722 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3725 static const struct panel_desc urt_umsh_8596md_lvds = {
3726 .timings = &urt_umsh_8596md_timing,
3733 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3734 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3737 static const struct panel_desc urt_umsh_8596md_parallel = {
3738 .timings = &urt_umsh_8596md_timing,
3745 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3748 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3751 .hsync_start = 800 + 210,
3752 .hsync_end = 800 + 210 + 20,
3753 .htotal = 800 + 210 + 20 + 46,
3755 .vsync_start = 480 + 22,
3756 .vsync_end = 480 + 22 + 10,
3757 .vtotal = 480 + 22 + 10 + 23,
3758 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3761 static const struct panel_desc vl050_8048nt_c01 = {
3762 .modes = &vl050_8048nt_c01_mode,
3769 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3770 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3773 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3776 .hsync_start = 320 + 20,
3777 .hsync_end = 320 + 20 + 30,
3778 .htotal = 320 + 20 + 30 + 38,
3780 .vsync_start = 240 + 4,
3781 .vsync_end = 240 + 4 + 3,
3782 .vtotal = 240 + 4 + 3 + 15,
3783 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3786 static const struct panel_desc winstar_wf35ltiacd = {
3787 .modes = &winstar_wf35ltiacd_mode,
3794 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3797 static const struct drm_display_mode arm_rtsm_mode[] = {
3801 .hsync_start = 1024 + 24,
3802 .hsync_end = 1024 + 24 + 136,
3803 .htotal = 1024 + 24 + 136 + 160,
3805 .vsync_start = 768 + 3,
3806 .vsync_end = 768 + 3 + 6,
3807 .vtotal = 768 + 3 + 6 + 29,
3808 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3812 static const struct panel_desc arm_rtsm = {
3813 .modes = arm_rtsm_mode,
3820 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3823 static const struct of_device_id platform_of_match[] = {
3825 .compatible = "ampire,am-480272h3tmqw-t01h",
3826 .data = &ire_am_480272h3tmqw_t01h,
3828 .compatible = "ampire,am800480r3tmqwa1h",
3829 .data = &ire_am800480r3tmqwa1h,
3831 .compatible = "arm,rtsm-display",
3834 .compatible = "armadeus,st0700-adapt",
3835 .data = &armadeus_st0700_adapt,
3837 .compatible = "auo,b101aw03",
3838 .data = &auo_b101aw03,
3840 .compatible = "auo,b101ean01",
3841 .data = &auo_b101ean01,
3843 .compatible = "auo,b101xtn01",
3844 .data = &auo_b101xtn01,
3846 .compatible = "auo,b116xa01",
3847 .data = &auo_b116xak01,
3849 .compatible = "auo,b116xw03",
3850 .data = &auo_b116xw03,
3852 .compatible = "auo,b133htn01",
3853 .data = &auo_b133htn01,
3855 .compatible = "auo,b133xtn01",
3856 .data = &auo_b133xtn01,
3858 .compatible = "auo,g070vvn01",
3859 .data = &auo_g070vvn01,
3861 .compatible = "auo,g101evn010",
3862 .data = &auo_g101evn010,
3864 .compatible = "auo,g104sn02",
3865 .data = &auo_g104sn02,
3867 .compatible = "auo,g121ean01",
3868 .data = &auo_g121ean01,
3870 .compatible = "auo,g133han01",
3871 .data = &auo_g133han01,
3873 .compatible = "auo,g156xtn01",
3874 .data = &auo_g156xtn01,
3876 .compatible = "auo,g185han01",
3877 .data = &auo_g185han01,
3879 .compatible = "auo,g190ean01",
3880 .data = &auo_g190ean01,
3882 .compatible = "auo,p320hvn03",
3883 .data = &auo_p320hvn03,
3885 .compatible = "auo,t215hvn01",
3886 .data = &auo_t215hvn01,
3888 .compatible = "avic,tm070ddh03",
3889 .data = &avic_tm070ddh03,
3891 .compatible = "bananapi,s070wv20-ct16",
3892 .data = &bananapi_s070wv20_ct16,
3894 .compatible = "boe,hv070wsa-100",
3895 .data = &boe_hv070wsa
3897 .compatible = "boe,nv101wxmn51",
3898 .data = &boe_nv101wxmn51,
3900 .compatible = "boe,nv133fhm-n61",
3901 .data = &boe_nv133fhm_n61,
3903 .compatible = "boe,nv133fhm-n62",
3904 .data = &boe_nv133fhm_n61,
3906 .compatible = "boe,nv140fhmn49",
3907 .data = &boe_nv140fhmn49,
3909 .compatible = "cdtech,s043wq26h-ct7",
3910 .data = &cdtech_s043wq26h_ct7,
3912 .compatible = "cdtech,s070pws19hp-fc21",
3913 .data = &cdtech_s070pws19hp_fc21,
3915 .compatible = "cdtech,s070swv29hg-dc44",
3916 .data = &cdtech_s070swv29hg_dc44,
3918 .compatible = "cdtech,s070wv95-ct16",
3919 .data = &cdtech_s070wv95_ct16,
3921 .compatible = "chefree,ch101olhlwh-002",
3922 .data = &chefree_ch101olhlwh_002,
3924 .compatible = "chunghwa,claa070wp03xg",
3925 .data = &chunghwa_claa070wp03xg,
3927 .compatible = "chunghwa,claa101wa01a",
3928 .data = &chunghwa_claa101wa01a
3930 .compatible = "chunghwa,claa101wb01",
3931 .data = &chunghwa_claa101wb01
3933 .compatible = "dataimage,scf0700c48ggu18",
3934 .data = &dataimage_scf0700c48ggu18,
3936 .compatible = "dlc,dlc0700yzg-1",
3937 .data = &dlc_dlc0700yzg_1,
3939 .compatible = "dlc,dlc1010gig",
3940 .data = &dlc_dlc1010gig,
3942 .compatible = "edt,et035012dm6",
3943 .data = &edt_et035012dm6,
3945 .compatible = "edt,etm043080dh6gp",
3946 .data = &edt_etm043080dh6gp,
3948 .compatible = "edt,etm0430g0dh6",
3949 .data = &edt_etm0430g0dh6,
3951 .compatible = "edt,et057090dhu",
3952 .data = &edt_et057090dhu,
3954 .compatible = "edt,et070080dh6",
3955 .data = &edt_etm0700g0dh6,
3957 .compatible = "edt,etm0700g0dh6",
3958 .data = &edt_etm0700g0dh6,
3960 .compatible = "edt,etm0700g0bdh6",
3961 .data = &edt_etm0700g0bdh6,
3963 .compatible = "edt,etm0700g0edh6",
3964 .data = &edt_etm0700g0bdh6,
3966 .compatible = "evervision,vgg804821",
3967 .data = &evervision_vgg804821,
3969 .compatible = "foxlink,fl500wvr00-a0t",
3970 .data = &foxlink_fl500wvr00_a0t,
3972 .compatible = "frida,frd350h54004",
3973 .data = &frida_frd350h54004,
3975 .compatible = "friendlyarm,hd702e",
3976 .data = &friendlyarm_hd702e,
3978 .compatible = "giantplus,gpg482739qs5",
3979 .data = &giantplus_gpg482739qs5
3981 .compatible = "giantplus,gpm940b0",
3982 .data = &giantplus_gpm940b0,
3984 .compatible = "hannstar,hsd070pww1",
3985 .data = &hannstar_hsd070pww1,
3987 .compatible = "hannstar,hsd100pxn1",
3988 .data = &hannstar_hsd100pxn1,
3990 .compatible = "hit,tx23d38vm0caa",
3991 .data = &hitachi_tx23d38vm0caa
3993 .compatible = "innolux,at043tn24",
3994 .data = &innolux_at043tn24,
3996 .compatible = "innolux,at070tn92",
3997 .data = &innolux_at070tn92,
3999 .compatible = "innolux,g070y2-l01",
4000 .data = &innolux_g070y2_l01,
4002 .compatible = "innolux,g101ice-l01",
4003 .data = &innolux_g101ice_l01
4005 .compatible = "innolux,g121i1-l01",
4006 .data = &innolux_g121i1_l01
4008 .compatible = "innolux,g121x1-l03",
4009 .data = &innolux_g121x1_l03,
4011 .compatible = "innolux,n116bge",
4012 .data = &innolux_n116bge,
4014 .compatible = "innolux,n156bge-l21",
4015 .data = &innolux_n156bge_l21,
4017 .compatible = "innolux,p120zdg-bf1",
4018 .data = &innolux_p120zdg_bf1,
4020 .compatible = "innolux,zj070na-01p",
4021 .data = &innolux_zj070na_01p,
4023 .compatible = "ivo,m133nwf4-r0",
4024 .data = &ivo_m133nwf4_r0,
4026 .compatible = "koe,tx14d24vm1bpa",
4027 .data = &koe_tx14d24vm1bpa,
4029 .compatible = "koe,tx26d202vm0bwa",
4030 .data = &koe_tx26d202vm0bwa,
4032 .compatible = "koe,tx31d200vm0baa",
4033 .data = &koe_tx31d200vm0baa,
4035 .compatible = "kyo,tcg121xglp",
4036 .data = &kyo_tcg121xglp,
4038 .compatible = "lemaker,bl035-rgb-002",
4039 .data = &lemaker_bl035_rgb_002,
4041 .compatible = "lg,lb070wv8",
4042 .data = &lg_lb070wv8,
4044 .compatible = "lg,lp079qx1-sp0v",
4045 .data = &lg_lp079qx1_sp0v,
4047 .compatible = "lg,lp097qx1-spa1",
4048 .data = &lg_lp097qx1_spa1,
4050 .compatible = "lg,lp120up1",
4051 .data = &lg_lp120up1,
4053 .compatible = "lg,lp129qe",
4054 .data = &lg_lp129qe,
4056 .compatible = "logicpd,type28",
4057 .data = &logicpd_type_28,
4059 .compatible = "logictechno,lt161010-2nhc",
4060 .data = &logictechno_lt161010_2nh,
4062 .compatible = "logictechno,lt161010-2nhr",
4063 .data = &logictechno_lt161010_2nh,
4065 .compatible = "logictechno,lt170410-2whc",
4066 .data = &logictechno_lt170410_2whc,
4068 .compatible = "mitsubishi,aa070mc01-ca1",
4069 .data = &mitsubishi_aa070mc01,
4071 .compatible = "nec,nl12880bc20-05",
4072 .data = &nec_nl12880bc20_05,
4074 .compatible = "nec,nl4827hc19-05b",
4075 .data = &nec_nl4827hc19_05b,
4077 .compatible = "netron-dy,e231732",
4078 .data = &netron_dy_e231732,
4080 .compatible = "neweast,wjfh116008a",
4081 .data = &neweast_wjfh116008a,
4083 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4084 .data = &newhaven_nhd_43_480272ef_atxl,
4086 .compatible = "nlt,nl192108ac18-02d",
4087 .data = &nlt_nl192108ac18_02d,
4089 .compatible = "nvd,9128",
4092 .compatible = "okaya,rs800480t-7x0gp",
4093 .data = &okaya_rs800480t_7x0gp,
4095 .compatible = "olimex,lcd-olinuxino-43-ts",
4096 .data = &olimex_lcd_olinuxino_43ts,
4098 .compatible = "ontat,yx700wv03",
4099 .data = &ontat_yx700wv03,
4101 .compatible = "ortustech,com37h3m05dtc",
4102 .data = &ortustech_com37h3m,
4104 .compatible = "ortustech,com37h3m99dtc",
4105 .data = &ortustech_com37h3m,
4107 .compatible = "ortustech,com43h4m85ulc",
4108 .data = &ortustech_com43h4m85ulc,
4110 .compatible = "osddisplays,osd070t1718-19ts",
4111 .data = &osddisplays_osd070t1718_19ts,
4113 .compatible = "pda,91-00156-a0",
4114 .data = &pda_91_00156_a0,
4116 .compatible = "powertip,ph800480t013-idf02",
4117 .data = &powertip_ph800480t013_idf02,
4119 .compatible = "qiaodian,qd43003c0-40",
4120 .data = &qd43003c0_40,
4122 .compatible = "rocktech,rk070er9427",
4123 .data = &rocktech_rk070er9427,
4125 .compatible = "rocktech,rk101ii01d-ct",
4126 .data = &rocktech_rk101ii01d_ct,
4128 .compatible = "samsung,lsn122dl01-c01",
4129 .data = &samsung_lsn122dl01_c01,
4131 .compatible = "samsung,ltn101nt05",
4132 .data = &samsung_ltn101nt05,
4134 .compatible = "samsung,ltn140at29-301",
4135 .data = &samsung_ltn140at29_301,
4137 .compatible = "satoz,sat050at40h12r2",
4138 .data = &satoz_sat050at40h12r2,
4140 .compatible = "sharp,ld-d5116z01b",
4141 .data = &sharp_ld_d5116z01b,
4143 .compatible = "sharp,lq035q7db03",
4144 .data = &sharp_lq035q7db03,
4146 .compatible = "sharp,lq070y3dg3b",
4147 .data = &sharp_lq070y3dg3b,
4149 .compatible = "sharp,lq101k1ly04",
4150 .data = &sharp_lq101k1ly04,
4152 .compatible = "sharp,lq123p1jx31",
4153 .data = &sharp_lq123p1jx31,
4155 .compatible = "sharp,ls020b1dd01d",
4156 .data = &sharp_ls020b1dd01d,
4158 .compatible = "shelly,sca07010-bfn-lnn",
4159 .data = &shelly_sca07010_bfn_lnn,
4161 .compatible = "starry,kr070pe2t",
4162 .data = &starry_kr070pe2t,
4164 .compatible = "starry,kr122ea0sra",
4165 .data = &starry_kr122ea0sra,
4167 .compatible = "tfc,s9700rtwv43tr-01b",
4168 .data = &tfc_s9700rtwv43tr_01b,
4170 .compatible = "tianma,tm070jdhg30",
4171 .data = &tianma_tm070jdhg30,
4173 .compatible = "tianma,tm070jvhg33",
4174 .data = &tianma_tm070jvhg33,
4176 .compatible = "tianma,tm070rvhg71",
4177 .data = &tianma_tm070rvhg71,
4179 .compatible = "ti,nspire-cx-lcd-panel",
4180 .data = &ti_nspire_cx_lcd_panel,
4182 .compatible = "ti,nspire-classic-lcd-panel",
4183 .data = &ti_nspire_classic_lcd_panel,
4185 .compatible = "toshiba,lt089ac29000",
4186 .data = &toshiba_lt089ac29000,
4188 .compatible = "tpk,f07a-0102",
4189 .data = &tpk_f07a_0102,
4191 .compatible = "tpk,f10a-0102",
4192 .data = &tpk_f10a_0102,
4194 .compatible = "urt,umsh-8596md-t",
4195 .data = &urt_umsh_8596md_parallel,
4197 .compatible = "urt,umsh-8596md-1t",
4198 .data = &urt_umsh_8596md_parallel,
4200 .compatible = "urt,umsh-8596md-7t",
4201 .data = &urt_umsh_8596md_parallel,
4203 .compatible = "urt,umsh-8596md-11t",
4204 .data = &urt_umsh_8596md_lvds,
4206 .compatible = "urt,umsh-8596md-19t",
4207 .data = &urt_umsh_8596md_lvds,
4209 .compatible = "urt,umsh-8596md-20t",
4210 .data = &urt_umsh_8596md_parallel,
4212 .compatible = "vxt,vl050-8048nt-c01",
4213 .data = &vl050_8048nt_c01,
4215 .compatible = "winstar,wf35ltiacd",
4216 .data = &winstar_wf35ltiacd,
4218 /* Must be the last entry */
4219 .compatible = "panel-dpi",
4225 MODULE_DEVICE_TABLE(of, platform_of_match);
4227 static int panel_simple_platform_probe(struct platform_device *pdev)
4229 const struct of_device_id *id;
4231 id = of_match_node(platform_of_match, pdev->dev.of_node);
4235 return panel_simple_probe(&pdev->dev, id->data);
4238 static int panel_simple_platform_remove(struct platform_device *pdev)
4240 return panel_simple_remove(&pdev->dev);
4243 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4245 panel_simple_shutdown(&pdev->dev);
4248 static struct platform_driver panel_simple_platform_driver = {
4250 .name = "panel-simple",
4251 .of_match_table = platform_of_match,
4253 .probe = panel_simple_platform_probe,
4254 .remove = panel_simple_platform_remove,
4255 .shutdown = panel_simple_platform_shutdown,
4258 struct panel_desc_dsi {
4259 struct panel_desc desc;
4261 unsigned long flags;
4262 enum mipi_dsi_pixel_format format;
4266 static const struct drm_display_mode auo_b080uan01_mode = {
4269 .hsync_start = 1200 + 62,
4270 .hsync_end = 1200 + 62 + 4,
4271 .htotal = 1200 + 62 + 4 + 62,
4273 .vsync_start = 1920 + 9,
4274 .vsync_end = 1920 + 9 + 2,
4275 .vtotal = 1920 + 9 + 2 + 8,
4278 static const struct panel_desc_dsi auo_b080uan01 = {
4280 .modes = &auo_b080uan01_mode,
4287 .connector_type = DRM_MODE_CONNECTOR_DSI,
4289 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4290 .format = MIPI_DSI_FMT_RGB888,
4294 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4297 .hsync_start = 1200 + 120,
4298 .hsync_end = 1200 + 120 + 20,
4299 .htotal = 1200 + 120 + 20 + 21,
4301 .vsync_start = 1920 + 21,
4302 .vsync_end = 1920 + 21 + 3,
4303 .vtotal = 1920 + 21 + 3 + 18,
4304 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4307 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4309 .modes = &boe_tv080wum_nl0_mode,
4315 .connector_type = DRM_MODE_CONNECTOR_DSI,
4317 .flags = MIPI_DSI_MODE_VIDEO |
4318 MIPI_DSI_MODE_VIDEO_BURST |
4319 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4320 .format = MIPI_DSI_FMT_RGB888,
4324 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4327 .hsync_start = 800 + 32,
4328 .hsync_end = 800 + 32 + 1,
4329 .htotal = 800 + 32 + 1 + 57,
4331 .vsync_start = 1280 + 28,
4332 .vsync_end = 1280 + 28 + 1,
4333 .vtotal = 1280 + 28 + 1 + 14,
4336 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4338 .modes = &lg_ld070wx3_sl01_mode,
4345 .connector_type = DRM_MODE_CONNECTOR_DSI,
4347 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4348 .format = MIPI_DSI_FMT_RGB888,
4352 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4355 .hsync_start = 720 + 12,
4356 .hsync_end = 720 + 12 + 4,
4357 .htotal = 720 + 12 + 4 + 112,
4359 .vsync_start = 1280 + 8,
4360 .vsync_end = 1280 + 8 + 4,
4361 .vtotal = 1280 + 8 + 4 + 12,
4364 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4366 .modes = &lg_lh500wx1_sd03_mode,
4373 .connector_type = DRM_MODE_CONNECTOR_DSI,
4375 .flags = MIPI_DSI_MODE_VIDEO,
4376 .format = MIPI_DSI_FMT_RGB888,
4380 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4383 .hsync_start = 1920 + 154,
4384 .hsync_end = 1920 + 154 + 16,
4385 .htotal = 1920 + 154 + 16 + 32,
4387 .vsync_start = 1200 + 17,
4388 .vsync_end = 1200 + 17 + 2,
4389 .vtotal = 1200 + 17 + 2 + 16,
4392 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4394 .modes = &panasonic_vvx10f004b00_mode,
4401 .connector_type = DRM_MODE_CONNECTOR_DSI,
4403 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4404 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4405 .format = MIPI_DSI_FMT_RGB888,
4409 static const struct drm_display_mode lg_acx467akm_7_mode = {
4412 .hsync_start = 1080 + 2,
4413 .hsync_end = 1080 + 2 + 2,
4414 .htotal = 1080 + 2 + 2 + 2,
4416 .vsync_start = 1920 + 2,
4417 .vsync_end = 1920 + 2 + 2,
4418 .vtotal = 1920 + 2 + 2 + 2,
4421 static const struct panel_desc_dsi lg_acx467akm_7 = {
4423 .modes = &lg_acx467akm_7_mode,
4430 .connector_type = DRM_MODE_CONNECTOR_DSI,
4433 .format = MIPI_DSI_FMT_RGB888,
4437 static const struct drm_display_mode osd101t2045_53ts_mode = {
4440 .hsync_start = 1920 + 112,
4441 .hsync_end = 1920 + 112 + 16,
4442 .htotal = 1920 + 112 + 16 + 32,
4444 .vsync_start = 1200 + 16,
4445 .vsync_end = 1200 + 16 + 2,
4446 .vtotal = 1200 + 16 + 2 + 16,
4447 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4450 static const struct panel_desc_dsi osd101t2045_53ts = {
4452 .modes = &osd101t2045_53ts_mode,
4459 .connector_type = DRM_MODE_CONNECTOR_DSI,
4461 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4462 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4463 MIPI_DSI_MODE_EOT_PACKET,
4464 .format = MIPI_DSI_FMT_RGB888,
4468 static const struct of_device_id dsi_of_match[] = {
4470 .compatible = "auo,b080uan01",
4471 .data = &auo_b080uan01
4473 .compatible = "boe,tv080wum-nl0",
4474 .data = &boe_tv080wum_nl0
4476 .compatible = "lg,ld070wx3-sl01",
4477 .data = &lg_ld070wx3_sl01
4479 .compatible = "lg,lh500wx1-sd03",
4480 .data = &lg_lh500wx1_sd03
4482 .compatible = "panasonic,vvx10f004b00",
4483 .data = &panasonic_vvx10f004b00
4485 .compatible = "lg,acx467akm-7",
4486 .data = &lg_acx467akm_7
4488 .compatible = "osddisplays,osd101t2045-53ts",
4489 .data = &osd101t2045_53ts
4494 MODULE_DEVICE_TABLE(of, dsi_of_match);
4496 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4498 const struct panel_desc_dsi *desc;
4499 const struct of_device_id *id;
4502 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4508 err = panel_simple_probe(&dsi->dev, &desc->desc);
4512 dsi->mode_flags = desc->flags;
4513 dsi->format = desc->format;
4514 dsi->lanes = desc->lanes;
4516 err = mipi_dsi_attach(dsi);
4518 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4520 drm_panel_remove(&panel->base);
4526 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4530 err = mipi_dsi_detach(dsi);
4532 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4534 return panel_simple_remove(&dsi->dev);
4537 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4539 panel_simple_shutdown(&dsi->dev);
4542 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4544 .name = "panel-simple-dsi",
4545 .of_match_table = dsi_of_match,
4547 .probe = panel_simple_dsi_probe,
4548 .remove = panel_simple_dsi_remove,
4549 .shutdown = panel_simple_dsi_shutdown,
4552 static int __init panel_simple_init(void)
4556 err = platform_driver_register(&panel_simple_platform_driver);
4560 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4561 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4568 module_init(panel_simple_init);
4570 static void __exit panel_simple_exit(void)
4572 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4573 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4575 platform_driver_unregister(&panel_simple_platform_driver);
4577 module_exit(panel_simple_exit);
4579 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4580 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4581 MODULE_LICENSE("GPL and additional rights");