2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/i2c.h>
27 #include <linux/media-bus-format.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regulator/consumer.h>
34 #include <video/display_timing.h>
35 #include <video/of_display_timing.h>
36 #include <video/videomode.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_mipi_dsi.h>
42 #include <drm/drm_panel.h>
45 * struct panel_desc - Describes a simple panel.
49 * @modes: Pointer to array of fixed modes appropriate for this panel.
51 * If only one mode then this can just be the address of the mode.
52 * NOTE: cannot be used with "timings" and also if this is specified
53 * then you cannot override the mode in the device tree.
55 const struct drm_display_mode *modes;
57 /** @num_modes: Number of elements in modes array. */
58 unsigned int num_modes;
61 * @timings: Pointer to array of display timings
63 * NOTE: cannot be used with "modes" and also these will be used to
64 * validate a device tree override if one is present.
66 const struct display_timing *timings;
68 /** @num_timings: Number of elements in timings array. */
69 unsigned int num_timings;
71 /** @bpc: Bits per color. */
74 /** @size: Structure containing the physical size of this panel. */
77 * @size.width: Width (in mm) of the active display area.
82 * @size.height: Height (in mm) of the active display area.
87 /** @delay: Structure containing various delay values for this panel. */
90 * @delay.prepare: Time for the panel to become ready.
92 * The time (in milliseconds) that it takes for the panel to
93 * become ready and start receiving video data
98 * @delay.enable: Time for the panel to display a valid frame.
100 * The time (in milliseconds) that it takes for the panel to
101 * display the first valid frame after starting to receive
107 * @delay.disable: Time for the panel to turn the display off.
109 * The time (in milliseconds) that it takes for the panel to
110 * turn the display off (no content is visible).
112 unsigned int disable;
115 * @delay.unprepare: Time to power down completely.
117 * The time (in milliseconds) that it takes for the panel
118 * to power itself down completely.
120 * This time is used to prevent a future "prepare" from
121 * starting until at least this many milliseconds has passed.
122 * If at prepare time less time has passed since unprepare
123 * finished, the driver waits for the remaining time.
125 unsigned int unprepare;
128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
138 struct panel_simple {
139 struct drm_panel base;
144 ktime_t prepared_time;
145 ktime_t unprepared_time;
147 const struct panel_desc *desc;
149 struct regulator *supply;
150 struct i2c_adapter *ddc;
152 struct gpio_desc *enable_gpio;
156 struct drm_display_mode override_mode;
158 enum drm_panel_orientation orientation;
161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
163 return container_of(panel, struct panel_simple, base);
166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
167 struct drm_connector *connector)
169 struct drm_display_mode *mode;
170 unsigned int i, num = 0;
172 for (i = 0; i < panel->desc->num_timings; i++) {
173 const struct display_timing *dt = &panel->desc->timings[i];
176 videomode_from_timing(dt, &vm);
177 mode = drm_mode_create(connector->dev);
179 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
180 dt->hactive.typ, dt->vactive.typ);
184 drm_display_mode_from_videomode(&vm, mode);
186 mode->type |= DRM_MODE_TYPE_DRIVER;
188 if (panel->desc->num_timings == 1)
189 mode->type |= DRM_MODE_TYPE_PREFERRED;
191 drm_mode_probed_add(connector, mode);
198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
199 struct drm_connector *connector)
201 struct drm_display_mode *mode;
202 unsigned int i, num = 0;
204 for (i = 0; i < panel->desc->num_modes; i++) {
205 const struct drm_display_mode *m = &panel->desc->modes[i];
207 mode = drm_mode_duplicate(connector->dev, m);
209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
210 m->hdisplay, m->vdisplay,
211 drm_mode_vrefresh(m));
215 mode->type |= DRM_MODE_TYPE_DRIVER;
217 if (panel->desc->num_modes == 1)
218 mode->type |= DRM_MODE_TYPE_PREFERRED;
220 drm_mode_set_name(mode);
222 drm_mode_probed_add(connector, mode);
229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
230 struct drm_connector *connector)
232 struct drm_display_mode *mode;
233 bool has_override = panel->override_mode.type;
234 unsigned int num = 0;
240 mode = drm_mode_duplicate(connector->dev,
241 &panel->override_mode);
243 drm_mode_probed_add(connector, mode);
246 dev_err(panel->base.dev, "failed to add override mode\n");
250 /* Only add timings if override was not there or failed to validate */
251 if (num == 0 && panel->desc->num_timings)
252 num = panel_simple_get_timings_modes(panel, connector);
255 * Only add fixed modes if timings/override added no mode.
257 * We should only ever have either the display timings specified
258 * or a fixed mode. Anything else is rather bogus.
260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
262 num = panel_simple_get_display_modes(panel, connector);
264 connector->display_info.bpc = panel->desc->bpc;
265 connector->display_info.width_mm = panel->desc->size.width;
266 connector->display_info.height_mm = panel->desc->size.height;
267 if (panel->desc->bus_format)
268 drm_display_info_set_bus_formats(&connector->display_info,
269 &panel->desc->bus_format, 1);
270 connector->display_info.bus_flags = panel->desc->bus_flags;
275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
277 ktime_t now_ktime, min_ktime;
282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
283 now_ktime = ktime_get_boottime();
285 if (ktime_before(now_ktime, min_ktime))
286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
289 static int panel_simple_disable(struct drm_panel *panel)
291 struct panel_simple *p = to_panel_simple(panel);
296 if (p->desc->delay.disable)
297 msleep(p->desc->delay.disable);
304 static int panel_simple_suspend(struct device *dev)
306 struct panel_simple *p = dev_get_drvdata(dev);
308 gpiod_set_value_cansleep(p->enable_gpio, 0);
309 regulator_disable(p->supply);
310 p->unprepared_time = ktime_get_boottime();
318 static int panel_simple_unprepare(struct drm_panel *panel)
320 struct panel_simple *p = to_panel_simple(panel);
323 /* Unpreparing when already unprepared is a no-op */
327 pm_runtime_mark_last_busy(panel->dev);
328 ret = pm_runtime_put_autosuspend(panel->dev);
336 static int panel_simple_resume(struct device *dev)
338 struct panel_simple *p = dev_get_drvdata(dev);
341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
343 err = regulator_enable(p->supply);
345 dev_err(dev, "failed to enable supply: %d\n", err);
349 gpiod_set_value_cansleep(p->enable_gpio, 1);
351 if (p->desc->delay.prepare)
352 msleep(p->desc->delay.prepare);
354 p->prepared_time = ktime_get_boottime();
359 static int panel_simple_prepare(struct drm_panel *panel)
361 struct panel_simple *p = to_panel_simple(panel);
364 /* Preparing when already prepared is a no-op */
368 ret = pm_runtime_get_sync(panel->dev);
370 pm_runtime_put_autosuspend(panel->dev);
379 static int panel_simple_enable(struct drm_panel *panel)
381 struct panel_simple *p = to_panel_simple(panel);
386 if (p->desc->delay.enable)
387 msleep(p->desc->delay.enable);
394 static int panel_simple_get_modes(struct drm_panel *panel,
395 struct drm_connector *connector)
397 struct panel_simple *p = to_panel_simple(panel);
400 /* probe EDID if a DDC bus is available */
402 pm_runtime_get_sync(panel->dev);
405 p->edid = drm_get_edid(connector, p->ddc);
408 num += drm_add_edid_modes(connector, p->edid);
410 pm_runtime_mark_last_busy(panel->dev);
411 pm_runtime_put_autosuspend(panel->dev);
414 /* add hard-coded panel modes */
415 num += panel_simple_get_non_edid_modes(p, connector);
418 * TODO: Remove once all drm drivers call
419 * drm_connector_set_orientation_from_panel()
421 drm_connector_set_panel_orientation(connector, p->orientation);
426 static int panel_simple_get_timings(struct drm_panel *panel,
427 unsigned int num_timings,
428 struct display_timing *timings)
430 struct panel_simple *p = to_panel_simple(panel);
433 if (p->desc->num_timings < num_timings)
434 num_timings = p->desc->num_timings;
437 for (i = 0; i < num_timings; i++)
438 timings[i] = p->desc->timings[i];
440 return p->desc->num_timings;
443 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
445 struct panel_simple *p = to_panel_simple(panel);
447 return p->orientation;
450 static const struct drm_panel_funcs panel_simple_funcs = {
451 .disable = panel_simple_disable,
452 .unprepare = panel_simple_unprepare,
453 .prepare = panel_simple_prepare,
454 .enable = panel_simple_enable,
455 .get_modes = panel_simple_get_modes,
456 .get_orientation = panel_simple_get_orientation,
457 .get_timings = panel_simple_get_timings,
460 static struct panel_desc panel_dpi;
462 static int panel_dpi_probe(struct device *dev,
463 struct panel_simple *panel)
465 struct display_timing *timing;
466 const struct device_node *np;
467 struct panel_desc *desc;
468 unsigned int bus_flags;
473 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
477 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
481 ret = of_get_display_timing(np, "panel-timing", timing);
483 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
488 desc->timings = timing;
489 desc->num_timings = 1;
491 of_property_read_u32(np, "width-mm", &desc->size.width);
492 of_property_read_u32(np, "height-mm", &desc->size.height);
494 /* Extract bus_flags from display_timing */
496 vm.flags = timing->flags;
497 drm_bus_flags_from_videomode(&vm, &bus_flags);
498 desc->bus_flags = bus_flags;
500 /* We do not know the connector for the DT node, so guess it */
501 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
508 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
509 (to_check->field.typ >= bounds->field.min && \
510 to_check->field.typ <= bounds->field.max)
511 static void panel_simple_parse_panel_timing_node(struct device *dev,
512 struct panel_simple *panel,
513 const struct display_timing *ot)
515 const struct panel_desc *desc = panel->desc;
519 if (WARN_ON(desc->num_modes)) {
520 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
523 if (WARN_ON(!desc->num_timings)) {
524 dev_err(dev, "Reject override mode: no timings specified\n");
528 for (i = 0; i < panel->desc->num_timings; i++) {
529 const struct display_timing *dt = &panel->desc->timings[i];
531 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
537 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
538 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
541 if (ot->flags != dt->flags)
544 videomode_from_timing(ot, &vm);
545 drm_display_mode_from_videomode(&vm, &panel->override_mode);
546 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
547 DRM_MODE_TYPE_PREFERRED;
551 if (WARN_ON(!panel->override_mode.type))
552 dev_err(dev, "Reject override mode: No display_timing found\n");
555 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
557 struct panel_simple *panel;
558 struct display_timing dt;
559 struct device_node *ddc;
564 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
568 panel->enabled = false;
569 panel->prepared_time = 0;
572 panel->supply = devm_regulator_get(dev, "power");
573 if (IS_ERR(panel->supply))
574 return PTR_ERR(panel->supply);
576 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
578 if (IS_ERR(panel->enable_gpio))
579 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
580 "failed to request GPIO\n");
582 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
584 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
588 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
590 panel->ddc = of_find_i2c_adapter_by_node(ddc);
594 return -EPROBE_DEFER;
597 if (desc == &panel_dpi) {
598 /* Handle the generic panel-dpi binding */
599 err = panel_dpi_probe(dev, panel);
604 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
605 panel_simple_parse_panel_timing_node(dev, panel, &dt);
608 connector_type = desc->connector_type;
609 /* Catch common mistakes for panels. */
610 switch (connector_type) {
612 dev_warn(dev, "Specify missing connector_type\n");
613 connector_type = DRM_MODE_CONNECTOR_DPI;
615 case DRM_MODE_CONNECTOR_LVDS:
616 WARN_ON(desc->bus_flags &
617 ~(DRM_BUS_FLAG_DE_LOW |
618 DRM_BUS_FLAG_DE_HIGH |
619 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
620 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
621 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
622 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
623 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
624 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
626 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
627 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
630 case DRM_MODE_CONNECTOR_eDP:
631 dev_warn(dev, "eDP panels moved to panel-edp\n");
634 case DRM_MODE_CONNECTOR_DSI:
635 if (desc->bpc != 6 && desc->bpc != 8)
636 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
638 case DRM_MODE_CONNECTOR_DPI:
639 bus_flags = DRM_BUS_FLAG_DE_LOW |
640 DRM_BUS_FLAG_DE_HIGH |
641 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
642 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
643 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
644 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
645 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
646 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
647 if (desc->bus_flags & ~bus_flags)
648 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
649 if (!(desc->bus_flags & bus_flags))
650 dev_warn(dev, "Specify missing bus_flags\n");
651 if (desc->bus_format == 0)
652 dev_warn(dev, "Specify missing bus_format\n");
653 if (desc->bpc != 6 && desc->bpc != 8)
654 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
657 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
658 connector_type = DRM_MODE_CONNECTOR_DPI;
662 dev_set_drvdata(dev, panel);
665 * We use runtime PM for prepare / unprepare since those power the panel
666 * on and off and those can be very slow operations. This is important
667 * to optimize powering the panel on briefly to read the EDID before
668 * fully enabling the panel.
670 pm_runtime_enable(dev);
671 pm_runtime_set_autosuspend_delay(dev, 1000);
672 pm_runtime_use_autosuspend(dev);
674 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
676 err = drm_panel_of_backlight(&panel->base);
678 dev_err_probe(dev, err, "Could not find backlight\n");
679 goto disable_pm_runtime;
682 drm_panel_add(&panel->base);
687 pm_runtime_dont_use_autosuspend(dev);
688 pm_runtime_disable(dev);
691 put_device(&panel->ddc->dev);
696 static void panel_simple_remove(struct device *dev)
698 struct panel_simple *panel = dev_get_drvdata(dev);
700 drm_panel_remove(&panel->base);
701 drm_panel_disable(&panel->base);
702 drm_panel_unprepare(&panel->base);
704 pm_runtime_dont_use_autosuspend(dev);
705 pm_runtime_disable(dev);
707 put_device(&panel->ddc->dev);
710 static void panel_simple_shutdown(struct device *dev)
712 struct panel_simple *panel = dev_get_drvdata(dev);
714 drm_panel_disable(&panel->base);
715 drm_panel_unprepare(&panel->base);
718 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
721 .hsync_start = 1280 + 40,
722 .hsync_end = 1280 + 40 + 80,
723 .htotal = 1280 + 40 + 80 + 40,
725 .vsync_start = 800 + 3,
726 .vsync_end = 800 + 3 + 10,
727 .vtotal = 800 + 3 + 10 + 10,
728 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
731 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
732 .modes = &ire_am_1280800n3tzqw_t00h_mode,
739 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
740 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
741 .connector_type = DRM_MODE_CONNECTOR_LVDS,
744 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
747 .hsync_start = 480 + 2,
748 .hsync_end = 480 + 2 + 41,
749 .htotal = 480 + 2 + 41 + 2,
751 .vsync_start = 272 + 2,
752 .vsync_end = 272 + 2 + 10,
753 .vtotal = 272 + 2 + 10 + 2,
754 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
757 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
758 .modes = &ire_am_480272h3tmqw_t01h_mode,
765 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
768 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
771 .hsync_start = 800 + 0,
772 .hsync_end = 800 + 0 + 255,
773 .htotal = 800 + 0 + 255 + 0,
775 .vsync_start = 480 + 2,
776 .vsync_end = 480 + 2 + 45,
777 .vtotal = 480 + 2 + 45 + 0,
778 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
781 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
782 .pixelclock = { 29930000, 33260000, 36590000 },
783 .hactive = { 800, 800, 800 },
784 .hfront_porch = { 1, 40, 168 },
785 .hback_porch = { 88, 88, 88 },
786 .hsync_len = { 1, 128, 128 },
787 .vactive = { 480, 480, 480 },
788 .vfront_porch = { 1, 35, 37 },
789 .vback_porch = { 8, 8, 8 },
790 .vsync_len = { 1, 2, 2 },
791 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
792 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
793 DISPLAY_FLAGS_SYNC_POSEDGE,
796 static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
797 .timings = &ire_am_800480l1tmqw_t00h_timing,
804 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
805 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
806 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
807 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
808 .connector_type = DRM_MODE_CONNECTOR_DPI,
811 static const struct panel_desc ampire_am800480r3tmqwa1h = {
812 .modes = &ire_am800480r3tmqwa1h_mode,
819 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
822 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
823 .pixelclock = { 34500000, 39600000, 50400000 },
824 .hactive = { 800, 800, 800 },
825 .hfront_porch = { 12, 112, 312 },
826 .hback_porch = { 87, 87, 48 },
827 .hsync_len = { 1, 1, 40 },
828 .vactive = { 600, 600, 600 },
829 .vfront_porch = { 1, 21, 61 },
830 .vback_porch = { 38, 38, 19 },
831 .vsync_len = { 1, 1, 20 },
832 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
833 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
834 DISPLAY_FLAGS_SYNC_POSEDGE,
837 static const struct panel_desc ampire_am800600p5tmqwtb8h = {
838 .timings = &ire_am800600p5tmqw_tb8h_timing,
845 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
846 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
847 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
848 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
849 .connector_type = DRM_MODE_CONNECTOR_DPI,
852 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
853 .pixelclock = { 26400000, 33300000, 46800000 },
854 .hactive = { 800, 800, 800 },
855 .hfront_porch = { 16, 210, 354 },
856 .hback_porch = { 45, 36, 6 },
857 .hsync_len = { 1, 10, 40 },
858 .vactive = { 480, 480, 480 },
859 .vfront_porch = { 7, 22, 147 },
860 .vback_porch = { 22, 13, 3 },
861 .vsync_len = { 1, 10, 20 },
862 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
863 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
866 static const struct panel_desc armadeus_st0700_adapt = {
867 .timings = &santek_st0700i5y_rbslw_f_timing,
874 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
875 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
878 static const struct drm_display_mode auo_b101aw03_mode = {
881 .hsync_start = 1024 + 156,
882 .hsync_end = 1024 + 156 + 8,
883 .htotal = 1024 + 156 + 8 + 156,
885 .vsync_start = 600 + 16,
886 .vsync_end = 600 + 16 + 6,
887 .vtotal = 600 + 16 + 6 + 16,
890 static const struct panel_desc auo_b101aw03 = {
891 .modes = &auo_b101aw03_mode,
898 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
899 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
900 .connector_type = DRM_MODE_CONNECTOR_LVDS,
903 static const struct drm_display_mode auo_b101xtn01_mode = {
906 .hsync_start = 1366 + 20,
907 .hsync_end = 1366 + 20 + 70,
908 .htotal = 1366 + 20 + 70,
910 .vsync_start = 768 + 14,
911 .vsync_end = 768 + 14 + 42,
912 .vtotal = 768 + 14 + 42,
913 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
916 static const struct panel_desc auo_b101xtn01 = {
917 .modes = &auo_b101xtn01_mode,
926 static const struct display_timing auo_g070vvn01_timings = {
927 .pixelclock = { 33300000, 34209000, 45000000 },
928 .hactive = { 800, 800, 800 },
929 .hfront_porch = { 20, 40, 200 },
930 .hback_porch = { 87, 40, 1 },
931 .hsync_len = { 1, 48, 87 },
932 .vactive = { 480, 480, 480 },
933 .vfront_porch = { 5, 13, 200 },
934 .vback_porch = { 31, 31, 29 },
935 .vsync_len = { 1, 1, 3 },
938 static const struct panel_desc auo_g070vvn01 = {
939 .timings = &auo_g070vvn01_timings,
954 static const struct drm_display_mode auo_g101evn010_mode = {
957 .hsync_start = 1280 + 82,
958 .hsync_end = 1280 + 82 + 2,
959 .htotal = 1280 + 82 + 2 + 84,
961 .vsync_start = 800 + 8,
962 .vsync_end = 800 + 8 + 2,
963 .vtotal = 800 + 8 + 2 + 6,
966 static const struct panel_desc auo_g101evn010 = {
967 .modes = &auo_g101evn010_mode,
974 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
975 .connector_type = DRM_MODE_CONNECTOR_LVDS,
978 static const struct drm_display_mode auo_g104sn02_mode = {
981 .hsync_start = 800 + 40,
982 .hsync_end = 800 + 40 + 216,
983 .htotal = 800 + 40 + 216 + 128,
985 .vsync_start = 600 + 10,
986 .vsync_end = 600 + 10 + 35,
987 .vtotal = 600 + 10 + 35 + 2,
990 static const struct panel_desc auo_g104sn02 = {
991 .modes = &auo_g104sn02_mode,
998 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
999 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1002 static const struct drm_display_mode auo_g121ean01_mode = {
1005 .hsync_start = 1280 + 58,
1006 .hsync_end = 1280 + 58 + 8,
1007 .htotal = 1280 + 58 + 8 + 70,
1009 .vsync_start = 800 + 6,
1010 .vsync_end = 800 + 6 + 4,
1011 .vtotal = 800 + 6 + 4 + 10,
1014 static const struct panel_desc auo_g121ean01 = {
1015 .modes = &auo_g121ean01_mode,
1022 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1023 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1026 static const struct display_timing auo_g133han01_timings = {
1027 .pixelclock = { 134000000, 141200000, 149000000 },
1028 .hactive = { 1920, 1920, 1920 },
1029 .hfront_porch = { 39, 58, 77 },
1030 .hback_porch = { 59, 88, 117 },
1031 .hsync_len = { 28, 42, 56 },
1032 .vactive = { 1080, 1080, 1080 },
1033 .vfront_porch = { 3, 8, 11 },
1034 .vback_porch = { 5, 14, 19 },
1035 .vsync_len = { 4, 14, 19 },
1038 static const struct panel_desc auo_g133han01 = {
1039 .timings = &auo_g133han01_timings,
1052 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1053 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1056 static const struct drm_display_mode auo_g156xtn01_mode = {
1059 .hsync_start = 1366 + 33,
1060 .hsync_end = 1366 + 33 + 67,
1063 .vsync_start = 768 + 4,
1064 .vsync_end = 768 + 4 + 4,
1068 static const struct panel_desc auo_g156xtn01 = {
1069 .modes = &auo_g156xtn01_mode,
1076 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1077 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1080 static const struct display_timing auo_g185han01_timings = {
1081 .pixelclock = { 120000000, 144000000, 175000000 },
1082 .hactive = { 1920, 1920, 1920 },
1083 .hfront_porch = { 36, 120, 148 },
1084 .hback_porch = { 24, 88, 108 },
1085 .hsync_len = { 20, 48, 64 },
1086 .vactive = { 1080, 1080, 1080 },
1087 .vfront_porch = { 6, 10, 40 },
1088 .vback_porch = { 2, 5, 20 },
1089 .vsync_len = { 2, 5, 20 },
1092 static const struct panel_desc auo_g185han01 = {
1093 .timings = &auo_g185han01_timings,
1106 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1107 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1110 static const struct display_timing auo_g190ean01_timings = {
1111 .pixelclock = { 90000000, 108000000, 135000000 },
1112 .hactive = { 1280, 1280, 1280 },
1113 .hfront_porch = { 126, 184, 1266 },
1114 .hback_porch = { 84, 122, 844 },
1115 .hsync_len = { 70, 102, 704 },
1116 .vactive = { 1024, 1024, 1024 },
1117 .vfront_porch = { 4, 26, 76 },
1118 .vback_porch = { 2, 8, 25 },
1119 .vsync_len = { 2, 8, 25 },
1122 static const struct panel_desc auo_g190ean01 = {
1123 .timings = &auo_g190ean01_timings,
1136 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1137 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1140 static const struct display_timing auo_p320hvn03_timings = {
1141 .pixelclock = { 106000000, 148500000, 164000000 },
1142 .hactive = { 1920, 1920, 1920 },
1143 .hfront_porch = { 25, 50, 130 },
1144 .hback_porch = { 25, 50, 130 },
1145 .hsync_len = { 20, 40, 105 },
1146 .vactive = { 1080, 1080, 1080 },
1147 .vfront_porch = { 8, 17, 150 },
1148 .vback_porch = { 8, 17, 150 },
1149 .vsync_len = { 4, 11, 100 },
1152 static const struct panel_desc auo_p320hvn03 = {
1153 .timings = &auo_p320hvn03_timings,
1165 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1166 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1169 static const struct drm_display_mode auo_t215hvn01_mode = {
1172 .hsync_start = 1920 + 88,
1173 .hsync_end = 1920 + 88 + 44,
1174 .htotal = 1920 + 88 + 44 + 148,
1176 .vsync_start = 1080 + 4,
1177 .vsync_end = 1080 + 4 + 5,
1178 .vtotal = 1080 + 4 + 5 + 36,
1181 static const struct panel_desc auo_t215hvn01 = {
1182 .modes = &auo_t215hvn01_mode,
1195 static const struct drm_display_mode avic_tm070ddh03_mode = {
1198 .hsync_start = 1024 + 160,
1199 .hsync_end = 1024 + 160 + 4,
1200 .htotal = 1024 + 160 + 4 + 156,
1202 .vsync_start = 600 + 17,
1203 .vsync_end = 600 + 17 + 1,
1204 .vtotal = 600 + 17 + 1 + 17,
1207 static const struct panel_desc avic_tm070ddh03 = {
1208 .modes = &avic_tm070ddh03_mode,
1222 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1225 .hsync_start = 800 + 40,
1226 .hsync_end = 800 + 40 + 48,
1227 .htotal = 800 + 40 + 48 + 40,
1229 .vsync_start = 480 + 13,
1230 .vsync_end = 480 + 13 + 3,
1231 .vtotal = 480 + 13 + 3 + 29,
1234 static const struct panel_desc bananapi_s070wv20_ct16 = {
1235 .modes = &bananapi_s070wv20_ct16_mode,
1244 static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1245 .pixelclock = { 69922000, 71000000, 72293000 },
1246 .hactive = { 1280, 1280, 1280 },
1247 .hfront_porch = { 48, 48, 48 },
1248 .hback_porch = { 80, 80, 80 },
1249 .hsync_len = { 32, 32, 32 },
1250 .vactive = { 800, 800, 800 },
1251 .vfront_porch = { 3, 3, 3 },
1252 .vback_porch = { 14, 14, 14 },
1253 .vsync_len = { 6, 6, 6 },
1256 static const struct panel_desc boe_ev121wxm_n10_1850 = {
1257 .timings = &boe_ev121wxm_n10_1850_timing,
1270 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1271 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1272 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1275 static const struct drm_display_mode boe_hv070wsa_mode = {
1278 .hsync_start = 1024 + 30,
1279 .hsync_end = 1024 + 30 + 30,
1280 .htotal = 1024 + 30 + 30 + 30,
1282 .vsync_start = 600 + 10,
1283 .vsync_end = 600 + 10 + 10,
1284 .vtotal = 600 + 10 + 10 + 10,
1287 static const struct panel_desc boe_hv070wsa = {
1288 .modes = &boe_hv070wsa_mode,
1295 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1296 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1297 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1300 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1303 .hsync_start = 480 + 5,
1304 .hsync_end = 480 + 5 + 5,
1305 .htotal = 480 + 5 + 5 + 40,
1307 .vsync_start = 272 + 8,
1308 .vsync_end = 272 + 8 + 8,
1309 .vtotal = 272 + 8 + 8 + 8,
1310 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1313 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1314 .modes = &cdtech_s043wq26h_ct7_mode,
1321 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1324 /* S070PWS19HP-FC21 2017/04/22 */
1325 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1328 .hsync_start = 1024 + 160,
1329 .hsync_end = 1024 + 160 + 20,
1330 .htotal = 1024 + 160 + 20 + 140,
1332 .vsync_start = 600 + 12,
1333 .vsync_end = 600 + 12 + 3,
1334 .vtotal = 600 + 12 + 3 + 20,
1335 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1338 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1339 .modes = &cdtech_s070pws19hp_fc21_mode,
1346 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1347 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1348 .connector_type = DRM_MODE_CONNECTOR_DPI,
1351 /* S070SWV29HG-DC44 2017/09/21 */
1352 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1355 .hsync_start = 800 + 210,
1356 .hsync_end = 800 + 210 + 2,
1357 .htotal = 800 + 210 + 2 + 44,
1359 .vsync_start = 480 + 22,
1360 .vsync_end = 480 + 22 + 2,
1361 .vtotal = 480 + 22 + 2 + 21,
1362 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1365 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1366 .modes = &cdtech_s070swv29hg_dc44_mode,
1373 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1374 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1375 .connector_type = DRM_MODE_CONNECTOR_DPI,
1378 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1381 .hsync_start = 800 + 40,
1382 .hsync_end = 800 + 40 + 40,
1383 .htotal = 800 + 40 + 40 + 48,
1385 .vsync_start = 480 + 29,
1386 .vsync_end = 480 + 29 + 13,
1387 .vtotal = 480 + 29 + 13 + 3,
1388 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1391 static const struct panel_desc cdtech_s070wv95_ct16 = {
1392 .modes = &cdtech_s070wv95_ct16_mode,
1401 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1402 .pixelclock = { 68900000, 71100000, 73400000 },
1403 .hactive = { 1280, 1280, 1280 },
1404 .hfront_porch = { 65, 80, 95 },
1405 .hback_porch = { 64, 79, 94 },
1406 .hsync_len = { 1, 1, 1 },
1407 .vactive = { 800, 800, 800 },
1408 .vfront_porch = { 7, 11, 14 },
1409 .vback_porch = { 7, 11, 14 },
1410 .vsync_len = { 1, 1, 1 },
1411 .flags = DISPLAY_FLAGS_DE_HIGH,
1414 static const struct panel_desc chefree_ch101olhlwh_002 = {
1415 .timings = &chefree_ch101olhlwh_002_timing,
1426 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1427 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1428 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1431 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1434 .hsync_start = 800 + 49,
1435 .hsync_end = 800 + 49 + 33,
1436 .htotal = 800 + 49 + 33 + 17,
1438 .vsync_start = 1280 + 1,
1439 .vsync_end = 1280 + 1 + 7,
1440 .vtotal = 1280 + 1 + 7 + 15,
1441 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1444 static const struct panel_desc chunghwa_claa070wp03xg = {
1445 .modes = &chunghwa_claa070wp03xg_mode,
1452 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1453 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1454 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1457 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1460 .hsync_start = 1366 + 58,
1461 .hsync_end = 1366 + 58 + 58,
1462 .htotal = 1366 + 58 + 58 + 58,
1464 .vsync_start = 768 + 4,
1465 .vsync_end = 768 + 4 + 4,
1466 .vtotal = 768 + 4 + 4 + 4,
1469 static const struct panel_desc chunghwa_claa101wa01a = {
1470 .modes = &chunghwa_claa101wa01a_mode,
1477 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1478 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1479 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1482 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1485 .hsync_start = 1366 + 48,
1486 .hsync_end = 1366 + 48 + 32,
1487 .htotal = 1366 + 48 + 32 + 20,
1489 .vsync_start = 768 + 16,
1490 .vsync_end = 768 + 16 + 8,
1491 .vtotal = 768 + 16 + 8 + 16,
1494 static const struct panel_desc chunghwa_claa101wb01 = {
1495 .modes = &chunghwa_claa101wb01_mode,
1502 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1503 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1504 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1507 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1508 .pixelclock = { 5000000, 9000000, 12000000 },
1509 .hactive = { 480, 480, 480 },
1510 .hfront_porch = { 12, 12, 12 },
1511 .hback_porch = { 12, 12, 12 },
1512 .hsync_len = { 21, 21, 21 },
1513 .vactive = { 272, 272, 272 },
1514 .vfront_porch = { 4, 4, 4 },
1515 .vback_porch = { 4, 4, 4 },
1516 .vsync_len = { 8, 8, 8 },
1519 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1520 .timings = &dataimage_fg040346dsswbg04_timing,
1527 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1528 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1529 .connector_type = DRM_MODE_CONNECTOR_DPI,
1532 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1533 .pixelclock = { 68900000, 71110000, 73400000 },
1534 .hactive = { 1280, 1280, 1280 },
1535 .vactive = { 800, 800, 800 },
1536 .hback_porch = { 100, 100, 100 },
1537 .hfront_porch = { 100, 100, 100 },
1538 .vback_porch = { 5, 5, 5 },
1539 .vfront_porch = { 5, 5, 5 },
1540 .hsync_len = { 24, 24, 24 },
1541 .vsync_len = { 3, 3, 3 },
1542 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1543 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1546 static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1547 .timings = &dataimage_fg1001l0dsswmg01_timing,
1556 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1559 .hsync_start = 800 + 40,
1560 .hsync_end = 800 + 40 + 128,
1561 .htotal = 800 + 40 + 128 + 88,
1563 .vsync_start = 480 + 10,
1564 .vsync_end = 480 + 10 + 2,
1565 .vtotal = 480 + 10 + 2 + 33,
1566 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1569 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1570 .modes = &dataimage_scf0700c48ggu18_mode,
1577 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1578 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1581 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1582 .pixelclock = { 45000000, 51200000, 57000000 },
1583 .hactive = { 1024, 1024, 1024 },
1584 .hfront_porch = { 100, 106, 113 },
1585 .hback_porch = { 100, 106, 113 },
1586 .hsync_len = { 100, 108, 114 },
1587 .vactive = { 600, 600, 600 },
1588 .vfront_porch = { 8, 11, 15 },
1589 .vback_porch = { 8, 11, 15 },
1590 .vsync_len = { 9, 13, 15 },
1591 .flags = DISPLAY_FLAGS_DE_HIGH,
1594 static const struct panel_desc dlc_dlc0700yzg_1 = {
1595 .timings = &dlc_dlc0700yzg_1_timing,
1607 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1608 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1611 static const struct display_timing dlc_dlc1010gig_timing = {
1612 .pixelclock = { 68900000, 71100000, 73400000 },
1613 .hactive = { 1280, 1280, 1280 },
1614 .hfront_porch = { 43, 53, 63 },
1615 .hback_porch = { 43, 53, 63 },
1616 .hsync_len = { 44, 54, 64 },
1617 .vactive = { 800, 800, 800 },
1618 .vfront_porch = { 5, 8, 11 },
1619 .vback_porch = { 5, 8, 11 },
1620 .vsync_len = { 5, 7, 11 },
1621 .flags = DISPLAY_FLAGS_DE_HIGH,
1624 static const struct panel_desc dlc_dlc1010gig = {
1625 .timings = &dlc_dlc1010gig_timing,
1638 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1639 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1642 static const struct drm_display_mode edt_et035012dm6_mode = {
1645 .hsync_start = 320 + 20,
1646 .hsync_end = 320 + 20 + 30,
1647 .htotal = 320 + 20 + 68,
1649 .vsync_start = 240 + 4,
1650 .vsync_end = 240 + 4 + 4,
1651 .vtotal = 240 + 4 + 4 + 14,
1652 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1655 static const struct panel_desc edt_et035012dm6 = {
1656 .modes = &edt_et035012dm6_mode,
1663 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1664 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1667 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1670 .hsync_start = 320 + 20,
1671 .hsync_end = 320 + 20 + 68,
1672 .htotal = 320 + 20 + 68,
1674 .vsync_start = 240 + 4,
1675 .vsync_end = 240 + 4 + 18,
1676 .vtotal = 240 + 4 + 18,
1677 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1680 static const struct panel_desc edt_etm0350g0dh6 = {
1681 .modes = &edt_etm0350g0dh6_mode,
1688 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1689 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1690 .connector_type = DRM_MODE_CONNECTOR_DPI,
1693 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1696 .hsync_start = 480 + 8,
1697 .hsync_end = 480 + 8 + 4,
1698 .htotal = 480 + 8 + 4 + 41,
1701 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1706 .vsync_start = 288 + 2,
1707 .vsync_end = 288 + 2 + 4,
1708 .vtotal = 288 + 2 + 4 + 10,
1711 static const struct panel_desc edt_etm043080dh6gp = {
1712 .modes = &edt_etm043080dh6gp_mode,
1719 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1720 .connector_type = DRM_MODE_CONNECTOR_DPI,
1723 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1726 .hsync_start = 480 + 2,
1727 .hsync_end = 480 + 2 + 41,
1728 .htotal = 480 + 2 + 41 + 2,
1730 .vsync_start = 272 + 2,
1731 .vsync_end = 272 + 2 + 10,
1732 .vtotal = 272 + 2 + 10 + 2,
1733 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1736 static const struct panel_desc edt_etm0430g0dh6 = {
1737 .modes = &edt_etm0430g0dh6_mode,
1744 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1745 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1746 .connector_type = DRM_MODE_CONNECTOR_DPI,
1749 static const struct drm_display_mode edt_et057090dhu_mode = {
1752 .hsync_start = 640 + 16,
1753 .hsync_end = 640 + 16 + 30,
1754 .htotal = 640 + 16 + 30 + 114,
1756 .vsync_start = 480 + 10,
1757 .vsync_end = 480 + 10 + 3,
1758 .vtotal = 480 + 10 + 3 + 32,
1759 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1762 static const struct panel_desc edt_et057090dhu = {
1763 .modes = &edt_et057090dhu_mode,
1770 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1771 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1772 .connector_type = DRM_MODE_CONNECTOR_DPI,
1775 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1778 .hsync_start = 800 + 40,
1779 .hsync_end = 800 + 40 + 128,
1780 .htotal = 800 + 40 + 128 + 88,
1782 .vsync_start = 480 + 10,
1783 .vsync_end = 480 + 10 + 2,
1784 .vtotal = 480 + 10 + 2 + 33,
1785 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1788 static const struct panel_desc edt_etm0700g0dh6 = {
1789 .modes = &edt_etm0700g0dh6_mode,
1796 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1797 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1798 .connector_type = DRM_MODE_CONNECTOR_DPI,
1801 static const struct panel_desc edt_etm0700g0bdh6 = {
1802 .modes = &edt_etm0700g0dh6_mode,
1809 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1810 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1811 .connector_type = DRM_MODE_CONNECTOR_DPI,
1814 static const struct display_timing edt_etml0700y5dha_timing = {
1815 .pixelclock = { 40800000, 51200000, 67200000 },
1816 .hactive = { 1024, 1024, 1024 },
1817 .hfront_porch = { 30, 106, 125 },
1818 .hback_porch = { 30, 106, 125 },
1819 .hsync_len = { 30, 108, 126 },
1820 .vactive = { 600, 600, 600 },
1821 .vfront_porch = { 3, 12, 67},
1822 .vback_porch = { 3, 12, 67 },
1823 .vsync_len = { 4, 11, 66 },
1824 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1825 DISPLAY_FLAGS_DE_HIGH,
1828 static const struct panel_desc edt_etml0700y5dha = {
1829 .timings = &edt_etml0700y5dha_timing,
1836 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1837 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1840 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
1844 .hsync_end = 640 + 16,
1845 .htotal = 640 + 16 + 30 + 114,
1847 .vsync_start = 480 + 10,
1848 .vsync_end = 480 + 10 + 3,
1849 .vtotal = 480 + 10 + 3 + 35,
1850 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
1853 static const struct panel_desc edt_etmv570g2dhu = {
1854 .modes = &edt_etmv570g2dhu_mode,
1861 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1862 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1863 .connector_type = DRM_MODE_CONNECTOR_DPI,
1866 static const struct display_timing eink_vb3300_kca_timing = {
1867 .pixelclock = { 40000000, 40000000, 40000000 },
1868 .hactive = { 334, 334, 334 },
1869 .hfront_porch = { 1, 1, 1 },
1870 .hback_porch = { 1, 1, 1 },
1871 .hsync_len = { 1, 1, 1 },
1872 .vactive = { 1405, 1405, 1405 },
1873 .vfront_porch = { 1, 1, 1 },
1874 .vback_porch = { 1, 1, 1 },
1875 .vsync_len = { 1, 1, 1 },
1876 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1877 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
1880 static const struct panel_desc eink_vb3300_kca = {
1881 .timings = &eink_vb3300_kca_timing,
1888 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1889 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1890 .connector_type = DRM_MODE_CONNECTOR_DPI,
1893 static const struct display_timing evervision_vgg804821_timing = {
1894 .pixelclock = { 27600000, 33300000, 50000000 },
1895 .hactive = { 800, 800, 800 },
1896 .hfront_porch = { 40, 66, 70 },
1897 .hback_porch = { 40, 67, 70 },
1898 .hsync_len = { 40, 67, 70 },
1899 .vactive = { 480, 480, 480 },
1900 .vfront_porch = { 6, 10, 10 },
1901 .vback_porch = { 7, 11, 11 },
1902 .vsync_len = { 7, 11, 11 },
1903 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1904 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1905 DISPLAY_FLAGS_SYNC_NEGEDGE,
1908 static const struct panel_desc evervision_vgg804821 = {
1909 .timings = &evervision_vgg804821_timing,
1916 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1917 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1920 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1923 .hsync_start = 800 + 168,
1924 .hsync_end = 800 + 168 + 64,
1925 .htotal = 800 + 168 + 64 + 88,
1927 .vsync_start = 480 + 37,
1928 .vsync_end = 480 + 37 + 2,
1929 .vtotal = 480 + 37 + 2 + 8,
1932 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1933 .modes = &foxlink_fl500wvr00_a0t_mode,
1940 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1943 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1947 .hsync_start = 320 + 44,
1948 .hsync_end = 320 + 44 + 16,
1949 .htotal = 320 + 44 + 16 + 20,
1951 .vsync_start = 240 + 2,
1952 .vsync_end = 240 + 2 + 6,
1953 .vtotal = 240 + 2 + 6 + 2,
1954 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1959 .hsync_start = 320 + 56,
1960 .hsync_end = 320 + 56 + 16,
1961 .htotal = 320 + 56 + 16 + 40,
1963 .vsync_start = 240 + 2,
1964 .vsync_end = 240 + 2 + 6,
1965 .vtotal = 240 + 2 + 6 + 2,
1966 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1970 static const struct panel_desc frida_frd350h54004 = {
1971 .modes = frida_frd350h54004_modes,
1972 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1978 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1979 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1980 .connector_type = DRM_MODE_CONNECTOR_DPI,
1983 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1986 .hsync_start = 800 + 20,
1987 .hsync_end = 800 + 20 + 24,
1988 .htotal = 800 + 20 + 24 + 20,
1990 .vsync_start = 1280 + 4,
1991 .vsync_end = 1280 + 4 + 8,
1992 .vtotal = 1280 + 4 + 8 + 4,
1993 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1996 static const struct panel_desc friendlyarm_hd702e = {
1997 .modes = &friendlyarm_hd702e_mode,
2005 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2008 .hsync_start = 480 + 5,
2009 .hsync_end = 480 + 5 + 1,
2010 .htotal = 480 + 5 + 1 + 40,
2012 .vsync_start = 272 + 8,
2013 .vsync_end = 272 + 8 + 1,
2014 .vtotal = 272 + 8 + 1 + 8,
2017 static const struct panel_desc giantplus_gpg482739qs5 = {
2018 .modes = &giantplus_gpg482739qs5_mode,
2025 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2028 static const struct display_timing giantplus_gpm940b0_timing = {
2029 .pixelclock = { 13500000, 27000000, 27500000 },
2030 .hactive = { 320, 320, 320 },
2031 .hfront_porch = { 14, 686, 718 },
2032 .hback_porch = { 50, 70, 255 },
2033 .hsync_len = { 1, 1, 1 },
2034 .vactive = { 240, 240, 240 },
2035 .vfront_porch = { 1, 1, 179 },
2036 .vback_porch = { 1, 21, 31 },
2037 .vsync_len = { 1, 1, 6 },
2038 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2041 static const struct panel_desc giantplus_gpm940b0 = {
2042 .timings = &giantplus_gpm940b0_timing,
2049 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2050 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2053 static const struct display_timing hannstar_hsd070pww1_timing = {
2054 .pixelclock = { 64300000, 71100000, 82000000 },
2055 .hactive = { 1280, 1280, 1280 },
2056 .hfront_porch = { 1, 1, 10 },
2057 .hback_porch = { 1, 1, 10 },
2059 * According to the data sheet, the minimum horizontal blanking interval
2060 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2061 * minimum working horizontal blanking interval to be 60 clocks.
2063 .hsync_len = { 58, 158, 661 },
2064 .vactive = { 800, 800, 800 },
2065 .vfront_porch = { 1, 1, 10 },
2066 .vback_porch = { 1, 1, 10 },
2067 .vsync_len = { 1, 21, 203 },
2068 .flags = DISPLAY_FLAGS_DE_HIGH,
2071 static const struct panel_desc hannstar_hsd070pww1 = {
2072 .timings = &hannstar_hsd070pww1_timing,
2079 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2080 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2083 static const struct display_timing hannstar_hsd100pxn1_timing = {
2084 .pixelclock = { 55000000, 65000000, 75000000 },
2085 .hactive = { 1024, 1024, 1024 },
2086 .hfront_porch = { 40, 40, 40 },
2087 .hback_porch = { 220, 220, 220 },
2088 .hsync_len = { 20, 60, 100 },
2089 .vactive = { 768, 768, 768 },
2090 .vfront_porch = { 7, 7, 7 },
2091 .vback_porch = { 21, 21, 21 },
2092 .vsync_len = { 10, 10, 10 },
2093 .flags = DISPLAY_FLAGS_DE_HIGH,
2096 static const struct panel_desc hannstar_hsd100pxn1 = {
2097 .timings = &hannstar_hsd100pxn1_timing,
2104 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2105 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2108 static const struct display_timing hannstar_hsd101pww2_timing = {
2109 .pixelclock = { 64300000, 71100000, 82000000 },
2110 .hactive = { 1280, 1280, 1280 },
2111 .hfront_porch = { 1, 1, 10 },
2112 .hback_porch = { 1, 1, 10 },
2113 .hsync_len = { 58, 158, 661 },
2114 .vactive = { 800, 800, 800 },
2115 .vfront_porch = { 1, 1, 10 },
2116 .vback_porch = { 1, 1, 10 },
2117 .vsync_len = { 1, 21, 203 },
2118 .flags = DISPLAY_FLAGS_DE_HIGH,
2121 static const struct panel_desc hannstar_hsd101pww2 = {
2122 .timings = &hannstar_hsd101pww2_timing,
2129 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2130 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2133 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2136 .hsync_start = 800 + 85,
2137 .hsync_end = 800 + 85 + 86,
2138 .htotal = 800 + 85 + 86 + 85,
2140 .vsync_start = 480 + 16,
2141 .vsync_end = 480 + 16 + 13,
2142 .vtotal = 480 + 16 + 13 + 16,
2145 static const struct panel_desc hitachi_tx23d38vm0caa = {
2146 .modes = &hitachi_tx23d38vm0caa_mode,
2159 static const struct drm_display_mode innolux_at043tn24_mode = {
2162 .hsync_start = 480 + 2,
2163 .hsync_end = 480 + 2 + 41,
2164 .htotal = 480 + 2 + 41 + 2,
2166 .vsync_start = 272 + 2,
2167 .vsync_end = 272 + 2 + 10,
2168 .vtotal = 272 + 2 + 10 + 2,
2169 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2172 static const struct panel_desc innolux_at043tn24 = {
2173 .modes = &innolux_at043tn24_mode,
2180 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2181 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2184 static const struct drm_display_mode innolux_at070tn92_mode = {
2187 .hsync_start = 800 + 210,
2188 .hsync_end = 800 + 210 + 20,
2189 .htotal = 800 + 210 + 20 + 46,
2191 .vsync_start = 480 + 22,
2192 .vsync_end = 480 + 22 + 10,
2193 .vtotal = 480 + 22 + 23 + 10,
2196 static const struct panel_desc innolux_at070tn92 = {
2197 .modes = &innolux_at070tn92_mode,
2203 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2206 static const struct display_timing innolux_g070ace_l01_timing = {
2207 .pixelclock = { 25200000, 35000000, 35700000 },
2208 .hactive = { 800, 800, 800 },
2209 .hfront_porch = { 30, 32, 87 },
2210 .hback_porch = { 30, 32, 87 },
2211 .hsync_len = { 1, 1, 1 },
2212 .vactive = { 480, 480, 480 },
2213 .vfront_porch = { 3, 3, 3 },
2214 .vback_porch = { 13, 13, 13 },
2215 .vsync_len = { 1, 1, 4 },
2216 .flags = DISPLAY_FLAGS_DE_HIGH,
2219 static const struct panel_desc innolux_g070ace_l01 = {
2220 .timings = &innolux_g070ace_l01_timing,
2233 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2234 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2235 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2238 static const struct display_timing innolux_g070y2_l01_timing = {
2239 .pixelclock = { 28000000, 29500000, 32000000 },
2240 .hactive = { 800, 800, 800 },
2241 .hfront_porch = { 61, 91, 141 },
2242 .hback_porch = { 60, 90, 140 },
2243 .hsync_len = { 12, 12, 12 },
2244 .vactive = { 480, 480, 480 },
2245 .vfront_porch = { 4, 9, 30 },
2246 .vback_porch = { 4, 8, 28 },
2247 .vsync_len = { 2, 2, 2 },
2248 .flags = DISPLAY_FLAGS_DE_HIGH,
2251 static const struct panel_desc innolux_g070y2_l01 = {
2252 .timings = &innolux_g070y2_l01_timing,
2265 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2266 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2267 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2270 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2273 .hsync_start = 800 + 210,
2274 .hsync_end = 800 + 210 + 20,
2275 .htotal = 800 + 210 + 20 + 46,
2277 .vsync_start = 480 + 22,
2278 .vsync_end = 480 + 22 + 10,
2279 .vtotal = 480 + 22 + 23 + 10,
2282 static const struct panel_desc innolux_g070y2_t02 = {
2283 .modes = &innolux_g070y2_t02_mode,
2290 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2291 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2292 .connector_type = DRM_MODE_CONNECTOR_DPI,
2295 static const struct display_timing innolux_g101ice_l01_timing = {
2296 .pixelclock = { 60400000, 71100000, 74700000 },
2297 .hactive = { 1280, 1280, 1280 },
2298 .hfront_porch = { 41, 80, 100 },
2299 .hback_porch = { 40, 79, 99 },
2300 .hsync_len = { 1, 1, 1 },
2301 .vactive = { 800, 800, 800 },
2302 .vfront_porch = { 5, 11, 14 },
2303 .vback_porch = { 4, 11, 14 },
2304 .vsync_len = { 1, 1, 1 },
2305 .flags = DISPLAY_FLAGS_DE_HIGH,
2308 static const struct panel_desc innolux_g101ice_l01 = {
2309 .timings = &innolux_g101ice_l01_timing,
2320 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2321 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2324 static const struct display_timing innolux_g121i1_l01_timing = {
2325 .pixelclock = { 67450000, 71000000, 74550000 },
2326 .hactive = { 1280, 1280, 1280 },
2327 .hfront_porch = { 40, 80, 160 },
2328 .hback_porch = { 39, 79, 159 },
2329 .hsync_len = { 1, 1, 1 },
2330 .vactive = { 800, 800, 800 },
2331 .vfront_porch = { 5, 11, 100 },
2332 .vback_porch = { 4, 11, 99 },
2333 .vsync_len = { 1, 1, 1 },
2336 static const struct panel_desc innolux_g121i1_l01 = {
2337 .timings = &innolux_g121i1_l01_timing,
2348 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2349 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2352 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2355 .hsync_start = 1024 + 0,
2356 .hsync_end = 1024 + 1,
2357 .htotal = 1024 + 0 + 1 + 320,
2359 .vsync_start = 768 + 38,
2360 .vsync_end = 768 + 38 + 1,
2361 .vtotal = 768 + 38 + 1 + 0,
2362 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2365 static const struct panel_desc innolux_g121x1_l03 = {
2366 .modes = &innolux_g121x1_l03_mode,
2380 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2383 .hsync_start = 1366 + 16,
2384 .hsync_end = 1366 + 16 + 34,
2385 .htotal = 1366 + 16 + 34 + 50,
2387 .vsync_start = 768 + 2,
2388 .vsync_end = 768 + 2 + 6,
2389 .vtotal = 768 + 2 + 6 + 12,
2392 static const struct panel_desc innolux_n156bge_l21 = {
2393 .modes = &innolux_n156bge_l21_mode,
2400 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2401 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2402 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2405 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2408 .hsync_start = 1024 + 128,
2409 .hsync_end = 1024 + 128 + 64,
2410 .htotal = 1024 + 128 + 64 + 128,
2412 .vsync_start = 600 + 16,
2413 .vsync_end = 600 + 16 + 4,
2414 .vtotal = 600 + 16 + 4 + 16,
2417 static const struct panel_desc innolux_zj070na_01p = {
2418 .modes = &innolux_zj070na_01p_mode,
2427 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2428 .pixelclock = { 5580000, 5850000, 6200000 },
2429 .hactive = { 320, 320, 320 },
2430 .hfront_porch = { 30, 30, 30 },
2431 .hback_porch = { 30, 30, 30 },
2432 .hsync_len = { 1, 5, 17 },
2433 .vactive = { 240, 240, 240 },
2434 .vfront_porch = { 6, 6, 6 },
2435 .vback_porch = { 5, 5, 5 },
2436 .vsync_len = { 1, 2, 11 },
2437 .flags = DISPLAY_FLAGS_DE_HIGH,
2440 static const struct panel_desc koe_tx14d24vm1bpa = {
2441 .timings = &koe_tx14d24vm1bpa_timing,
2450 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2451 .pixelclock = { 151820000, 156720000, 159780000 },
2452 .hactive = { 1920, 1920, 1920 },
2453 .hfront_porch = { 105, 130, 142 },
2454 .hback_porch = { 45, 70, 82 },
2455 .hsync_len = { 30, 30, 30 },
2456 .vactive = { 1200, 1200, 1200},
2457 .vfront_porch = { 3, 5, 10 },
2458 .vback_porch = { 2, 5, 10 },
2459 .vsync_len = { 5, 5, 5 },
2462 static const struct panel_desc koe_tx26d202vm0bwa = {
2463 .timings = &koe_tx26d202vm0bwa_timing,
2476 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2477 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2478 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2481 static const struct display_timing koe_tx31d200vm0baa_timing = {
2482 .pixelclock = { 39600000, 43200000, 48000000 },
2483 .hactive = { 1280, 1280, 1280 },
2484 .hfront_porch = { 16, 36, 56 },
2485 .hback_porch = { 16, 36, 56 },
2486 .hsync_len = { 8, 8, 8 },
2487 .vactive = { 480, 480, 480 },
2488 .vfront_porch = { 6, 21, 33 },
2489 .vback_porch = { 6, 21, 33 },
2490 .vsync_len = { 8, 8, 8 },
2491 .flags = DISPLAY_FLAGS_DE_HIGH,
2494 static const struct panel_desc koe_tx31d200vm0baa = {
2495 .timings = &koe_tx31d200vm0baa_timing,
2502 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2503 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2506 static const struct display_timing kyo_tcg121xglp_timing = {
2507 .pixelclock = { 52000000, 65000000, 71000000 },
2508 .hactive = { 1024, 1024, 1024 },
2509 .hfront_porch = { 2, 2, 2 },
2510 .hback_porch = { 2, 2, 2 },
2511 .hsync_len = { 86, 124, 244 },
2512 .vactive = { 768, 768, 768 },
2513 .vfront_porch = { 2, 2, 2 },
2514 .vback_porch = { 2, 2, 2 },
2515 .vsync_len = { 6, 34, 73 },
2516 .flags = DISPLAY_FLAGS_DE_HIGH,
2519 static const struct panel_desc kyo_tcg121xglp = {
2520 .timings = &kyo_tcg121xglp_timing,
2527 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2528 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2531 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2534 .hsync_start = 320 + 20,
2535 .hsync_end = 320 + 20 + 30,
2536 .htotal = 320 + 20 + 30 + 38,
2538 .vsync_start = 240 + 4,
2539 .vsync_end = 240 + 4 + 3,
2540 .vtotal = 240 + 4 + 3 + 15,
2543 static const struct panel_desc lemaker_bl035_rgb_002 = {
2544 .modes = &lemaker_bl035_rgb_002_mode,
2550 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2551 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2554 static const struct drm_display_mode lg_lb070wv8_mode = {
2557 .hsync_start = 800 + 88,
2558 .hsync_end = 800 + 88 + 80,
2559 .htotal = 800 + 88 + 80 + 88,
2561 .vsync_start = 480 + 10,
2562 .vsync_end = 480 + 10 + 25,
2563 .vtotal = 480 + 10 + 25 + 10,
2566 static const struct panel_desc lg_lb070wv8 = {
2567 .modes = &lg_lb070wv8_mode,
2574 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2575 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2578 static const struct display_timing logictechno_lt161010_2nh_timing = {
2579 .pixelclock = { 26400000, 33300000, 46800000 },
2580 .hactive = { 800, 800, 800 },
2581 .hfront_porch = { 16, 210, 354 },
2582 .hback_porch = { 46, 46, 46 },
2583 .hsync_len = { 1, 20, 40 },
2584 .vactive = { 480, 480, 480 },
2585 .vfront_porch = { 7, 22, 147 },
2586 .vback_porch = { 23, 23, 23 },
2587 .vsync_len = { 1, 10, 20 },
2588 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2589 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2590 DISPLAY_FLAGS_SYNC_POSEDGE,
2593 static const struct panel_desc logictechno_lt161010_2nh = {
2594 .timings = &logictechno_lt161010_2nh_timing,
2601 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2602 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2603 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2604 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2605 .connector_type = DRM_MODE_CONNECTOR_DPI,
2608 static const struct display_timing logictechno_lt170410_2whc_timing = {
2609 .pixelclock = { 68900000, 71100000, 73400000 },
2610 .hactive = { 1280, 1280, 1280 },
2611 .hfront_porch = { 23, 60, 71 },
2612 .hback_porch = { 23, 60, 71 },
2613 .hsync_len = { 15, 40, 47 },
2614 .vactive = { 800, 800, 800 },
2615 .vfront_porch = { 5, 7, 10 },
2616 .vback_porch = { 5, 7, 10 },
2617 .vsync_len = { 6, 9, 12 },
2618 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2619 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2620 DISPLAY_FLAGS_SYNC_POSEDGE,
2623 static const struct panel_desc logictechno_lt170410_2whc = {
2624 .timings = &logictechno_lt170410_2whc_timing,
2631 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2632 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2633 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2636 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2639 .hsync_start = 800 + 112,
2640 .hsync_end = 800 + 112 + 3,
2641 .htotal = 800 + 112 + 3 + 85,
2643 .vsync_start = 480 + 38,
2644 .vsync_end = 480 + 38 + 3,
2645 .vtotal = 480 + 38 + 3 + 29,
2646 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2649 static const struct panel_desc logictechno_lttd800480070_l2rt = {
2650 .modes = &logictechno_lttd800480070_l2rt_mode,
2663 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2664 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2665 .connector_type = DRM_MODE_CONNECTOR_DPI,
2668 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2671 .hsync_start = 800 + 154,
2672 .hsync_end = 800 + 154 + 3,
2673 .htotal = 800 + 154 + 3 + 43,
2675 .vsync_start = 480 + 47,
2676 .vsync_end = 480 + 47 + 3,
2677 .vtotal = 480 + 47 + 3 + 20,
2678 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2681 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2682 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
2695 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2696 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2697 .connector_type = DRM_MODE_CONNECTOR_DPI,
2700 static const struct drm_display_mode logicpd_type_28_mode = {
2703 .hsync_start = 480 + 3,
2704 .hsync_end = 480 + 3 + 42,
2705 .htotal = 480 + 3 + 42 + 2,
2708 .vsync_start = 272 + 2,
2709 .vsync_end = 272 + 2 + 11,
2710 .vtotal = 272 + 2 + 11 + 3,
2711 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2714 static const struct panel_desc logicpd_type_28 = {
2715 .modes = &logicpd_type_28_mode,
2728 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2729 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2730 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2731 .connector_type = DRM_MODE_CONNECTOR_DPI,
2734 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2737 .hsync_start = 800 + 0,
2738 .hsync_end = 800 + 1,
2739 .htotal = 800 + 0 + 1 + 160,
2741 .vsync_start = 480 + 0,
2742 .vsync_end = 480 + 48 + 1,
2743 .vtotal = 480 + 48 + 1 + 0,
2744 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2747 static const struct panel_desc mitsubishi_aa070mc01 = {
2748 .modes = &mitsubishi_aa070mc01_mode,
2761 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2762 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2763 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2766 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
2767 .pixelclock = { 29000000, 33000000, 38000000 },
2768 .hactive = { 800, 800, 800 },
2769 .hfront_porch = { 180, 210, 240 },
2770 .hback_porch = { 16, 16, 16 },
2771 .hsync_len = { 30, 30, 30 },
2772 .vactive = { 480, 480, 480 },
2773 .vfront_porch = { 12, 22, 32 },
2774 .vback_porch = { 10, 10, 10 },
2775 .vsync_len = { 13, 13, 13 },
2776 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2777 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2778 DISPLAY_FLAGS_SYNC_POSEDGE,
2781 static const struct panel_desc multi_inno_mi0700s4t_6 = {
2782 .timings = &multi_inno_mi0700s4t_6_timing,
2789 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2790 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2791 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2792 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2793 .connector_type = DRM_MODE_CONNECTOR_DPI,
2796 static const struct display_timing multi_inno_mi0800ft_9_timing = {
2797 .pixelclock = { 32000000, 40000000, 50000000 },
2798 .hactive = { 800, 800, 800 },
2799 .hfront_porch = { 16, 210, 354 },
2800 .hback_porch = { 6, 26, 45 },
2801 .hsync_len = { 1, 20, 40 },
2802 .vactive = { 600, 600, 600 },
2803 .vfront_porch = { 1, 12, 77 },
2804 .vback_porch = { 3, 13, 22 },
2805 .vsync_len = { 1, 10, 20 },
2806 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2807 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2808 DISPLAY_FLAGS_SYNC_POSEDGE,
2811 static const struct panel_desc multi_inno_mi0800ft_9 = {
2812 .timings = &multi_inno_mi0800ft_9_timing,
2819 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2820 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2821 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2822 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2823 .connector_type = DRM_MODE_CONNECTOR_DPI,
2826 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
2827 .pixelclock = { 68900000, 70000000, 73400000 },
2828 .hactive = { 1280, 1280, 1280 },
2829 .hfront_porch = { 30, 60, 71 },
2830 .hback_porch = { 30, 60, 71 },
2831 .hsync_len = { 10, 10, 48 },
2832 .vactive = { 800, 800, 800 },
2833 .vfront_porch = { 5, 10, 10 },
2834 .vback_porch = { 5, 10, 10 },
2835 .vsync_len = { 5, 6, 13 },
2836 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2837 DISPLAY_FLAGS_DE_HIGH,
2840 static const struct panel_desc multi_inno_mi1010ait_1cp = {
2841 .timings = &multi_inno_mi1010ait_1cp_timing,
2852 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2853 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2854 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2857 static const struct display_timing nec_nl12880bc20_05_timing = {
2858 .pixelclock = { 67000000, 71000000, 75000000 },
2859 .hactive = { 1280, 1280, 1280 },
2860 .hfront_porch = { 2, 30, 30 },
2861 .hback_porch = { 6, 100, 100 },
2862 .hsync_len = { 2, 30, 30 },
2863 .vactive = { 800, 800, 800 },
2864 .vfront_porch = { 5, 5, 5 },
2865 .vback_porch = { 11, 11, 11 },
2866 .vsync_len = { 7, 7, 7 },
2869 static const struct panel_desc nec_nl12880bc20_05 = {
2870 .timings = &nec_nl12880bc20_05_timing,
2881 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2882 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2885 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2888 .hsync_start = 480 + 2,
2889 .hsync_end = 480 + 2 + 41,
2890 .htotal = 480 + 2 + 41 + 2,
2892 .vsync_start = 272 + 2,
2893 .vsync_end = 272 + 2 + 4,
2894 .vtotal = 272 + 2 + 4 + 2,
2895 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2898 static const struct panel_desc nec_nl4827hc19_05b = {
2899 .modes = &nec_nl4827hc19_05b_mode,
2906 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2907 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2910 static const struct drm_display_mode netron_dy_e231732_mode = {
2913 .hsync_start = 1024 + 160,
2914 .hsync_end = 1024 + 160 + 70,
2915 .htotal = 1024 + 160 + 70 + 90,
2917 .vsync_start = 600 + 127,
2918 .vsync_end = 600 + 127 + 20,
2919 .vtotal = 600 + 127 + 20 + 3,
2922 static const struct panel_desc netron_dy_e231732 = {
2923 .modes = &netron_dy_e231732_mode,
2929 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2932 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2935 .hsync_start = 480 + 2,
2936 .hsync_end = 480 + 2 + 41,
2937 .htotal = 480 + 2 + 41 + 2,
2939 .vsync_start = 272 + 2,
2940 .vsync_end = 272 + 2 + 10,
2941 .vtotal = 272 + 2 + 10 + 2,
2942 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2945 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2946 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2953 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2954 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2955 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2956 .connector_type = DRM_MODE_CONNECTOR_DPI,
2959 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2960 .pixelclock = { 130000000, 148350000, 163000000 },
2961 .hactive = { 1920, 1920, 1920 },
2962 .hfront_porch = { 80, 100, 100 },
2963 .hback_porch = { 100, 120, 120 },
2964 .hsync_len = { 50, 60, 60 },
2965 .vactive = { 1080, 1080, 1080 },
2966 .vfront_porch = { 12, 30, 30 },
2967 .vback_porch = { 4, 10, 10 },
2968 .vsync_len = { 4, 5, 5 },
2971 static const struct panel_desc nlt_nl192108ac18_02d = {
2972 .timings = &nlt_nl192108ac18_02d_timing,
2982 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2983 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2986 static const struct drm_display_mode nvd_9128_mode = {
2989 .hsync_start = 800 + 130,
2990 .hsync_end = 800 + 130 + 98,
2991 .htotal = 800 + 0 + 130 + 98,
2993 .vsync_start = 480 + 10,
2994 .vsync_end = 480 + 10 + 50,
2995 .vtotal = 480 + 0 + 10 + 50,
2998 static const struct panel_desc nvd_9128 = {
2999 .modes = &nvd_9128_mode,
3006 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3007 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3010 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3011 .pixelclock = { 30000000, 30000000, 40000000 },
3012 .hactive = { 800, 800, 800 },
3013 .hfront_porch = { 40, 40, 40 },
3014 .hback_porch = { 40, 40, 40 },
3015 .hsync_len = { 1, 48, 48 },
3016 .vactive = { 480, 480, 480 },
3017 .vfront_porch = { 13, 13, 13 },
3018 .vback_porch = { 29, 29, 29 },
3019 .vsync_len = { 3, 3, 3 },
3020 .flags = DISPLAY_FLAGS_DE_HIGH,
3023 static const struct panel_desc okaya_rs800480t_7x0gp = {
3024 .timings = &okaya_rs800480t_7x0gp_timing,
3037 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3040 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3043 .hsync_start = 480 + 5,
3044 .hsync_end = 480 + 5 + 30,
3045 .htotal = 480 + 5 + 30 + 10,
3047 .vsync_start = 272 + 8,
3048 .vsync_end = 272 + 8 + 5,
3049 .vtotal = 272 + 8 + 5 + 3,
3052 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3053 .modes = &olimex_lcd_olinuxino_43ts_mode,
3059 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3063 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3064 * pixel clocks, but this is the timing that was being used in the Adafruit
3065 * installation instructions.
3067 static const struct drm_display_mode ontat_yx700wv03_mode = {
3077 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3082 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3084 static const struct panel_desc ontat_yx700wv03 = {
3085 .modes = &ontat_yx700wv03_mode,
3092 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3095 static const struct drm_display_mode ortustech_com37h3m_mode = {
3098 .hsync_start = 480 + 40,
3099 .hsync_end = 480 + 40 + 10,
3100 .htotal = 480 + 40 + 10 + 40,
3102 .vsync_start = 640 + 4,
3103 .vsync_end = 640 + 4 + 2,
3104 .vtotal = 640 + 4 + 2 + 4,
3105 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3108 static const struct panel_desc ortustech_com37h3m = {
3109 .modes = &ortustech_com37h3m_mode,
3113 .width = 56, /* 56.16mm */
3114 .height = 75, /* 74.88mm */
3116 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3117 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3118 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3121 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3124 .hsync_start = 480 + 10,
3125 .hsync_end = 480 + 10 + 10,
3126 .htotal = 480 + 10 + 10 + 15,
3128 .vsync_start = 800 + 3,
3129 .vsync_end = 800 + 3 + 3,
3130 .vtotal = 800 + 3 + 3 + 3,
3133 static const struct panel_desc ortustech_com43h4m85ulc = {
3134 .modes = &ortustech_com43h4m85ulc_mode,
3141 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3142 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3143 .connector_type = DRM_MODE_CONNECTOR_DPI,
3146 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3149 .hsync_start = 800 + 210,
3150 .hsync_end = 800 + 210 + 30,
3151 .htotal = 800 + 210 + 30 + 16,
3153 .vsync_start = 480 + 22,
3154 .vsync_end = 480 + 22 + 13,
3155 .vtotal = 480 + 22 + 13 + 10,
3156 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3159 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3160 .modes = &osddisplays_osd070t1718_19ts_mode,
3167 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3168 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3169 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3170 .connector_type = DRM_MODE_CONNECTOR_DPI,
3173 static const struct drm_display_mode pda_91_00156_a0_mode = {
3176 .hsync_start = 800 + 1,
3177 .hsync_end = 800 + 1 + 64,
3178 .htotal = 800 + 1 + 64 + 64,
3180 .vsync_start = 480 + 1,
3181 .vsync_end = 480 + 1 + 23,
3182 .vtotal = 480 + 1 + 23 + 22,
3185 static const struct panel_desc pda_91_00156_a0 = {
3186 .modes = &pda_91_00156_a0_mode,
3192 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3195 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3198 .hsync_start = 800 + 54,
3199 .hsync_end = 800 + 54 + 2,
3200 .htotal = 800 + 54 + 2 + 44,
3202 .vsync_start = 480 + 49,
3203 .vsync_end = 480 + 49 + 2,
3204 .vtotal = 480 + 49 + 2 + 22,
3207 static const struct panel_desc powertip_ph800480t013_idf02 = {
3208 .modes = &powertip_ph800480t013_idf02_mode,
3214 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3215 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3216 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3217 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3218 .connector_type = DRM_MODE_CONNECTOR_DPI,
3221 static const struct drm_display_mode qd43003c0_40_mode = {
3224 .hsync_start = 480 + 8,
3225 .hsync_end = 480 + 8 + 4,
3226 .htotal = 480 + 8 + 4 + 39,
3228 .vsync_start = 272 + 4,
3229 .vsync_end = 272 + 4 + 10,
3230 .vtotal = 272 + 4 + 10 + 2,
3233 static const struct panel_desc qd43003c0_40 = {
3234 .modes = &qd43003c0_40_mode,
3241 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3244 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3248 .hsync_start = 480 + 77,
3249 .hsync_end = 480 + 77 + 41,
3250 .htotal = 480 + 77 + 41 + 2,
3252 .vsync_start = 272 + 16,
3253 .vsync_end = 272 + 16 + 10,
3254 .vtotal = 272 + 16 + 10 + 2,
3255 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3260 .hsync_start = 480 + 17,
3261 .hsync_end = 480 + 17 + 41,
3262 .htotal = 480 + 17 + 41 + 2,
3264 .vsync_start = 272 + 116,
3265 .vsync_end = 272 + 116 + 10,
3266 .vtotal = 272 + 116 + 10 + 2,
3267 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3271 static const struct panel_desc qishenglong_gopher2b_lcd = {
3272 .modes = qishenglong_gopher2b_lcd_modes,
3273 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3279 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3280 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3281 .connector_type = DRM_MODE_CONNECTOR_DPI,
3284 static const struct display_timing rocktech_rk043fn48h_timing = {
3285 .pixelclock = { 6000000, 9000000, 12000000 },
3286 .hactive = { 480, 480, 480 },
3287 .hback_porch = { 8, 43, 43 },
3288 .hfront_porch = { 2, 8, 8 },
3289 .hsync_len = { 1, 1, 1 },
3290 .vactive = { 272, 272, 272 },
3291 .vback_porch = { 2, 12, 12 },
3292 .vfront_porch = { 1, 4, 4 },
3293 .vsync_len = { 1, 10, 10 },
3294 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
3295 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3298 static const struct panel_desc rocktech_rk043fn48h = {
3299 .timings = &rocktech_rk043fn48h_timing,
3306 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3307 .connector_type = DRM_MODE_CONNECTOR_DPI,
3310 static const struct display_timing rocktech_rk070er9427_timing = {
3311 .pixelclock = { 26400000, 33300000, 46800000 },
3312 .hactive = { 800, 800, 800 },
3313 .hfront_porch = { 16, 210, 354 },
3314 .hback_porch = { 46, 46, 46 },
3315 .hsync_len = { 1, 1, 1 },
3316 .vactive = { 480, 480, 480 },
3317 .vfront_porch = { 7, 22, 147 },
3318 .vback_porch = { 23, 23, 23 },
3319 .vsync_len = { 1, 1, 1 },
3320 .flags = DISPLAY_FLAGS_DE_HIGH,
3323 static const struct panel_desc rocktech_rk070er9427 = {
3324 .timings = &rocktech_rk070er9427_timing,
3337 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3340 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3343 .hsync_start = 1280 + 48,
3344 .hsync_end = 1280 + 48 + 32,
3345 .htotal = 1280 + 48 + 32 + 80,
3347 .vsync_start = 800 + 2,
3348 .vsync_end = 800 + 2 + 5,
3349 .vtotal = 800 + 2 + 5 + 16,
3352 static const struct panel_desc rocktech_rk101ii01d_ct = {
3353 .modes = &rocktech_rk101ii01d_ct_mode,
3364 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3365 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3366 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3369 static const struct display_timing samsung_ltl101al01_timing = {
3370 .pixelclock = { 66663000, 66663000, 66663000 },
3371 .hactive = { 1280, 1280, 1280 },
3372 .hfront_porch = { 18, 18, 18 },
3373 .hback_porch = { 36, 36, 36 },
3374 .hsync_len = { 16, 16, 16 },
3375 .vactive = { 800, 800, 800 },
3376 .vfront_porch = { 4, 4, 4 },
3377 .vback_porch = { 16, 16, 16 },
3378 .vsync_len = { 3, 3, 3 },
3379 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3382 static const struct panel_desc samsung_ltl101al01 = {
3383 .timings = &samsung_ltl101al01_timing,
3396 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3397 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3400 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3403 .hsync_start = 1024 + 24,
3404 .hsync_end = 1024 + 24 + 136,
3405 .htotal = 1024 + 24 + 136 + 160,
3407 .vsync_start = 600 + 3,
3408 .vsync_end = 600 + 3 + 6,
3409 .vtotal = 600 + 3 + 6 + 61,
3412 static const struct panel_desc samsung_ltn101nt05 = {
3413 .modes = &samsung_ltn101nt05_mode,
3420 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3421 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3422 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3425 static const struct display_timing satoz_sat050at40h12r2_timing = {
3426 .pixelclock = {33300000, 33300000, 50000000},
3427 .hactive = {800, 800, 800},
3428 .hfront_porch = {16, 210, 354},
3429 .hback_porch = {46, 46, 46},
3430 .hsync_len = {1, 1, 40},
3431 .vactive = {480, 480, 480},
3432 .vfront_porch = {7, 22, 147},
3433 .vback_porch = {23, 23, 23},
3434 .vsync_len = {1, 1, 20},
3437 static const struct panel_desc satoz_sat050at40h12r2 = {
3438 .timings = &satoz_sat050at40h12r2_timing,
3445 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3446 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3449 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3452 .hsync_start = 800 + 64,
3453 .hsync_end = 800 + 64 + 128,
3454 .htotal = 800 + 64 + 128 + 64,
3456 .vsync_start = 480 + 8,
3457 .vsync_end = 480 + 8 + 2,
3458 .vtotal = 480 + 8 + 2 + 35,
3459 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3462 static const struct panel_desc sharp_lq070y3dg3b = {
3463 .modes = &sharp_lq070y3dg3b_mode,
3467 .width = 152, /* 152.4mm */
3468 .height = 91, /* 91.4mm */
3470 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3471 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3472 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3475 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3478 .hsync_start = 240 + 16,
3479 .hsync_end = 240 + 16 + 7,
3480 .htotal = 240 + 16 + 7 + 5,
3482 .vsync_start = 320 + 9,
3483 .vsync_end = 320 + 9 + 1,
3484 .vtotal = 320 + 9 + 1 + 7,
3487 static const struct panel_desc sharp_lq035q7db03 = {
3488 .modes = &sharp_lq035q7db03_mode,
3495 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3498 static const struct display_timing sharp_lq101k1ly04_timing = {
3499 .pixelclock = { 60000000, 65000000, 80000000 },
3500 .hactive = { 1280, 1280, 1280 },
3501 .hfront_porch = { 20, 20, 20 },
3502 .hback_porch = { 20, 20, 20 },
3503 .hsync_len = { 10, 10, 10 },
3504 .vactive = { 800, 800, 800 },
3505 .vfront_porch = { 4, 4, 4 },
3506 .vback_porch = { 4, 4, 4 },
3507 .vsync_len = { 4, 4, 4 },
3508 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3511 static const struct panel_desc sharp_lq101k1ly04 = {
3512 .timings = &sharp_lq101k1ly04_timing,
3519 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3520 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3523 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3527 .hsync_start = 240 + 58,
3528 .hsync_end = 240 + 58 + 1,
3529 .htotal = 240 + 58 + 1 + 1,
3531 .vsync_start = 160 + 24,
3532 .vsync_end = 160 + 24 + 10,
3533 .vtotal = 160 + 24 + 10 + 6,
3534 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3539 .hsync_start = 240 + 8,
3540 .hsync_end = 240 + 8 + 1,
3541 .htotal = 240 + 8 + 1 + 1,
3543 .vsync_start = 160 + 24,
3544 .vsync_end = 160 + 24 + 10,
3545 .vtotal = 160 + 24 + 10 + 6,
3546 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3550 static const struct panel_desc sharp_ls020b1dd01d = {
3551 .modes = sharp_ls020b1dd01d_modes,
3552 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3558 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3559 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3560 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3561 | DRM_BUS_FLAG_SHARP_SIGNALS,
3564 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3567 .hsync_start = 800 + 1,
3568 .hsync_end = 800 + 1 + 64,
3569 .htotal = 800 + 1 + 64 + 64,
3571 .vsync_start = 480 + 1,
3572 .vsync_end = 480 + 1 + 23,
3573 .vtotal = 480 + 1 + 23 + 22,
3576 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3577 .modes = &shelly_sca07010_bfn_lnn_mode,
3583 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3586 static const struct drm_display_mode starry_kr070pe2t_mode = {
3589 .hsync_start = 800 + 209,
3590 .hsync_end = 800 + 209 + 1,
3591 .htotal = 800 + 209 + 1 + 45,
3593 .vsync_start = 480 + 22,
3594 .vsync_end = 480 + 22 + 1,
3595 .vtotal = 480 + 22 + 1 + 22,
3598 static const struct panel_desc starry_kr070pe2t = {
3599 .modes = &starry_kr070pe2t_mode,
3606 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3607 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3608 .connector_type = DRM_MODE_CONNECTOR_DPI,
3611 static const struct display_timing startek_kd070wvfpa_mode = {
3612 .pixelclock = { 25200000, 27200000, 30500000 },
3613 .hactive = { 800, 800, 800 },
3614 .hfront_porch = { 19, 44, 115 },
3615 .hback_porch = { 5, 16, 101 },
3616 .hsync_len = { 1, 2, 100 },
3617 .vactive = { 480, 480, 480 },
3618 .vfront_porch = { 5, 43, 67 },
3619 .vback_porch = { 5, 5, 67 },
3620 .vsync_len = { 1, 2, 66 },
3621 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3622 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3623 DISPLAY_FLAGS_SYNC_POSEDGE,
3626 static const struct panel_desc startek_kd070wvfpa = {
3627 .timings = &startek_kd070wvfpa_mode,
3639 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3640 .connector_type = DRM_MODE_CONNECTOR_DPI,
3641 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3642 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3643 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3646 static const struct display_timing tsd_tst043015cmhx_timing = {
3647 .pixelclock = { 5000000, 9000000, 12000000 },
3648 .hactive = { 480, 480, 480 },
3649 .hfront_porch = { 4, 5, 65 },
3650 .hback_porch = { 36, 40, 255 },
3651 .hsync_len = { 1, 1, 1 },
3652 .vactive = { 272, 272, 272 },
3653 .vfront_porch = { 2, 8, 97 },
3654 .vback_porch = { 3, 8, 31 },
3655 .vsync_len = { 1, 1, 1 },
3657 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3658 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3661 static const struct panel_desc tsd_tst043015cmhx = {
3662 .timings = &tsd_tst043015cmhx_timing,
3669 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3670 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3673 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3676 .hsync_start = 800 + 39,
3677 .hsync_end = 800 + 39 + 47,
3678 .htotal = 800 + 39 + 47 + 39,
3680 .vsync_start = 480 + 13,
3681 .vsync_end = 480 + 13 + 2,
3682 .vtotal = 480 + 13 + 2 + 29,
3685 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3686 .modes = &tfc_s9700rtwv43tr_01b_mode,
3693 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3694 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3697 static const struct display_timing tianma_tm070jdhg30_timing = {
3698 .pixelclock = { 62600000, 68200000, 78100000 },
3699 .hactive = { 1280, 1280, 1280 },
3700 .hfront_porch = { 15, 64, 159 },
3701 .hback_porch = { 5, 5, 5 },
3702 .hsync_len = { 1, 1, 256 },
3703 .vactive = { 800, 800, 800 },
3704 .vfront_porch = { 3, 40, 99 },
3705 .vback_porch = { 2, 2, 2 },
3706 .vsync_len = { 1, 1, 128 },
3707 .flags = DISPLAY_FLAGS_DE_HIGH,
3710 static const struct panel_desc tianma_tm070jdhg30 = {
3711 .timings = &tianma_tm070jdhg30_timing,
3718 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3719 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3722 static const struct panel_desc tianma_tm070jvhg33 = {
3723 .timings = &tianma_tm070jdhg30_timing,
3730 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3731 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3734 static const struct display_timing tianma_tm070rvhg71_timing = {
3735 .pixelclock = { 27700000, 29200000, 39600000 },
3736 .hactive = { 800, 800, 800 },
3737 .hfront_porch = { 12, 40, 212 },
3738 .hback_porch = { 88, 88, 88 },
3739 .hsync_len = { 1, 1, 40 },
3740 .vactive = { 480, 480, 480 },
3741 .vfront_porch = { 1, 13, 88 },
3742 .vback_porch = { 32, 32, 32 },
3743 .vsync_len = { 1, 1, 3 },
3744 .flags = DISPLAY_FLAGS_DE_HIGH,
3747 static const struct panel_desc tianma_tm070rvhg71 = {
3748 .timings = &tianma_tm070rvhg71_timing,
3755 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3756 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3759 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3763 .hsync_start = 320 + 50,
3764 .hsync_end = 320 + 50 + 6,
3765 .htotal = 320 + 50 + 6 + 38,
3767 .vsync_start = 240 + 3,
3768 .vsync_end = 240 + 3 + 1,
3769 .vtotal = 240 + 3 + 1 + 17,
3770 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3774 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3775 .modes = ti_nspire_cx_lcd_mode,
3782 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3783 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3786 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3790 .hsync_start = 320 + 6,
3791 .hsync_end = 320 + 6 + 6,
3792 .htotal = 320 + 6 + 6 + 6,
3794 .vsync_start = 240 + 0,
3795 .vsync_end = 240 + 0 + 1,
3796 .vtotal = 240 + 0 + 1 + 0,
3797 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3801 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3802 .modes = ti_nspire_classic_lcd_mode,
3804 /* The grayscale panel has 8 bit for the color .. Y (black) */
3810 /* This is the grayscale bus format */
3811 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3812 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3815 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3818 .hsync_start = 1280 + 192,
3819 .hsync_end = 1280 + 192 + 128,
3820 .htotal = 1280 + 192 + 128 + 64,
3822 .vsync_start = 768 + 20,
3823 .vsync_end = 768 + 20 + 7,
3824 .vtotal = 768 + 20 + 7 + 3,
3827 static const struct panel_desc toshiba_lt089ac29000 = {
3828 .modes = &toshiba_lt089ac29000_mode,
3834 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3835 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3836 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3839 static const struct drm_display_mode tpk_f07a_0102_mode = {
3842 .hsync_start = 800 + 40,
3843 .hsync_end = 800 + 40 + 128,
3844 .htotal = 800 + 40 + 128 + 88,
3846 .vsync_start = 480 + 10,
3847 .vsync_end = 480 + 10 + 2,
3848 .vtotal = 480 + 10 + 2 + 33,
3851 static const struct panel_desc tpk_f07a_0102 = {
3852 .modes = &tpk_f07a_0102_mode,
3858 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3861 static const struct drm_display_mode tpk_f10a_0102_mode = {
3864 .hsync_start = 1024 + 176,
3865 .hsync_end = 1024 + 176 + 5,
3866 .htotal = 1024 + 176 + 5 + 88,
3868 .vsync_start = 600 + 20,
3869 .vsync_end = 600 + 20 + 5,
3870 .vtotal = 600 + 20 + 5 + 25,
3873 static const struct panel_desc tpk_f10a_0102 = {
3874 .modes = &tpk_f10a_0102_mode,
3882 static const struct display_timing urt_umsh_8596md_timing = {
3883 .pixelclock = { 33260000, 33260000, 33260000 },
3884 .hactive = { 800, 800, 800 },
3885 .hfront_porch = { 41, 41, 41 },
3886 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3887 .hsync_len = { 71, 128, 128 },
3888 .vactive = { 480, 480, 480 },
3889 .vfront_porch = { 10, 10, 10 },
3890 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3891 .vsync_len = { 2, 2, 2 },
3892 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3893 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3896 static const struct panel_desc urt_umsh_8596md_lvds = {
3897 .timings = &urt_umsh_8596md_timing,
3904 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3905 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3908 static const struct panel_desc urt_umsh_8596md_parallel = {
3909 .timings = &urt_umsh_8596md_timing,
3916 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3919 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
3922 .hsync_start = 1024 + 160,
3923 .hsync_end = 1024 + 160 + 100,
3924 .htotal = 1024 + 160 + 100 + 60,
3926 .vsync_start = 600 + 12,
3927 .vsync_end = 600 + 12 + 10,
3928 .vtotal = 600 + 12 + 10 + 13,
3931 static const struct panel_desc vivax_tpc9150_panel = {
3932 .modes = &vivax_tpc9150_panel_mode,
3939 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3940 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3941 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3944 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3947 .hsync_start = 800 + 210,
3948 .hsync_end = 800 + 210 + 20,
3949 .htotal = 800 + 210 + 20 + 46,
3951 .vsync_start = 480 + 22,
3952 .vsync_end = 480 + 22 + 10,
3953 .vtotal = 480 + 22 + 10 + 23,
3954 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3957 static const struct panel_desc vl050_8048nt_c01 = {
3958 .modes = &vl050_8048nt_c01_mode,
3965 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3966 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3969 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3972 .hsync_start = 320 + 20,
3973 .hsync_end = 320 + 20 + 30,
3974 .htotal = 320 + 20 + 30 + 38,
3976 .vsync_start = 240 + 4,
3977 .vsync_end = 240 + 4 + 3,
3978 .vtotal = 240 + 4 + 3 + 15,
3979 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3982 static const struct panel_desc winstar_wf35ltiacd = {
3983 .modes = &winstar_wf35ltiacd_mode,
3990 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3993 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
3996 .hsync_start = 1024 + 100,
3997 .hsync_end = 1024 + 100 + 100,
3998 .htotal = 1024 + 100 + 100 + 120,
4000 .vsync_start = 600 + 10,
4001 .vsync_end = 600 + 10 + 10,
4002 .vtotal = 600 + 10 + 10 + 15,
4003 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4006 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4007 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4014 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4015 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4016 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4019 static const struct drm_display_mode arm_rtsm_mode[] = {
4023 .hsync_start = 1024 + 24,
4024 .hsync_end = 1024 + 24 + 136,
4025 .htotal = 1024 + 24 + 136 + 160,
4027 .vsync_start = 768 + 3,
4028 .vsync_end = 768 + 3 + 6,
4029 .vtotal = 768 + 3 + 6 + 29,
4030 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4034 static const struct panel_desc arm_rtsm = {
4035 .modes = arm_rtsm_mode,
4042 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4045 static const struct of_device_id platform_of_match[] = {
4047 .compatible = "ampire,am-1280800n3tzqw-t00h",
4048 .data = &ire_am_1280800n3tzqw_t00h,
4050 .compatible = "ampire,am-480272h3tmqw-t01h",
4051 .data = &ire_am_480272h3tmqw_t01h,
4053 .compatible = "ampire,am-800480l1tmqw-t00h",
4054 .data = &ire_am_800480l1tmqw_t00h,
4056 .compatible = "ampire,am800480r3tmqwa1h",
4057 .data = &ire_am800480r3tmqwa1h,
4059 .compatible = "ampire,am800600p5tmqw-tb8h",
4060 .data = &ire_am800600p5tmqwtb8h,
4062 .compatible = "arm,rtsm-display",
4065 .compatible = "armadeus,st0700-adapt",
4066 .data = &armadeus_st0700_adapt,
4068 .compatible = "auo,b101aw03",
4069 .data = &auo_b101aw03,
4071 .compatible = "auo,b101xtn01",
4072 .data = &auo_b101xtn01,
4074 .compatible = "auo,g070vvn01",
4075 .data = &auo_g070vvn01,
4077 .compatible = "auo,g101evn010",
4078 .data = &auo_g101evn010,
4080 .compatible = "auo,g104sn02",
4081 .data = &auo_g104sn02,
4083 .compatible = "auo,g121ean01",
4084 .data = &auo_g121ean01,
4086 .compatible = "auo,g133han01",
4087 .data = &auo_g133han01,
4089 .compatible = "auo,g156xtn01",
4090 .data = &auo_g156xtn01,
4092 .compatible = "auo,g185han01",
4093 .data = &auo_g185han01,
4095 .compatible = "auo,g190ean01",
4096 .data = &auo_g190ean01,
4098 .compatible = "auo,p320hvn03",
4099 .data = &auo_p320hvn03,
4101 .compatible = "auo,t215hvn01",
4102 .data = &auo_t215hvn01,
4104 .compatible = "avic,tm070ddh03",
4105 .data = &avic_tm070ddh03,
4107 .compatible = "bananapi,s070wv20-ct16",
4108 .data = &bananapi_s070wv20_ct16,
4110 .compatible = "boe,ev121wxm-n10-1850",
4111 .data = &boe_ev121wxm_n10_1850,
4113 .compatible = "boe,hv070wsa-100",
4114 .data = &boe_hv070wsa
4116 .compatible = "cdtech,s043wq26h-ct7",
4117 .data = &cdtech_s043wq26h_ct7,
4119 .compatible = "cdtech,s070pws19hp-fc21",
4120 .data = &cdtech_s070pws19hp_fc21,
4122 .compatible = "cdtech,s070swv29hg-dc44",
4123 .data = &cdtech_s070swv29hg_dc44,
4125 .compatible = "cdtech,s070wv95-ct16",
4126 .data = &cdtech_s070wv95_ct16,
4128 .compatible = "chefree,ch101olhlwh-002",
4129 .data = &chefree_ch101olhlwh_002,
4131 .compatible = "chunghwa,claa070wp03xg",
4132 .data = &chunghwa_claa070wp03xg,
4134 .compatible = "chunghwa,claa101wa01a",
4135 .data = &chunghwa_claa101wa01a
4137 .compatible = "chunghwa,claa101wb01",
4138 .data = &chunghwa_claa101wb01
4140 .compatible = "dataimage,fg040346dsswbg04",
4141 .data = &dataimage_fg040346dsswbg04,
4143 .compatible = "dataimage,fg1001l0dsswmg01",
4144 .data = &dataimage_fg1001l0dsswmg01,
4146 .compatible = "dataimage,scf0700c48ggu18",
4147 .data = &dataimage_scf0700c48ggu18,
4149 .compatible = "dlc,dlc0700yzg-1",
4150 .data = &dlc_dlc0700yzg_1,
4152 .compatible = "dlc,dlc1010gig",
4153 .data = &dlc_dlc1010gig,
4155 .compatible = "edt,et035012dm6",
4156 .data = &edt_et035012dm6,
4158 .compatible = "edt,etm0350g0dh6",
4159 .data = &edt_etm0350g0dh6,
4161 .compatible = "edt,etm043080dh6gp",
4162 .data = &edt_etm043080dh6gp,
4164 .compatible = "edt,etm0430g0dh6",
4165 .data = &edt_etm0430g0dh6,
4167 .compatible = "edt,et057090dhu",
4168 .data = &edt_et057090dhu,
4170 .compatible = "edt,et070080dh6",
4171 .data = &edt_etm0700g0dh6,
4173 .compatible = "edt,etm0700g0dh6",
4174 .data = &edt_etm0700g0dh6,
4176 .compatible = "edt,etm0700g0bdh6",
4177 .data = &edt_etm0700g0bdh6,
4179 .compatible = "edt,etm0700g0edh6",
4180 .data = &edt_etm0700g0bdh6,
4182 .compatible = "edt,etml0700y5dha",
4183 .data = &edt_etml0700y5dha,
4185 .compatible = "edt,etmv570g2dhu",
4186 .data = &edt_etmv570g2dhu,
4188 .compatible = "eink,vb3300-kca",
4189 .data = &eink_vb3300_kca,
4191 .compatible = "evervision,vgg804821",
4192 .data = &evervision_vgg804821,
4194 .compatible = "foxlink,fl500wvr00-a0t",
4195 .data = &foxlink_fl500wvr00_a0t,
4197 .compatible = "frida,frd350h54004",
4198 .data = &frida_frd350h54004,
4200 .compatible = "friendlyarm,hd702e",
4201 .data = &friendlyarm_hd702e,
4203 .compatible = "giantplus,gpg482739qs5",
4204 .data = &giantplus_gpg482739qs5
4206 .compatible = "giantplus,gpm940b0",
4207 .data = &giantplus_gpm940b0,
4209 .compatible = "hannstar,hsd070pww1",
4210 .data = &hannstar_hsd070pww1,
4212 .compatible = "hannstar,hsd100pxn1",
4213 .data = &hannstar_hsd100pxn1,
4215 .compatible = "hannstar,hsd101pww2",
4216 .data = &hannstar_hsd101pww2,
4218 .compatible = "hit,tx23d38vm0caa",
4219 .data = &hitachi_tx23d38vm0caa
4221 .compatible = "innolux,at043tn24",
4222 .data = &innolux_at043tn24,
4224 .compatible = "innolux,at070tn92",
4225 .data = &innolux_at070tn92,
4227 .compatible = "innolux,g070ace-l01",
4228 .data = &innolux_g070ace_l01,
4230 .compatible = "innolux,g070y2-l01",
4231 .data = &innolux_g070y2_l01,
4233 .compatible = "innolux,g070y2-t02",
4234 .data = &innolux_g070y2_t02,
4236 .compatible = "innolux,g101ice-l01",
4237 .data = &innolux_g101ice_l01
4239 .compatible = "innolux,g121i1-l01",
4240 .data = &innolux_g121i1_l01
4242 .compatible = "innolux,g121x1-l03",
4243 .data = &innolux_g121x1_l03,
4245 .compatible = "innolux,n156bge-l21",
4246 .data = &innolux_n156bge_l21,
4248 .compatible = "innolux,zj070na-01p",
4249 .data = &innolux_zj070na_01p,
4251 .compatible = "koe,tx14d24vm1bpa",
4252 .data = &koe_tx14d24vm1bpa,
4254 .compatible = "koe,tx26d202vm0bwa",
4255 .data = &koe_tx26d202vm0bwa,
4257 .compatible = "koe,tx31d200vm0baa",
4258 .data = &koe_tx31d200vm0baa,
4260 .compatible = "kyo,tcg121xglp",
4261 .data = &kyo_tcg121xglp,
4263 .compatible = "lemaker,bl035-rgb-002",
4264 .data = &lemaker_bl035_rgb_002,
4266 .compatible = "lg,lb070wv8",
4267 .data = &lg_lb070wv8,
4269 .compatible = "logicpd,type28",
4270 .data = &logicpd_type_28,
4272 .compatible = "logictechno,lt161010-2nhc",
4273 .data = &logictechno_lt161010_2nh,
4275 .compatible = "logictechno,lt161010-2nhr",
4276 .data = &logictechno_lt161010_2nh,
4278 .compatible = "logictechno,lt170410-2whc",
4279 .data = &logictechno_lt170410_2whc,
4281 .compatible = "logictechno,lttd800480070-l2rt",
4282 .data = &logictechno_lttd800480070_l2rt,
4284 .compatible = "logictechno,lttd800480070-l6wh-rt",
4285 .data = &logictechno_lttd800480070_l6wh_rt,
4287 .compatible = "mitsubishi,aa070mc01-ca1",
4288 .data = &mitsubishi_aa070mc01,
4290 .compatible = "multi-inno,mi0700s4t-6",
4291 .data = &multi_inno_mi0700s4t_6,
4293 .compatible = "multi-inno,mi0800ft-9",
4294 .data = &multi_inno_mi0800ft_9,
4296 .compatible = "multi-inno,mi1010ait-1cp",
4297 .data = &multi_inno_mi1010ait_1cp,
4299 .compatible = "nec,nl12880bc20-05",
4300 .data = &nec_nl12880bc20_05,
4302 .compatible = "nec,nl4827hc19-05b",
4303 .data = &nec_nl4827hc19_05b,
4305 .compatible = "netron-dy,e231732",
4306 .data = &netron_dy_e231732,
4308 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4309 .data = &newhaven_nhd_43_480272ef_atxl,
4311 .compatible = "nlt,nl192108ac18-02d",
4312 .data = &nlt_nl192108ac18_02d,
4314 .compatible = "nvd,9128",
4317 .compatible = "okaya,rs800480t-7x0gp",
4318 .data = &okaya_rs800480t_7x0gp,
4320 .compatible = "olimex,lcd-olinuxino-43-ts",
4321 .data = &olimex_lcd_olinuxino_43ts,
4323 .compatible = "ontat,yx700wv03",
4324 .data = &ontat_yx700wv03,
4326 .compatible = "ortustech,com37h3m05dtc",
4327 .data = &ortustech_com37h3m,
4329 .compatible = "ortustech,com37h3m99dtc",
4330 .data = &ortustech_com37h3m,
4332 .compatible = "ortustech,com43h4m85ulc",
4333 .data = &ortustech_com43h4m85ulc,
4335 .compatible = "osddisplays,osd070t1718-19ts",
4336 .data = &osddisplays_osd070t1718_19ts,
4338 .compatible = "pda,91-00156-a0",
4339 .data = &pda_91_00156_a0,
4341 .compatible = "powertip,ph800480t013-idf02",
4342 .data = &powertip_ph800480t013_idf02,
4344 .compatible = "qiaodian,qd43003c0-40",
4345 .data = &qd43003c0_40,
4347 .compatible = "qishenglong,gopher2b-lcd",
4348 .data = &qishenglong_gopher2b_lcd,
4350 .compatible = "rocktech,rk043fn48h",
4351 .data = &rocktech_rk043fn48h,
4353 .compatible = "rocktech,rk070er9427",
4354 .data = &rocktech_rk070er9427,
4356 .compatible = "rocktech,rk101ii01d-ct",
4357 .data = &rocktech_rk101ii01d_ct,
4359 .compatible = "samsung,ltl101al01",
4360 .data = &samsung_ltl101al01,
4362 .compatible = "samsung,ltn101nt05",
4363 .data = &samsung_ltn101nt05,
4365 .compatible = "satoz,sat050at40h12r2",
4366 .data = &satoz_sat050at40h12r2,
4368 .compatible = "sharp,lq035q7db03",
4369 .data = &sharp_lq035q7db03,
4371 .compatible = "sharp,lq070y3dg3b",
4372 .data = &sharp_lq070y3dg3b,
4374 .compatible = "sharp,lq101k1ly04",
4375 .data = &sharp_lq101k1ly04,
4377 .compatible = "sharp,ls020b1dd01d",
4378 .data = &sharp_ls020b1dd01d,
4380 .compatible = "shelly,sca07010-bfn-lnn",
4381 .data = &shelly_sca07010_bfn_lnn,
4383 .compatible = "starry,kr070pe2t",
4384 .data = &starry_kr070pe2t,
4386 .compatible = "startek,kd070wvfpa",
4387 .data = &startek_kd070wvfpa,
4389 .compatible = "team-source-display,tst043015cmhx",
4390 .data = &tsd_tst043015cmhx,
4392 .compatible = "tfc,s9700rtwv43tr-01b",
4393 .data = &tfc_s9700rtwv43tr_01b,
4395 .compatible = "tianma,tm070jdhg30",
4396 .data = &tianma_tm070jdhg30,
4398 .compatible = "tianma,tm070jvhg33",
4399 .data = &tianma_tm070jvhg33,
4401 .compatible = "tianma,tm070rvhg71",
4402 .data = &tianma_tm070rvhg71,
4404 .compatible = "ti,nspire-cx-lcd-panel",
4405 .data = &ti_nspire_cx_lcd_panel,
4407 .compatible = "ti,nspire-classic-lcd-panel",
4408 .data = &ti_nspire_classic_lcd_panel,
4410 .compatible = "toshiba,lt089ac29000",
4411 .data = &toshiba_lt089ac29000,
4413 .compatible = "tpk,f07a-0102",
4414 .data = &tpk_f07a_0102,
4416 .compatible = "tpk,f10a-0102",
4417 .data = &tpk_f10a_0102,
4419 .compatible = "urt,umsh-8596md-t",
4420 .data = &urt_umsh_8596md_parallel,
4422 .compatible = "urt,umsh-8596md-1t",
4423 .data = &urt_umsh_8596md_parallel,
4425 .compatible = "urt,umsh-8596md-7t",
4426 .data = &urt_umsh_8596md_parallel,
4428 .compatible = "urt,umsh-8596md-11t",
4429 .data = &urt_umsh_8596md_lvds,
4431 .compatible = "urt,umsh-8596md-19t",
4432 .data = &urt_umsh_8596md_lvds,
4434 .compatible = "urt,umsh-8596md-20t",
4435 .data = &urt_umsh_8596md_parallel,
4437 .compatible = "vivax,tpc9150-panel",
4438 .data = &vivax_tpc9150_panel,
4440 .compatible = "vxt,vl050-8048nt-c01",
4441 .data = &vl050_8048nt_c01,
4443 .compatible = "winstar,wf35ltiacd",
4444 .data = &winstar_wf35ltiacd,
4446 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4447 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4449 /* Must be the last entry */
4450 .compatible = "panel-dpi",
4456 MODULE_DEVICE_TABLE(of, platform_of_match);
4458 static int panel_simple_platform_probe(struct platform_device *pdev)
4460 const struct of_device_id *id;
4462 id = of_match_node(platform_of_match, pdev->dev.of_node);
4466 return panel_simple_probe(&pdev->dev, id->data);
4469 static int panel_simple_platform_remove(struct platform_device *pdev)
4471 panel_simple_remove(&pdev->dev);
4476 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4478 panel_simple_shutdown(&pdev->dev);
4481 static const struct dev_pm_ops panel_simple_pm_ops = {
4482 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4483 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4484 pm_runtime_force_resume)
4487 static struct platform_driver panel_simple_platform_driver = {
4489 .name = "panel-simple",
4490 .of_match_table = platform_of_match,
4491 .pm = &panel_simple_pm_ops,
4493 .probe = panel_simple_platform_probe,
4494 .remove = panel_simple_platform_remove,
4495 .shutdown = panel_simple_platform_shutdown,
4498 struct panel_desc_dsi {
4499 struct panel_desc desc;
4501 unsigned long flags;
4502 enum mipi_dsi_pixel_format format;
4506 static const struct drm_display_mode auo_b080uan01_mode = {
4509 .hsync_start = 1200 + 62,
4510 .hsync_end = 1200 + 62 + 4,
4511 .htotal = 1200 + 62 + 4 + 62,
4513 .vsync_start = 1920 + 9,
4514 .vsync_end = 1920 + 9 + 2,
4515 .vtotal = 1920 + 9 + 2 + 8,
4518 static const struct panel_desc_dsi auo_b080uan01 = {
4520 .modes = &auo_b080uan01_mode,
4527 .connector_type = DRM_MODE_CONNECTOR_DSI,
4529 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4530 .format = MIPI_DSI_FMT_RGB888,
4534 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4537 .hsync_start = 1200 + 120,
4538 .hsync_end = 1200 + 120 + 20,
4539 .htotal = 1200 + 120 + 20 + 21,
4541 .vsync_start = 1920 + 21,
4542 .vsync_end = 1920 + 21 + 3,
4543 .vtotal = 1920 + 21 + 3 + 18,
4544 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4547 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4549 .modes = &boe_tv080wum_nl0_mode,
4555 .connector_type = DRM_MODE_CONNECTOR_DSI,
4557 .flags = MIPI_DSI_MODE_VIDEO |
4558 MIPI_DSI_MODE_VIDEO_BURST |
4559 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4560 .format = MIPI_DSI_FMT_RGB888,
4564 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4567 .hsync_start = 800 + 32,
4568 .hsync_end = 800 + 32 + 1,
4569 .htotal = 800 + 32 + 1 + 57,
4571 .vsync_start = 1280 + 28,
4572 .vsync_end = 1280 + 28 + 1,
4573 .vtotal = 1280 + 28 + 1 + 14,
4576 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4578 .modes = &lg_ld070wx3_sl01_mode,
4585 .connector_type = DRM_MODE_CONNECTOR_DSI,
4587 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4588 .format = MIPI_DSI_FMT_RGB888,
4592 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4595 .hsync_start = 720 + 12,
4596 .hsync_end = 720 + 12 + 4,
4597 .htotal = 720 + 12 + 4 + 112,
4599 .vsync_start = 1280 + 8,
4600 .vsync_end = 1280 + 8 + 4,
4601 .vtotal = 1280 + 8 + 4 + 12,
4604 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4606 .modes = &lg_lh500wx1_sd03_mode,
4613 .connector_type = DRM_MODE_CONNECTOR_DSI,
4615 .flags = MIPI_DSI_MODE_VIDEO,
4616 .format = MIPI_DSI_FMT_RGB888,
4620 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4623 .hsync_start = 1920 + 154,
4624 .hsync_end = 1920 + 154 + 16,
4625 .htotal = 1920 + 154 + 16 + 32,
4627 .vsync_start = 1200 + 17,
4628 .vsync_end = 1200 + 17 + 2,
4629 .vtotal = 1200 + 17 + 2 + 16,
4632 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4634 .modes = &panasonic_vvx10f004b00_mode,
4641 .connector_type = DRM_MODE_CONNECTOR_DSI,
4643 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4644 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4645 .format = MIPI_DSI_FMT_RGB888,
4649 static const struct drm_display_mode lg_acx467akm_7_mode = {
4652 .hsync_start = 1080 + 2,
4653 .hsync_end = 1080 + 2 + 2,
4654 .htotal = 1080 + 2 + 2 + 2,
4656 .vsync_start = 1920 + 2,
4657 .vsync_end = 1920 + 2 + 2,
4658 .vtotal = 1920 + 2 + 2 + 2,
4661 static const struct panel_desc_dsi lg_acx467akm_7 = {
4663 .modes = &lg_acx467akm_7_mode,
4670 .connector_type = DRM_MODE_CONNECTOR_DSI,
4673 .format = MIPI_DSI_FMT_RGB888,
4677 static const struct drm_display_mode osd101t2045_53ts_mode = {
4680 .hsync_start = 1920 + 112,
4681 .hsync_end = 1920 + 112 + 16,
4682 .htotal = 1920 + 112 + 16 + 32,
4684 .vsync_start = 1200 + 16,
4685 .vsync_end = 1200 + 16 + 2,
4686 .vtotal = 1200 + 16 + 2 + 16,
4687 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4690 static const struct panel_desc_dsi osd101t2045_53ts = {
4692 .modes = &osd101t2045_53ts_mode,
4699 .connector_type = DRM_MODE_CONNECTOR_DSI,
4701 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4702 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4703 MIPI_DSI_MODE_NO_EOT_PACKET,
4704 .format = MIPI_DSI_FMT_RGB888,
4708 static const struct of_device_id dsi_of_match[] = {
4710 .compatible = "auo,b080uan01",
4711 .data = &auo_b080uan01
4713 .compatible = "boe,tv080wum-nl0",
4714 .data = &boe_tv080wum_nl0
4716 .compatible = "lg,ld070wx3-sl01",
4717 .data = &lg_ld070wx3_sl01
4719 .compatible = "lg,lh500wx1-sd03",
4720 .data = &lg_lh500wx1_sd03
4722 .compatible = "panasonic,vvx10f004b00",
4723 .data = &panasonic_vvx10f004b00
4725 .compatible = "lg,acx467akm-7",
4726 .data = &lg_acx467akm_7
4728 .compatible = "osddisplays,osd101t2045-53ts",
4729 .data = &osd101t2045_53ts
4734 MODULE_DEVICE_TABLE(of, dsi_of_match);
4736 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4738 const struct panel_desc_dsi *desc;
4739 const struct of_device_id *id;
4742 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4748 err = panel_simple_probe(&dsi->dev, &desc->desc);
4752 dsi->mode_flags = desc->flags;
4753 dsi->format = desc->format;
4754 dsi->lanes = desc->lanes;
4756 err = mipi_dsi_attach(dsi);
4758 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
4760 drm_panel_remove(&panel->base);
4766 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4770 err = mipi_dsi_detach(dsi);
4772 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4774 panel_simple_remove(&dsi->dev);
4777 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4779 panel_simple_shutdown(&dsi->dev);
4782 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4784 .name = "panel-simple-dsi",
4785 .of_match_table = dsi_of_match,
4786 .pm = &panel_simple_pm_ops,
4788 .probe = panel_simple_dsi_probe,
4789 .remove = panel_simple_dsi_remove,
4790 .shutdown = panel_simple_dsi_shutdown,
4793 static int __init panel_simple_init(void)
4797 err = platform_driver_register(&panel_simple_platform_driver);
4801 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4802 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4804 goto err_did_platform_register;
4809 err_did_platform_register:
4810 platform_driver_unregister(&panel_simple_platform_driver);
4814 module_init(panel_simple_init);
4816 static void __exit panel_simple_exit(void)
4818 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4819 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4821 platform_driver_unregister(&panel_simple_platform_driver);
4823 module_exit(panel_simple_exit);
4825 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4826 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4827 MODULE_LICENSE("GPL and additional rights");