2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
60 const struct display_timing *timings;
61 unsigned int num_timings;
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
89 unsigned int hpd_absent_delay;
92 unsigned int unprepare;
100 struct panel_simple {
101 struct drm_panel base;
106 const struct panel_desc *desc;
108 struct regulator *supply;
109 struct i2c_adapter *ddc;
111 struct gpio_desc *enable_gpio;
112 struct gpio_desc *hpd_gpio;
114 struct drm_display_mode override_mode;
116 enum drm_panel_orientation orientation;
119 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
121 return container_of(panel, struct panel_simple, base);
124 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
125 struct drm_connector *connector)
127 struct drm_display_mode *mode;
128 unsigned int i, num = 0;
130 for (i = 0; i < panel->desc->num_timings; i++) {
131 const struct display_timing *dt = &panel->desc->timings[i];
134 videomode_from_timing(dt, &vm);
135 mode = drm_mode_create(connector->dev);
137 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
138 dt->hactive.typ, dt->vactive.typ);
142 drm_display_mode_from_videomode(&vm, mode);
144 mode->type |= DRM_MODE_TYPE_DRIVER;
146 if (panel->desc->num_timings == 1)
147 mode->type |= DRM_MODE_TYPE_PREFERRED;
149 drm_mode_probed_add(connector, mode);
156 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
157 struct drm_connector *connector)
159 struct drm_display_mode *mode;
160 unsigned int i, num = 0;
162 for (i = 0; i < panel->desc->num_modes; i++) {
163 const struct drm_display_mode *m = &panel->desc->modes[i];
165 mode = drm_mode_duplicate(connector->dev, m);
167 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
168 m->hdisplay, m->vdisplay,
169 drm_mode_vrefresh(m));
173 mode->type |= DRM_MODE_TYPE_DRIVER;
175 if (panel->desc->num_modes == 1)
176 mode->type |= DRM_MODE_TYPE_PREFERRED;
178 drm_mode_set_name(mode);
180 drm_mode_probed_add(connector, mode);
187 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
188 struct drm_connector *connector)
190 struct drm_display_mode *mode;
191 bool has_override = panel->override_mode.type;
192 unsigned int num = 0;
198 mode = drm_mode_duplicate(connector->dev,
199 &panel->override_mode);
201 drm_mode_probed_add(connector, mode);
204 dev_err(panel->base.dev, "failed to add override mode\n");
208 /* Only add timings if override was not there or failed to validate */
209 if (num == 0 && panel->desc->num_timings)
210 num = panel_simple_get_timings_modes(panel, connector);
213 * Only add fixed modes if timings/override added no mode.
215 * We should only ever have either the display timings specified
216 * or a fixed mode. Anything else is rather bogus.
218 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
220 num = panel_simple_get_display_modes(panel, connector);
222 connector->display_info.bpc = panel->desc->bpc;
223 connector->display_info.width_mm = panel->desc->size.width;
224 connector->display_info.height_mm = panel->desc->size.height;
225 if (panel->desc->bus_format)
226 drm_display_info_set_bus_formats(&connector->display_info,
227 &panel->desc->bus_format, 1);
228 connector->display_info.bus_flags = panel->desc->bus_flags;
233 static int panel_simple_disable(struct drm_panel *panel)
235 struct panel_simple *p = to_panel_simple(panel);
240 if (p->desc->delay.disable)
241 msleep(p->desc->delay.disable);
248 static int panel_simple_unprepare(struct drm_panel *panel)
250 struct panel_simple *p = to_panel_simple(panel);
255 gpiod_set_value_cansleep(p->enable_gpio, 0);
257 regulator_disable(p->supply);
259 if (p->desc->delay.unprepare)
260 msleep(p->desc->delay.unprepare);
267 static int panel_simple_get_hpd_gpio(struct device *dev,
268 struct panel_simple *p, bool from_probe)
272 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
273 if (IS_ERR(p->hpd_gpio)) {
274 err = PTR_ERR(p->hpd_gpio);
277 * If we're called from probe we won't consider '-EPROBE_DEFER'
278 * to be an error--we'll leave the error code in "hpd_gpio".
279 * When we try to use it we'll try again. This allows for
280 * circular dependencies where the component providing the
281 * hpd gpio needs the panel to init before probing.
283 if (err != -EPROBE_DEFER || !from_probe) {
284 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
292 static int panel_simple_prepare(struct drm_panel *panel)
294 struct panel_simple *p = to_panel_simple(panel);
302 err = regulator_enable(p->supply);
304 dev_err(panel->dev, "failed to enable supply: %d\n", err);
308 gpiod_set_value_cansleep(p->enable_gpio, 1);
310 delay = p->desc->delay.prepare;
312 delay += p->desc->delay.hpd_absent_delay;
317 if (IS_ERR(p->hpd_gpio)) {
318 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
323 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
324 hpd_asserted, hpd_asserted,
326 if (hpd_asserted < 0)
331 "error waiting for hpd GPIO: %d\n", err);
341 static int panel_simple_enable(struct drm_panel *panel)
343 struct panel_simple *p = to_panel_simple(panel);
348 if (p->desc->delay.enable)
349 msleep(p->desc->delay.enable);
356 static int panel_simple_get_modes(struct drm_panel *panel,
357 struct drm_connector *connector)
359 struct panel_simple *p = to_panel_simple(panel);
362 /* probe EDID if a DDC bus is available */
364 struct edid *edid = drm_get_edid(connector, p->ddc);
366 drm_connector_update_edid_property(connector, edid);
368 num += drm_add_edid_modes(connector, edid);
373 /* add hard-coded panel modes */
374 num += panel_simple_get_non_edid_modes(p, connector);
376 /* set up connector's "panel orientation" property */
377 drm_connector_set_panel_orientation(connector, p->orientation);
382 static int panel_simple_get_timings(struct drm_panel *panel,
383 unsigned int num_timings,
384 struct display_timing *timings)
386 struct panel_simple *p = to_panel_simple(panel);
389 if (p->desc->num_timings < num_timings)
390 num_timings = p->desc->num_timings;
393 for (i = 0; i < num_timings; i++)
394 timings[i] = p->desc->timings[i];
396 return p->desc->num_timings;
399 static const struct drm_panel_funcs panel_simple_funcs = {
400 .disable = panel_simple_disable,
401 .unprepare = panel_simple_unprepare,
402 .prepare = panel_simple_prepare,
403 .enable = panel_simple_enable,
404 .get_modes = panel_simple_get_modes,
405 .get_timings = panel_simple_get_timings,
408 static struct panel_desc panel_dpi;
410 static int panel_dpi_probe(struct device *dev,
411 struct panel_simple *panel)
413 struct display_timing *timing;
414 const struct device_node *np;
415 struct panel_desc *desc;
416 unsigned int bus_flags;
421 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
425 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
429 ret = of_get_display_timing(np, "panel-timing", timing);
431 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
436 desc->timings = timing;
437 desc->num_timings = 1;
439 of_property_read_u32(np, "width-mm", &desc->size.width);
440 of_property_read_u32(np, "height-mm", &desc->size.height);
442 /* Extract bus_flags from display_timing */
444 vm.flags = timing->flags;
445 drm_bus_flags_from_videomode(&vm, &bus_flags);
446 desc->bus_flags = bus_flags;
448 /* We do not know the connector for the DT node, so guess it */
449 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
456 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
457 (to_check->field.typ >= bounds->field.min && \
458 to_check->field.typ <= bounds->field.max)
459 static void panel_simple_parse_panel_timing_node(struct device *dev,
460 struct panel_simple *panel,
461 const struct display_timing *ot)
463 const struct panel_desc *desc = panel->desc;
467 if (WARN_ON(desc->num_modes)) {
468 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
471 if (WARN_ON(!desc->num_timings)) {
472 dev_err(dev, "Reject override mode: no timings specified\n");
476 for (i = 0; i < panel->desc->num_timings; i++) {
477 const struct display_timing *dt = &panel->desc->timings[i];
479 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
482 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
483 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
484 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
485 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
486 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
489 if (ot->flags != dt->flags)
492 videomode_from_timing(ot, &vm);
493 drm_display_mode_from_videomode(&vm, &panel->override_mode);
494 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
495 DRM_MODE_TYPE_PREFERRED;
499 if (WARN_ON(!panel->override_mode.type))
500 dev_err(dev, "Reject override mode: No display_timing found\n");
503 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
505 struct panel_simple *panel;
506 struct display_timing dt;
507 struct device_node *ddc;
512 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
516 panel->enabled = false;
517 panel->prepared = false;
520 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
521 if (!panel->no_hpd) {
522 err = panel_simple_get_hpd_gpio(dev, panel, true);
527 panel->supply = devm_regulator_get(dev, "power");
528 if (IS_ERR(panel->supply))
529 return PTR_ERR(panel->supply);
531 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
533 if (IS_ERR(panel->enable_gpio)) {
534 err = PTR_ERR(panel->enable_gpio);
535 if (err != -EPROBE_DEFER)
536 dev_err(dev, "failed to request GPIO: %d\n", err);
540 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
542 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
546 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
548 panel->ddc = of_find_i2c_adapter_by_node(ddc);
552 return -EPROBE_DEFER;
555 if (desc == &panel_dpi) {
556 /* Handle the generic panel-dpi binding */
557 err = panel_dpi_probe(dev, panel);
561 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
562 panel_simple_parse_panel_timing_node(dev, panel, &dt);
565 connector_type = desc->connector_type;
566 /* Catch common mistakes for panels. */
567 switch (connector_type) {
569 dev_warn(dev, "Specify missing connector_type\n");
570 connector_type = DRM_MODE_CONNECTOR_DPI;
572 case DRM_MODE_CONNECTOR_LVDS:
573 WARN_ON(desc->bus_flags &
574 ~(DRM_BUS_FLAG_DE_LOW |
575 DRM_BUS_FLAG_DE_HIGH |
576 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
577 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
578 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
579 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
580 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
581 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
583 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
584 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
587 case DRM_MODE_CONNECTOR_eDP:
588 if (desc->bus_format == 0)
589 dev_warn(dev, "Specify missing bus_format\n");
590 if (desc->bpc != 6 && desc->bpc != 8)
591 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
593 case DRM_MODE_CONNECTOR_DSI:
594 if (desc->bpc != 6 && desc->bpc != 8)
595 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
597 case DRM_MODE_CONNECTOR_DPI:
598 bus_flags = DRM_BUS_FLAG_DE_LOW |
599 DRM_BUS_FLAG_DE_HIGH |
600 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
601 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
602 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
603 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
604 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
605 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
606 if (desc->bus_flags & ~bus_flags)
607 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
608 if (!(desc->bus_flags & bus_flags))
609 dev_warn(dev, "Specify missing bus_flags\n");
610 if (desc->bus_format == 0)
611 dev_warn(dev, "Specify missing bus_format\n");
612 if (desc->bpc != 6 && desc->bpc != 8)
613 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
616 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
617 connector_type = DRM_MODE_CONNECTOR_DPI;
621 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
623 err = drm_panel_of_backlight(&panel->base);
627 drm_panel_add(&panel->base);
629 dev_set_drvdata(dev, panel);
635 put_device(&panel->ddc->dev);
640 static int panel_simple_remove(struct device *dev)
642 struct panel_simple *panel = dev_get_drvdata(dev);
644 drm_panel_remove(&panel->base);
645 drm_panel_disable(&panel->base);
646 drm_panel_unprepare(&panel->base);
649 put_device(&panel->ddc->dev);
654 static void panel_simple_shutdown(struct device *dev)
656 struct panel_simple *panel = dev_get_drvdata(dev);
658 drm_panel_disable(&panel->base);
659 drm_panel_unprepare(&panel->base);
662 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
665 .hsync_start = 1280 + 40,
666 .hsync_end = 1280 + 40 + 80,
667 .htotal = 1280 + 40 + 80 + 40,
669 .vsync_start = 800 + 3,
670 .vsync_end = 800 + 3 + 10,
671 .vtotal = 800 + 3 + 10 + 10,
672 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
675 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
676 .modes = &ire_am_1280800n3tzqw_t00h_mode,
683 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
684 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
685 .connector_type = DRM_MODE_CONNECTOR_LVDS,
688 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
691 .hsync_start = 480 + 2,
692 .hsync_end = 480 + 2 + 41,
693 .htotal = 480 + 2 + 41 + 2,
695 .vsync_start = 272 + 2,
696 .vsync_end = 272 + 2 + 10,
697 .vtotal = 272 + 2 + 10 + 2,
698 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
701 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
702 .modes = &ire_am_480272h3tmqw_t01h_mode,
709 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
712 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
715 .hsync_start = 800 + 0,
716 .hsync_end = 800 + 0 + 255,
717 .htotal = 800 + 0 + 255 + 0,
719 .vsync_start = 480 + 2,
720 .vsync_end = 480 + 2 + 45,
721 .vtotal = 480 + 2 + 45 + 0,
722 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
725 static const struct panel_desc ampire_am800480r3tmqwa1h = {
726 .modes = &ire_am800480r3tmqwa1h_mode,
733 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
736 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
737 .pixelclock = { 26400000, 33300000, 46800000 },
738 .hactive = { 800, 800, 800 },
739 .hfront_porch = { 16, 210, 354 },
740 .hback_porch = { 45, 36, 6 },
741 .hsync_len = { 1, 10, 40 },
742 .vactive = { 480, 480, 480 },
743 .vfront_porch = { 7, 22, 147 },
744 .vback_porch = { 22, 13, 3 },
745 .vsync_len = { 1, 10, 20 },
746 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
747 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
750 static const struct panel_desc armadeus_st0700_adapt = {
751 .timings = &santek_st0700i5y_rbslw_f_timing,
758 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
759 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
762 static const struct drm_display_mode auo_b101aw03_mode = {
765 .hsync_start = 1024 + 156,
766 .hsync_end = 1024 + 156 + 8,
767 .htotal = 1024 + 156 + 8 + 156,
769 .vsync_start = 600 + 16,
770 .vsync_end = 600 + 16 + 6,
771 .vtotal = 600 + 16 + 6 + 16,
774 static const struct panel_desc auo_b101aw03 = {
775 .modes = &auo_b101aw03_mode,
782 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
783 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
784 .connector_type = DRM_MODE_CONNECTOR_LVDS,
787 static const struct display_timing auo_b101ean01_timing = {
788 .pixelclock = { 65300000, 72500000, 75000000 },
789 .hactive = { 1280, 1280, 1280 },
790 .hfront_porch = { 18, 119, 119 },
791 .hback_porch = { 21, 21, 21 },
792 .hsync_len = { 32, 32, 32 },
793 .vactive = { 800, 800, 800 },
794 .vfront_porch = { 4, 4, 4 },
795 .vback_porch = { 8, 8, 8 },
796 .vsync_len = { 18, 20, 20 },
799 static const struct panel_desc auo_b101ean01 = {
800 .timings = &auo_b101ean01_timing,
809 static const struct drm_display_mode auo_b101xtn01_mode = {
812 .hsync_start = 1366 + 20,
813 .hsync_end = 1366 + 20 + 70,
814 .htotal = 1366 + 20 + 70,
816 .vsync_start = 768 + 14,
817 .vsync_end = 768 + 14 + 42,
818 .vtotal = 768 + 14 + 42,
819 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
822 static const struct panel_desc auo_b101xtn01 = {
823 .modes = &auo_b101xtn01_mode,
832 static const struct drm_display_mode auo_b116xak01_mode = {
835 .hsync_start = 1366 + 48,
836 .hsync_end = 1366 + 48 + 32,
837 .htotal = 1366 + 48 + 32 + 10,
839 .vsync_start = 768 + 4,
840 .vsync_end = 768 + 4 + 6,
841 .vtotal = 768 + 4 + 6 + 15,
842 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
845 static const struct panel_desc auo_b116xak01 = {
846 .modes = &auo_b116xak01_mode,
854 .hpd_absent_delay = 200,
856 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
857 .connector_type = DRM_MODE_CONNECTOR_eDP,
860 static const struct drm_display_mode auo_b116xw03_mode = {
863 .hsync_start = 1366 + 40,
864 .hsync_end = 1366 + 40 + 40,
865 .htotal = 1366 + 40 + 40 + 32,
867 .vsync_start = 768 + 10,
868 .vsync_end = 768 + 10 + 12,
869 .vtotal = 768 + 10 + 12 + 6,
870 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
873 static const struct panel_desc auo_b116xw03 = {
874 .modes = &auo_b116xw03_mode,
884 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
885 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
886 .connector_type = DRM_MODE_CONNECTOR_eDP,
889 static const struct drm_display_mode auo_b133xtn01_mode = {
892 .hsync_start = 1366 + 48,
893 .hsync_end = 1366 + 48 + 32,
894 .htotal = 1366 + 48 + 32 + 20,
896 .vsync_start = 768 + 3,
897 .vsync_end = 768 + 3 + 6,
898 .vtotal = 768 + 3 + 6 + 13,
901 static const struct panel_desc auo_b133xtn01 = {
902 .modes = &auo_b133xtn01_mode,
911 static const struct drm_display_mode auo_b133htn01_mode = {
914 .hsync_start = 1920 + 172,
915 .hsync_end = 1920 + 172 + 80,
916 .htotal = 1920 + 172 + 80 + 60,
918 .vsync_start = 1080 + 25,
919 .vsync_end = 1080 + 25 + 10,
920 .vtotal = 1080 + 25 + 10 + 10,
923 static const struct panel_desc auo_b133htn01 = {
924 .modes = &auo_b133htn01_mode,
938 static const struct display_timing auo_g070vvn01_timings = {
939 .pixelclock = { 33300000, 34209000, 45000000 },
940 .hactive = { 800, 800, 800 },
941 .hfront_porch = { 20, 40, 200 },
942 .hback_porch = { 87, 40, 1 },
943 .hsync_len = { 1, 48, 87 },
944 .vactive = { 480, 480, 480 },
945 .vfront_porch = { 5, 13, 200 },
946 .vback_porch = { 31, 31, 29 },
947 .vsync_len = { 1, 1, 3 },
950 static const struct panel_desc auo_g070vvn01 = {
951 .timings = &auo_g070vvn01_timings,
966 static const struct drm_display_mode auo_g101evn010_mode = {
969 .hsync_start = 1280 + 82,
970 .hsync_end = 1280 + 82 + 2,
971 .htotal = 1280 + 82 + 2 + 84,
973 .vsync_start = 800 + 8,
974 .vsync_end = 800 + 8 + 2,
975 .vtotal = 800 + 8 + 2 + 6,
978 static const struct panel_desc auo_g101evn010 = {
979 .modes = &auo_g101evn010_mode,
986 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
987 .connector_type = DRM_MODE_CONNECTOR_LVDS,
990 static const struct drm_display_mode auo_g104sn02_mode = {
993 .hsync_start = 800 + 40,
994 .hsync_end = 800 + 40 + 216,
995 .htotal = 800 + 40 + 216 + 128,
997 .vsync_start = 600 + 10,
998 .vsync_end = 600 + 10 + 35,
999 .vtotal = 600 + 10 + 35 + 2,
1002 static const struct panel_desc auo_g104sn02 = {
1003 .modes = &auo_g104sn02_mode,
1012 static const struct drm_display_mode auo_g121ean01_mode = {
1015 .hsync_start = 1280 + 58,
1016 .hsync_end = 1280 + 58 + 8,
1017 .htotal = 1280 + 58 + 8 + 70,
1019 .vsync_start = 800 + 6,
1020 .vsync_end = 800 + 6 + 4,
1021 .vtotal = 800 + 6 + 4 + 10,
1024 static const struct panel_desc auo_g121ean01 = {
1025 .modes = &auo_g121ean01_mode,
1032 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1033 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1036 static const struct display_timing auo_g133han01_timings = {
1037 .pixelclock = { 134000000, 141200000, 149000000 },
1038 .hactive = { 1920, 1920, 1920 },
1039 .hfront_porch = { 39, 58, 77 },
1040 .hback_porch = { 59, 88, 117 },
1041 .hsync_len = { 28, 42, 56 },
1042 .vactive = { 1080, 1080, 1080 },
1043 .vfront_porch = { 3, 8, 11 },
1044 .vback_porch = { 5, 14, 19 },
1045 .vsync_len = { 4, 14, 19 },
1048 static const struct panel_desc auo_g133han01 = {
1049 .timings = &auo_g133han01_timings,
1062 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1063 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1066 static const struct drm_display_mode auo_g156xtn01_mode = {
1069 .hsync_start = 1366 + 33,
1070 .hsync_end = 1366 + 33 + 67,
1073 .vsync_start = 768 + 4,
1074 .vsync_end = 768 + 4 + 4,
1078 static const struct panel_desc auo_g156xtn01 = {
1079 .modes = &auo_g156xtn01_mode,
1086 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1087 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1090 static const struct display_timing auo_g185han01_timings = {
1091 .pixelclock = { 120000000, 144000000, 175000000 },
1092 .hactive = { 1920, 1920, 1920 },
1093 .hfront_porch = { 36, 120, 148 },
1094 .hback_porch = { 24, 88, 108 },
1095 .hsync_len = { 20, 48, 64 },
1096 .vactive = { 1080, 1080, 1080 },
1097 .vfront_porch = { 6, 10, 40 },
1098 .vback_porch = { 2, 5, 20 },
1099 .vsync_len = { 2, 5, 20 },
1102 static const struct panel_desc auo_g185han01 = {
1103 .timings = &auo_g185han01_timings,
1116 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1117 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1120 static const struct display_timing auo_g190ean01_timings = {
1121 .pixelclock = { 90000000, 108000000, 135000000 },
1122 .hactive = { 1280, 1280, 1280 },
1123 .hfront_porch = { 126, 184, 1266 },
1124 .hback_porch = { 84, 122, 844 },
1125 .hsync_len = { 70, 102, 704 },
1126 .vactive = { 1024, 1024, 1024 },
1127 .vfront_porch = { 4, 26, 76 },
1128 .vback_porch = { 2, 8, 25 },
1129 .vsync_len = { 2, 8, 25 },
1132 static const struct panel_desc auo_g190ean01 = {
1133 .timings = &auo_g190ean01_timings,
1146 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1147 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1150 static const struct display_timing auo_p320hvn03_timings = {
1151 .pixelclock = { 106000000, 148500000, 164000000 },
1152 .hactive = { 1920, 1920, 1920 },
1153 .hfront_porch = { 25, 50, 130 },
1154 .hback_porch = { 25, 50, 130 },
1155 .hsync_len = { 20, 40, 105 },
1156 .vactive = { 1080, 1080, 1080 },
1157 .vfront_porch = { 8, 17, 150 },
1158 .vback_porch = { 8, 17, 150 },
1159 .vsync_len = { 4, 11, 100 },
1162 static const struct panel_desc auo_p320hvn03 = {
1163 .timings = &auo_p320hvn03_timings,
1175 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1176 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1179 static const struct drm_display_mode auo_t215hvn01_mode = {
1182 .hsync_start = 1920 + 88,
1183 .hsync_end = 1920 + 88 + 44,
1184 .htotal = 1920 + 88 + 44 + 148,
1186 .vsync_start = 1080 + 4,
1187 .vsync_end = 1080 + 4 + 5,
1188 .vtotal = 1080 + 4 + 5 + 36,
1191 static const struct panel_desc auo_t215hvn01 = {
1192 .modes = &auo_t215hvn01_mode,
1205 static const struct drm_display_mode avic_tm070ddh03_mode = {
1208 .hsync_start = 1024 + 160,
1209 .hsync_end = 1024 + 160 + 4,
1210 .htotal = 1024 + 160 + 4 + 156,
1212 .vsync_start = 600 + 17,
1213 .vsync_end = 600 + 17 + 1,
1214 .vtotal = 600 + 17 + 1 + 17,
1217 static const struct panel_desc avic_tm070ddh03 = {
1218 .modes = &avic_tm070ddh03_mode,
1232 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1235 .hsync_start = 800 + 40,
1236 .hsync_end = 800 + 40 + 48,
1237 .htotal = 800 + 40 + 48 + 40,
1239 .vsync_start = 480 + 13,
1240 .vsync_end = 480 + 13 + 3,
1241 .vtotal = 480 + 13 + 3 + 29,
1244 static const struct panel_desc bananapi_s070wv20_ct16 = {
1245 .modes = &bananapi_s070wv20_ct16_mode,
1254 static const struct drm_display_mode boe_hv070wsa_mode = {
1257 .hsync_start = 1024 + 30,
1258 .hsync_end = 1024 + 30 + 30,
1259 .htotal = 1024 + 30 + 30 + 30,
1261 .vsync_start = 600 + 10,
1262 .vsync_end = 600 + 10 + 10,
1263 .vtotal = 600 + 10 + 10 + 10,
1266 static const struct panel_desc boe_hv070wsa = {
1267 .modes = &boe_hv070wsa_mode,
1274 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1275 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1276 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1279 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1283 .hsync_start = 1280 + 48,
1284 .hsync_end = 1280 + 48 + 32,
1285 .htotal = 1280 + 48 + 32 + 80,
1287 .vsync_start = 800 + 3,
1288 .vsync_end = 800 + 3 + 5,
1289 .vtotal = 800 + 3 + 5 + 24,
1294 .hsync_start = 1280 + 48,
1295 .hsync_end = 1280 + 48 + 32,
1296 .htotal = 1280 + 48 + 32 + 80,
1298 .vsync_start = 800 + 3,
1299 .vsync_end = 800 + 3 + 5,
1300 .vtotal = 800 + 3 + 5 + 24,
1304 static const struct panel_desc boe_nv101wxmn51 = {
1305 .modes = boe_nv101wxmn51_modes,
1306 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1319 /* Also used for boe_nv133fhm_n62 */
1320 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1323 .hsync_start = 1920 + 48,
1324 .hsync_end = 1920 + 48 + 32,
1325 .htotal = 1920 + 48 + 32 + 200,
1327 .vsync_start = 1080 + 3,
1328 .vsync_end = 1080 + 3 + 6,
1329 .vtotal = 1080 + 3 + 6 + 31,
1332 /* Also used for boe_nv133fhm_n62 */
1333 static const struct panel_desc boe_nv133fhm_n61 = {
1334 .modes = &boe_nv133fhm_n61_modes,
1343 * When power is first given to the panel there's a short
1344 * spike on the HPD line. It was explained that this spike
1345 * was until the TCON data download was complete. On
1346 * one system this was measured at 8 ms. We'll put 15 ms
1347 * in the prepare delay just to be safe and take it away
1348 * from the hpd_absent_delay (which would otherwise be 200 ms)
1349 * to handle this. That means:
1350 * - If HPD isn't hooked up you still have 200 ms delay.
1351 * - If HPD is hooked up we won't try to look at it for the
1355 .hpd_absent_delay = 185,
1359 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1360 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1361 .connector_type = DRM_MODE_CONNECTOR_eDP,
1364 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1368 .hsync_start = 1920 + 48,
1369 .hsync_end = 1920 + 48 + 32,
1372 .vsync_start = 1080 + 3,
1373 .vsync_end = 1080 + 3 + 5,
1378 static const struct panel_desc boe_nv140fhmn49 = {
1379 .modes = boe_nv140fhmn49_modes,
1380 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1391 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1392 .connector_type = DRM_MODE_CONNECTOR_eDP,
1395 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1398 .hsync_start = 480 + 5,
1399 .hsync_end = 480 + 5 + 5,
1400 .htotal = 480 + 5 + 5 + 40,
1402 .vsync_start = 272 + 8,
1403 .vsync_end = 272 + 8 + 8,
1404 .vtotal = 272 + 8 + 8 + 8,
1405 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1408 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1409 .modes = &cdtech_s043wq26h_ct7_mode,
1416 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1419 /* S070PWS19HP-FC21 2017/04/22 */
1420 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1423 .hsync_start = 1024 + 160,
1424 .hsync_end = 1024 + 160 + 20,
1425 .htotal = 1024 + 160 + 20 + 140,
1427 .vsync_start = 600 + 12,
1428 .vsync_end = 600 + 12 + 3,
1429 .vtotal = 600 + 12 + 3 + 20,
1430 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1433 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1434 .modes = &cdtech_s070pws19hp_fc21_mode,
1441 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1442 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1443 .connector_type = DRM_MODE_CONNECTOR_DPI,
1446 /* S070SWV29HG-DC44 2017/09/21 */
1447 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1450 .hsync_start = 800 + 210,
1451 .hsync_end = 800 + 210 + 2,
1452 .htotal = 800 + 210 + 2 + 44,
1454 .vsync_start = 480 + 22,
1455 .vsync_end = 480 + 22 + 2,
1456 .vtotal = 480 + 22 + 2 + 21,
1457 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1460 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1461 .modes = &cdtech_s070swv29hg_dc44_mode,
1468 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1469 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1470 .connector_type = DRM_MODE_CONNECTOR_DPI,
1473 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1476 .hsync_start = 800 + 40,
1477 .hsync_end = 800 + 40 + 40,
1478 .htotal = 800 + 40 + 40 + 48,
1480 .vsync_start = 480 + 29,
1481 .vsync_end = 480 + 29 + 13,
1482 .vtotal = 480 + 29 + 13 + 3,
1483 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1486 static const struct panel_desc cdtech_s070wv95_ct16 = {
1487 .modes = &cdtech_s070wv95_ct16_mode,
1496 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1497 .pixelclock = { 68900000, 71100000, 73400000 },
1498 .hactive = { 1280, 1280, 1280 },
1499 .hfront_porch = { 65, 80, 95 },
1500 .hback_porch = { 64, 79, 94 },
1501 .hsync_len = { 1, 1, 1 },
1502 .vactive = { 800, 800, 800 },
1503 .vfront_porch = { 7, 11, 14 },
1504 .vback_porch = { 7, 11, 14 },
1505 .vsync_len = { 1, 1, 1 },
1506 .flags = DISPLAY_FLAGS_DE_HIGH,
1509 static const struct panel_desc chefree_ch101olhlwh_002 = {
1510 .timings = &chefree_ch101olhlwh_002_timing,
1521 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1522 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1523 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1526 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1529 .hsync_start = 800 + 49,
1530 .hsync_end = 800 + 49 + 33,
1531 .htotal = 800 + 49 + 33 + 17,
1533 .vsync_start = 1280 + 1,
1534 .vsync_end = 1280 + 1 + 7,
1535 .vtotal = 1280 + 1 + 7 + 15,
1536 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1539 static const struct panel_desc chunghwa_claa070wp03xg = {
1540 .modes = &chunghwa_claa070wp03xg_mode,
1547 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1548 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1549 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1552 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1555 .hsync_start = 1366 + 58,
1556 .hsync_end = 1366 + 58 + 58,
1557 .htotal = 1366 + 58 + 58 + 58,
1559 .vsync_start = 768 + 4,
1560 .vsync_end = 768 + 4 + 4,
1561 .vtotal = 768 + 4 + 4 + 4,
1564 static const struct panel_desc chunghwa_claa101wa01a = {
1565 .modes = &chunghwa_claa101wa01a_mode,
1572 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1573 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1574 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1577 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1580 .hsync_start = 1366 + 48,
1581 .hsync_end = 1366 + 48 + 32,
1582 .htotal = 1366 + 48 + 32 + 20,
1584 .vsync_start = 768 + 16,
1585 .vsync_end = 768 + 16 + 8,
1586 .vtotal = 768 + 16 + 8 + 16,
1589 static const struct panel_desc chunghwa_claa101wb01 = {
1590 .modes = &chunghwa_claa101wb01_mode,
1597 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1598 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1599 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1602 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1605 .hsync_start = 800 + 40,
1606 .hsync_end = 800 + 40 + 128,
1607 .htotal = 800 + 40 + 128 + 88,
1609 .vsync_start = 480 + 10,
1610 .vsync_end = 480 + 10 + 2,
1611 .vtotal = 480 + 10 + 2 + 33,
1612 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1615 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1616 .modes = &dataimage_scf0700c48ggu18_mode,
1623 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1624 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1627 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1628 .pixelclock = { 45000000, 51200000, 57000000 },
1629 .hactive = { 1024, 1024, 1024 },
1630 .hfront_porch = { 100, 106, 113 },
1631 .hback_porch = { 100, 106, 113 },
1632 .hsync_len = { 100, 108, 114 },
1633 .vactive = { 600, 600, 600 },
1634 .vfront_porch = { 8, 11, 15 },
1635 .vback_porch = { 8, 11, 15 },
1636 .vsync_len = { 9, 13, 15 },
1637 .flags = DISPLAY_FLAGS_DE_HIGH,
1640 static const struct panel_desc dlc_dlc0700yzg_1 = {
1641 .timings = &dlc_dlc0700yzg_1_timing,
1653 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1654 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1657 static const struct display_timing dlc_dlc1010gig_timing = {
1658 .pixelclock = { 68900000, 71100000, 73400000 },
1659 .hactive = { 1280, 1280, 1280 },
1660 .hfront_porch = { 43, 53, 63 },
1661 .hback_porch = { 43, 53, 63 },
1662 .hsync_len = { 44, 54, 64 },
1663 .vactive = { 800, 800, 800 },
1664 .vfront_porch = { 5, 8, 11 },
1665 .vback_porch = { 5, 8, 11 },
1666 .vsync_len = { 5, 7, 11 },
1667 .flags = DISPLAY_FLAGS_DE_HIGH,
1670 static const struct panel_desc dlc_dlc1010gig = {
1671 .timings = &dlc_dlc1010gig_timing,
1684 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1685 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1688 static const struct drm_display_mode edt_et035012dm6_mode = {
1691 .hsync_start = 320 + 20,
1692 .hsync_end = 320 + 20 + 30,
1693 .htotal = 320 + 20 + 68,
1695 .vsync_start = 240 + 4,
1696 .vsync_end = 240 + 4 + 4,
1697 .vtotal = 240 + 4 + 4 + 14,
1698 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1701 static const struct panel_desc edt_et035012dm6 = {
1702 .modes = &edt_et035012dm6_mode,
1709 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1710 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1713 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1716 .hsync_start = 480 + 8,
1717 .hsync_end = 480 + 8 + 4,
1718 .htotal = 480 + 8 + 4 + 41,
1721 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1726 .vsync_start = 288 + 2,
1727 .vsync_end = 288 + 2 + 4,
1728 .vtotal = 288 + 2 + 4 + 10,
1731 static const struct panel_desc edt_etm043080dh6gp = {
1732 .modes = &edt_etm043080dh6gp_mode,
1739 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1740 .connector_type = DRM_MODE_CONNECTOR_DPI,
1743 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1746 .hsync_start = 480 + 2,
1747 .hsync_end = 480 + 2 + 41,
1748 .htotal = 480 + 2 + 41 + 2,
1750 .vsync_start = 272 + 2,
1751 .vsync_end = 272 + 2 + 10,
1752 .vtotal = 272 + 2 + 10 + 2,
1753 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1756 static const struct panel_desc edt_etm0430g0dh6 = {
1757 .modes = &edt_etm0430g0dh6_mode,
1766 static const struct drm_display_mode edt_et057090dhu_mode = {
1769 .hsync_start = 640 + 16,
1770 .hsync_end = 640 + 16 + 30,
1771 .htotal = 640 + 16 + 30 + 114,
1773 .vsync_start = 480 + 10,
1774 .vsync_end = 480 + 10 + 3,
1775 .vtotal = 480 + 10 + 3 + 32,
1776 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1779 static const struct panel_desc edt_et057090dhu = {
1780 .modes = &edt_et057090dhu_mode,
1787 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1788 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1789 .connector_type = DRM_MODE_CONNECTOR_DPI,
1792 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1795 .hsync_start = 800 + 40,
1796 .hsync_end = 800 + 40 + 128,
1797 .htotal = 800 + 40 + 128 + 88,
1799 .vsync_start = 480 + 10,
1800 .vsync_end = 480 + 10 + 2,
1801 .vtotal = 480 + 10 + 2 + 33,
1802 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1805 static const struct panel_desc edt_etm0700g0dh6 = {
1806 .modes = &edt_etm0700g0dh6_mode,
1813 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1814 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1817 static const struct panel_desc edt_etm0700g0bdh6 = {
1818 .modes = &edt_etm0700g0dh6_mode,
1825 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1826 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1829 static const struct display_timing evervision_vgg804821_timing = {
1830 .pixelclock = { 27600000, 33300000, 50000000 },
1831 .hactive = { 800, 800, 800 },
1832 .hfront_porch = { 40, 66, 70 },
1833 .hback_porch = { 40, 67, 70 },
1834 .hsync_len = { 40, 67, 70 },
1835 .vactive = { 480, 480, 480 },
1836 .vfront_porch = { 6, 10, 10 },
1837 .vback_porch = { 7, 11, 11 },
1838 .vsync_len = { 7, 11, 11 },
1839 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1840 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1841 DISPLAY_FLAGS_SYNC_NEGEDGE,
1844 static const struct panel_desc evervision_vgg804821 = {
1845 .timings = &evervision_vgg804821_timing,
1852 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1853 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1856 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1859 .hsync_start = 800 + 168,
1860 .hsync_end = 800 + 168 + 64,
1861 .htotal = 800 + 168 + 64 + 88,
1863 .vsync_start = 480 + 37,
1864 .vsync_end = 480 + 37 + 2,
1865 .vtotal = 480 + 37 + 2 + 8,
1868 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1869 .modes = &foxlink_fl500wvr00_a0t_mode,
1876 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1879 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1883 .hsync_start = 320 + 44,
1884 .hsync_end = 320 + 44 + 16,
1885 .htotal = 320 + 44 + 16 + 20,
1887 .vsync_start = 240 + 2,
1888 .vsync_end = 240 + 2 + 6,
1889 .vtotal = 240 + 2 + 6 + 2,
1890 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1895 .hsync_start = 320 + 56,
1896 .hsync_end = 320 + 56 + 16,
1897 .htotal = 320 + 56 + 16 + 40,
1899 .vsync_start = 240 + 2,
1900 .vsync_end = 240 + 2 + 6,
1901 .vtotal = 240 + 2 + 6 + 2,
1902 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1906 static const struct panel_desc frida_frd350h54004 = {
1907 .modes = frida_frd350h54004_modes,
1908 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1914 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1915 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1916 .connector_type = DRM_MODE_CONNECTOR_DPI,
1919 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1922 .hsync_start = 800 + 20,
1923 .hsync_end = 800 + 20 + 24,
1924 .htotal = 800 + 20 + 24 + 20,
1926 .vsync_start = 1280 + 4,
1927 .vsync_end = 1280 + 4 + 8,
1928 .vtotal = 1280 + 4 + 8 + 4,
1929 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1932 static const struct panel_desc friendlyarm_hd702e = {
1933 .modes = &friendlyarm_hd702e_mode,
1941 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1944 .hsync_start = 480 + 5,
1945 .hsync_end = 480 + 5 + 1,
1946 .htotal = 480 + 5 + 1 + 40,
1948 .vsync_start = 272 + 8,
1949 .vsync_end = 272 + 8 + 1,
1950 .vtotal = 272 + 8 + 1 + 8,
1953 static const struct panel_desc giantplus_gpg482739qs5 = {
1954 .modes = &giantplus_gpg482739qs5_mode,
1961 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1964 static const struct display_timing giantplus_gpm940b0_timing = {
1965 .pixelclock = { 13500000, 27000000, 27500000 },
1966 .hactive = { 320, 320, 320 },
1967 .hfront_porch = { 14, 686, 718 },
1968 .hback_porch = { 50, 70, 255 },
1969 .hsync_len = { 1, 1, 1 },
1970 .vactive = { 240, 240, 240 },
1971 .vfront_porch = { 1, 1, 179 },
1972 .vback_porch = { 1, 21, 31 },
1973 .vsync_len = { 1, 1, 6 },
1974 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1977 static const struct panel_desc giantplus_gpm940b0 = {
1978 .timings = &giantplus_gpm940b0_timing,
1985 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1986 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1989 static const struct display_timing hannstar_hsd070pww1_timing = {
1990 .pixelclock = { 64300000, 71100000, 82000000 },
1991 .hactive = { 1280, 1280, 1280 },
1992 .hfront_porch = { 1, 1, 10 },
1993 .hback_porch = { 1, 1, 10 },
1995 * According to the data sheet, the minimum horizontal blanking interval
1996 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1997 * minimum working horizontal blanking interval to be 60 clocks.
1999 .hsync_len = { 58, 158, 661 },
2000 .vactive = { 800, 800, 800 },
2001 .vfront_porch = { 1, 1, 10 },
2002 .vback_porch = { 1, 1, 10 },
2003 .vsync_len = { 1, 21, 203 },
2004 .flags = DISPLAY_FLAGS_DE_HIGH,
2007 static const struct panel_desc hannstar_hsd070pww1 = {
2008 .timings = &hannstar_hsd070pww1_timing,
2015 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2016 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2019 static const struct display_timing hannstar_hsd100pxn1_timing = {
2020 .pixelclock = { 55000000, 65000000, 75000000 },
2021 .hactive = { 1024, 1024, 1024 },
2022 .hfront_porch = { 40, 40, 40 },
2023 .hback_porch = { 220, 220, 220 },
2024 .hsync_len = { 20, 60, 100 },
2025 .vactive = { 768, 768, 768 },
2026 .vfront_porch = { 7, 7, 7 },
2027 .vback_porch = { 21, 21, 21 },
2028 .vsync_len = { 10, 10, 10 },
2029 .flags = DISPLAY_FLAGS_DE_HIGH,
2032 static const struct panel_desc hannstar_hsd100pxn1 = {
2033 .timings = &hannstar_hsd100pxn1_timing,
2040 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2041 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2044 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2047 .hsync_start = 800 + 85,
2048 .hsync_end = 800 + 85 + 86,
2049 .htotal = 800 + 85 + 86 + 85,
2051 .vsync_start = 480 + 16,
2052 .vsync_end = 480 + 16 + 13,
2053 .vtotal = 480 + 16 + 13 + 16,
2056 static const struct panel_desc hitachi_tx23d38vm0caa = {
2057 .modes = &hitachi_tx23d38vm0caa_mode,
2070 static const struct drm_display_mode innolux_at043tn24_mode = {
2073 .hsync_start = 480 + 2,
2074 .hsync_end = 480 + 2 + 41,
2075 .htotal = 480 + 2 + 41 + 2,
2077 .vsync_start = 272 + 2,
2078 .vsync_end = 272 + 2 + 10,
2079 .vtotal = 272 + 2 + 10 + 2,
2080 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2083 static const struct panel_desc innolux_at043tn24 = {
2084 .modes = &innolux_at043tn24_mode,
2091 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2092 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2095 static const struct drm_display_mode innolux_at070tn92_mode = {
2098 .hsync_start = 800 + 210,
2099 .hsync_end = 800 + 210 + 20,
2100 .htotal = 800 + 210 + 20 + 46,
2102 .vsync_start = 480 + 22,
2103 .vsync_end = 480 + 22 + 10,
2104 .vtotal = 480 + 22 + 23 + 10,
2107 static const struct panel_desc innolux_at070tn92 = {
2108 .modes = &innolux_at070tn92_mode,
2114 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2117 static const struct display_timing innolux_g070y2_l01_timing = {
2118 .pixelclock = { 28000000, 29500000, 32000000 },
2119 .hactive = { 800, 800, 800 },
2120 .hfront_porch = { 61, 91, 141 },
2121 .hback_porch = { 60, 90, 140 },
2122 .hsync_len = { 12, 12, 12 },
2123 .vactive = { 480, 480, 480 },
2124 .vfront_porch = { 4, 9, 30 },
2125 .vback_porch = { 4, 8, 28 },
2126 .vsync_len = { 2, 2, 2 },
2127 .flags = DISPLAY_FLAGS_DE_HIGH,
2130 static const struct panel_desc innolux_g070y2_l01 = {
2131 .timings = &innolux_g070y2_l01_timing,
2144 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2145 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2148 static const struct display_timing innolux_g101ice_l01_timing = {
2149 .pixelclock = { 60400000, 71100000, 74700000 },
2150 .hactive = { 1280, 1280, 1280 },
2151 .hfront_porch = { 41, 80, 100 },
2152 .hback_porch = { 40, 79, 99 },
2153 .hsync_len = { 1, 1, 1 },
2154 .vactive = { 800, 800, 800 },
2155 .vfront_porch = { 5, 11, 14 },
2156 .vback_porch = { 4, 11, 14 },
2157 .vsync_len = { 1, 1, 1 },
2158 .flags = DISPLAY_FLAGS_DE_HIGH,
2161 static const struct panel_desc innolux_g101ice_l01 = {
2162 .timings = &innolux_g101ice_l01_timing,
2173 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2174 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2177 static const struct display_timing innolux_g121i1_l01_timing = {
2178 .pixelclock = { 67450000, 71000000, 74550000 },
2179 .hactive = { 1280, 1280, 1280 },
2180 .hfront_porch = { 40, 80, 160 },
2181 .hback_porch = { 39, 79, 159 },
2182 .hsync_len = { 1, 1, 1 },
2183 .vactive = { 800, 800, 800 },
2184 .vfront_porch = { 5, 11, 100 },
2185 .vback_porch = { 4, 11, 99 },
2186 .vsync_len = { 1, 1, 1 },
2189 static const struct panel_desc innolux_g121i1_l01 = {
2190 .timings = &innolux_g121i1_l01_timing,
2201 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2202 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2205 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2208 .hsync_start = 1024 + 0,
2209 .hsync_end = 1024 + 1,
2210 .htotal = 1024 + 0 + 1 + 320,
2212 .vsync_start = 768 + 38,
2213 .vsync_end = 768 + 38 + 1,
2214 .vtotal = 768 + 38 + 1 + 0,
2215 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2218 static const struct panel_desc innolux_g121x1_l03 = {
2219 .modes = &innolux_g121x1_l03_mode,
2234 * Datasheet specifies that at 60 Hz refresh rate:
2235 * - total horizontal time: { 1506, 1592, 1716 }
2236 * - total vertical time: { 788, 800, 868 }
2238 * ...but doesn't go into exactly how that should be split into a front
2239 * porch, back porch, or sync length. For now we'll leave a single setting
2240 * here which allows a bit of tweaking of the pixel clock at the expense of
2243 static const struct display_timing innolux_n116bge_timing = {
2244 .pixelclock = { 72600000, 76420000, 80240000 },
2245 .hactive = { 1366, 1366, 1366 },
2246 .hfront_porch = { 136, 136, 136 },
2247 .hback_porch = { 60, 60, 60 },
2248 .hsync_len = { 30, 30, 30 },
2249 .vactive = { 768, 768, 768 },
2250 .vfront_porch = { 8, 8, 8 },
2251 .vback_porch = { 12, 12, 12 },
2252 .vsync_len = { 12, 12, 12 },
2253 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2256 static const struct panel_desc innolux_n116bge = {
2257 .timings = &innolux_n116bge_timing,
2266 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2269 .hsync_start = 1366 + 16,
2270 .hsync_end = 1366 + 16 + 34,
2271 .htotal = 1366 + 16 + 34 + 50,
2273 .vsync_start = 768 + 2,
2274 .vsync_end = 768 + 2 + 6,
2275 .vtotal = 768 + 2 + 6 + 12,
2278 static const struct panel_desc innolux_n156bge_l21 = {
2279 .modes = &innolux_n156bge_l21_mode,
2286 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2287 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2288 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2291 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2294 .hsync_start = 2160 + 48,
2295 .hsync_end = 2160 + 48 + 32,
2296 .htotal = 2160 + 48 + 32 + 80,
2298 .vsync_start = 1440 + 3,
2299 .vsync_end = 1440 + 3 + 10,
2300 .vtotal = 1440 + 3 + 10 + 27,
2301 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2304 static const struct panel_desc innolux_p120zdg_bf1 = {
2305 .modes = &innolux_p120zdg_bf1_mode,
2313 .hpd_absent_delay = 200,
2318 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2321 .hsync_start = 1024 + 128,
2322 .hsync_end = 1024 + 128 + 64,
2323 .htotal = 1024 + 128 + 64 + 128,
2325 .vsync_start = 600 + 16,
2326 .vsync_end = 600 + 16 + 4,
2327 .vtotal = 600 + 16 + 4 + 16,
2330 static const struct panel_desc innolux_zj070na_01p = {
2331 .modes = &innolux_zj070na_01p_mode,
2340 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2343 .hsync_start = 1920 + 24,
2344 .hsync_end = 1920 + 24 + 48,
2345 .htotal = 1920 + 24 + 48 + 88,
2347 .vsync_start = 1080 + 3,
2348 .vsync_end = 1080 + 3 + 12,
2349 .vtotal = 1080 + 3 + 12 + 17,
2350 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2353 static const struct panel_desc ivo_m133nwf4_r0 = {
2354 .modes = &ivo_m133nwf4_r0_mode,
2362 .hpd_absent_delay = 200,
2365 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2366 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2367 .connector_type = DRM_MODE_CONNECTOR_eDP,
2370 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2373 .hsync_start = 1366 + 40,
2374 .hsync_end = 1366 + 40 + 32,
2375 .htotal = 1366 + 40 + 32 + 62,
2377 .vsync_start = 768 + 5,
2378 .vsync_end = 768 + 5 + 5,
2379 .vtotal = 768 + 5 + 5 + 122,
2380 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2383 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2384 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2392 .hpd_absent_delay = 200,
2394 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2395 .connector_type = DRM_MODE_CONNECTOR_eDP,
2398 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2399 .pixelclock = { 5580000, 5850000, 6200000 },
2400 .hactive = { 320, 320, 320 },
2401 .hfront_porch = { 30, 30, 30 },
2402 .hback_porch = { 30, 30, 30 },
2403 .hsync_len = { 1, 5, 17 },
2404 .vactive = { 240, 240, 240 },
2405 .vfront_porch = { 6, 6, 6 },
2406 .vback_porch = { 5, 5, 5 },
2407 .vsync_len = { 1, 2, 11 },
2408 .flags = DISPLAY_FLAGS_DE_HIGH,
2411 static const struct panel_desc koe_tx14d24vm1bpa = {
2412 .timings = &koe_tx14d24vm1bpa_timing,
2421 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2422 .pixelclock = { 151820000, 156720000, 159780000 },
2423 .hactive = { 1920, 1920, 1920 },
2424 .hfront_porch = { 105, 130, 142 },
2425 .hback_porch = { 45, 70, 82 },
2426 .hsync_len = { 30, 30, 30 },
2427 .vactive = { 1200, 1200, 1200},
2428 .vfront_porch = { 3, 5, 10 },
2429 .vback_porch = { 2, 5, 10 },
2430 .vsync_len = { 5, 5, 5 },
2433 static const struct panel_desc koe_tx26d202vm0bwa = {
2434 .timings = &koe_tx26d202vm0bwa_timing,
2447 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2448 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2449 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2452 static const struct display_timing koe_tx31d200vm0baa_timing = {
2453 .pixelclock = { 39600000, 43200000, 48000000 },
2454 .hactive = { 1280, 1280, 1280 },
2455 .hfront_porch = { 16, 36, 56 },
2456 .hback_porch = { 16, 36, 56 },
2457 .hsync_len = { 8, 8, 8 },
2458 .vactive = { 480, 480, 480 },
2459 .vfront_porch = { 6, 21, 33 },
2460 .vback_porch = { 6, 21, 33 },
2461 .vsync_len = { 8, 8, 8 },
2462 .flags = DISPLAY_FLAGS_DE_HIGH,
2465 static const struct panel_desc koe_tx31d200vm0baa = {
2466 .timings = &koe_tx31d200vm0baa_timing,
2473 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2474 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2477 static const struct display_timing kyo_tcg121xglp_timing = {
2478 .pixelclock = { 52000000, 65000000, 71000000 },
2479 .hactive = { 1024, 1024, 1024 },
2480 .hfront_porch = { 2, 2, 2 },
2481 .hback_porch = { 2, 2, 2 },
2482 .hsync_len = { 86, 124, 244 },
2483 .vactive = { 768, 768, 768 },
2484 .vfront_porch = { 2, 2, 2 },
2485 .vback_porch = { 2, 2, 2 },
2486 .vsync_len = { 6, 34, 73 },
2487 .flags = DISPLAY_FLAGS_DE_HIGH,
2490 static const struct panel_desc kyo_tcg121xglp = {
2491 .timings = &kyo_tcg121xglp_timing,
2498 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2499 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2502 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2505 .hsync_start = 320 + 20,
2506 .hsync_end = 320 + 20 + 30,
2507 .htotal = 320 + 20 + 30 + 38,
2509 .vsync_start = 240 + 4,
2510 .vsync_end = 240 + 4 + 3,
2511 .vtotal = 240 + 4 + 3 + 15,
2514 static const struct panel_desc lemaker_bl035_rgb_002 = {
2515 .modes = &lemaker_bl035_rgb_002_mode,
2521 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2522 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2525 static const struct drm_display_mode lg_lb070wv8_mode = {
2528 .hsync_start = 800 + 88,
2529 .hsync_end = 800 + 88 + 80,
2530 .htotal = 800 + 88 + 80 + 88,
2532 .vsync_start = 480 + 10,
2533 .vsync_end = 480 + 10 + 25,
2534 .vtotal = 480 + 10 + 25 + 10,
2537 static const struct panel_desc lg_lb070wv8 = {
2538 .modes = &lg_lb070wv8_mode,
2545 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2546 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2549 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2552 .hsync_start = 1536 + 12,
2553 .hsync_end = 1536 + 12 + 16,
2554 .htotal = 1536 + 12 + 16 + 48,
2556 .vsync_start = 2048 + 8,
2557 .vsync_end = 2048 + 8 + 4,
2558 .vtotal = 2048 + 8 + 4 + 8,
2559 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2562 static const struct panel_desc lg_lp079qx1_sp0v = {
2563 .modes = &lg_lp079qx1_sp0v_mode,
2571 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2574 .hsync_start = 2048 + 150,
2575 .hsync_end = 2048 + 150 + 5,
2576 .htotal = 2048 + 150 + 5 + 5,
2578 .vsync_start = 1536 + 3,
2579 .vsync_end = 1536 + 3 + 1,
2580 .vtotal = 1536 + 3 + 1 + 9,
2583 static const struct panel_desc lg_lp097qx1_spa1 = {
2584 .modes = &lg_lp097qx1_spa1_mode,
2592 static const struct drm_display_mode lg_lp120up1_mode = {
2595 .hsync_start = 1920 + 40,
2596 .hsync_end = 1920 + 40 + 40,
2597 .htotal = 1920 + 40 + 40+ 80,
2599 .vsync_start = 1280 + 4,
2600 .vsync_end = 1280 + 4 + 4,
2601 .vtotal = 1280 + 4 + 4 + 12,
2604 static const struct panel_desc lg_lp120up1 = {
2605 .modes = &lg_lp120up1_mode,
2612 .connector_type = DRM_MODE_CONNECTOR_eDP,
2615 static const struct drm_display_mode lg_lp129qe_mode = {
2618 .hsync_start = 2560 + 48,
2619 .hsync_end = 2560 + 48 + 32,
2620 .htotal = 2560 + 48 + 32 + 80,
2622 .vsync_start = 1700 + 3,
2623 .vsync_end = 1700 + 3 + 10,
2624 .vtotal = 1700 + 3 + 10 + 36,
2627 static const struct panel_desc lg_lp129qe = {
2628 .modes = &lg_lp129qe_mode,
2637 static const struct display_timing logictechno_lt161010_2nh_timing = {
2638 .pixelclock = { 26400000, 33300000, 46800000 },
2639 .hactive = { 800, 800, 800 },
2640 .hfront_porch = { 16, 210, 354 },
2641 .hback_porch = { 46, 46, 46 },
2642 .hsync_len = { 1, 20, 40 },
2643 .vactive = { 480, 480, 480 },
2644 .vfront_porch = { 7, 22, 147 },
2645 .vback_porch = { 23, 23, 23 },
2646 .vsync_len = { 1, 10, 20 },
2647 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2648 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2649 DISPLAY_FLAGS_SYNC_POSEDGE,
2652 static const struct panel_desc logictechno_lt161010_2nh = {
2653 .timings = &logictechno_lt161010_2nh_timing,
2659 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2660 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2661 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2662 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2663 .connector_type = DRM_MODE_CONNECTOR_DPI,
2666 static const struct display_timing logictechno_lt170410_2whc_timing = {
2667 .pixelclock = { 68900000, 71100000, 73400000 },
2668 .hactive = { 1280, 1280, 1280 },
2669 .hfront_porch = { 23, 60, 71 },
2670 .hback_porch = { 23, 60, 71 },
2671 .hsync_len = { 15, 40, 47 },
2672 .vactive = { 800, 800, 800 },
2673 .vfront_porch = { 5, 7, 10 },
2674 .vback_porch = { 5, 7, 10 },
2675 .vsync_len = { 6, 9, 12 },
2676 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2677 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2678 DISPLAY_FLAGS_SYNC_POSEDGE,
2681 static const struct panel_desc logictechno_lt170410_2whc = {
2682 .timings = &logictechno_lt170410_2whc_timing,
2688 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2689 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2690 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2693 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2696 .hsync_start = 800 + 0,
2697 .hsync_end = 800 + 1,
2698 .htotal = 800 + 0 + 1 + 160,
2700 .vsync_start = 480 + 0,
2701 .vsync_end = 480 + 48 + 1,
2702 .vtotal = 480 + 48 + 1 + 0,
2703 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2706 static const struct drm_display_mode logicpd_type_28_mode = {
2709 .hsync_start = 480 + 3,
2710 .hsync_end = 480 + 3 + 42,
2711 .htotal = 480 + 3 + 42 + 2,
2714 .vsync_start = 272 + 2,
2715 .vsync_end = 272 + 2 + 11,
2716 .vtotal = 272 + 2 + 11 + 3,
2717 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2720 static const struct panel_desc logicpd_type_28 = {
2721 .modes = &logicpd_type_28_mode,
2734 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2735 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2736 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2737 .connector_type = DRM_MODE_CONNECTOR_DPI,
2740 static const struct panel_desc mitsubishi_aa070mc01 = {
2741 .modes = &mitsubishi_aa070mc01_mode,
2754 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2755 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2756 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2759 static const struct display_timing nec_nl12880bc20_05_timing = {
2760 .pixelclock = { 67000000, 71000000, 75000000 },
2761 .hactive = { 1280, 1280, 1280 },
2762 .hfront_porch = { 2, 30, 30 },
2763 .hback_porch = { 6, 100, 100 },
2764 .hsync_len = { 2, 30, 30 },
2765 .vactive = { 800, 800, 800 },
2766 .vfront_porch = { 5, 5, 5 },
2767 .vback_porch = { 11, 11, 11 },
2768 .vsync_len = { 7, 7, 7 },
2771 static const struct panel_desc nec_nl12880bc20_05 = {
2772 .timings = &nec_nl12880bc20_05_timing,
2783 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2784 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2787 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2790 .hsync_start = 480 + 2,
2791 .hsync_end = 480 + 2 + 41,
2792 .htotal = 480 + 2 + 41 + 2,
2794 .vsync_start = 272 + 2,
2795 .vsync_end = 272 + 2 + 4,
2796 .vtotal = 272 + 2 + 4 + 2,
2797 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2800 static const struct panel_desc nec_nl4827hc19_05b = {
2801 .modes = &nec_nl4827hc19_05b_mode,
2808 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2809 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2812 static const struct drm_display_mode netron_dy_e231732_mode = {
2815 .hsync_start = 1024 + 160,
2816 .hsync_end = 1024 + 160 + 70,
2817 .htotal = 1024 + 160 + 70 + 90,
2819 .vsync_start = 600 + 127,
2820 .vsync_end = 600 + 127 + 20,
2821 .vtotal = 600 + 127 + 20 + 3,
2824 static const struct panel_desc netron_dy_e231732 = {
2825 .modes = &netron_dy_e231732_mode,
2831 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2834 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2838 .hsync_start = 1920 + 48,
2839 .hsync_end = 1920 + 48 + 32,
2840 .htotal = 1920 + 48 + 32 + 80,
2842 .vsync_start = 1080 + 3,
2843 .vsync_end = 1080 + 3 + 5,
2844 .vtotal = 1080 + 3 + 5 + 23,
2845 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2849 .hsync_start = 1920 + 48,
2850 .hsync_end = 1920 + 48 + 32,
2851 .htotal = 1920 + 48 + 32 + 80,
2853 .vsync_start = 1080 + 3,
2854 .vsync_end = 1080 + 3 + 5,
2855 .vtotal = 1080 + 3 + 5 + 23,
2856 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2860 static const struct panel_desc neweast_wjfh116008a = {
2861 .modes = neweast_wjfh116008a_modes,
2873 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2874 .connector_type = DRM_MODE_CONNECTOR_eDP,
2877 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2880 .hsync_start = 480 + 2,
2881 .hsync_end = 480 + 2 + 41,
2882 .htotal = 480 + 2 + 41 + 2,
2884 .vsync_start = 272 + 2,
2885 .vsync_end = 272 + 2 + 10,
2886 .vtotal = 272 + 2 + 10 + 2,
2887 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2890 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2891 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2898 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2899 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2900 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2901 .connector_type = DRM_MODE_CONNECTOR_DPI,
2904 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2905 .pixelclock = { 130000000, 148350000, 163000000 },
2906 .hactive = { 1920, 1920, 1920 },
2907 .hfront_porch = { 80, 100, 100 },
2908 .hback_porch = { 100, 120, 120 },
2909 .hsync_len = { 50, 60, 60 },
2910 .vactive = { 1080, 1080, 1080 },
2911 .vfront_porch = { 12, 30, 30 },
2912 .vback_porch = { 4, 10, 10 },
2913 .vsync_len = { 4, 5, 5 },
2916 static const struct panel_desc nlt_nl192108ac18_02d = {
2917 .timings = &nlt_nl192108ac18_02d_timing,
2927 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2928 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2931 static const struct drm_display_mode nvd_9128_mode = {
2934 .hsync_start = 800 + 130,
2935 .hsync_end = 800 + 130 + 98,
2936 .htotal = 800 + 0 + 130 + 98,
2938 .vsync_start = 480 + 10,
2939 .vsync_end = 480 + 10 + 50,
2940 .vtotal = 480 + 0 + 10 + 50,
2943 static const struct panel_desc nvd_9128 = {
2944 .modes = &nvd_9128_mode,
2951 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2952 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2955 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2956 .pixelclock = { 30000000, 30000000, 40000000 },
2957 .hactive = { 800, 800, 800 },
2958 .hfront_porch = { 40, 40, 40 },
2959 .hback_porch = { 40, 40, 40 },
2960 .hsync_len = { 1, 48, 48 },
2961 .vactive = { 480, 480, 480 },
2962 .vfront_porch = { 13, 13, 13 },
2963 .vback_porch = { 29, 29, 29 },
2964 .vsync_len = { 3, 3, 3 },
2965 .flags = DISPLAY_FLAGS_DE_HIGH,
2968 static const struct panel_desc okaya_rs800480t_7x0gp = {
2969 .timings = &okaya_rs800480t_7x0gp_timing,
2982 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2985 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2988 .hsync_start = 480 + 5,
2989 .hsync_end = 480 + 5 + 30,
2990 .htotal = 480 + 5 + 30 + 10,
2992 .vsync_start = 272 + 8,
2993 .vsync_end = 272 + 8 + 5,
2994 .vtotal = 272 + 8 + 5 + 3,
2997 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2998 .modes = &olimex_lcd_olinuxino_43ts_mode,
3004 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3008 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3009 * pixel clocks, but this is the timing that was being used in the Adafruit
3010 * installation instructions.
3012 static const struct drm_display_mode ontat_yx700wv03_mode = {
3022 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3027 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3029 static const struct panel_desc ontat_yx700wv03 = {
3030 .modes = &ontat_yx700wv03_mode,
3037 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3040 static const struct drm_display_mode ortustech_com37h3m_mode = {
3043 .hsync_start = 480 + 40,
3044 .hsync_end = 480 + 40 + 10,
3045 .htotal = 480 + 40 + 10 + 40,
3047 .vsync_start = 640 + 4,
3048 .vsync_end = 640 + 4 + 2,
3049 .vtotal = 640 + 4 + 2 + 4,
3050 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3053 static const struct panel_desc ortustech_com37h3m = {
3054 .modes = &ortustech_com37h3m_mode,
3058 .width = 56, /* 56.16mm */
3059 .height = 75, /* 74.88mm */
3061 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3062 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3063 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3066 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3069 .hsync_start = 480 + 10,
3070 .hsync_end = 480 + 10 + 10,
3071 .htotal = 480 + 10 + 10 + 15,
3073 .vsync_start = 800 + 3,
3074 .vsync_end = 800 + 3 + 3,
3075 .vtotal = 800 + 3 + 3 + 3,
3078 static const struct panel_desc ortustech_com43h4m85ulc = {
3079 .modes = &ortustech_com43h4m85ulc_mode,
3086 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3087 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3088 .connector_type = DRM_MODE_CONNECTOR_DPI,
3091 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3094 .hsync_start = 800 + 210,
3095 .hsync_end = 800 + 210 + 30,
3096 .htotal = 800 + 210 + 30 + 16,
3098 .vsync_start = 480 + 22,
3099 .vsync_end = 480 + 22 + 13,
3100 .vtotal = 480 + 22 + 13 + 10,
3101 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3104 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3105 .modes = &osddisplays_osd070t1718_19ts_mode,
3112 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3113 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3114 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3115 .connector_type = DRM_MODE_CONNECTOR_DPI,
3118 static const struct drm_display_mode pda_91_00156_a0_mode = {
3121 .hsync_start = 800 + 1,
3122 .hsync_end = 800 + 1 + 64,
3123 .htotal = 800 + 1 + 64 + 64,
3125 .vsync_start = 480 + 1,
3126 .vsync_end = 480 + 1 + 23,
3127 .vtotal = 480 + 1 + 23 + 22,
3130 static const struct panel_desc pda_91_00156_a0 = {
3131 .modes = &pda_91_00156_a0_mode,
3137 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3140 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3143 .hsync_start = 800 + 54,
3144 .hsync_end = 800 + 54 + 2,
3145 .htotal = 800 + 54 + 2 + 44,
3147 .vsync_start = 480 + 49,
3148 .vsync_end = 480 + 49 + 2,
3149 .vtotal = 480 + 49 + 2 + 22,
3152 static const struct panel_desc powertip_ph800480t013_idf02 = {
3153 .modes = &powertip_ph800480t013_idf02_mode,
3159 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3160 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3161 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3162 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3163 .connector_type = DRM_MODE_CONNECTOR_DPI,
3166 static const struct drm_display_mode qd43003c0_40_mode = {
3169 .hsync_start = 480 + 8,
3170 .hsync_end = 480 + 8 + 4,
3171 .htotal = 480 + 8 + 4 + 39,
3173 .vsync_start = 272 + 4,
3174 .vsync_end = 272 + 4 + 10,
3175 .vtotal = 272 + 4 + 10 + 2,
3178 static const struct panel_desc qd43003c0_40 = {
3179 .modes = &qd43003c0_40_mode,
3186 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3189 static const struct display_timing rocktech_rk070er9427_timing = {
3190 .pixelclock = { 26400000, 33300000, 46800000 },
3191 .hactive = { 800, 800, 800 },
3192 .hfront_porch = { 16, 210, 354 },
3193 .hback_porch = { 46, 46, 46 },
3194 .hsync_len = { 1, 1, 1 },
3195 .vactive = { 480, 480, 480 },
3196 .vfront_porch = { 7, 22, 147 },
3197 .vback_porch = { 23, 23, 23 },
3198 .vsync_len = { 1, 1, 1 },
3199 .flags = DISPLAY_FLAGS_DE_HIGH,
3202 static const struct panel_desc rocktech_rk070er9427 = {
3203 .timings = &rocktech_rk070er9427_timing,
3216 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3219 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3222 .hsync_start = 1280 + 48,
3223 .hsync_end = 1280 + 48 + 32,
3224 .htotal = 1280 + 48 + 32 + 80,
3226 .vsync_start = 800 + 2,
3227 .vsync_end = 800 + 2 + 5,
3228 .vtotal = 800 + 2 + 5 + 16,
3231 static const struct panel_desc rocktech_rk101ii01d_ct = {
3232 .modes = &rocktech_rk101ii01d_ct_mode,
3242 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3243 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3244 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3247 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3250 .hsync_start = 2560 + 48,
3251 .hsync_end = 2560 + 48 + 32,
3252 .htotal = 2560 + 48 + 32 + 80,
3254 .vsync_start = 1600 + 2,
3255 .vsync_end = 1600 + 2 + 5,
3256 .vtotal = 1600 + 2 + 5 + 57,
3259 static const struct panel_desc samsung_lsn122dl01_c01 = {
3260 .modes = &samsung_lsn122dl01_c01_mode,
3268 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3271 .hsync_start = 1024 + 24,
3272 .hsync_end = 1024 + 24 + 136,
3273 .htotal = 1024 + 24 + 136 + 160,
3275 .vsync_start = 600 + 3,
3276 .vsync_end = 600 + 3 + 6,
3277 .vtotal = 600 + 3 + 6 + 61,
3280 static const struct panel_desc samsung_ltn101nt05 = {
3281 .modes = &samsung_ltn101nt05_mode,
3288 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3289 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3290 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3293 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3296 .hsync_start = 1366 + 64,
3297 .hsync_end = 1366 + 64 + 48,
3298 .htotal = 1366 + 64 + 48 + 128,
3300 .vsync_start = 768 + 2,
3301 .vsync_end = 768 + 2 + 5,
3302 .vtotal = 768 + 2 + 5 + 17,
3305 static const struct panel_desc samsung_ltn140at29_301 = {
3306 .modes = &samsung_ltn140at29_301_mode,
3315 static const struct display_timing satoz_sat050at40h12r2_timing = {
3316 .pixelclock = {33300000, 33300000, 50000000},
3317 .hactive = {800, 800, 800},
3318 .hfront_porch = {16, 210, 354},
3319 .hback_porch = {46, 46, 46},
3320 .hsync_len = {1, 1, 40},
3321 .vactive = {480, 480, 480},
3322 .vfront_porch = {7, 22, 147},
3323 .vback_porch = {23, 23, 23},
3324 .vsync_len = {1, 1, 20},
3327 static const struct panel_desc satoz_sat050at40h12r2 = {
3328 .timings = &satoz_sat050at40h12r2_timing,
3335 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3336 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3339 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3342 .hsync_start = 1920 + 48,
3343 .hsync_end = 1920 + 48 + 32,
3344 .htotal = 1920 + 48 + 32 + 80,
3346 .vsync_start = 1280 + 3,
3347 .vsync_end = 1280 + 3 + 10,
3348 .vtotal = 1280 + 3 + 10 + 57,
3349 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3352 static const struct panel_desc sharp_ld_d5116z01b = {
3353 .modes = &sharp_ld_d5116z01b_mode,
3360 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3361 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3364 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3367 .hsync_start = 800 + 64,
3368 .hsync_end = 800 + 64 + 128,
3369 .htotal = 800 + 64 + 128 + 64,
3371 .vsync_start = 480 + 8,
3372 .vsync_end = 480 + 8 + 2,
3373 .vtotal = 480 + 8 + 2 + 35,
3374 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3377 static const struct panel_desc sharp_lq070y3dg3b = {
3378 .modes = &sharp_lq070y3dg3b_mode,
3382 .width = 152, /* 152.4mm */
3383 .height = 91, /* 91.4mm */
3385 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3386 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3387 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3390 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3393 .hsync_start = 240 + 16,
3394 .hsync_end = 240 + 16 + 7,
3395 .htotal = 240 + 16 + 7 + 5,
3397 .vsync_start = 320 + 9,
3398 .vsync_end = 320 + 9 + 1,
3399 .vtotal = 320 + 9 + 1 + 7,
3402 static const struct panel_desc sharp_lq035q7db03 = {
3403 .modes = &sharp_lq035q7db03_mode,
3410 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3413 static const struct display_timing sharp_lq101k1ly04_timing = {
3414 .pixelclock = { 60000000, 65000000, 80000000 },
3415 .hactive = { 1280, 1280, 1280 },
3416 .hfront_porch = { 20, 20, 20 },
3417 .hback_porch = { 20, 20, 20 },
3418 .hsync_len = { 10, 10, 10 },
3419 .vactive = { 800, 800, 800 },
3420 .vfront_porch = { 4, 4, 4 },
3421 .vback_porch = { 4, 4, 4 },
3422 .vsync_len = { 4, 4, 4 },
3423 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3426 static const struct panel_desc sharp_lq101k1ly04 = {
3427 .timings = &sharp_lq101k1ly04_timing,
3434 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3435 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3438 static const struct display_timing sharp_lq123p1jx31_timing = {
3439 .pixelclock = { 252750000, 252750000, 266604720 },
3440 .hactive = { 2400, 2400, 2400 },
3441 .hfront_porch = { 48, 48, 48 },
3442 .hback_porch = { 80, 80, 84 },
3443 .hsync_len = { 32, 32, 32 },
3444 .vactive = { 1600, 1600, 1600 },
3445 .vfront_porch = { 3, 3, 3 },
3446 .vback_porch = { 33, 33, 120 },
3447 .vsync_len = { 10, 10, 10 },
3448 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3451 static const struct panel_desc sharp_lq123p1jx31 = {
3452 .timings = &sharp_lq123p1jx31_timing,
3466 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3470 .hsync_start = 240 + 58,
3471 .hsync_end = 240 + 58 + 1,
3472 .htotal = 240 + 58 + 1 + 1,
3474 .vsync_start = 160 + 24,
3475 .vsync_end = 160 + 24 + 10,
3476 .vtotal = 160 + 24 + 10 + 6,
3477 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3482 .hsync_start = 240 + 8,
3483 .hsync_end = 240 + 8 + 1,
3484 .htotal = 240 + 8 + 1 + 1,
3486 .vsync_start = 160 + 24,
3487 .vsync_end = 160 + 24 + 10,
3488 .vtotal = 160 + 24 + 10 + 6,
3489 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3493 static const struct panel_desc sharp_ls020b1dd01d = {
3494 .modes = sharp_ls020b1dd01d_modes,
3495 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3501 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3502 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3503 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3504 | DRM_BUS_FLAG_SHARP_SIGNALS,
3507 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3510 .hsync_start = 800 + 1,
3511 .hsync_end = 800 + 1 + 64,
3512 .htotal = 800 + 1 + 64 + 64,
3514 .vsync_start = 480 + 1,
3515 .vsync_end = 480 + 1 + 23,
3516 .vtotal = 480 + 1 + 23 + 22,
3519 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3520 .modes = &shelly_sca07010_bfn_lnn_mode,
3526 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3529 static const struct drm_display_mode starry_kr070pe2t_mode = {
3532 .hsync_start = 800 + 209,
3533 .hsync_end = 800 + 209 + 1,
3534 .htotal = 800 + 209 + 1 + 45,
3536 .vsync_start = 480 + 22,
3537 .vsync_end = 480 + 22 + 1,
3538 .vtotal = 480 + 22 + 1 + 22,
3541 static const struct panel_desc starry_kr070pe2t = {
3542 .modes = &starry_kr070pe2t_mode,
3549 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3550 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3551 .connector_type = DRM_MODE_CONNECTOR_DPI,
3554 static const struct drm_display_mode starry_kr122ea0sra_mode = {
3557 .hsync_start = 1920 + 16,
3558 .hsync_end = 1920 + 16 + 16,
3559 .htotal = 1920 + 16 + 16 + 32,
3561 .vsync_start = 1200 + 15,
3562 .vsync_end = 1200 + 15 + 2,
3563 .vtotal = 1200 + 15 + 2 + 18,
3564 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3567 static const struct panel_desc starry_kr122ea0sra = {
3568 .modes = &starry_kr122ea0sra_mode,
3575 .prepare = 10 + 200,
3577 .unprepare = 10 + 500,
3581 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3584 .hsync_start = 800 + 39,
3585 .hsync_end = 800 + 39 + 47,
3586 .htotal = 800 + 39 + 47 + 39,
3588 .vsync_start = 480 + 13,
3589 .vsync_end = 480 + 13 + 2,
3590 .vtotal = 480 + 13 + 2 + 29,
3593 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3594 .modes = &tfc_s9700rtwv43tr_01b_mode,
3601 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3602 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3605 static const struct display_timing tianma_tm070jdhg30_timing = {
3606 .pixelclock = { 62600000, 68200000, 78100000 },
3607 .hactive = { 1280, 1280, 1280 },
3608 .hfront_porch = { 15, 64, 159 },
3609 .hback_porch = { 5, 5, 5 },
3610 .hsync_len = { 1, 1, 256 },
3611 .vactive = { 800, 800, 800 },
3612 .vfront_porch = { 3, 40, 99 },
3613 .vback_porch = { 2, 2, 2 },
3614 .vsync_len = { 1, 1, 128 },
3615 .flags = DISPLAY_FLAGS_DE_HIGH,
3618 static const struct panel_desc tianma_tm070jdhg30 = {
3619 .timings = &tianma_tm070jdhg30_timing,
3626 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3627 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3630 static const struct panel_desc tianma_tm070jvhg33 = {
3631 .timings = &tianma_tm070jdhg30_timing,
3638 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3639 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3642 static const struct display_timing tianma_tm070rvhg71_timing = {
3643 .pixelclock = { 27700000, 29200000, 39600000 },
3644 .hactive = { 800, 800, 800 },
3645 .hfront_porch = { 12, 40, 212 },
3646 .hback_porch = { 88, 88, 88 },
3647 .hsync_len = { 1, 1, 40 },
3648 .vactive = { 480, 480, 480 },
3649 .vfront_porch = { 1, 13, 88 },
3650 .vback_porch = { 32, 32, 32 },
3651 .vsync_len = { 1, 1, 3 },
3652 .flags = DISPLAY_FLAGS_DE_HIGH,
3655 static const struct panel_desc tianma_tm070rvhg71 = {
3656 .timings = &tianma_tm070rvhg71_timing,
3663 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3664 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3667 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3671 .hsync_start = 320 + 50,
3672 .hsync_end = 320 + 50 + 6,
3673 .htotal = 320 + 50 + 6 + 38,
3675 .vsync_start = 240 + 3,
3676 .vsync_end = 240 + 3 + 1,
3677 .vtotal = 240 + 3 + 1 + 17,
3678 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3682 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3683 .modes = ti_nspire_cx_lcd_mode,
3690 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3691 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3694 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3698 .hsync_start = 320 + 6,
3699 .hsync_end = 320 + 6 + 6,
3700 .htotal = 320 + 6 + 6 + 6,
3702 .vsync_start = 240 + 0,
3703 .vsync_end = 240 + 0 + 1,
3704 .vtotal = 240 + 0 + 1 + 0,
3705 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3709 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3710 .modes = ti_nspire_classic_lcd_mode,
3712 /* The grayscale panel has 8 bit for the color .. Y (black) */
3718 /* This is the grayscale bus format */
3719 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3720 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3723 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3726 .hsync_start = 1280 + 192,
3727 .hsync_end = 1280 + 192 + 128,
3728 .htotal = 1280 + 192 + 128 + 64,
3730 .vsync_start = 768 + 20,
3731 .vsync_end = 768 + 20 + 7,
3732 .vtotal = 768 + 20 + 7 + 3,
3735 static const struct panel_desc toshiba_lt089ac29000 = {
3736 .modes = &toshiba_lt089ac29000_mode,
3742 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3743 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3744 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3747 static const struct drm_display_mode tpk_f07a_0102_mode = {
3750 .hsync_start = 800 + 40,
3751 .hsync_end = 800 + 40 + 128,
3752 .htotal = 800 + 40 + 128 + 88,
3754 .vsync_start = 480 + 10,
3755 .vsync_end = 480 + 10 + 2,
3756 .vtotal = 480 + 10 + 2 + 33,
3759 static const struct panel_desc tpk_f07a_0102 = {
3760 .modes = &tpk_f07a_0102_mode,
3766 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3769 static const struct drm_display_mode tpk_f10a_0102_mode = {
3772 .hsync_start = 1024 + 176,
3773 .hsync_end = 1024 + 176 + 5,
3774 .htotal = 1024 + 176 + 5 + 88,
3776 .vsync_start = 600 + 20,
3777 .vsync_end = 600 + 20 + 5,
3778 .vtotal = 600 + 20 + 5 + 25,
3781 static const struct panel_desc tpk_f10a_0102 = {
3782 .modes = &tpk_f10a_0102_mode,
3790 static const struct display_timing urt_umsh_8596md_timing = {
3791 .pixelclock = { 33260000, 33260000, 33260000 },
3792 .hactive = { 800, 800, 800 },
3793 .hfront_porch = { 41, 41, 41 },
3794 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3795 .hsync_len = { 71, 128, 128 },
3796 .vactive = { 480, 480, 480 },
3797 .vfront_porch = { 10, 10, 10 },
3798 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3799 .vsync_len = { 2, 2, 2 },
3800 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3801 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3804 static const struct panel_desc urt_umsh_8596md_lvds = {
3805 .timings = &urt_umsh_8596md_timing,
3812 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3813 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3816 static const struct panel_desc urt_umsh_8596md_parallel = {
3817 .timings = &urt_umsh_8596md_timing,
3824 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3827 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3830 .hsync_start = 800 + 210,
3831 .hsync_end = 800 + 210 + 20,
3832 .htotal = 800 + 210 + 20 + 46,
3834 .vsync_start = 480 + 22,
3835 .vsync_end = 480 + 22 + 10,
3836 .vtotal = 480 + 22 + 10 + 23,
3837 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3840 static const struct panel_desc vl050_8048nt_c01 = {
3841 .modes = &vl050_8048nt_c01_mode,
3848 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3849 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3852 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3855 .hsync_start = 320 + 20,
3856 .hsync_end = 320 + 20 + 30,
3857 .htotal = 320 + 20 + 30 + 38,
3859 .vsync_start = 240 + 4,
3860 .vsync_end = 240 + 4 + 3,
3861 .vtotal = 240 + 4 + 3 + 15,
3862 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3865 static const struct panel_desc winstar_wf35ltiacd = {
3866 .modes = &winstar_wf35ltiacd_mode,
3873 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3876 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
3879 .hsync_start = 1024 + 100,
3880 .hsync_end = 1024 + 100 + 100,
3881 .htotal = 1024 + 100 + 100 + 120,
3883 .vsync_start = 600 + 10,
3884 .vsync_end = 600 + 10 + 10,
3885 .vtotal = 600 + 10 + 10 + 15,
3886 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3889 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
3890 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
3897 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3898 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3899 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3902 static const struct drm_display_mode arm_rtsm_mode[] = {
3906 .hsync_start = 1024 + 24,
3907 .hsync_end = 1024 + 24 + 136,
3908 .htotal = 1024 + 24 + 136 + 160,
3910 .vsync_start = 768 + 3,
3911 .vsync_end = 768 + 3 + 6,
3912 .vtotal = 768 + 3 + 6 + 29,
3913 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3917 static const struct panel_desc arm_rtsm = {
3918 .modes = arm_rtsm_mode,
3925 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3928 static const struct of_device_id platform_of_match[] = {
3930 .compatible = "ampire,am-1280800n3tzqw-t00h",
3931 .data = &ire_am_1280800n3tzqw_t00h,
3933 .compatible = "ampire,am-480272h3tmqw-t01h",
3934 .data = &ire_am_480272h3tmqw_t01h,
3936 .compatible = "ampire,am800480r3tmqwa1h",
3937 .data = &ire_am800480r3tmqwa1h,
3939 .compatible = "arm,rtsm-display",
3942 .compatible = "armadeus,st0700-adapt",
3943 .data = &armadeus_st0700_adapt,
3945 .compatible = "auo,b101aw03",
3946 .data = &auo_b101aw03,
3948 .compatible = "auo,b101ean01",
3949 .data = &auo_b101ean01,
3951 .compatible = "auo,b101xtn01",
3952 .data = &auo_b101xtn01,
3954 .compatible = "auo,b116xa01",
3955 .data = &auo_b116xak01,
3957 .compatible = "auo,b116xw03",
3958 .data = &auo_b116xw03,
3960 .compatible = "auo,b133htn01",
3961 .data = &auo_b133htn01,
3963 .compatible = "auo,b133xtn01",
3964 .data = &auo_b133xtn01,
3966 .compatible = "auo,g070vvn01",
3967 .data = &auo_g070vvn01,
3969 .compatible = "auo,g101evn010",
3970 .data = &auo_g101evn010,
3972 .compatible = "auo,g104sn02",
3973 .data = &auo_g104sn02,
3975 .compatible = "auo,g121ean01",
3976 .data = &auo_g121ean01,
3978 .compatible = "auo,g133han01",
3979 .data = &auo_g133han01,
3981 .compatible = "auo,g156xtn01",
3982 .data = &auo_g156xtn01,
3984 .compatible = "auo,g185han01",
3985 .data = &auo_g185han01,
3987 .compatible = "auo,g190ean01",
3988 .data = &auo_g190ean01,
3990 .compatible = "auo,p320hvn03",
3991 .data = &auo_p320hvn03,
3993 .compatible = "auo,t215hvn01",
3994 .data = &auo_t215hvn01,
3996 .compatible = "avic,tm070ddh03",
3997 .data = &avic_tm070ddh03,
3999 .compatible = "bananapi,s070wv20-ct16",
4000 .data = &bananapi_s070wv20_ct16,
4002 .compatible = "boe,hv070wsa-100",
4003 .data = &boe_hv070wsa
4005 .compatible = "boe,nv101wxmn51",
4006 .data = &boe_nv101wxmn51,
4008 .compatible = "boe,nv133fhm-n61",
4009 .data = &boe_nv133fhm_n61,
4011 .compatible = "boe,nv133fhm-n62",
4012 .data = &boe_nv133fhm_n61,
4014 .compatible = "boe,nv140fhmn49",
4015 .data = &boe_nv140fhmn49,
4017 .compatible = "cdtech,s043wq26h-ct7",
4018 .data = &cdtech_s043wq26h_ct7,
4020 .compatible = "cdtech,s070pws19hp-fc21",
4021 .data = &cdtech_s070pws19hp_fc21,
4023 .compatible = "cdtech,s070swv29hg-dc44",
4024 .data = &cdtech_s070swv29hg_dc44,
4026 .compatible = "cdtech,s070wv95-ct16",
4027 .data = &cdtech_s070wv95_ct16,
4029 .compatible = "chefree,ch101olhlwh-002",
4030 .data = &chefree_ch101olhlwh_002,
4032 .compatible = "chunghwa,claa070wp03xg",
4033 .data = &chunghwa_claa070wp03xg,
4035 .compatible = "chunghwa,claa101wa01a",
4036 .data = &chunghwa_claa101wa01a
4038 .compatible = "chunghwa,claa101wb01",
4039 .data = &chunghwa_claa101wb01
4041 .compatible = "dataimage,scf0700c48ggu18",
4042 .data = &dataimage_scf0700c48ggu18,
4044 .compatible = "dlc,dlc0700yzg-1",
4045 .data = &dlc_dlc0700yzg_1,
4047 .compatible = "dlc,dlc1010gig",
4048 .data = &dlc_dlc1010gig,
4050 .compatible = "edt,et035012dm6",
4051 .data = &edt_et035012dm6,
4053 .compatible = "edt,etm043080dh6gp",
4054 .data = &edt_etm043080dh6gp,
4056 .compatible = "edt,etm0430g0dh6",
4057 .data = &edt_etm0430g0dh6,
4059 .compatible = "edt,et057090dhu",
4060 .data = &edt_et057090dhu,
4062 .compatible = "edt,et070080dh6",
4063 .data = &edt_etm0700g0dh6,
4065 .compatible = "edt,etm0700g0dh6",
4066 .data = &edt_etm0700g0dh6,
4068 .compatible = "edt,etm0700g0bdh6",
4069 .data = &edt_etm0700g0bdh6,
4071 .compatible = "edt,etm0700g0edh6",
4072 .data = &edt_etm0700g0bdh6,
4074 .compatible = "evervision,vgg804821",
4075 .data = &evervision_vgg804821,
4077 .compatible = "foxlink,fl500wvr00-a0t",
4078 .data = &foxlink_fl500wvr00_a0t,
4080 .compatible = "frida,frd350h54004",
4081 .data = &frida_frd350h54004,
4083 .compatible = "friendlyarm,hd702e",
4084 .data = &friendlyarm_hd702e,
4086 .compatible = "giantplus,gpg482739qs5",
4087 .data = &giantplus_gpg482739qs5
4089 .compatible = "giantplus,gpm940b0",
4090 .data = &giantplus_gpm940b0,
4092 .compatible = "hannstar,hsd070pww1",
4093 .data = &hannstar_hsd070pww1,
4095 .compatible = "hannstar,hsd100pxn1",
4096 .data = &hannstar_hsd100pxn1,
4098 .compatible = "hit,tx23d38vm0caa",
4099 .data = &hitachi_tx23d38vm0caa
4101 .compatible = "innolux,at043tn24",
4102 .data = &innolux_at043tn24,
4104 .compatible = "innolux,at070tn92",
4105 .data = &innolux_at070tn92,
4107 .compatible = "innolux,g070y2-l01",
4108 .data = &innolux_g070y2_l01,
4110 .compatible = "innolux,g101ice-l01",
4111 .data = &innolux_g101ice_l01
4113 .compatible = "innolux,g121i1-l01",
4114 .data = &innolux_g121i1_l01
4116 .compatible = "innolux,g121x1-l03",
4117 .data = &innolux_g121x1_l03,
4119 .compatible = "innolux,n116bge",
4120 .data = &innolux_n116bge,
4122 .compatible = "innolux,n156bge-l21",
4123 .data = &innolux_n156bge_l21,
4125 .compatible = "innolux,p120zdg-bf1",
4126 .data = &innolux_p120zdg_bf1,
4128 .compatible = "innolux,zj070na-01p",
4129 .data = &innolux_zj070na_01p,
4131 .compatible = "ivo,m133nwf4-r0",
4132 .data = &ivo_m133nwf4_r0,
4134 .compatible = "kingdisplay,kd116n21-30nv-a010",
4135 .data = &kingdisplay_kd116n21_30nv_a010,
4137 .compatible = "koe,tx14d24vm1bpa",
4138 .data = &koe_tx14d24vm1bpa,
4140 .compatible = "koe,tx26d202vm0bwa",
4141 .data = &koe_tx26d202vm0bwa,
4143 .compatible = "koe,tx31d200vm0baa",
4144 .data = &koe_tx31d200vm0baa,
4146 .compatible = "kyo,tcg121xglp",
4147 .data = &kyo_tcg121xglp,
4149 .compatible = "lemaker,bl035-rgb-002",
4150 .data = &lemaker_bl035_rgb_002,
4152 .compatible = "lg,lb070wv8",
4153 .data = &lg_lb070wv8,
4155 .compatible = "lg,lp079qx1-sp0v",
4156 .data = &lg_lp079qx1_sp0v,
4158 .compatible = "lg,lp097qx1-spa1",
4159 .data = &lg_lp097qx1_spa1,
4161 .compatible = "lg,lp120up1",
4162 .data = &lg_lp120up1,
4164 .compatible = "lg,lp129qe",
4165 .data = &lg_lp129qe,
4167 .compatible = "logicpd,type28",
4168 .data = &logicpd_type_28,
4170 .compatible = "logictechno,lt161010-2nhc",
4171 .data = &logictechno_lt161010_2nh,
4173 .compatible = "logictechno,lt161010-2nhr",
4174 .data = &logictechno_lt161010_2nh,
4176 .compatible = "logictechno,lt170410-2whc",
4177 .data = &logictechno_lt170410_2whc,
4179 .compatible = "mitsubishi,aa070mc01-ca1",
4180 .data = &mitsubishi_aa070mc01,
4182 .compatible = "nec,nl12880bc20-05",
4183 .data = &nec_nl12880bc20_05,
4185 .compatible = "nec,nl4827hc19-05b",
4186 .data = &nec_nl4827hc19_05b,
4188 .compatible = "netron-dy,e231732",
4189 .data = &netron_dy_e231732,
4191 .compatible = "neweast,wjfh116008a",
4192 .data = &neweast_wjfh116008a,
4194 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4195 .data = &newhaven_nhd_43_480272ef_atxl,
4197 .compatible = "nlt,nl192108ac18-02d",
4198 .data = &nlt_nl192108ac18_02d,
4200 .compatible = "nvd,9128",
4203 .compatible = "okaya,rs800480t-7x0gp",
4204 .data = &okaya_rs800480t_7x0gp,
4206 .compatible = "olimex,lcd-olinuxino-43-ts",
4207 .data = &olimex_lcd_olinuxino_43ts,
4209 .compatible = "ontat,yx700wv03",
4210 .data = &ontat_yx700wv03,
4212 .compatible = "ortustech,com37h3m05dtc",
4213 .data = &ortustech_com37h3m,
4215 .compatible = "ortustech,com37h3m99dtc",
4216 .data = &ortustech_com37h3m,
4218 .compatible = "ortustech,com43h4m85ulc",
4219 .data = &ortustech_com43h4m85ulc,
4221 .compatible = "osddisplays,osd070t1718-19ts",
4222 .data = &osddisplays_osd070t1718_19ts,
4224 .compatible = "pda,91-00156-a0",
4225 .data = &pda_91_00156_a0,
4227 .compatible = "powertip,ph800480t013-idf02",
4228 .data = &powertip_ph800480t013_idf02,
4230 .compatible = "qiaodian,qd43003c0-40",
4231 .data = &qd43003c0_40,
4233 .compatible = "rocktech,rk070er9427",
4234 .data = &rocktech_rk070er9427,
4236 .compatible = "rocktech,rk101ii01d-ct",
4237 .data = &rocktech_rk101ii01d_ct,
4239 .compatible = "samsung,lsn122dl01-c01",
4240 .data = &samsung_lsn122dl01_c01,
4242 .compatible = "samsung,ltn101nt05",
4243 .data = &samsung_ltn101nt05,
4245 .compatible = "samsung,ltn140at29-301",
4246 .data = &samsung_ltn140at29_301,
4248 .compatible = "satoz,sat050at40h12r2",
4249 .data = &satoz_sat050at40h12r2,
4251 .compatible = "sharp,ld-d5116z01b",
4252 .data = &sharp_ld_d5116z01b,
4254 .compatible = "sharp,lq035q7db03",
4255 .data = &sharp_lq035q7db03,
4257 .compatible = "sharp,lq070y3dg3b",
4258 .data = &sharp_lq070y3dg3b,
4260 .compatible = "sharp,lq101k1ly04",
4261 .data = &sharp_lq101k1ly04,
4263 .compatible = "sharp,lq123p1jx31",
4264 .data = &sharp_lq123p1jx31,
4266 .compatible = "sharp,ls020b1dd01d",
4267 .data = &sharp_ls020b1dd01d,
4269 .compatible = "shelly,sca07010-bfn-lnn",
4270 .data = &shelly_sca07010_bfn_lnn,
4272 .compatible = "starry,kr070pe2t",
4273 .data = &starry_kr070pe2t,
4275 .compatible = "starry,kr122ea0sra",
4276 .data = &starry_kr122ea0sra,
4278 .compatible = "tfc,s9700rtwv43tr-01b",
4279 .data = &tfc_s9700rtwv43tr_01b,
4281 .compatible = "tianma,tm070jdhg30",
4282 .data = &tianma_tm070jdhg30,
4284 .compatible = "tianma,tm070jvhg33",
4285 .data = &tianma_tm070jvhg33,
4287 .compatible = "tianma,tm070rvhg71",
4288 .data = &tianma_tm070rvhg71,
4290 .compatible = "ti,nspire-cx-lcd-panel",
4291 .data = &ti_nspire_cx_lcd_panel,
4293 .compatible = "ti,nspire-classic-lcd-panel",
4294 .data = &ti_nspire_classic_lcd_panel,
4296 .compatible = "toshiba,lt089ac29000",
4297 .data = &toshiba_lt089ac29000,
4299 .compatible = "tpk,f07a-0102",
4300 .data = &tpk_f07a_0102,
4302 .compatible = "tpk,f10a-0102",
4303 .data = &tpk_f10a_0102,
4305 .compatible = "urt,umsh-8596md-t",
4306 .data = &urt_umsh_8596md_parallel,
4308 .compatible = "urt,umsh-8596md-1t",
4309 .data = &urt_umsh_8596md_parallel,
4311 .compatible = "urt,umsh-8596md-7t",
4312 .data = &urt_umsh_8596md_parallel,
4314 .compatible = "urt,umsh-8596md-11t",
4315 .data = &urt_umsh_8596md_lvds,
4317 .compatible = "urt,umsh-8596md-19t",
4318 .data = &urt_umsh_8596md_lvds,
4320 .compatible = "urt,umsh-8596md-20t",
4321 .data = &urt_umsh_8596md_parallel,
4323 .compatible = "vxt,vl050-8048nt-c01",
4324 .data = &vl050_8048nt_c01,
4326 .compatible = "winstar,wf35ltiacd",
4327 .data = &winstar_wf35ltiacd,
4329 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4330 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4332 /* Must be the last entry */
4333 .compatible = "panel-dpi",
4339 MODULE_DEVICE_TABLE(of, platform_of_match);
4341 static int panel_simple_platform_probe(struct platform_device *pdev)
4343 const struct of_device_id *id;
4345 id = of_match_node(platform_of_match, pdev->dev.of_node);
4349 return panel_simple_probe(&pdev->dev, id->data);
4352 static int panel_simple_platform_remove(struct platform_device *pdev)
4354 return panel_simple_remove(&pdev->dev);
4357 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4359 panel_simple_shutdown(&pdev->dev);
4362 static struct platform_driver panel_simple_platform_driver = {
4364 .name = "panel-simple",
4365 .of_match_table = platform_of_match,
4367 .probe = panel_simple_platform_probe,
4368 .remove = panel_simple_platform_remove,
4369 .shutdown = panel_simple_platform_shutdown,
4372 struct panel_desc_dsi {
4373 struct panel_desc desc;
4375 unsigned long flags;
4376 enum mipi_dsi_pixel_format format;
4380 static const struct drm_display_mode auo_b080uan01_mode = {
4383 .hsync_start = 1200 + 62,
4384 .hsync_end = 1200 + 62 + 4,
4385 .htotal = 1200 + 62 + 4 + 62,
4387 .vsync_start = 1920 + 9,
4388 .vsync_end = 1920 + 9 + 2,
4389 .vtotal = 1920 + 9 + 2 + 8,
4392 static const struct panel_desc_dsi auo_b080uan01 = {
4394 .modes = &auo_b080uan01_mode,
4401 .connector_type = DRM_MODE_CONNECTOR_DSI,
4403 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4404 .format = MIPI_DSI_FMT_RGB888,
4408 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4411 .hsync_start = 1200 + 120,
4412 .hsync_end = 1200 + 120 + 20,
4413 .htotal = 1200 + 120 + 20 + 21,
4415 .vsync_start = 1920 + 21,
4416 .vsync_end = 1920 + 21 + 3,
4417 .vtotal = 1920 + 21 + 3 + 18,
4418 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4421 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4423 .modes = &boe_tv080wum_nl0_mode,
4429 .connector_type = DRM_MODE_CONNECTOR_DSI,
4431 .flags = MIPI_DSI_MODE_VIDEO |
4432 MIPI_DSI_MODE_VIDEO_BURST |
4433 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4434 .format = MIPI_DSI_FMT_RGB888,
4438 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4441 .hsync_start = 800 + 32,
4442 .hsync_end = 800 + 32 + 1,
4443 .htotal = 800 + 32 + 1 + 57,
4445 .vsync_start = 1280 + 28,
4446 .vsync_end = 1280 + 28 + 1,
4447 .vtotal = 1280 + 28 + 1 + 14,
4450 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4452 .modes = &lg_ld070wx3_sl01_mode,
4459 .connector_type = DRM_MODE_CONNECTOR_DSI,
4461 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4462 .format = MIPI_DSI_FMT_RGB888,
4466 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4469 .hsync_start = 720 + 12,
4470 .hsync_end = 720 + 12 + 4,
4471 .htotal = 720 + 12 + 4 + 112,
4473 .vsync_start = 1280 + 8,
4474 .vsync_end = 1280 + 8 + 4,
4475 .vtotal = 1280 + 8 + 4 + 12,
4478 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4480 .modes = &lg_lh500wx1_sd03_mode,
4487 .connector_type = DRM_MODE_CONNECTOR_DSI,
4489 .flags = MIPI_DSI_MODE_VIDEO,
4490 .format = MIPI_DSI_FMT_RGB888,
4494 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4497 .hsync_start = 1920 + 154,
4498 .hsync_end = 1920 + 154 + 16,
4499 .htotal = 1920 + 154 + 16 + 32,
4501 .vsync_start = 1200 + 17,
4502 .vsync_end = 1200 + 17 + 2,
4503 .vtotal = 1200 + 17 + 2 + 16,
4506 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4508 .modes = &panasonic_vvx10f004b00_mode,
4515 .connector_type = DRM_MODE_CONNECTOR_DSI,
4517 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4518 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4519 .format = MIPI_DSI_FMT_RGB888,
4523 static const struct drm_display_mode lg_acx467akm_7_mode = {
4526 .hsync_start = 1080 + 2,
4527 .hsync_end = 1080 + 2 + 2,
4528 .htotal = 1080 + 2 + 2 + 2,
4530 .vsync_start = 1920 + 2,
4531 .vsync_end = 1920 + 2 + 2,
4532 .vtotal = 1920 + 2 + 2 + 2,
4535 static const struct panel_desc_dsi lg_acx467akm_7 = {
4537 .modes = &lg_acx467akm_7_mode,
4544 .connector_type = DRM_MODE_CONNECTOR_DSI,
4547 .format = MIPI_DSI_FMT_RGB888,
4551 static const struct drm_display_mode osd101t2045_53ts_mode = {
4554 .hsync_start = 1920 + 112,
4555 .hsync_end = 1920 + 112 + 16,
4556 .htotal = 1920 + 112 + 16 + 32,
4558 .vsync_start = 1200 + 16,
4559 .vsync_end = 1200 + 16 + 2,
4560 .vtotal = 1200 + 16 + 2 + 16,
4561 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4564 static const struct panel_desc_dsi osd101t2045_53ts = {
4566 .modes = &osd101t2045_53ts_mode,
4573 .connector_type = DRM_MODE_CONNECTOR_DSI,
4575 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4576 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4577 MIPI_DSI_MODE_EOT_PACKET,
4578 .format = MIPI_DSI_FMT_RGB888,
4582 static const struct of_device_id dsi_of_match[] = {
4584 .compatible = "auo,b080uan01",
4585 .data = &auo_b080uan01
4587 .compatible = "boe,tv080wum-nl0",
4588 .data = &boe_tv080wum_nl0
4590 .compatible = "lg,ld070wx3-sl01",
4591 .data = &lg_ld070wx3_sl01
4593 .compatible = "lg,lh500wx1-sd03",
4594 .data = &lg_lh500wx1_sd03
4596 .compatible = "panasonic,vvx10f004b00",
4597 .data = &panasonic_vvx10f004b00
4599 .compatible = "lg,acx467akm-7",
4600 .data = &lg_acx467akm_7
4602 .compatible = "osddisplays,osd101t2045-53ts",
4603 .data = &osd101t2045_53ts
4608 MODULE_DEVICE_TABLE(of, dsi_of_match);
4610 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4612 const struct panel_desc_dsi *desc;
4613 const struct of_device_id *id;
4616 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4622 err = panel_simple_probe(&dsi->dev, &desc->desc);
4626 dsi->mode_flags = desc->flags;
4627 dsi->format = desc->format;
4628 dsi->lanes = desc->lanes;
4630 err = mipi_dsi_attach(dsi);
4632 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4634 drm_panel_remove(&panel->base);
4640 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4644 err = mipi_dsi_detach(dsi);
4646 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4648 return panel_simple_remove(&dsi->dev);
4651 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4653 panel_simple_shutdown(&dsi->dev);
4656 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4658 .name = "panel-simple-dsi",
4659 .of_match_table = dsi_of_match,
4661 .probe = panel_simple_dsi_probe,
4662 .remove = panel_simple_dsi_remove,
4663 .shutdown = panel_simple_dsi_shutdown,
4666 static int __init panel_simple_init(void)
4670 err = platform_driver_register(&panel_simple_platform_driver);
4674 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4675 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4682 module_init(panel_simple_init);
4684 static void __exit panel_simple_exit(void)
4686 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4687 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4689 platform_driver_unregister(&panel_simple_platform_driver);
4691 module_exit(panel_simple_exit);
4693 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4694 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4695 MODULE_LICENSE("GPL and additional rights");