2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/videomode.h>
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
60 * Plug Detect isn't used.
61 * @enable: the time (in milliseconds) that it takes for the panel to
62 * display the first valid frame after starting to receive
64 * @disable: the time (in milliseconds) that it takes for the panel to
65 * turn the display off (no content is visible)
66 * @unprepare: the time (in milliseconds) that it takes for the panel
67 * to power itself down completely
71 unsigned int hpd_absent_delay;
74 unsigned int unprepare;
82 struct drm_panel base;
87 const struct panel_desc *desc;
89 struct backlight_device *backlight;
90 struct regulator *supply;
91 struct i2c_adapter *ddc;
93 struct gpio_desc *enable_gpio;
96 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
98 return container_of(panel, struct panel_simple, base);
101 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
103 struct drm_connector *connector = panel->base.connector;
104 struct drm_device *drm = panel->base.drm;
105 struct drm_display_mode *mode;
106 unsigned int i, num = 0;
111 for (i = 0; i < panel->desc->num_timings; i++) {
112 const struct display_timing *dt = &panel->desc->timings[i];
115 videomode_from_timing(dt, &vm);
116 mode = drm_mode_create(drm);
118 dev_err(drm->dev, "failed to add mode %ux%u\n",
119 dt->hactive.typ, dt->vactive.typ);
123 drm_display_mode_from_videomode(&vm, mode);
125 mode->type |= DRM_MODE_TYPE_DRIVER;
127 if (panel->desc->num_timings == 1)
128 mode->type |= DRM_MODE_TYPE_PREFERRED;
130 drm_mode_probed_add(connector, mode);
134 for (i = 0; i < panel->desc->num_modes; i++) {
135 const struct drm_display_mode *m = &panel->desc->modes[i];
137 mode = drm_mode_duplicate(drm, m);
139 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
140 m->hdisplay, m->vdisplay, m->vrefresh);
144 mode->type |= DRM_MODE_TYPE_DRIVER;
146 if (panel->desc->num_modes == 1)
147 mode->type |= DRM_MODE_TYPE_PREFERRED;
149 drm_mode_set_name(mode);
151 drm_mode_probed_add(connector, mode);
155 connector->display_info.bpc = panel->desc->bpc;
156 connector->display_info.width_mm = panel->desc->size.width;
157 connector->display_info.height_mm = panel->desc->size.height;
158 if (panel->desc->bus_format)
159 drm_display_info_set_bus_formats(&connector->display_info,
160 &panel->desc->bus_format, 1);
161 connector->display_info.bus_flags = panel->desc->bus_flags;
166 static int panel_simple_disable(struct drm_panel *panel)
168 struct panel_simple *p = to_panel_simple(panel);
174 p->backlight->props.power = FB_BLANK_POWERDOWN;
175 p->backlight->props.state |= BL_CORE_FBBLANK;
176 backlight_update_status(p->backlight);
179 if (p->desc->delay.disable)
180 msleep(p->desc->delay.disable);
187 static int panel_simple_unprepare(struct drm_panel *panel)
189 struct panel_simple *p = to_panel_simple(panel);
194 gpiod_set_value_cansleep(p->enable_gpio, 0);
196 regulator_disable(p->supply);
198 if (p->desc->delay.unprepare)
199 msleep(p->desc->delay.unprepare);
206 static int panel_simple_prepare(struct drm_panel *panel)
208 struct panel_simple *p = to_panel_simple(panel);
215 err = regulator_enable(p->supply);
217 dev_err(panel->dev, "failed to enable supply: %d\n", err);
221 gpiod_set_value_cansleep(p->enable_gpio, 1);
223 delay = p->desc->delay.prepare;
225 delay += p->desc->delay.hpd_absent_delay;
234 static int panel_simple_enable(struct drm_panel *panel)
236 struct panel_simple *p = to_panel_simple(panel);
241 if (p->desc->delay.enable)
242 msleep(p->desc->delay.enable);
245 p->backlight->props.state &= ~BL_CORE_FBBLANK;
246 p->backlight->props.power = FB_BLANK_UNBLANK;
247 backlight_update_status(p->backlight);
255 static int panel_simple_get_modes(struct drm_panel *panel)
257 struct panel_simple *p = to_panel_simple(panel);
260 /* probe EDID if a DDC bus is available */
262 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
263 drm_connector_update_edid_property(panel->connector, edid);
265 num += drm_add_edid_modes(panel->connector, edid);
270 /* add hard-coded panel modes */
271 num += panel_simple_get_fixed_modes(p);
276 static int panel_simple_get_timings(struct drm_panel *panel,
277 unsigned int num_timings,
278 struct display_timing *timings)
280 struct panel_simple *p = to_panel_simple(panel);
283 if (p->desc->num_timings < num_timings)
284 num_timings = p->desc->num_timings;
287 for (i = 0; i < num_timings; i++)
288 timings[i] = p->desc->timings[i];
290 return p->desc->num_timings;
293 static const struct drm_panel_funcs panel_simple_funcs = {
294 .disable = panel_simple_disable,
295 .unprepare = panel_simple_unprepare,
296 .prepare = panel_simple_prepare,
297 .enable = panel_simple_enable,
298 .get_modes = panel_simple_get_modes,
299 .get_timings = panel_simple_get_timings,
302 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
304 struct device_node *backlight, *ddc;
305 struct panel_simple *panel;
308 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
312 panel->enabled = false;
313 panel->prepared = false;
316 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
318 panel->supply = devm_regulator_get(dev, "power");
319 if (IS_ERR(panel->supply))
320 return PTR_ERR(panel->supply);
322 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
324 if (IS_ERR(panel->enable_gpio)) {
325 err = PTR_ERR(panel->enable_gpio);
326 if (err != -EPROBE_DEFER)
327 dev_err(dev, "failed to request GPIO: %d\n", err);
331 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
333 panel->backlight = of_find_backlight_by_node(backlight);
334 of_node_put(backlight);
336 if (!panel->backlight)
337 return -EPROBE_DEFER;
340 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
342 panel->ddc = of_find_i2c_adapter_by_node(ddc);
351 drm_panel_init(&panel->base);
352 panel->base.dev = dev;
353 panel->base.funcs = &panel_simple_funcs;
355 err = drm_panel_add(&panel->base);
359 dev_set_drvdata(dev, panel);
365 put_device(&panel->ddc->dev);
367 if (panel->backlight)
368 put_device(&panel->backlight->dev);
373 static int panel_simple_remove(struct device *dev)
375 struct panel_simple *panel = dev_get_drvdata(dev);
377 drm_panel_remove(&panel->base);
379 panel_simple_disable(&panel->base);
380 panel_simple_unprepare(&panel->base);
383 put_device(&panel->ddc->dev);
385 if (panel->backlight)
386 put_device(&panel->backlight->dev);
391 static void panel_simple_shutdown(struct device *dev)
393 struct panel_simple *panel = dev_get_drvdata(dev);
395 panel_simple_disable(&panel->base);
396 panel_simple_unprepare(&panel->base);
399 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
402 .hsync_start = 480 + 2,
403 .hsync_end = 480 + 2 + 41,
404 .htotal = 480 + 2 + 41 + 2,
406 .vsync_start = 272 + 2,
407 .vsync_end = 272 + 2 + 10,
408 .vtotal = 272 + 2 + 10 + 2,
410 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
413 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
414 .modes = &ire_am_480272h3tmqw_t01h_mode,
421 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
424 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
427 .hsync_start = 800 + 0,
428 .hsync_end = 800 + 0 + 255,
429 .htotal = 800 + 0 + 255 + 0,
431 .vsync_start = 480 + 2,
432 .vsync_end = 480 + 2 + 45,
433 .vtotal = 480 + 2 + 45 + 0,
435 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
438 static const struct panel_desc ampire_am800480r3tmqwa1h = {
439 .modes = &ire_am800480r3tmqwa1h_mode,
446 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
449 static const struct drm_display_mode auo_b101aw03_mode = {
452 .hsync_start = 1024 + 156,
453 .hsync_end = 1024 + 156 + 8,
454 .htotal = 1024 + 156 + 8 + 156,
456 .vsync_start = 600 + 16,
457 .vsync_end = 600 + 16 + 6,
458 .vtotal = 600 + 16 + 6 + 16,
462 static const struct panel_desc auo_b101aw03 = {
463 .modes = &auo_b101aw03_mode,
472 static const struct drm_display_mode auo_b101ean01_mode = {
475 .hsync_start = 1280 + 119,
476 .hsync_end = 1280 + 119 + 32,
477 .htotal = 1280 + 119 + 32 + 21,
479 .vsync_start = 800 + 4,
480 .vsync_end = 800 + 4 + 20,
481 .vtotal = 800 + 4 + 20 + 8,
485 static const struct panel_desc auo_b101ean01 = {
486 .modes = &auo_b101ean01_mode,
495 static const struct drm_display_mode auo_b101xtn01_mode = {
498 .hsync_start = 1366 + 20,
499 .hsync_end = 1366 + 20 + 70,
500 .htotal = 1366 + 20 + 70,
502 .vsync_start = 768 + 14,
503 .vsync_end = 768 + 14 + 42,
504 .vtotal = 768 + 14 + 42,
506 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
509 static const struct panel_desc auo_b101xtn01 = {
510 .modes = &auo_b101xtn01_mode,
519 static const struct drm_display_mode auo_b116xw03_mode = {
522 .hsync_start = 1366 + 40,
523 .hsync_end = 1366 + 40 + 40,
524 .htotal = 1366 + 40 + 40 + 32,
526 .vsync_start = 768 + 10,
527 .vsync_end = 768 + 10 + 12,
528 .vtotal = 768 + 10 + 12 + 6,
532 static const struct panel_desc auo_b116xw03 = {
533 .modes = &auo_b116xw03_mode,
542 static const struct drm_display_mode auo_b133xtn01_mode = {
545 .hsync_start = 1366 + 48,
546 .hsync_end = 1366 + 48 + 32,
547 .htotal = 1366 + 48 + 32 + 20,
549 .vsync_start = 768 + 3,
550 .vsync_end = 768 + 3 + 6,
551 .vtotal = 768 + 3 + 6 + 13,
555 static const struct panel_desc auo_b133xtn01 = {
556 .modes = &auo_b133xtn01_mode,
565 static const struct drm_display_mode auo_b133htn01_mode = {
568 .hsync_start = 1920 + 172,
569 .hsync_end = 1920 + 172 + 80,
570 .htotal = 1920 + 172 + 80 + 60,
572 .vsync_start = 1080 + 25,
573 .vsync_end = 1080 + 25 + 10,
574 .vtotal = 1080 + 25 + 10 + 10,
578 static const struct panel_desc auo_b133htn01 = {
579 .modes = &auo_b133htn01_mode,
593 static const struct display_timing auo_g070vvn01_timings = {
594 .pixelclock = { 33300000, 34209000, 45000000 },
595 .hactive = { 800, 800, 800 },
596 .hfront_porch = { 20, 40, 200 },
597 .hback_porch = { 87, 40, 1 },
598 .hsync_len = { 1, 48, 87 },
599 .vactive = { 480, 480, 480 },
600 .vfront_porch = { 5, 13, 200 },
601 .vback_porch = { 31, 31, 29 },
602 .vsync_len = { 1, 1, 3 },
605 static const struct panel_desc auo_g070vvn01 = {
606 .timings = &auo_g070vvn01_timings,
621 static const struct drm_display_mode auo_g101evn010_mode = {
624 .hsync_start = 1280 + 82,
625 .hsync_end = 1280 + 82 + 2,
626 .htotal = 1280 + 82 + 2 + 84,
628 .vsync_start = 800 + 8,
629 .vsync_end = 800 + 8 + 2,
630 .vtotal = 800 + 8 + 2 + 6,
634 static const struct panel_desc auo_g101evn010 = {
635 .modes = &auo_g101evn010_mode,
642 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
645 static const struct drm_display_mode auo_g104sn02_mode = {
648 .hsync_start = 800 + 40,
649 .hsync_end = 800 + 40 + 216,
650 .htotal = 800 + 40 + 216 + 128,
652 .vsync_start = 600 + 10,
653 .vsync_end = 600 + 10 + 35,
654 .vtotal = 600 + 10 + 35 + 2,
658 static const struct panel_desc auo_g104sn02 = {
659 .modes = &auo_g104sn02_mode,
668 static const struct display_timing auo_g133han01_timings = {
669 .pixelclock = { 134000000, 141200000, 149000000 },
670 .hactive = { 1920, 1920, 1920 },
671 .hfront_porch = { 39, 58, 77 },
672 .hback_porch = { 59, 88, 117 },
673 .hsync_len = { 28, 42, 56 },
674 .vactive = { 1080, 1080, 1080 },
675 .vfront_porch = { 3, 8, 11 },
676 .vback_porch = { 5, 14, 19 },
677 .vsync_len = { 4, 14, 19 },
680 static const struct panel_desc auo_g133han01 = {
681 .timings = &auo_g133han01_timings,
694 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
697 static const struct display_timing auo_g185han01_timings = {
698 .pixelclock = { 120000000, 144000000, 175000000 },
699 .hactive = { 1920, 1920, 1920 },
700 .hfront_porch = { 18, 60, 74 },
701 .hback_porch = { 12, 44, 54 },
702 .hsync_len = { 10, 24, 32 },
703 .vactive = { 1080, 1080, 1080 },
704 .vfront_porch = { 6, 10, 40 },
705 .vback_porch = { 2, 5, 20 },
706 .vsync_len = { 2, 5, 20 },
709 static const struct panel_desc auo_g185han01 = {
710 .timings = &auo_g185han01_timings,
723 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
726 static const struct display_timing auo_p320hvn03_timings = {
727 .pixelclock = { 106000000, 148500000, 164000000 },
728 .hactive = { 1920, 1920, 1920 },
729 .hfront_porch = { 25, 50, 130 },
730 .hback_porch = { 25, 50, 130 },
731 .hsync_len = { 20, 40, 105 },
732 .vactive = { 1080, 1080, 1080 },
733 .vfront_porch = { 8, 17, 150 },
734 .vback_porch = { 8, 17, 150 },
735 .vsync_len = { 4, 11, 100 },
738 static const struct panel_desc auo_p320hvn03 = {
739 .timings = &auo_p320hvn03_timings,
751 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
754 static const struct drm_display_mode auo_t215hvn01_mode = {
757 .hsync_start = 1920 + 88,
758 .hsync_end = 1920 + 88 + 44,
759 .htotal = 1920 + 88 + 44 + 148,
761 .vsync_start = 1080 + 4,
762 .vsync_end = 1080 + 4 + 5,
763 .vtotal = 1080 + 4 + 5 + 36,
767 static const struct panel_desc auo_t215hvn01 = {
768 .modes = &auo_t215hvn01_mode,
781 static const struct drm_display_mode avic_tm070ddh03_mode = {
784 .hsync_start = 1024 + 160,
785 .hsync_end = 1024 + 160 + 4,
786 .htotal = 1024 + 160 + 4 + 156,
788 .vsync_start = 600 + 17,
789 .vsync_end = 600 + 17 + 1,
790 .vtotal = 600 + 17 + 1 + 17,
794 static const struct panel_desc avic_tm070ddh03 = {
795 .modes = &avic_tm070ddh03_mode,
809 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
812 .hsync_start = 800 + 40,
813 .hsync_end = 800 + 40 + 48,
814 .htotal = 800 + 40 + 48 + 40,
816 .vsync_start = 480 + 13,
817 .vsync_end = 480 + 13 + 3,
818 .vtotal = 480 + 13 + 3 + 29,
821 static const struct panel_desc bananapi_s070wv20_ct16 = {
822 .modes = &bananapi_s070wv20_ct16_mode,
831 static const struct drm_display_mode boe_hv070wsa_mode = {
834 .hsync_start = 1024 + 30,
835 .hsync_end = 1024 + 30 + 30,
836 .htotal = 1024 + 30 + 30 + 30,
838 .vsync_start = 600 + 10,
839 .vsync_end = 600 + 10 + 10,
840 .vtotal = 600 + 10 + 10 + 10,
844 static const struct panel_desc boe_hv070wsa = {
845 .modes = &boe_hv070wsa_mode,
853 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
857 .hsync_start = 1280 + 48,
858 .hsync_end = 1280 + 48 + 32,
859 .htotal = 1280 + 48 + 32 + 80,
861 .vsync_start = 800 + 3,
862 .vsync_end = 800 + 3 + 5,
863 .vtotal = 800 + 3 + 5 + 24,
869 .hsync_start = 1280 + 48,
870 .hsync_end = 1280 + 48 + 32,
871 .htotal = 1280 + 48 + 32 + 80,
873 .vsync_start = 800 + 3,
874 .vsync_end = 800 + 3 + 5,
875 .vtotal = 800 + 3 + 5 + 24,
880 static const struct panel_desc boe_nv101wxmn51 = {
881 .modes = boe_nv101wxmn51_modes,
882 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
895 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
898 .hsync_start = 480 + 5,
899 .hsync_end = 480 + 5 + 5,
900 .htotal = 480 + 5 + 5 + 40,
902 .vsync_start = 272 + 8,
903 .vsync_end = 272 + 8 + 8,
904 .vtotal = 272 + 8 + 8 + 8,
906 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
909 static const struct panel_desc cdtech_s043wq26h_ct7 = {
910 .modes = &cdtech_s043wq26h_ct7_mode,
917 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
920 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
923 .hsync_start = 800 + 40,
924 .hsync_end = 800 + 40 + 40,
925 .htotal = 800 + 40 + 40 + 48,
927 .vsync_start = 480 + 29,
928 .vsync_end = 480 + 29 + 13,
929 .vtotal = 480 + 29 + 13 + 3,
931 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
934 static const struct panel_desc cdtech_s070wv95_ct16 = {
935 .modes = &cdtech_s070wv95_ct16_mode,
944 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
947 .hsync_start = 800 + 49,
948 .hsync_end = 800 + 49 + 33,
949 .htotal = 800 + 49 + 33 + 17,
951 .vsync_start = 1280 + 1,
952 .vsync_end = 1280 + 1 + 7,
953 .vtotal = 1280 + 1 + 7 + 15,
955 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
958 static const struct panel_desc chunghwa_claa070wp03xg = {
959 .modes = &chunghwa_claa070wp03xg_mode,
968 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
971 .hsync_start = 1366 + 58,
972 .hsync_end = 1366 + 58 + 58,
973 .htotal = 1366 + 58 + 58 + 58,
975 .vsync_start = 768 + 4,
976 .vsync_end = 768 + 4 + 4,
977 .vtotal = 768 + 4 + 4 + 4,
981 static const struct panel_desc chunghwa_claa101wa01a = {
982 .modes = &chunghwa_claa101wa01a_mode,
991 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
994 .hsync_start = 1366 + 48,
995 .hsync_end = 1366 + 48 + 32,
996 .htotal = 1366 + 48 + 32 + 20,
998 .vsync_start = 768 + 16,
999 .vsync_end = 768 + 16 + 8,
1000 .vtotal = 768 + 16 + 8 + 16,
1004 static const struct panel_desc chunghwa_claa101wb01 = {
1005 .modes = &chunghwa_claa101wb01_mode,
1014 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1017 .hsync_start = 800 + 40,
1018 .hsync_end = 800 + 40 + 128,
1019 .htotal = 800 + 40 + 128 + 88,
1021 .vsync_start = 480 + 10,
1022 .vsync_end = 480 + 10 + 2,
1023 .vtotal = 480 + 10 + 2 + 33,
1025 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1028 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1029 .modes = &dataimage_scf0700c48ggu18_mode,
1036 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1037 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1040 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1041 .pixelclock = { 45000000, 51200000, 57000000 },
1042 .hactive = { 1024, 1024, 1024 },
1043 .hfront_porch = { 100, 106, 113 },
1044 .hback_porch = { 100, 106, 113 },
1045 .hsync_len = { 100, 108, 114 },
1046 .vactive = { 600, 600, 600 },
1047 .vfront_porch = { 8, 11, 15 },
1048 .vback_porch = { 8, 11, 15 },
1049 .vsync_len = { 9, 13, 15 },
1050 .flags = DISPLAY_FLAGS_DE_HIGH,
1053 static const struct panel_desc dlc_dlc0700yzg_1 = {
1054 .timings = &dlc_dlc0700yzg_1_timing,
1066 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1069 static const struct display_timing dlc_dlc1010gig_timing = {
1070 .pixelclock = { 68900000, 71100000, 73400000 },
1071 .hactive = { 1280, 1280, 1280 },
1072 .hfront_porch = { 43, 53, 63 },
1073 .hback_porch = { 43, 53, 63 },
1074 .hsync_len = { 44, 54, 64 },
1075 .vactive = { 800, 800, 800 },
1076 .vfront_porch = { 5, 8, 11 },
1077 .vback_porch = { 5, 8, 11 },
1078 .vsync_len = { 5, 7, 11 },
1079 .flags = DISPLAY_FLAGS_DE_HIGH,
1082 static const struct panel_desc dlc_dlc1010gig = {
1083 .timings = &dlc_dlc1010gig_timing,
1096 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1099 static const struct drm_display_mode edt_et057090dhu_mode = {
1102 .hsync_start = 640 + 16,
1103 .hsync_end = 640 + 16 + 30,
1104 .htotal = 640 + 16 + 30 + 114,
1106 .vsync_start = 480 + 10,
1107 .vsync_end = 480 + 10 + 3,
1108 .vtotal = 480 + 10 + 3 + 32,
1110 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1113 static const struct panel_desc edt_et057090dhu = {
1114 .modes = &edt_et057090dhu_mode,
1121 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1122 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1125 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1128 .hsync_start = 800 + 40,
1129 .hsync_end = 800 + 40 + 128,
1130 .htotal = 800 + 40 + 128 + 88,
1132 .vsync_start = 480 + 10,
1133 .vsync_end = 480 + 10 + 2,
1134 .vtotal = 480 + 10 + 2 + 33,
1136 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1139 static const struct panel_desc edt_etm0700g0dh6 = {
1140 .modes = &edt_etm0700g0dh6_mode,
1147 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1148 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1151 static const struct panel_desc edt_etm0700g0bdh6 = {
1152 .modes = &edt_etm0700g0dh6_mode,
1159 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1160 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1163 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1166 .hsync_start = 800 + 168,
1167 .hsync_end = 800 + 168 + 64,
1168 .htotal = 800 + 168 + 64 + 88,
1170 .vsync_start = 480 + 37,
1171 .vsync_end = 480 + 37 + 2,
1172 .vtotal = 480 + 37 + 2 + 8,
1176 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1177 .modes = &foxlink_fl500wvr00_a0t_mode,
1184 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1187 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1190 .hsync_start = 480 + 5,
1191 .hsync_end = 480 + 5 + 1,
1192 .htotal = 480 + 5 + 1 + 40,
1194 .vsync_start = 272 + 8,
1195 .vsync_end = 272 + 8 + 1,
1196 .vtotal = 272 + 8 + 1 + 8,
1200 static const struct panel_desc giantplus_gpg482739qs5 = {
1201 .modes = &giantplus_gpg482739qs5_mode,
1208 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1211 static const struct display_timing hannstar_hsd070pww1_timing = {
1212 .pixelclock = { 64300000, 71100000, 82000000 },
1213 .hactive = { 1280, 1280, 1280 },
1214 .hfront_porch = { 1, 1, 10 },
1215 .hback_porch = { 1, 1, 10 },
1217 * According to the data sheet, the minimum horizontal blanking interval
1218 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1219 * minimum working horizontal blanking interval to be 60 clocks.
1221 .hsync_len = { 58, 158, 661 },
1222 .vactive = { 800, 800, 800 },
1223 .vfront_porch = { 1, 1, 10 },
1224 .vback_porch = { 1, 1, 10 },
1225 .vsync_len = { 1, 21, 203 },
1226 .flags = DISPLAY_FLAGS_DE_HIGH,
1229 static const struct panel_desc hannstar_hsd070pww1 = {
1230 .timings = &hannstar_hsd070pww1_timing,
1237 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1240 static const struct display_timing hannstar_hsd100pxn1_timing = {
1241 .pixelclock = { 55000000, 65000000, 75000000 },
1242 .hactive = { 1024, 1024, 1024 },
1243 .hfront_porch = { 40, 40, 40 },
1244 .hback_porch = { 220, 220, 220 },
1245 .hsync_len = { 20, 60, 100 },
1246 .vactive = { 768, 768, 768 },
1247 .vfront_porch = { 7, 7, 7 },
1248 .vback_porch = { 21, 21, 21 },
1249 .vsync_len = { 10, 10, 10 },
1250 .flags = DISPLAY_FLAGS_DE_HIGH,
1253 static const struct panel_desc hannstar_hsd100pxn1 = {
1254 .timings = &hannstar_hsd100pxn1_timing,
1261 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1264 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1267 .hsync_start = 800 + 85,
1268 .hsync_end = 800 + 85 + 86,
1269 .htotal = 800 + 85 + 86 + 85,
1271 .vsync_start = 480 + 16,
1272 .vsync_end = 480 + 16 + 13,
1273 .vtotal = 480 + 16 + 13 + 16,
1277 static const struct panel_desc hitachi_tx23d38vm0caa = {
1278 .modes = &hitachi_tx23d38vm0caa_mode,
1291 static const struct drm_display_mode innolux_at043tn24_mode = {
1294 .hsync_start = 480 + 2,
1295 .hsync_end = 480 + 2 + 41,
1296 .htotal = 480 + 2 + 41 + 2,
1298 .vsync_start = 272 + 2,
1299 .vsync_end = 272 + 2 + 10,
1300 .vtotal = 272 + 2 + 10 + 2,
1302 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1305 static const struct panel_desc innolux_at043tn24 = {
1306 .modes = &innolux_at043tn24_mode,
1313 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1314 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1317 static const struct drm_display_mode innolux_at070tn92_mode = {
1320 .hsync_start = 800 + 210,
1321 .hsync_end = 800 + 210 + 20,
1322 .htotal = 800 + 210 + 20 + 46,
1324 .vsync_start = 480 + 22,
1325 .vsync_end = 480 + 22 + 10,
1326 .vtotal = 480 + 22 + 23 + 10,
1330 static const struct panel_desc innolux_at070tn92 = {
1331 .modes = &innolux_at070tn92_mode,
1337 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1340 static const struct display_timing innolux_g070y2_l01_timing = {
1341 .pixelclock = { 28000000, 29500000, 32000000 },
1342 .hactive = { 800, 800, 800 },
1343 .hfront_porch = { 61, 91, 141 },
1344 .hback_porch = { 60, 90, 140 },
1345 .hsync_len = { 12, 12, 12 },
1346 .vactive = { 480, 480, 480 },
1347 .vfront_porch = { 4, 9, 30 },
1348 .vback_porch = { 4, 8, 28 },
1349 .vsync_len = { 2, 2, 2 },
1350 .flags = DISPLAY_FLAGS_DE_HIGH,
1353 static const struct panel_desc innolux_g070y2_l01 = {
1354 .timings = &innolux_g070y2_l01_timing,
1367 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1370 static const struct display_timing innolux_g101ice_l01_timing = {
1371 .pixelclock = { 60400000, 71100000, 74700000 },
1372 .hactive = { 1280, 1280, 1280 },
1373 .hfront_porch = { 41, 80, 100 },
1374 .hback_porch = { 40, 79, 99 },
1375 .hsync_len = { 1, 1, 1 },
1376 .vactive = { 800, 800, 800 },
1377 .vfront_porch = { 5, 11, 14 },
1378 .vback_porch = { 4, 11, 14 },
1379 .vsync_len = { 1, 1, 1 },
1380 .flags = DISPLAY_FLAGS_DE_HIGH,
1383 static const struct panel_desc innolux_g101ice_l01 = {
1384 .timings = &innolux_g101ice_l01_timing,
1395 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1398 static const struct display_timing innolux_g121i1_l01_timing = {
1399 .pixelclock = { 67450000, 71000000, 74550000 },
1400 .hactive = { 1280, 1280, 1280 },
1401 .hfront_porch = { 40, 80, 160 },
1402 .hback_porch = { 39, 79, 159 },
1403 .hsync_len = { 1, 1, 1 },
1404 .vactive = { 800, 800, 800 },
1405 .vfront_porch = { 5, 11, 100 },
1406 .vback_porch = { 4, 11, 99 },
1407 .vsync_len = { 1, 1, 1 },
1410 static const struct panel_desc innolux_g121i1_l01 = {
1411 .timings = &innolux_g121i1_l01_timing,
1422 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1425 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1428 .hsync_start = 1024 + 0,
1429 .hsync_end = 1024 + 1,
1430 .htotal = 1024 + 0 + 1 + 320,
1432 .vsync_start = 768 + 38,
1433 .vsync_end = 768 + 38 + 1,
1434 .vtotal = 768 + 38 + 1 + 0,
1436 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1439 static const struct panel_desc innolux_g121x1_l03 = {
1440 .modes = &innolux_g121x1_l03_mode,
1454 static const struct drm_display_mode innolux_n116bge_mode = {
1457 .hsync_start = 1366 + 136,
1458 .hsync_end = 1366 + 136 + 30,
1459 .htotal = 1366 + 136 + 30 + 60,
1461 .vsync_start = 768 + 8,
1462 .vsync_end = 768 + 8 + 12,
1463 .vtotal = 768 + 8 + 12 + 12,
1465 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1468 static const struct panel_desc innolux_n116bge = {
1469 .modes = &innolux_n116bge_mode,
1478 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1481 .hsync_start = 1366 + 16,
1482 .hsync_end = 1366 + 16 + 34,
1483 .htotal = 1366 + 16 + 34 + 50,
1485 .vsync_start = 768 + 2,
1486 .vsync_end = 768 + 2 + 6,
1487 .vtotal = 768 + 2 + 6 + 12,
1491 static const struct panel_desc innolux_n156bge_l21 = {
1492 .modes = &innolux_n156bge_l21_mode,
1501 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1504 .hsync_start = 2160 + 48,
1505 .hsync_end = 2160 + 48 + 32,
1506 .htotal = 2160 + 48 + 32 + 80,
1508 .vsync_start = 1440 + 3,
1509 .vsync_end = 1440 + 3 + 10,
1510 .vtotal = 1440 + 3 + 10 + 27,
1512 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1515 static const struct panel_desc innolux_p120zdg_bf1 = {
1516 .modes = &innolux_p120zdg_bf1_mode,
1524 .hpd_absent_delay = 200,
1529 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1532 .hsync_start = 1024 + 128,
1533 .hsync_end = 1024 + 128 + 64,
1534 .htotal = 1024 + 128 + 64 + 128,
1536 .vsync_start = 600 + 16,
1537 .vsync_end = 600 + 16 + 4,
1538 .vtotal = 600 + 16 + 4 + 16,
1542 static const struct panel_desc innolux_zj070na_01p = {
1543 .modes = &innolux_zj070na_01p_mode,
1552 static const struct display_timing koe_tx31d200vm0baa_timing = {
1553 .pixelclock = { 39600000, 43200000, 48000000 },
1554 .hactive = { 1280, 1280, 1280 },
1555 .hfront_porch = { 16, 36, 56 },
1556 .hback_porch = { 16, 36, 56 },
1557 .hsync_len = { 8, 8, 8 },
1558 .vactive = { 480, 480, 480 },
1559 .vfront_porch = { 6, 21, 33 },
1560 .vback_porch = { 6, 21, 33 },
1561 .vsync_len = { 8, 8, 8 },
1562 .flags = DISPLAY_FLAGS_DE_HIGH,
1565 static const struct panel_desc koe_tx31d200vm0baa = {
1566 .timings = &koe_tx31d200vm0baa_timing,
1573 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1576 static const struct display_timing kyo_tcg121xglp_timing = {
1577 .pixelclock = { 52000000, 65000000, 71000000 },
1578 .hactive = { 1024, 1024, 1024 },
1579 .hfront_porch = { 2, 2, 2 },
1580 .hback_porch = { 2, 2, 2 },
1581 .hsync_len = { 86, 124, 244 },
1582 .vactive = { 768, 768, 768 },
1583 .vfront_porch = { 2, 2, 2 },
1584 .vback_porch = { 2, 2, 2 },
1585 .vsync_len = { 6, 34, 73 },
1586 .flags = DISPLAY_FLAGS_DE_HIGH,
1589 static const struct panel_desc kyo_tcg121xglp = {
1590 .timings = &kyo_tcg121xglp_timing,
1597 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1600 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
1603 .hsync_start = 320 + 20,
1604 .hsync_end = 320 + 20 + 30,
1605 .htotal = 320 + 20 + 30 + 38,
1607 .vsync_start = 240 + 4,
1608 .vsync_end = 240 + 4 + 3,
1609 .vtotal = 240 + 4 + 3 + 15,
1613 static const struct panel_desc lemaker_bl035_rgb_002 = {
1614 .modes = &lemaker_bl035_rgb_002_mode,
1620 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1621 .bus_flags = DRM_BUS_FLAG_DE_LOW,
1624 static const struct drm_display_mode lg_lb070wv8_mode = {
1627 .hsync_start = 800 + 88,
1628 .hsync_end = 800 + 88 + 80,
1629 .htotal = 800 + 88 + 80 + 88,
1631 .vsync_start = 480 + 10,
1632 .vsync_end = 480 + 10 + 25,
1633 .vtotal = 480 + 10 + 25 + 10,
1637 static const struct panel_desc lg_lb070wv8 = {
1638 .modes = &lg_lb070wv8_mode,
1645 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1648 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1651 .hsync_start = 1536 + 12,
1652 .hsync_end = 1536 + 12 + 16,
1653 .htotal = 1536 + 12 + 16 + 48,
1655 .vsync_start = 2048 + 8,
1656 .vsync_end = 2048 + 8 + 4,
1657 .vtotal = 2048 + 8 + 4 + 8,
1659 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1662 static const struct panel_desc lg_lp079qx1_sp0v = {
1663 .modes = &lg_lp079qx1_sp0v_mode,
1671 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1674 .hsync_start = 2048 + 150,
1675 .hsync_end = 2048 + 150 + 5,
1676 .htotal = 2048 + 150 + 5 + 5,
1678 .vsync_start = 1536 + 3,
1679 .vsync_end = 1536 + 3 + 1,
1680 .vtotal = 1536 + 3 + 1 + 9,
1684 static const struct panel_desc lg_lp097qx1_spa1 = {
1685 .modes = &lg_lp097qx1_spa1_mode,
1693 static const struct drm_display_mode lg_lp120up1_mode = {
1696 .hsync_start = 1920 + 40,
1697 .hsync_end = 1920 + 40 + 40,
1698 .htotal = 1920 + 40 + 40+ 80,
1700 .vsync_start = 1280 + 4,
1701 .vsync_end = 1280 + 4 + 4,
1702 .vtotal = 1280 + 4 + 4 + 12,
1706 static const struct panel_desc lg_lp120up1 = {
1707 .modes = &lg_lp120up1_mode,
1716 static const struct drm_display_mode lg_lp129qe_mode = {
1719 .hsync_start = 2560 + 48,
1720 .hsync_end = 2560 + 48 + 32,
1721 .htotal = 2560 + 48 + 32 + 80,
1723 .vsync_start = 1700 + 3,
1724 .vsync_end = 1700 + 3 + 10,
1725 .vtotal = 1700 + 3 + 10 + 36,
1729 static const struct panel_desc lg_lp129qe = {
1730 .modes = &lg_lp129qe_mode,
1739 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
1742 .hsync_start = 800 + 0,
1743 .hsync_end = 800 + 1,
1744 .htotal = 800 + 0 + 1 + 160,
1746 .vsync_start = 480 + 0,
1747 .vsync_end = 480 + 48 + 1,
1748 .vtotal = 480 + 48 + 1 + 0,
1750 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1753 static const struct panel_desc mitsubishi_aa070mc01 = {
1754 .modes = &mitsubishi_aa070mc01_mode,
1767 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1768 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1771 static const struct display_timing nec_nl12880bc20_05_timing = {
1772 .pixelclock = { 67000000, 71000000, 75000000 },
1773 .hactive = { 1280, 1280, 1280 },
1774 .hfront_porch = { 2, 30, 30 },
1775 .hback_porch = { 6, 100, 100 },
1776 .hsync_len = { 2, 30, 30 },
1777 .vactive = { 800, 800, 800 },
1778 .vfront_porch = { 5, 5, 5 },
1779 .vback_porch = { 11, 11, 11 },
1780 .vsync_len = { 7, 7, 7 },
1783 static const struct panel_desc nec_nl12880bc20_05 = {
1784 .timings = &nec_nl12880bc20_05_timing,
1795 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1798 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1801 .hsync_start = 480 + 2,
1802 .hsync_end = 480 + 2 + 41,
1803 .htotal = 480 + 2 + 41 + 2,
1805 .vsync_start = 272 + 2,
1806 .vsync_end = 272 + 2 + 4,
1807 .vtotal = 272 + 2 + 4 + 2,
1809 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1812 static const struct panel_desc nec_nl4827hc19_05b = {
1813 .modes = &nec_nl4827hc19_05b_mode,
1820 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1821 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1824 static const struct drm_display_mode netron_dy_e231732_mode = {
1827 .hsync_start = 1024 + 160,
1828 .hsync_end = 1024 + 160 + 70,
1829 .htotal = 1024 + 160 + 70 + 90,
1831 .vsync_start = 600 + 127,
1832 .vsync_end = 600 + 127 + 20,
1833 .vtotal = 600 + 127 + 20 + 3,
1837 static const struct panel_desc netron_dy_e231732 = {
1838 .modes = &netron_dy_e231732_mode,
1844 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1847 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
1850 .hsync_start = 480 + 2,
1851 .hsync_end = 480 + 2 + 41,
1852 .htotal = 480 + 2 + 41 + 2,
1854 .vsync_start = 272 + 2,
1855 .vsync_end = 272 + 2 + 10,
1856 .vtotal = 272 + 2 + 10 + 2,
1858 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1861 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
1862 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
1869 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1870 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
1871 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
1874 static const struct display_timing nlt_nl192108ac18_02d_timing = {
1875 .pixelclock = { 130000000, 148350000, 163000000 },
1876 .hactive = { 1920, 1920, 1920 },
1877 .hfront_porch = { 80, 100, 100 },
1878 .hback_porch = { 100, 120, 120 },
1879 .hsync_len = { 50, 60, 60 },
1880 .vactive = { 1080, 1080, 1080 },
1881 .vfront_porch = { 12, 30, 30 },
1882 .vback_porch = { 4, 10, 10 },
1883 .vsync_len = { 4, 5, 5 },
1886 static const struct panel_desc nlt_nl192108ac18_02d = {
1887 .timings = &nlt_nl192108ac18_02d_timing,
1897 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1900 static const struct drm_display_mode nvd_9128_mode = {
1903 .hsync_start = 800 + 130,
1904 .hsync_end = 800 + 130 + 98,
1905 .htotal = 800 + 0 + 130 + 98,
1907 .vsync_start = 480 + 10,
1908 .vsync_end = 480 + 10 + 50,
1909 .vtotal = 480 + 0 + 10 + 50,
1912 static const struct panel_desc nvd_9128 = {
1913 .modes = &nvd_9128_mode,
1920 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1923 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1924 .pixelclock = { 30000000, 30000000, 40000000 },
1925 .hactive = { 800, 800, 800 },
1926 .hfront_porch = { 40, 40, 40 },
1927 .hback_porch = { 40, 40, 40 },
1928 .hsync_len = { 1, 48, 48 },
1929 .vactive = { 480, 480, 480 },
1930 .vfront_porch = { 13, 13, 13 },
1931 .vback_porch = { 29, 29, 29 },
1932 .vsync_len = { 3, 3, 3 },
1933 .flags = DISPLAY_FLAGS_DE_HIGH,
1936 static const struct panel_desc okaya_rs800480t_7x0gp = {
1937 .timings = &okaya_rs800480t_7x0gp_timing,
1950 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1953 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1956 .hsync_start = 480 + 5,
1957 .hsync_end = 480 + 5 + 30,
1958 .htotal = 480 + 5 + 30 + 10,
1960 .vsync_start = 272 + 8,
1961 .vsync_end = 272 + 8 + 5,
1962 .vtotal = 272 + 8 + 5 + 3,
1966 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1967 .modes = &olimex_lcd_olinuxino_43ts_mode,
1973 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1977 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1978 * pixel clocks, but this is the timing that was being used in the Adafruit
1979 * installation instructions.
1981 static const struct drm_display_mode ontat_yx700wv03_mode = {
1992 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1997 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1999 static const struct panel_desc ontat_yx700wv03 = {
2000 .modes = &ontat_yx700wv03_mode,
2007 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2010 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2013 .hsync_start = 480 + 10,
2014 .hsync_end = 480 + 10 + 10,
2015 .htotal = 480 + 10 + 10 + 15,
2017 .vsync_start = 800 + 3,
2018 .vsync_end = 800 + 3 + 3,
2019 .vtotal = 800 + 3 + 3 + 3,
2023 static const struct panel_desc ortustech_com43h4m85ulc = {
2024 .modes = &ortustech_com43h4m85ulc_mode,
2031 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2032 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2035 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2038 .hsync_start = 800 + 210,
2039 .hsync_end = 800 + 210 + 30,
2040 .htotal = 800 + 210 + 30 + 16,
2042 .vsync_start = 480 + 22,
2043 .vsync_end = 480 + 22 + 13,
2044 .vtotal = 480 + 22 + 13 + 10,
2046 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2049 static const struct panel_desc osddisplays_osd070t1718_19ts = {
2050 .modes = &osddisplays_osd070t1718_19ts_mode,
2057 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2058 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2061 static const struct drm_display_mode pda_91_00156_a0_mode = {
2064 .hsync_start = 800 + 1,
2065 .hsync_end = 800 + 1 + 64,
2066 .htotal = 800 + 1 + 64 + 64,
2068 .vsync_start = 480 + 1,
2069 .vsync_end = 480 + 1 + 23,
2070 .vtotal = 480 + 1 + 23 + 22,
2074 static const struct panel_desc pda_91_00156_a0 = {
2075 .modes = &pda_91_00156_a0_mode,
2081 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2085 static const struct drm_display_mode qd43003c0_40_mode = {
2088 .hsync_start = 480 + 8,
2089 .hsync_end = 480 + 8 + 4,
2090 .htotal = 480 + 8 + 4 + 39,
2092 .vsync_start = 272 + 4,
2093 .vsync_end = 272 + 4 + 10,
2094 .vtotal = 272 + 4 + 10 + 2,
2098 static const struct panel_desc qd43003c0_40 = {
2099 .modes = &qd43003c0_40_mode,
2106 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2109 static const struct display_timing rocktech_rk070er9427_timing = {
2110 .pixelclock = { 26400000, 33300000, 46800000 },
2111 .hactive = { 800, 800, 800 },
2112 .hfront_porch = { 16, 210, 354 },
2113 .hback_porch = { 46, 46, 46 },
2114 .hsync_len = { 1, 1, 1 },
2115 .vactive = { 480, 480, 480 },
2116 .vfront_porch = { 7, 22, 147 },
2117 .vback_porch = { 23, 23, 23 },
2118 .vsync_len = { 1, 1, 1 },
2119 .flags = DISPLAY_FLAGS_DE_HIGH,
2122 static const struct panel_desc rocktech_rk070er9427 = {
2123 .timings = &rocktech_rk070er9427_timing,
2136 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2139 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2142 .hsync_start = 2560 + 48,
2143 .hsync_end = 2560 + 48 + 32,
2144 .htotal = 2560 + 48 + 32 + 80,
2146 .vsync_start = 1600 + 2,
2147 .vsync_end = 1600 + 2 + 5,
2148 .vtotal = 1600 + 2 + 5 + 57,
2152 static const struct panel_desc samsung_lsn122dl01_c01 = {
2153 .modes = &samsung_lsn122dl01_c01_mode,
2161 static const struct drm_display_mode samsung_ltn101nt05_mode = {
2164 .hsync_start = 1024 + 24,
2165 .hsync_end = 1024 + 24 + 136,
2166 .htotal = 1024 + 24 + 136 + 160,
2168 .vsync_start = 600 + 3,
2169 .vsync_end = 600 + 3 + 6,
2170 .vtotal = 600 + 3 + 6 + 61,
2174 static const struct panel_desc samsung_ltn101nt05 = {
2175 .modes = &samsung_ltn101nt05_mode,
2184 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2187 .hsync_start = 1366 + 64,
2188 .hsync_end = 1366 + 64 + 48,
2189 .htotal = 1366 + 64 + 48 + 128,
2191 .vsync_start = 768 + 2,
2192 .vsync_end = 768 + 2 + 5,
2193 .vtotal = 768 + 2 + 5 + 17,
2197 static const struct panel_desc samsung_ltn140at29_301 = {
2198 .modes = &samsung_ltn140at29_301_mode,
2207 static const struct drm_display_mode sharp_lq035q7db03_mode = {
2210 .hsync_start = 240 + 16,
2211 .hsync_end = 240 + 16 + 7,
2212 .htotal = 240 + 16 + 7 + 5,
2214 .vsync_start = 320 + 9,
2215 .vsync_end = 320 + 9 + 1,
2216 .vtotal = 320 + 9 + 1 + 7,
2220 static const struct panel_desc sharp_lq035q7db03 = {
2221 .modes = &sharp_lq035q7db03_mode,
2228 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2231 static const struct display_timing sharp_lq101k1ly04_timing = {
2232 .pixelclock = { 60000000, 65000000, 80000000 },
2233 .hactive = { 1280, 1280, 1280 },
2234 .hfront_porch = { 20, 20, 20 },
2235 .hback_porch = { 20, 20, 20 },
2236 .hsync_len = { 10, 10, 10 },
2237 .vactive = { 800, 800, 800 },
2238 .vfront_porch = { 4, 4, 4 },
2239 .vback_porch = { 4, 4, 4 },
2240 .vsync_len = { 4, 4, 4 },
2241 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2244 static const struct panel_desc sharp_lq101k1ly04 = {
2245 .timings = &sharp_lq101k1ly04_timing,
2252 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2255 static const struct display_timing sharp_lq123p1jx31_timing = {
2256 .pixelclock = { 252750000, 252750000, 266604720 },
2257 .hactive = { 2400, 2400, 2400 },
2258 .hfront_porch = { 48, 48, 48 },
2259 .hback_porch = { 80, 80, 84 },
2260 .hsync_len = { 32, 32, 32 },
2261 .vactive = { 1600, 1600, 1600 },
2262 .vfront_porch = { 3, 3, 3 },
2263 .vback_porch = { 33, 33, 120 },
2264 .vsync_len = { 10, 10, 10 },
2265 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2268 static const struct panel_desc sharp_lq123p1jx31 = {
2269 .timings = &sharp_lq123p1jx31_timing,
2283 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2286 .hsync_start = 1024 + 168,
2287 .hsync_end = 1024 + 168 + 64,
2288 .htotal = 1024 + 168 + 64 + 88,
2290 .vsync_start = 768 + 37,
2291 .vsync_end = 768 + 37 + 2,
2292 .vtotal = 768 + 37 + 2 + 8,
2296 static const struct panel_desc sharp_lq150x1lg11 = {
2297 .modes = &sharp_lq150x1lg11_mode,
2304 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2307 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2310 .hsync_start = 800 + 1,
2311 .hsync_end = 800 + 1 + 64,
2312 .htotal = 800 + 1 + 64 + 64,
2314 .vsync_start = 480 + 1,
2315 .vsync_end = 480 + 1 + 23,
2316 .vtotal = 480 + 1 + 23 + 22,
2320 static const struct panel_desc shelly_sca07010_bfn_lnn = {
2321 .modes = &shelly_sca07010_bfn_lnn_mode,
2327 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2330 static const struct drm_display_mode starry_kr122ea0sra_mode = {
2333 .hsync_start = 1920 + 16,
2334 .hsync_end = 1920 + 16 + 16,
2335 .htotal = 1920 + 16 + 16 + 32,
2337 .vsync_start = 1200 + 15,
2338 .vsync_end = 1200 + 15 + 2,
2339 .vtotal = 1200 + 15 + 2 + 18,
2341 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2344 static const struct panel_desc starry_kr122ea0sra = {
2345 .modes = &starry_kr122ea0sra_mode,
2352 .prepare = 10 + 200,
2354 .unprepare = 10 + 500,
2358 static const struct display_timing tianma_tm070jdhg30_timing = {
2359 .pixelclock = { 62600000, 68200000, 78100000 },
2360 .hactive = { 1280, 1280, 1280 },
2361 .hfront_porch = { 15, 64, 159 },
2362 .hback_porch = { 5, 5, 5 },
2363 .hsync_len = { 1, 1, 256 },
2364 .vactive = { 800, 800, 800 },
2365 .vfront_porch = { 3, 40, 99 },
2366 .vback_porch = { 2, 2, 2 },
2367 .vsync_len = { 1, 1, 128 },
2368 .flags = DISPLAY_FLAGS_DE_HIGH,
2371 static const struct panel_desc tianma_tm070jdhg30 = {
2372 .timings = &tianma_tm070jdhg30_timing,
2379 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2382 static const struct display_timing tianma_tm070rvhg71_timing = {
2383 .pixelclock = { 27700000, 29200000, 39600000 },
2384 .hactive = { 800, 800, 800 },
2385 .hfront_porch = { 12, 40, 212 },
2386 .hback_porch = { 88, 88, 88 },
2387 .hsync_len = { 1, 1, 40 },
2388 .vactive = { 480, 480, 480 },
2389 .vfront_porch = { 1, 13, 88 },
2390 .vback_porch = { 32, 32, 32 },
2391 .vsync_len = { 1, 1, 3 },
2392 .flags = DISPLAY_FLAGS_DE_HIGH,
2395 static const struct panel_desc tianma_tm070rvhg71 = {
2396 .timings = &tianma_tm070rvhg71_timing,
2403 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2406 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2409 .hsync_start = 1280 + 192,
2410 .hsync_end = 1280 + 192 + 128,
2411 .htotal = 1280 + 192 + 128 + 64,
2413 .vsync_start = 768 + 20,
2414 .vsync_end = 768 + 20 + 7,
2415 .vtotal = 768 + 20 + 7 + 3,
2419 static const struct panel_desc toshiba_lt089ac29000 = {
2420 .modes = &toshiba_lt089ac29000_mode,
2426 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2427 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2430 static const struct drm_display_mode tpk_f07a_0102_mode = {
2433 .hsync_start = 800 + 40,
2434 .hsync_end = 800 + 40 + 128,
2435 .htotal = 800 + 40 + 128 + 88,
2437 .vsync_start = 480 + 10,
2438 .vsync_end = 480 + 10 + 2,
2439 .vtotal = 480 + 10 + 2 + 33,
2443 static const struct panel_desc tpk_f07a_0102 = {
2444 .modes = &tpk_f07a_0102_mode,
2450 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2453 static const struct drm_display_mode tpk_f10a_0102_mode = {
2456 .hsync_start = 1024 + 176,
2457 .hsync_end = 1024 + 176 + 5,
2458 .htotal = 1024 + 176 + 5 + 88,
2460 .vsync_start = 600 + 20,
2461 .vsync_end = 600 + 20 + 5,
2462 .vtotal = 600 + 20 + 5 + 25,
2466 static const struct panel_desc tpk_f10a_0102 = {
2467 .modes = &tpk_f10a_0102_mode,
2475 static const struct display_timing urt_umsh_8596md_timing = {
2476 .pixelclock = { 33260000, 33260000, 33260000 },
2477 .hactive = { 800, 800, 800 },
2478 .hfront_porch = { 41, 41, 41 },
2479 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2480 .hsync_len = { 71, 128, 128 },
2481 .vactive = { 480, 480, 480 },
2482 .vfront_porch = { 10, 10, 10 },
2483 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
2484 .vsync_len = { 2, 2, 2 },
2485 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2486 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2489 static const struct panel_desc urt_umsh_8596md_lvds = {
2490 .timings = &urt_umsh_8596md_timing,
2497 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2500 static const struct panel_desc urt_umsh_8596md_parallel = {
2501 .timings = &urt_umsh_8596md_timing,
2508 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2511 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
2514 .hsync_start = 320 + 20,
2515 .hsync_end = 320 + 20 + 30,
2516 .htotal = 320 + 20 + 30 + 38,
2518 .vsync_start = 240 + 4,
2519 .vsync_end = 240 + 4 + 3,
2520 .vtotal = 240 + 4 + 3 + 15,
2522 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2525 static const struct panel_desc winstar_wf35ltiacd = {
2526 .modes = &winstar_wf35ltiacd_mode,
2533 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2536 static const struct drm_display_mode arm_rtsm_mode[] = {
2540 .hsync_start = 1024 + 24,
2541 .hsync_end = 1024 + 24 + 136,
2542 .htotal = 1024 + 24 + 136 + 160,
2544 .vsync_start = 768 + 3,
2545 .vsync_end = 768 + 3 + 6,
2546 .vtotal = 768 + 3 + 6 + 29,
2548 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2552 static const struct panel_desc arm_rtsm = {
2553 .modes = arm_rtsm_mode,
2560 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2563 static const struct of_device_id platform_of_match[] = {
2565 .compatible = "ampire,am-480272h3tmqw-t01h",
2566 .data = &ire_am_480272h3tmqw_t01h,
2568 .compatible = "ampire,am800480r3tmqwa1h",
2569 .data = &ire_am800480r3tmqwa1h,
2571 .compatible = "arm,rtsm-display",
2574 .compatible = "auo,b101aw03",
2575 .data = &auo_b101aw03,
2577 .compatible = "auo,b101ean01",
2578 .data = &auo_b101ean01,
2580 .compatible = "auo,b101xtn01",
2581 .data = &auo_b101xtn01,
2583 .compatible = "auo,b116xw03",
2584 .data = &auo_b116xw03,
2586 .compatible = "auo,b133htn01",
2587 .data = &auo_b133htn01,
2589 .compatible = "auo,b133xtn01",
2590 .data = &auo_b133xtn01,
2592 .compatible = "auo,g070vvn01",
2593 .data = &auo_g070vvn01,
2595 .compatible = "auo,g101evn010",
2596 .data = &auo_g101evn010,
2598 .compatible = "auo,g104sn02",
2599 .data = &auo_g104sn02,
2601 .compatible = "auo,g133han01",
2602 .data = &auo_g133han01,
2604 .compatible = "auo,g185han01",
2605 .data = &auo_g185han01,
2607 .compatible = "auo,p320hvn03",
2608 .data = &auo_p320hvn03,
2610 .compatible = "auo,t215hvn01",
2611 .data = &auo_t215hvn01,
2613 .compatible = "avic,tm070ddh03",
2614 .data = &avic_tm070ddh03,
2616 .compatible = "bananapi,s070wv20-ct16",
2617 .data = &bananapi_s070wv20_ct16,
2619 .compatible = "boe,hv070wsa-100",
2620 .data = &boe_hv070wsa
2622 .compatible = "boe,nv101wxmn51",
2623 .data = &boe_nv101wxmn51,
2625 .compatible = "cdtech,s043wq26h-ct7",
2626 .data = &cdtech_s043wq26h_ct7,
2628 .compatible = "cdtech,s070wv95-ct16",
2629 .data = &cdtech_s070wv95_ct16,
2631 .compatible = "chunghwa,claa070wp03xg",
2632 .data = &chunghwa_claa070wp03xg,
2634 .compatible = "chunghwa,claa101wa01a",
2635 .data = &chunghwa_claa101wa01a
2637 .compatible = "chunghwa,claa101wb01",
2638 .data = &chunghwa_claa101wb01
2640 .compatible = "dataimage,scf0700c48ggu18",
2641 .data = &dataimage_scf0700c48ggu18,
2643 .compatible = "dlc,dlc0700yzg-1",
2644 .data = &dlc_dlc0700yzg_1,
2646 .compatible = "dlc,dlc1010gig",
2647 .data = &dlc_dlc1010gig,
2649 .compatible = "edt,et057090dhu",
2650 .data = &edt_et057090dhu,
2652 .compatible = "edt,et070080dh6",
2653 .data = &edt_etm0700g0dh6,
2655 .compatible = "edt,etm0700g0dh6",
2656 .data = &edt_etm0700g0dh6,
2658 .compatible = "edt,etm0700g0bdh6",
2659 .data = &edt_etm0700g0bdh6,
2661 .compatible = "edt,etm0700g0edh6",
2662 .data = &edt_etm0700g0bdh6,
2664 .compatible = "foxlink,fl500wvr00-a0t",
2665 .data = &foxlink_fl500wvr00_a0t,
2667 .compatible = "giantplus,gpg482739qs5",
2668 .data = &giantplus_gpg482739qs5
2670 .compatible = "hannstar,hsd070pww1",
2671 .data = &hannstar_hsd070pww1,
2673 .compatible = "hannstar,hsd100pxn1",
2674 .data = &hannstar_hsd100pxn1,
2676 .compatible = "hit,tx23d38vm0caa",
2677 .data = &hitachi_tx23d38vm0caa
2679 .compatible = "innolux,at043tn24",
2680 .data = &innolux_at043tn24,
2682 .compatible = "innolux,at070tn92",
2683 .data = &innolux_at070tn92,
2685 .compatible = "innolux,g070y2-l01",
2686 .data = &innolux_g070y2_l01,
2688 .compatible = "innolux,g101ice-l01",
2689 .data = &innolux_g101ice_l01
2691 .compatible = "innolux,g121i1-l01",
2692 .data = &innolux_g121i1_l01
2694 .compatible = "innolux,g121x1-l03",
2695 .data = &innolux_g121x1_l03,
2697 .compatible = "innolux,n116bge",
2698 .data = &innolux_n116bge,
2700 .compatible = "innolux,n156bge-l21",
2701 .data = &innolux_n156bge_l21,
2703 .compatible = "innolux,p120zdg-bf1",
2704 .data = &innolux_p120zdg_bf1,
2706 .compatible = "innolux,zj070na-01p",
2707 .data = &innolux_zj070na_01p,
2709 .compatible = "koe,tx31d200vm0baa",
2710 .data = &koe_tx31d200vm0baa,
2712 .compatible = "kyo,tcg121xglp",
2713 .data = &kyo_tcg121xglp,
2715 .compatible = "lemaker,bl035-rgb-002",
2716 .data = &lemaker_bl035_rgb_002,
2718 .compatible = "lg,lb070wv8",
2719 .data = &lg_lb070wv8,
2721 .compatible = "lg,lp079qx1-sp0v",
2722 .data = &lg_lp079qx1_sp0v,
2724 .compatible = "lg,lp097qx1-spa1",
2725 .data = &lg_lp097qx1_spa1,
2727 .compatible = "lg,lp120up1",
2728 .data = &lg_lp120up1,
2730 .compatible = "lg,lp129qe",
2731 .data = &lg_lp129qe,
2733 .compatible = "mitsubishi,aa070mc01-ca1",
2734 .data = &mitsubishi_aa070mc01,
2736 .compatible = "nec,nl12880bc20-05",
2737 .data = &nec_nl12880bc20_05,
2739 .compatible = "nec,nl4827hc19-05b",
2740 .data = &nec_nl4827hc19_05b,
2742 .compatible = "netron-dy,e231732",
2743 .data = &netron_dy_e231732,
2745 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
2746 .data = &newhaven_nhd_43_480272ef_atxl,
2748 .compatible = "nlt,nl192108ac18-02d",
2749 .data = &nlt_nl192108ac18_02d,
2751 .compatible = "nvd,9128",
2754 .compatible = "okaya,rs800480t-7x0gp",
2755 .data = &okaya_rs800480t_7x0gp,
2757 .compatible = "olimex,lcd-olinuxino-43-ts",
2758 .data = &olimex_lcd_olinuxino_43ts,
2760 .compatible = "ontat,yx700wv03",
2761 .data = &ontat_yx700wv03,
2763 .compatible = "ortustech,com43h4m85ulc",
2764 .data = &ortustech_com43h4m85ulc,
2766 .compatible = "osddisplays,osd070t1718-19ts",
2767 .data = &osddisplays_osd070t1718_19ts,
2769 .compatible = "pda,91-00156-a0",
2770 .data = &pda_91_00156_a0,
2772 .compatible = "qiaodian,qd43003c0-40",
2773 .data = &qd43003c0_40,
2775 .compatible = "rocktech,rk070er9427",
2776 .data = &rocktech_rk070er9427,
2778 .compatible = "samsung,lsn122dl01-c01",
2779 .data = &samsung_lsn122dl01_c01,
2781 .compatible = "samsung,ltn101nt05",
2782 .data = &samsung_ltn101nt05,
2784 .compatible = "samsung,ltn140at29-301",
2785 .data = &samsung_ltn140at29_301,
2787 .compatible = "sharp,lq035q7db03",
2788 .data = &sharp_lq035q7db03,
2790 .compatible = "sharp,lq101k1ly04",
2791 .data = &sharp_lq101k1ly04,
2793 .compatible = "sharp,lq123p1jx31",
2794 .data = &sharp_lq123p1jx31,
2796 .compatible = "sharp,lq150x1lg11",
2797 .data = &sharp_lq150x1lg11,
2799 .compatible = "shelly,sca07010-bfn-lnn",
2800 .data = &shelly_sca07010_bfn_lnn,
2802 .compatible = "starry,kr122ea0sra",
2803 .data = &starry_kr122ea0sra,
2805 .compatible = "tianma,tm070jdhg30",
2806 .data = &tianma_tm070jdhg30,
2808 .compatible = "tianma,tm070rvhg71",
2809 .data = &tianma_tm070rvhg71,
2811 .compatible = "toshiba,lt089ac29000",
2812 .data = &toshiba_lt089ac29000,
2814 .compatible = "tpk,f07a-0102",
2815 .data = &tpk_f07a_0102,
2817 .compatible = "tpk,f10a-0102",
2818 .data = &tpk_f10a_0102,
2820 .compatible = "urt,umsh-8596md-t",
2821 .data = &urt_umsh_8596md_parallel,
2823 .compatible = "urt,umsh-8596md-1t",
2824 .data = &urt_umsh_8596md_parallel,
2826 .compatible = "urt,umsh-8596md-7t",
2827 .data = &urt_umsh_8596md_parallel,
2829 .compatible = "urt,umsh-8596md-11t",
2830 .data = &urt_umsh_8596md_lvds,
2832 .compatible = "urt,umsh-8596md-19t",
2833 .data = &urt_umsh_8596md_lvds,
2835 .compatible = "urt,umsh-8596md-20t",
2836 .data = &urt_umsh_8596md_parallel,
2838 .compatible = "winstar,wf35ltiacd",
2839 .data = &winstar_wf35ltiacd,
2844 MODULE_DEVICE_TABLE(of, platform_of_match);
2846 static int panel_simple_platform_probe(struct platform_device *pdev)
2848 const struct of_device_id *id;
2850 id = of_match_node(platform_of_match, pdev->dev.of_node);
2854 return panel_simple_probe(&pdev->dev, id->data);
2857 static int panel_simple_platform_remove(struct platform_device *pdev)
2859 return panel_simple_remove(&pdev->dev);
2862 static void panel_simple_platform_shutdown(struct platform_device *pdev)
2864 panel_simple_shutdown(&pdev->dev);
2867 static struct platform_driver panel_simple_platform_driver = {
2869 .name = "panel-simple",
2870 .of_match_table = platform_of_match,
2872 .probe = panel_simple_platform_probe,
2873 .remove = panel_simple_platform_remove,
2874 .shutdown = panel_simple_platform_shutdown,
2877 struct panel_desc_dsi {
2878 struct panel_desc desc;
2880 unsigned long flags;
2881 enum mipi_dsi_pixel_format format;
2885 static const struct drm_display_mode auo_b080uan01_mode = {
2888 .hsync_start = 1200 + 62,
2889 .hsync_end = 1200 + 62 + 4,
2890 .htotal = 1200 + 62 + 4 + 62,
2892 .vsync_start = 1920 + 9,
2893 .vsync_end = 1920 + 9 + 2,
2894 .vtotal = 1920 + 9 + 2 + 8,
2898 static const struct panel_desc_dsi auo_b080uan01 = {
2900 .modes = &auo_b080uan01_mode,
2908 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2909 .format = MIPI_DSI_FMT_RGB888,
2913 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
2916 .hsync_start = 1200 + 120,
2917 .hsync_end = 1200 + 120 + 20,
2918 .htotal = 1200 + 120 + 20 + 21,
2920 .vsync_start = 1920 + 21,
2921 .vsync_end = 1920 + 21 + 3,
2922 .vtotal = 1920 + 21 + 3 + 18,
2924 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2927 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
2929 .modes = &boe_tv080wum_nl0_mode,
2936 .flags = MIPI_DSI_MODE_VIDEO |
2937 MIPI_DSI_MODE_VIDEO_BURST |
2938 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
2939 .format = MIPI_DSI_FMT_RGB888,
2943 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
2946 .hsync_start = 800 + 32,
2947 .hsync_end = 800 + 32 + 1,
2948 .htotal = 800 + 32 + 1 + 57,
2950 .vsync_start = 1280 + 28,
2951 .vsync_end = 1280 + 28 + 1,
2952 .vtotal = 1280 + 28 + 1 + 14,
2956 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
2958 .modes = &lg_ld070wx3_sl01_mode,
2966 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2967 .format = MIPI_DSI_FMT_RGB888,
2971 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
2974 .hsync_start = 720 + 12,
2975 .hsync_end = 720 + 12 + 4,
2976 .htotal = 720 + 12 + 4 + 112,
2978 .vsync_start = 1280 + 8,
2979 .vsync_end = 1280 + 8 + 4,
2980 .vtotal = 1280 + 8 + 4 + 12,
2984 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
2986 .modes = &lg_lh500wx1_sd03_mode,
2994 .flags = MIPI_DSI_MODE_VIDEO,
2995 .format = MIPI_DSI_FMT_RGB888,
2999 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
3002 .hsync_start = 1920 + 154,
3003 .hsync_end = 1920 + 154 + 16,
3004 .htotal = 1920 + 154 + 16 + 32,
3006 .vsync_start = 1200 + 17,
3007 .vsync_end = 1200 + 17 + 2,
3008 .vtotal = 1200 + 17 + 2 + 16,
3012 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
3014 .modes = &panasonic_vvx10f004b00_mode,
3022 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3023 MIPI_DSI_CLOCK_NON_CONTINUOUS,
3024 .format = MIPI_DSI_FMT_RGB888,
3028 static const struct drm_display_mode lg_acx467akm_7_mode = {
3031 .hsync_start = 1080 + 2,
3032 .hsync_end = 1080 + 2 + 2,
3033 .htotal = 1080 + 2 + 2 + 2,
3035 .vsync_start = 1920 + 2,
3036 .vsync_end = 1920 + 2 + 2,
3037 .vtotal = 1920 + 2 + 2 + 2,
3041 static const struct panel_desc_dsi lg_acx467akm_7 = {
3043 .modes = &lg_acx467akm_7_mode,
3052 .format = MIPI_DSI_FMT_RGB888,
3056 static const struct of_device_id dsi_of_match[] = {
3058 .compatible = "auo,b080uan01",
3059 .data = &auo_b080uan01
3061 .compatible = "boe,tv080wum-nl0",
3062 .data = &boe_tv080wum_nl0
3064 .compatible = "lg,ld070wx3-sl01",
3065 .data = &lg_ld070wx3_sl01
3067 .compatible = "lg,lh500wx1-sd03",
3068 .data = &lg_lh500wx1_sd03
3070 .compatible = "panasonic,vvx10f004b00",
3071 .data = &panasonic_vvx10f004b00
3073 .compatible = "lg,acx467akm-7",
3074 .data = &lg_acx467akm_7
3079 MODULE_DEVICE_TABLE(of, dsi_of_match);
3081 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
3083 const struct panel_desc_dsi *desc;
3084 const struct of_device_id *id;
3087 id = of_match_node(dsi_of_match, dsi->dev.of_node);
3093 err = panel_simple_probe(&dsi->dev, &desc->desc);
3097 dsi->mode_flags = desc->flags;
3098 dsi->format = desc->format;
3099 dsi->lanes = desc->lanes;
3101 return mipi_dsi_attach(dsi);
3104 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
3108 err = mipi_dsi_detach(dsi);
3110 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
3112 return panel_simple_remove(&dsi->dev);
3115 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3117 panel_simple_shutdown(&dsi->dev);
3120 static struct mipi_dsi_driver panel_simple_dsi_driver = {
3122 .name = "panel-simple-dsi",
3123 .of_match_table = dsi_of_match,
3125 .probe = panel_simple_dsi_probe,
3126 .remove = panel_simple_dsi_remove,
3127 .shutdown = panel_simple_dsi_shutdown,
3130 static int __init panel_simple_init(void)
3134 err = platform_driver_register(&panel_simple_platform_driver);
3138 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3139 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3146 module_init(panel_simple_init);
3148 static void __exit panel_simple_exit(void)
3150 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3151 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3153 platform_driver_unregister(&panel_simple_platform_driver);
3155 module_exit(panel_simple_exit);
3157 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3158 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3159 MODULE_LICENSE("GPL and additional rights");