2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
43 * @modes: Pointer to array of fixed modes appropriate for this panel. If
44 * only one mode then this can just be the address of this the mode.
45 * NOTE: cannot be used with "timings" and also if this is specified
46 * then you cannot override the mode in the device tree.
47 * @num_modes: Number of elements in modes array.
48 * @timings: Pointer to array of display timings. NOTE: cannot be used with
49 * "modes" and also these will be used to validate a device tree
50 * override if one is present.
51 * @num_timings: Number of elements in timings array.
52 * @bpc: Bits per color.
53 * @size: Structure containing the physical size of this panel.
54 * @delay: Structure containing various delay values for this panel.
55 * @bus_format: See MEDIA_BUS_FMT_... defines.
56 * @bus_flags: See DRM_BUS_FLAG_... defines.
57 * @connector_type: LVDS, eDP, DSI, DPI, etc.
60 const struct drm_display_mode *modes;
61 unsigned int num_modes;
62 const struct display_timing *timings;
63 unsigned int num_timings;
68 * @width: width (in millimeters) of the panel's active display area
69 * @height: height (in millimeters) of the panel's active display area
77 * @prepare: the time (in milliseconds) that it takes for the panel to
78 * become ready and start receiving video data
79 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
80 * Plug Detect isn't used.
81 * @enable: the time (in milliseconds) that it takes for the panel to
82 * display the first valid frame after starting to receive
84 * @disable: the time (in milliseconds) that it takes for the panel to
85 * turn the display off (no content is visible)
86 * @unprepare: the time (in milliseconds) that it takes for the panel
87 * to power itself down completely
91 unsigned int hpd_absent_delay;
94 unsigned int unprepare;
102 struct panel_simple {
103 struct drm_panel base;
108 const struct panel_desc *desc;
110 struct regulator *supply;
111 struct i2c_adapter *ddc;
113 struct gpio_desc *enable_gpio;
114 struct gpio_desc *hpd_gpio;
116 struct drm_display_mode override_mode;
118 enum drm_panel_orientation orientation;
121 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
123 return container_of(panel, struct panel_simple, base);
126 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
127 struct drm_connector *connector)
129 struct drm_display_mode *mode;
130 unsigned int i, num = 0;
132 for (i = 0; i < panel->desc->num_timings; i++) {
133 const struct display_timing *dt = &panel->desc->timings[i];
136 videomode_from_timing(dt, &vm);
137 mode = drm_mode_create(connector->dev);
139 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
140 dt->hactive.typ, dt->vactive.typ);
144 drm_display_mode_from_videomode(&vm, mode);
146 mode->type |= DRM_MODE_TYPE_DRIVER;
148 if (panel->desc->num_timings == 1)
149 mode->type |= DRM_MODE_TYPE_PREFERRED;
151 drm_mode_probed_add(connector, mode);
158 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
159 struct drm_connector *connector)
161 struct drm_display_mode *mode;
162 unsigned int i, num = 0;
164 for (i = 0; i < panel->desc->num_modes; i++) {
165 const struct drm_display_mode *m = &panel->desc->modes[i];
167 mode = drm_mode_duplicate(connector->dev, m);
169 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
170 m->hdisplay, m->vdisplay,
171 drm_mode_vrefresh(m));
175 mode->type |= DRM_MODE_TYPE_DRIVER;
177 if (panel->desc->num_modes == 1)
178 mode->type |= DRM_MODE_TYPE_PREFERRED;
180 drm_mode_set_name(mode);
182 drm_mode_probed_add(connector, mode);
189 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
190 struct drm_connector *connector)
192 struct drm_display_mode *mode;
193 bool has_override = panel->override_mode.type;
194 unsigned int num = 0;
200 mode = drm_mode_duplicate(connector->dev,
201 &panel->override_mode);
203 drm_mode_probed_add(connector, mode);
206 dev_err(panel->base.dev, "failed to add override mode\n");
210 /* Only add timings if override was not there or failed to validate */
211 if (num == 0 && panel->desc->num_timings)
212 num = panel_simple_get_timings_modes(panel, connector);
215 * Only add fixed modes if timings/override added no mode.
217 * We should only ever have either the display timings specified
218 * or a fixed mode. Anything else is rather bogus.
220 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
222 num = panel_simple_get_display_modes(panel, connector);
224 connector->display_info.bpc = panel->desc->bpc;
225 connector->display_info.width_mm = panel->desc->size.width;
226 connector->display_info.height_mm = panel->desc->size.height;
227 if (panel->desc->bus_format)
228 drm_display_info_set_bus_formats(&connector->display_info,
229 &panel->desc->bus_format, 1);
230 connector->display_info.bus_flags = panel->desc->bus_flags;
235 static int panel_simple_disable(struct drm_panel *panel)
237 struct panel_simple *p = to_panel_simple(panel);
242 if (p->desc->delay.disable)
243 msleep(p->desc->delay.disable);
250 static int panel_simple_unprepare(struct drm_panel *panel)
252 struct panel_simple *p = to_panel_simple(panel);
257 gpiod_set_value_cansleep(p->enable_gpio, 0);
259 regulator_disable(p->supply);
261 if (p->desc->delay.unprepare)
262 msleep(p->desc->delay.unprepare);
269 static int panel_simple_get_hpd_gpio(struct device *dev,
270 struct panel_simple *p, bool from_probe)
274 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
275 if (IS_ERR(p->hpd_gpio)) {
276 err = PTR_ERR(p->hpd_gpio);
279 * If we're called from probe we won't consider '-EPROBE_DEFER'
280 * to be an error--we'll leave the error code in "hpd_gpio".
281 * When we try to use it we'll try again. This allows for
282 * circular dependencies where the component providing the
283 * hpd gpio needs the panel to init before probing.
285 if (err != -EPROBE_DEFER || !from_probe) {
286 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
294 static int panel_simple_prepare(struct drm_panel *panel)
296 struct panel_simple *p = to_panel_simple(panel);
304 err = regulator_enable(p->supply);
306 dev_err(panel->dev, "failed to enable supply: %d\n", err);
310 gpiod_set_value_cansleep(p->enable_gpio, 1);
312 delay = p->desc->delay.prepare;
314 delay += p->desc->delay.hpd_absent_delay;
319 if (IS_ERR(p->hpd_gpio)) {
320 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
325 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
326 hpd_asserted, hpd_asserted,
328 if (hpd_asserted < 0)
333 "error waiting for hpd GPIO: %d\n", err);
343 static int panel_simple_enable(struct drm_panel *panel)
345 struct panel_simple *p = to_panel_simple(panel);
350 if (p->desc->delay.enable)
351 msleep(p->desc->delay.enable);
358 static int panel_simple_get_modes(struct drm_panel *panel,
359 struct drm_connector *connector)
361 struct panel_simple *p = to_panel_simple(panel);
364 /* probe EDID if a DDC bus is available */
366 struct edid *edid = drm_get_edid(connector, p->ddc);
368 drm_connector_update_edid_property(connector, edid);
370 num += drm_add_edid_modes(connector, edid);
375 /* add hard-coded panel modes */
376 num += panel_simple_get_non_edid_modes(p, connector);
378 /* set up connector's "panel orientation" property */
379 drm_connector_set_panel_orientation(connector, p->orientation);
384 static int panel_simple_get_timings(struct drm_panel *panel,
385 unsigned int num_timings,
386 struct display_timing *timings)
388 struct panel_simple *p = to_panel_simple(panel);
391 if (p->desc->num_timings < num_timings)
392 num_timings = p->desc->num_timings;
395 for (i = 0; i < num_timings; i++)
396 timings[i] = p->desc->timings[i];
398 return p->desc->num_timings;
401 static const struct drm_panel_funcs panel_simple_funcs = {
402 .disable = panel_simple_disable,
403 .unprepare = panel_simple_unprepare,
404 .prepare = panel_simple_prepare,
405 .enable = panel_simple_enable,
406 .get_modes = panel_simple_get_modes,
407 .get_timings = panel_simple_get_timings,
410 static struct panel_desc panel_dpi;
412 static int panel_dpi_probe(struct device *dev,
413 struct panel_simple *panel)
415 struct display_timing *timing;
416 const struct device_node *np;
417 struct panel_desc *desc;
418 unsigned int bus_flags;
423 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
427 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
431 ret = of_get_display_timing(np, "panel-timing", timing);
433 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
438 desc->timings = timing;
439 desc->num_timings = 1;
441 of_property_read_u32(np, "width-mm", &desc->size.width);
442 of_property_read_u32(np, "height-mm", &desc->size.height);
444 /* Extract bus_flags from display_timing */
446 vm.flags = timing->flags;
447 drm_bus_flags_from_videomode(&vm, &bus_flags);
448 desc->bus_flags = bus_flags;
450 /* We do not know the connector for the DT node, so guess it */
451 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
458 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
459 (to_check->field.typ >= bounds->field.min && \
460 to_check->field.typ <= bounds->field.max)
461 static void panel_simple_parse_panel_timing_node(struct device *dev,
462 struct panel_simple *panel,
463 const struct display_timing *ot)
465 const struct panel_desc *desc = panel->desc;
469 if (WARN_ON(desc->num_modes)) {
470 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
473 if (WARN_ON(!desc->num_timings)) {
474 dev_err(dev, "Reject override mode: no timings specified\n");
478 for (i = 0; i < panel->desc->num_timings; i++) {
479 const struct display_timing *dt = &panel->desc->timings[i];
481 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
482 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
483 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
484 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
485 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
486 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
487 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
488 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
491 if (ot->flags != dt->flags)
494 videomode_from_timing(ot, &vm);
495 drm_display_mode_from_videomode(&vm, &panel->override_mode);
496 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
497 DRM_MODE_TYPE_PREFERRED;
501 if (WARN_ON(!panel->override_mode.type))
502 dev_err(dev, "Reject override mode: No display_timing found\n");
505 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
507 struct panel_simple *panel;
508 struct display_timing dt;
509 struct device_node *ddc;
514 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
518 panel->enabled = false;
519 panel->prepared = false;
522 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
523 if (!panel->no_hpd) {
524 err = panel_simple_get_hpd_gpio(dev, panel, true);
529 panel->supply = devm_regulator_get(dev, "power");
530 if (IS_ERR(panel->supply))
531 return PTR_ERR(panel->supply);
533 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
535 if (IS_ERR(panel->enable_gpio)) {
536 err = PTR_ERR(panel->enable_gpio);
537 if (err != -EPROBE_DEFER)
538 dev_err(dev, "failed to request GPIO: %d\n", err);
542 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
544 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
548 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
550 panel->ddc = of_find_i2c_adapter_by_node(ddc);
554 return -EPROBE_DEFER;
557 if (desc == &panel_dpi) {
558 /* Handle the generic panel-dpi binding */
559 err = panel_dpi_probe(dev, panel);
563 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
564 panel_simple_parse_panel_timing_node(dev, panel, &dt);
567 connector_type = desc->connector_type;
568 /* Catch common mistakes for panels. */
569 switch (connector_type) {
571 dev_warn(dev, "Specify missing connector_type\n");
572 connector_type = DRM_MODE_CONNECTOR_DPI;
574 case DRM_MODE_CONNECTOR_LVDS:
575 WARN_ON(desc->bus_flags &
576 ~(DRM_BUS_FLAG_DE_LOW |
577 DRM_BUS_FLAG_DE_HIGH |
578 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
579 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
580 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
581 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
582 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
583 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
585 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
586 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
589 case DRM_MODE_CONNECTOR_eDP:
590 if (desc->bus_format == 0)
591 dev_warn(dev, "Specify missing bus_format\n");
592 if (desc->bpc != 6 && desc->bpc != 8)
593 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
595 case DRM_MODE_CONNECTOR_DSI:
596 if (desc->bpc != 6 && desc->bpc != 8)
597 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
599 case DRM_MODE_CONNECTOR_DPI:
600 bus_flags = DRM_BUS_FLAG_DE_LOW |
601 DRM_BUS_FLAG_DE_HIGH |
602 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
603 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
604 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
605 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
606 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
607 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
608 if (desc->bus_flags & ~bus_flags)
609 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
610 if (!(desc->bus_flags & bus_flags))
611 dev_warn(dev, "Specify missing bus_flags\n");
612 if (desc->bus_format == 0)
613 dev_warn(dev, "Specify missing bus_format\n");
614 if (desc->bpc != 6 && desc->bpc != 8)
615 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
618 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
619 connector_type = DRM_MODE_CONNECTOR_DPI;
623 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
625 err = drm_panel_of_backlight(&panel->base);
629 drm_panel_add(&panel->base);
631 dev_set_drvdata(dev, panel);
637 put_device(&panel->ddc->dev);
642 static int panel_simple_remove(struct device *dev)
644 struct panel_simple *panel = dev_get_drvdata(dev);
646 drm_panel_remove(&panel->base);
647 drm_panel_disable(&panel->base);
648 drm_panel_unprepare(&panel->base);
651 put_device(&panel->ddc->dev);
656 static void panel_simple_shutdown(struct device *dev)
658 struct panel_simple *panel = dev_get_drvdata(dev);
660 drm_panel_disable(&panel->base);
661 drm_panel_unprepare(&panel->base);
664 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
667 .hsync_start = 1280 + 40,
668 .hsync_end = 1280 + 40 + 80,
669 .htotal = 1280 + 40 + 80 + 40,
671 .vsync_start = 800 + 3,
672 .vsync_end = 800 + 3 + 10,
673 .vtotal = 800 + 3 + 10 + 10,
674 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
677 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
678 .modes = &ire_am_1280800n3tzqw_t00h_mode,
685 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
686 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
687 .connector_type = DRM_MODE_CONNECTOR_LVDS,
690 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
693 .hsync_start = 480 + 2,
694 .hsync_end = 480 + 2 + 41,
695 .htotal = 480 + 2 + 41 + 2,
697 .vsync_start = 272 + 2,
698 .vsync_end = 272 + 2 + 10,
699 .vtotal = 272 + 2 + 10 + 2,
700 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
703 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
704 .modes = &ire_am_480272h3tmqw_t01h_mode,
711 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
714 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
717 .hsync_start = 800 + 0,
718 .hsync_end = 800 + 0 + 255,
719 .htotal = 800 + 0 + 255 + 0,
721 .vsync_start = 480 + 2,
722 .vsync_end = 480 + 2 + 45,
723 .vtotal = 480 + 2 + 45 + 0,
724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
727 static const struct panel_desc ampire_am800480r3tmqwa1h = {
728 .modes = &ire_am800480r3tmqwa1h_mode,
735 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
738 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
739 .pixelclock = { 26400000, 33300000, 46800000 },
740 .hactive = { 800, 800, 800 },
741 .hfront_porch = { 16, 210, 354 },
742 .hback_porch = { 45, 36, 6 },
743 .hsync_len = { 1, 10, 40 },
744 .vactive = { 480, 480, 480 },
745 .vfront_porch = { 7, 22, 147 },
746 .vback_porch = { 22, 13, 3 },
747 .vsync_len = { 1, 10, 20 },
748 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
749 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
752 static const struct panel_desc armadeus_st0700_adapt = {
753 .timings = &santek_st0700i5y_rbslw_f_timing,
760 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
761 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
764 static const struct drm_display_mode auo_b101aw03_mode = {
767 .hsync_start = 1024 + 156,
768 .hsync_end = 1024 + 156 + 8,
769 .htotal = 1024 + 156 + 8 + 156,
771 .vsync_start = 600 + 16,
772 .vsync_end = 600 + 16 + 6,
773 .vtotal = 600 + 16 + 6 + 16,
776 static const struct panel_desc auo_b101aw03 = {
777 .modes = &auo_b101aw03_mode,
784 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
785 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
786 .connector_type = DRM_MODE_CONNECTOR_LVDS,
789 static const struct display_timing auo_b101ean01_timing = {
790 .pixelclock = { 65300000, 72500000, 75000000 },
791 .hactive = { 1280, 1280, 1280 },
792 .hfront_porch = { 18, 119, 119 },
793 .hback_porch = { 21, 21, 21 },
794 .hsync_len = { 32, 32, 32 },
795 .vactive = { 800, 800, 800 },
796 .vfront_porch = { 4, 4, 4 },
797 .vback_porch = { 8, 8, 8 },
798 .vsync_len = { 18, 20, 20 },
801 static const struct panel_desc auo_b101ean01 = {
802 .timings = &auo_b101ean01_timing,
811 static const struct drm_display_mode auo_b101xtn01_mode = {
814 .hsync_start = 1366 + 20,
815 .hsync_end = 1366 + 20 + 70,
816 .htotal = 1366 + 20 + 70,
818 .vsync_start = 768 + 14,
819 .vsync_end = 768 + 14 + 42,
820 .vtotal = 768 + 14 + 42,
821 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
824 static const struct panel_desc auo_b101xtn01 = {
825 .modes = &auo_b101xtn01_mode,
834 static const struct drm_display_mode auo_b116xak01_mode = {
837 .hsync_start = 1366 + 48,
838 .hsync_end = 1366 + 48 + 32,
839 .htotal = 1366 + 48 + 32 + 10,
841 .vsync_start = 768 + 4,
842 .vsync_end = 768 + 4 + 6,
843 .vtotal = 768 + 4 + 6 + 15,
844 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
847 static const struct panel_desc auo_b116xak01 = {
848 .modes = &auo_b116xak01_mode,
856 .hpd_absent_delay = 200,
858 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
859 .connector_type = DRM_MODE_CONNECTOR_eDP,
862 static const struct drm_display_mode auo_b116xw03_mode = {
865 .hsync_start = 1366 + 40,
866 .hsync_end = 1366 + 40 + 40,
867 .htotal = 1366 + 40 + 40 + 32,
869 .vsync_start = 768 + 10,
870 .vsync_end = 768 + 10 + 12,
871 .vtotal = 768 + 10 + 12 + 6,
872 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
875 static const struct panel_desc auo_b116xw03 = {
876 .modes = &auo_b116xw03_mode,
886 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
887 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
888 .connector_type = DRM_MODE_CONNECTOR_eDP,
891 static const struct drm_display_mode auo_b133xtn01_mode = {
894 .hsync_start = 1366 + 48,
895 .hsync_end = 1366 + 48 + 32,
896 .htotal = 1366 + 48 + 32 + 20,
898 .vsync_start = 768 + 3,
899 .vsync_end = 768 + 3 + 6,
900 .vtotal = 768 + 3 + 6 + 13,
903 static const struct panel_desc auo_b133xtn01 = {
904 .modes = &auo_b133xtn01_mode,
913 static const struct drm_display_mode auo_b133htn01_mode = {
916 .hsync_start = 1920 + 172,
917 .hsync_end = 1920 + 172 + 80,
918 .htotal = 1920 + 172 + 80 + 60,
920 .vsync_start = 1080 + 25,
921 .vsync_end = 1080 + 25 + 10,
922 .vtotal = 1080 + 25 + 10 + 10,
925 static const struct panel_desc auo_b133htn01 = {
926 .modes = &auo_b133htn01_mode,
940 static const struct display_timing auo_g070vvn01_timings = {
941 .pixelclock = { 33300000, 34209000, 45000000 },
942 .hactive = { 800, 800, 800 },
943 .hfront_porch = { 20, 40, 200 },
944 .hback_porch = { 87, 40, 1 },
945 .hsync_len = { 1, 48, 87 },
946 .vactive = { 480, 480, 480 },
947 .vfront_porch = { 5, 13, 200 },
948 .vback_porch = { 31, 31, 29 },
949 .vsync_len = { 1, 1, 3 },
952 static const struct panel_desc auo_g070vvn01 = {
953 .timings = &auo_g070vvn01_timings,
968 static const struct drm_display_mode auo_g101evn010_mode = {
971 .hsync_start = 1280 + 82,
972 .hsync_end = 1280 + 82 + 2,
973 .htotal = 1280 + 82 + 2 + 84,
975 .vsync_start = 800 + 8,
976 .vsync_end = 800 + 8 + 2,
977 .vtotal = 800 + 8 + 2 + 6,
980 static const struct panel_desc auo_g101evn010 = {
981 .modes = &auo_g101evn010_mode,
988 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
989 .connector_type = DRM_MODE_CONNECTOR_LVDS,
992 static const struct drm_display_mode auo_g104sn02_mode = {
995 .hsync_start = 800 + 40,
996 .hsync_end = 800 + 40 + 216,
997 .htotal = 800 + 40 + 216 + 128,
999 .vsync_start = 600 + 10,
1000 .vsync_end = 600 + 10 + 35,
1001 .vtotal = 600 + 10 + 35 + 2,
1004 static const struct panel_desc auo_g104sn02 = {
1005 .modes = &auo_g104sn02_mode,
1014 static const struct drm_display_mode auo_g121ean01_mode = {
1017 .hsync_start = 1280 + 58,
1018 .hsync_end = 1280 + 58 + 8,
1019 .htotal = 1280 + 58 + 8 + 70,
1021 .vsync_start = 800 + 6,
1022 .vsync_end = 800 + 6 + 4,
1023 .vtotal = 800 + 6 + 4 + 10,
1026 static const struct panel_desc auo_g121ean01 = {
1027 .modes = &auo_g121ean01_mode,
1034 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1035 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1038 static const struct display_timing auo_g133han01_timings = {
1039 .pixelclock = { 134000000, 141200000, 149000000 },
1040 .hactive = { 1920, 1920, 1920 },
1041 .hfront_porch = { 39, 58, 77 },
1042 .hback_porch = { 59, 88, 117 },
1043 .hsync_len = { 28, 42, 56 },
1044 .vactive = { 1080, 1080, 1080 },
1045 .vfront_porch = { 3, 8, 11 },
1046 .vback_porch = { 5, 14, 19 },
1047 .vsync_len = { 4, 14, 19 },
1050 static const struct panel_desc auo_g133han01 = {
1051 .timings = &auo_g133han01_timings,
1064 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1065 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1068 static const struct drm_display_mode auo_g156xtn01_mode = {
1071 .hsync_start = 1366 + 33,
1072 .hsync_end = 1366 + 33 + 67,
1075 .vsync_start = 768 + 4,
1076 .vsync_end = 768 + 4 + 4,
1080 static const struct panel_desc auo_g156xtn01 = {
1081 .modes = &auo_g156xtn01_mode,
1088 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1089 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1092 static const struct display_timing auo_g185han01_timings = {
1093 .pixelclock = { 120000000, 144000000, 175000000 },
1094 .hactive = { 1920, 1920, 1920 },
1095 .hfront_porch = { 36, 120, 148 },
1096 .hback_porch = { 24, 88, 108 },
1097 .hsync_len = { 20, 48, 64 },
1098 .vactive = { 1080, 1080, 1080 },
1099 .vfront_porch = { 6, 10, 40 },
1100 .vback_porch = { 2, 5, 20 },
1101 .vsync_len = { 2, 5, 20 },
1104 static const struct panel_desc auo_g185han01 = {
1105 .timings = &auo_g185han01_timings,
1118 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1119 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1122 static const struct display_timing auo_g190ean01_timings = {
1123 .pixelclock = { 90000000, 108000000, 135000000 },
1124 .hactive = { 1280, 1280, 1280 },
1125 .hfront_porch = { 126, 184, 1266 },
1126 .hback_porch = { 84, 122, 844 },
1127 .hsync_len = { 70, 102, 704 },
1128 .vactive = { 1024, 1024, 1024 },
1129 .vfront_porch = { 4, 26, 76 },
1130 .vback_porch = { 2, 8, 25 },
1131 .vsync_len = { 2, 8, 25 },
1134 static const struct panel_desc auo_g190ean01 = {
1135 .timings = &auo_g190ean01_timings,
1148 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1149 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1152 static const struct display_timing auo_p320hvn03_timings = {
1153 .pixelclock = { 106000000, 148500000, 164000000 },
1154 .hactive = { 1920, 1920, 1920 },
1155 .hfront_porch = { 25, 50, 130 },
1156 .hback_porch = { 25, 50, 130 },
1157 .hsync_len = { 20, 40, 105 },
1158 .vactive = { 1080, 1080, 1080 },
1159 .vfront_porch = { 8, 17, 150 },
1160 .vback_porch = { 8, 17, 150 },
1161 .vsync_len = { 4, 11, 100 },
1164 static const struct panel_desc auo_p320hvn03 = {
1165 .timings = &auo_p320hvn03_timings,
1177 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1178 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1181 static const struct drm_display_mode auo_t215hvn01_mode = {
1184 .hsync_start = 1920 + 88,
1185 .hsync_end = 1920 + 88 + 44,
1186 .htotal = 1920 + 88 + 44 + 148,
1188 .vsync_start = 1080 + 4,
1189 .vsync_end = 1080 + 4 + 5,
1190 .vtotal = 1080 + 4 + 5 + 36,
1193 static const struct panel_desc auo_t215hvn01 = {
1194 .modes = &auo_t215hvn01_mode,
1207 static const struct drm_display_mode avic_tm070ddh03_mode = {
1210 .hsync_start = 1024 + 160,
1211 .hsync_end = 1024 + 160 + 4,
1212 .htotal = 1024 + 160 + 4 + 156,
1214 .vsync_start = 600 + 17,
1215 .vsync_end = 600 + 17 + 1,
1216 .vtotal = 600 + 17 + 1 + 17,
1219 static const struct panel_desc avic_tm070ddh03 = {
1220 .modes = &avic_tm070ddh03_mode,
1234 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1237 .hsync_start = 800 + 40,
1238 .hsync_end = 800 + 40 + 48,
1239 .htotal = 800 + 40 + 48 + 40,
1241 .vsync_start = 480 + 13,
1242 .vsync_end = 480 + 13 + 3,
1243 .vtotal = 480 + 13 + 3 + 29,
1246 static const struct panel_desc bananapi_s070wv20_ct16 = {
1247 .modes = &bananapi_s070wv20_ct16_mode,
1256 static const struct drm_display_mode boe_hv070wsa_mode = {
1259 .hsync_start = 1024 + 30,
1260 .hsync_end = 1024 + 30 + 30,
1261 .htotal = 1024 + 30 + 30 + 30,
1263 .vsync_start = 600 + 10,
1264 .vsync_end = 600 + 10 + 10,
1265 .vtotal = 600 + 10 + 10 + 10,
1268 static const struct panel_desc boe_hv070wsa = {
1269 .modes = &boe_hv070wsa_mode,
1276 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1277 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1278 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1281 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1285 .hsync_start = 1280 + 48,
1286 .hsync_end = 1280 + 48 + 32,
1287 .htotal = 1280 + 48 + 32 + 80,
1289 .vsync_start = 800 + 3,
1290 .vsync_end = 800 + 3 + 5,
1291 .vtotal = 800 + 3 + 5 + 24,
1296 .hsync_start = 1280 + 48,
1297 .hsync_end = 1280 + 48 + 32,
1298 .htotal = 1280 + 48 + 32 + 80,
1300 .vsync_start = 800 + 3,
1301 .vsync_end = 800 + 3 + 5,
1302 .vtotal = 800 + 3 + 5 + 24,
1306 static const struct panel_desc boe_nv101wxmn51 = {
1307 .modes = boe_nv101wxmn51_modes,
1308 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1321 /* Also used for boe_nv133fhm_n62 */
1322 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1325 .hsync_start = 1920 + 48,
1326 .hsync_end = 1920 + 48 + 32,
1327 .htotal = 1920 + 48 + 32 + 200,
1329 .vsync_start = 1080 + 3,
1330 .vsync_end = 1080 + 3 + 6,
1331 .vtotal = 1080 + 3 + 6 + 31,
1332 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1335 /* Also used for boe_nv133fhm_n62 */
1336 static const struct panel_desc boe_nv133fhm_n61 = {
1337 .modes = &boe_nv133fhm_n61_modes,
1346 * When power is first given to the panel there's a short
1347 * spike on the HPD line. It was explained that this spike
1348 * was until the TCON data download was complete. On
1349 * one system this was measured at 8 ms. We'll put 15 ms
1350 * in the prepare delay just to be safe and take it away
1351 * from the hpd_absent_delay (which would otherwise be 200 ms)
1352 * to handle this. That means:
1353 * - If HPD isn't hooked up you still have 200 ms delay.
1354 * - If HPD is hooked up we won't try to look at it for the
1358 .hpd_absent_delay = 185,
1362 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1363 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1364 .connector_type = DRM_MODE_CONNECTOR_eDP,
1367 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1371 .hsync_start = 1920 + 48,
1372 .hsync_end = 1920 + 48 + 32,
1375 .vsync_start = 1080 + 3,
1376 .vsync_end = 1080 + 3 + 5,
1381 static const struct panel_desc boe_nv140fhmn49 = {
1382 .modes = boe_nv140fhmn49_modes,
1383 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1394 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1395 .connector_type = DRM_MODE_CONNECTOR_eDP,
1398 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1401 .hsync_start = 480 + 5,
1402 .hsync_end = 480 + 5 + 5,
1403 .htotal = 480 + 5 + 5 + 40,
1405 .vsync_start = 272 + 8,
1406 .vsync_end = 272 + 8 + 8,
1407 .vtotal = 272 + 8 + 8 + 8,
1408 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1411 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1412 .modes = &cdtech_s043wq26h_ct7_mode,
1419 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1422 /* S070PWS19HP-FC21 2017/04/22 */
1423 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1426 .hsync_start = 1024 + 160,
1427 .hsync_end = 1024 + 160 + 20,
1428 .htotal = 1024 + 160 + 20 + 140,
1430 .vsync_start = 600 + 12,
1431 .vsync_end = 600 + 12 + 3,
1432 .vtotal = 600 + 12 + 3 + 20,
1433 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1436 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1437 .modes = &cdtech_s070pws19hp_fc21_mode,
1444 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1445 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1446 .connector_type = DRM_MODE_CONNECTOR_DPI,
1449 /* S070SWV29HG-DC44 2017/09/21 */
1450 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1453 .hsync_start = 800 + 210,
1454 .hsync_end = 800 + 210 + 2,
1455 .htotal = 800 + 210 + 2 + 44,
1457 .vsync_start = 480 + 22,
1458 .vsync_end = 480 + 22 + 2,
1459 .vtotal = 480 + 22 + 2 + 21,
1460 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1463 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1464 .modes = &cdtech_s070swv29hg_dc44_mode,
1471 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1472 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1473 .connector_type = DRM_MODE_CONNECTOR_DPI,
1476 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1479 .hsync_start = 800 + 40,
1480 .hsync_end = 800 + 40 + 40,
1481 .htotal = 800 + 40 + 40 + 48,
1483 .vsync_start = 480 + 29,
1484 .vsync_end = 480 + 29 + 13,
1485 .vtotal = 480 + 29 + 13 + 3,
1486 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1489 static const struct panel_desc cdtech_s070wv95_ct16 = {
1490 .modes = &cdtech_s070wv95_ct16_mode,
1499 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1500 .pixelclock = { 68900000, 71100000, 73400000 },
1501 .hactive = { 1280, 1280, 1280 },
1502 .hfront_porch = { 65, 80, 95 },
1503 .hback_porch = { 64, 79, 94 },
1504 .hsync_len = { 1, 1, 1 },
1505 .vactive = { 800, 800, 800 },
1506 .vfront_porch = { 7, 11, 14 },
1507 .vback_porch = { 7, 11, 14 },
1508 .vsync_len = { 1, 1, 1 },
1509 .flags = DISPLAY_FLAGS_DE_HIGH,
1512 static const struct panel_desc chefree_ch101olhlwh_002 = {
1513 .timings = &chefree_ch101olhlwh_002_timing,
1524 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1525 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1526 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1529 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1532 .hsync_start = 800 + 49,
1533 .hsync_end = 800 + 49 + 33,
1534 .htotal = 800 + 49 + 33 + 17,
1536 .vsync_start = 1280 + 1,
1537 .vsync_end = 1280 + 1 + 7,
1538 .vtotal = 1280 + 1 + 7 + 15,
1539 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1542 static const struct panel_desc chunghwa_claa070wp03xg = {
1543 .modes = &chunghwa_claa070wp03xg_mode,
1550 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1551 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1552 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1555 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1558 .hsync_start = 1366 + 58,
1559 .hsync_end = 1366 + 58 + 58,
1560 .htotal = 1366 + 58 + 58 + 58,
1562 .vsync_start = 768 + 4,
1563 .vsync_end = 768 + 4 + 4,
1564 .vtotal = 768 + 4 + 4 + 4,
1567 static const struct panel_desc chunghwa_claa101wa01a = {
1568 .modes = &chunghwa_claa101wa01a_mode,
1575 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1576 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1577 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1580 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1583 .hsync_start = 1366 + 48,
1584 .hsync_end = 1366 + 48 + 32,
1585 .htotal = 1366 + 48 + 32 + 20,
1587 .vsync_start = 768 + 16,
1588 .vsync_end = 768 + 16 + 8,
1589 .vtotal = 768 + 16 + 8 + 16,
1592 static const struct panel_desc chunghwa_claa101wb01 = {
1593 .modes = &chunghwa_claa101wb01_mode,
1600 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1601 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1602 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1605 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1608 .hsync_start = 800 + 40,
1609 .hsync_end = 800 + 40 + 128,
1610 .htotal = 800 + 40 + 128 + 88,
1612 .vsync_start = 480 + 10,
1613 .vsync_end = 480 + 10 + 2,
1614 .vtotal = 480 + 10 + 2 + 33,
1615 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1618 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1619 .modes = &dataimage_scf0700c48ggu18_mode,
1626 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1627 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1630 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1631 .pixelclock = { 45000000, 51200000, 57000000 },
1632 .hactive = { 1024, 1024, 1024 },
1633 .hfront_porch = { 100, 106, 113 },
1634 .hback_porch = { 100, 106, 113 },
1635 .hsync_len = { 100, 108, 114 },
1636 .vactive = { 600, 600, 600 },
1637 .vfront_porch = { 8, 11, 15 },
1638 .vback_porch = { 8, 11, 15 },
1639 .vsync_len = { 9, 13, 15 },
1640 .flags = DISPLAY_FLAGS_DE_HIGH,
1643 static const struct panel_desc dlc_dlc0700yzg_1 = {
1644 .timings = &dlc_dlc0700yzg_1_timing,
1656 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1657 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1660 static const struct display_timing dlc_dlc1010gig_timing = {
1661 .pixelclock = { 68900000, 71100000, 73400000 },
1662 .hactive = { 1280, 1280, 1280 },
1663 .hfront_porch = { 43, 53, 63 },
1664 .hback_porch = { 43, 53, 63 },
1665 .hsync_len = { 44, 54, 64 },
1666 .vactive = { 800, 800, 800 },
1667 .vfront_porch = { 5, 8, 11 },
1668 .vback_porch = { 5, 8, 11 },
1669 .vsync_len = { 5, 7, 11 },
1670 .flags = DISPLAY_FLAGS_DE_HIGH,
1673 static const struct panel_desc dlc_dlc1010gig = {
1674 .timings = &dlc_dlc1010gig_timing,
1687 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1688 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1691 static const struct drm_display_mode edt_et035012dm6_mode = {
1694 .hsync_start = 320 + 20,
1695 .hsync_end = 320 + 20 + 30,
1696 .htotal = 320 + 20 + 68,
1698 .vsync_start = 240 + 4,
1699 .vsync_end = 240 + 4 + 4,
1700 .vtotal = 240 + 4 + 4 + 14,
1701 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1704 static const struct panel_desc edt_et035012dm6 = {
1705 .modes = &edt_et035012dm6_mode,
1712 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1713 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1716 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1719 .hsync_start = 480 + 8,
1720 .hsync_end = 480 + 8 + 4,
1721 .htotal = 480 + 8 + 4 + 41,
1724 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1729 .vsync_start = 288 + 2,
1730 .vsync_end = 288 + 2 + 4,
1731 .vtotal = 288 + 2 + 4 + 10,
1734 static const struct panel_desc edt_etm043080dh6gp = {
1735 .modes = &edt_etm043080dh6gp_mode,
1742 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1743 .connector_type = DRM_MODE_CONNECTOR_DPI,
1746 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1749 .hsync_start = 480 + 2,
1750 .hsync_end = 480 + 2 + 41,
1751 .htotal = 480 + 2 + 41 + 2,
1753 .vsync_start = 272 + 2,
1754 .vsync_end = 272 + 2 + 10,
1755 .vtotal = 272 + 2 + 10 + 2,
1756 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1759 static const struct panel_desc edt_etm0430g0dh6 = {
1760 .modes = &edt_etm0430g0dh6_mode,
1769 static const struct drm_display_mode edt_et057090dhu_mode = {
1772 .hsync_start = 640 + 16,
1773 .hsync_end = 640 + 16 + 30,
1774 .htotal = 640 + 16 + 30 + 114,
1776 .vsync_start = 480 + 10,
1777 .vsync_end = 480 + 10 + 3,
1778 .vtotal = 480 + 10 + 3 + 32,
1779 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1782 static const struct panel_desc edt_et057090dhu = {
1783 .modes = &edt_et057090dhu_mode,
1790 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1791 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1792 .connector_type = DRM_MODE_CONNECTOR_DPI,
1795 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1798 .hsync_start = 800 + 40,
1799 .hsync_end = 800 + 40 + 128,
1800 .htotal = 800 + 40 + 128 + 88,
1802 .vsync_start = 480 + 10,
1803 .vsync_end = 480 + 10 + 2,
1804 .vtotal = 480 + 10 + 2 + 33,
1805 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1808 static const struct panel_desc edt_etm0700g0dh6 = {
1809 .modes = &edt_etm0700g0dh6_mode,
1816 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1817 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1818 .connector_type = DRM_MODE_CONNECTOR_DPI,
1821 static const struct panel_desc edt_etm0700g0bdh6 = {
1822 .modes = &edt_etm0700g0dh6_mode,
1829 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1830 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1833 static const struct display_timing evervision_vgg804821_timing = {
1834 .pixelclock = { 27600000, 33300000, 50000000 },
1835 .hactive = { 800, 800, 800 },
1836 .hfront_porch = { 40, 66, 70 },
1837 .hback_porch = { 40, 67, 70 },
1838 .hsync_len = { 40, 67, 70 },
1839 .vactive = { 480, 480, 480 },
1840 .vfront_porch = { 6, 10, 10 },
1841 .vback_porch = { 7, 11, 11 },
1842 .vsync_len = { 7, 11, 11 },
1843 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1844 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1845 DISPLAY_FLAGS_SYNC_NEGEDGE,
1848 static const struct panel_desc evervision_vgg804821 = {
1849 .timings = &evervision_vgg804821_timing,
1856 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1857 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1860 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1863 .hsync_start = 800 + 168,
1864 .hsync_end = 800 + 168 + 64,
1865 .htotal = 800 + 168 + 64 + 88,
1867 .vsync_start = 480 + 37,
1868 .vsync_end = 480 + 37 + 2,
1869 .vtotal = 480 + 37 + 2 + 8,
1872 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1873 .modes = &foxlink_fl500wvr00_a0t_mode,
1880 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1883 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1887 .hsync_start = 320 + 44,
1888 .hsync_end = 320 + 44 + 16,
1889 .htotal = 320 + 44 + 16 + 20,
1891 .vsync_start = 240 + 2,
1892 .vsync_end = 240 + 2 + 6,
1893 .vtotal = 240 + 2 + 6 + 2,
1894 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1899 .hsync_start = 320 + 56,
1900 .hsync_end = 320 + 56 + 16,
1901 .htotal = 320 + 56 + 16 + 40,
1903 .vsync_start = 240 + 2,
1904 .vsync_end = 240 + 2 + 6,
1905 .vtotal = 240 + 2 + 6 + 2,
1906 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1910 static const struct panel_desc frida_frd350h54004 = {
1911 .modes = frida_frd350h54004_modes,
1912 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1918 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1920 .connector_type = DRM_MODE_CONNECTOR_DPI,
1923 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1926 .hsync_start = 800 + 20,
1927 .hsync_end = 800 + 20 + 24,
1928 .htotal = 800 + 20 + 24 + 20,
1930 .vsync_start = 1280 + 4,
1931 .vsync_end = 1280 + 4 + 8,
1932 .vtotal = 1280 + 4 + 8 + 4,
1933 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1936 static const struct panel_desc friendlyarm_hd702e = {
1937 .modes = &friendlyarm_hd702e_mode,
1945 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1948 .hsync_start = 480 + 5,
1949 .hsync_end = 480 + 5 + 1,
1950 .htotal = 480 + 5 + 1 + 40,
1952 .vsync_start = 272 + 8,
1953 .vsync_end = 272 + 8 + 1,
1954 .vtotal = 272 + 8 + 1 + 8,
1957 static const struct panel_desc giantplus_gpg482739qs5 = {
1958 .modes = &giantplus_gpg482739qs5_mode,
1965 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1968 static const struct display_timing giantplus_gpm940b0_timing = {
1969 .pixelclock = { 13500000, 27000000, 27500000 },
1970 .hactive = { 320, 320, 320 },
1971 .hfront_porch = { 14, 686, 718 },
1972 .hback_porch = { 50, 70, 255 },
1973 .hsync_len = { 1, 1, 1 },
1974 .vactive = { 240, 240, 240 },
1975 .vfront_porch = { 1, 1, 179 },
1976 .vback_porch = { 1, 21, 31 },
1977 .vsync_len = { 1, 1, 6 },
1978 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1981 static const struct panel_desc giantplus_gpm940b0 = {
1982 .timings = &giantplus_gpm940b0_timing,
1989 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1990 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1993 static const struct display_timing hannstar_hsd070pww1_timing = {
1994 .pixelclock = { 64300000, 71100000, 82000000 },
1995 .hactive = { 1280, 1280, 1280 },
1996 .hfront_porch = { 1, 1, 10 },
1997 .hback_porch = { 1, 1, 10 },
1999 * According to the data sheet, the minimum horizontal blanking interval
2000 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2001 * minimum working horizontal blanking interval to be 60 clocks.
2003 .hsync_len = { 58, 158, 661 },
2004 .vactive = { 800, 800, 800 },
2005 .vfront_porch = { 1, 1, 10 },
2006 .vback_porch = { 1, 1, 10 },
2007 .vsync_len = { 1, 21, 203 },
2008 .flags = DISPLAY_FLAGS_DE_HIGH,
2011 static const struct panel_desc hannstar_hsd070pww1 = {
2012 .timings = &hannstar_hsd070pww1_timing,
2019 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2020 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2023 static const struct display_timing hannstar_hsd100pxn1_timing = {
2024 .pixelclock = { 55000000, 65000000, 75000000 },
2025 .hactive = { 1024, 1024, 1024 },
2026 .hfront_porch = { 40, 40, 40 },
2027 .hback_porch = { 220, 220, 220 },
2028 .hsync_len = { 20, 60, 100 },
2029 .vactive = { 768, 768, 768 },
2030 .vfront_porch = { 7, 7, 7 },
2031 .vback_porch = { 21, 21, 21 },
2032 .vsync_len = { 10, 10, 10 },
2033 .flags = DISPLAY_FLAGS_DE_HIGH,
2036 static const struct panel_desc hannstar_hsd100pxn1 = {
2037 .timings = &hannstar_hsd100pxn1_timing,
2044 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2045 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2048 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2051 .hsync_start = 800 + 85,
2052 .hsync_end = 800 + 85 + 86,
2053 .htotal = 800 + 85 + 86 + 85,
2055 .vsync_start = 480 + 16,
2056 .vsync_end = 480 + 16 + 13,
2057 .vtotal = 480 + 16 + 13 + 16,
2060 static const struct panel_desc hitachi_tx23d38vm0caa = {
2061 .modes = &hitachi_tx23d38vm0caa_mode,
2074 static const struct drm_display_mode innolux_at043tn24_mode = {
2077 .hsync_start = 480 + 2,
2078 .hsync_end = 480 + 2 + 41,
2079 .htotal = 480 + 2 + 41 + 2,
2081 .vsync_start = 272 + 2,
2082 .vsync_end = 272 + 2 + 10,
2083 .vtotal = 272 + 2 + 10 + 2,
2084 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2087 static const struct panel_desc innolux_at043tn24 = {
2088 .modes = &innolux_at043tn24_mode,
2095 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2096 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2099 static const struct drm_display_mode innolux_at070tn92_mode = {
2102 .hsync_start = 800 + 210,
2103 .hsync_end = 800 + 210 + 20,
2104 .htotal = 800 + 210 + 20 + 46,
2106 .vsync_start = 480 + 22,
2107 .vsync_end = 480 + 22 + 10,
2108 .vtotal = 480 + 22 + 23 + 10,
2111 static const struct panel_desc innolux_at070tn92 = {
2112 .modes = &innolux_at070tn92_mode,
2118 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2121 static const struct display_timing innolux_g070y2_l01_timing = {
2122 .pixelclock = { 28000000, 29500000, 32000000 },
2123 .hactive = { 800, 800, 800 },
2124 .hfront_porch = { 61, 91, 141 },
2125 .hback_porch = { 60, 90, 140 },
2126 .hsync_len = { 12, 12, 12 },
2127 .vactive = { 480, 480, 480 },
2128 .vfront_porch = { 4, 9, 30 },
2129 .vback_porch = { 4, 8, 28 },
2130 .vsync_len = { 2, 2, 2 },
2131 .flags = DISPLAY_FLAGS_DE_HIGH,
2134 static const struct panel_desc innolux_g070y2_l01 = {
2135 .timings = &innolux_g070y2_l01_timing,
2148 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2149 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2152 static const struct display_timing innolux_g101ice_l01_timing = {
2153 .pixelclock = { 60400000, 71100000, 74700000 },
2154 .hactive = { 1280, 1280, 1280 },
2155 .hfront_porch = { 41, 80, 100 },
2156 .hback_porch = { 40, 79, 99 },
2157 .hsync_len = { 1, 1, 1 },
2158 .vactive = { 800, 800, 800 },
2159 .vfront_porch = { 5, 11, 14 },
2160 .vback_porch = { 4, 11, 14 },
2161 .vsync_len = { 1, 1, 1 },
2162 .flags = DISPLAY_FLAGS_DE_HIGH,
2165 static const struct panel_desc innolux_g101ice_l01 = {
2166 .timings = &innolux_g101ice_l01_timing,
2177 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2178 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2181 static const struct display_timing innolux_g121i1_l01_timing = {
2182 .pixelclock = { 67450000, 71000000, 74550000 },
2183 .hactive = { 1280, 1280, 1280 },
2184 .hfront_porch = { 40, 80, 160 },
2185 .hback_porch = { 39, 79, 159 },
2186 .hsync_len = { 1, 1, 1 },
2187 .vactive = { 800, 800, 800 },
2188 .vfront_porch = { 5, 11, 100 },
2189 .vback_porch = { 4, 11, 99 },
2190 .vsync_len = { 1, 1, 1 },
2193 static const struct panel_desc innolux_g121i1_l01 = {
2194 .timings = &innolux_g121i1_l01_timing,
2205 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2206 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2209 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2212 .hsync_start = 1024 + 0,
2213 .hsync_end = 1024 + 1,
2214 .htotal = 1024 + 0 + 1 + 320,
2216 .vsync_start = 768 + 38,
2217 .vsync_end = 768 + 38 + 1,
2218 .vtotal = 768 + 38 + 1 + 0,
2219 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2222 static const struct panel_desc innolux_g121x1_l03 = {
2223 .modes = &innolux_g121x1_l03_mode,
2238 * Datasheet specifies that at 60 Hz refresh rate:
2239 * - total horizontal time: { 1506, 1592, 1716 }
2240 * - total vertical time: { 788, 800, 868 }
2242 * ...but doesn't go into exactly how that should be split into a front
2243 * porch, back porch, or sync length. For now we'll leave a single setting
2244 * here which allows a bit of tweaking of the pixel clock at the expense of
2247 static const struct display_timing innolux_n116bge_timing = {
2248 .pixelclock = { 72600000, 76420000, 80240000 },
2249 .hactive = { 1366, 1366, 1366 },
2250 .hfront_porch = { 136, 136, 136 },
2251 .hback_porch = { 60, 60, 60 },
2252 .hsync_len = { 30, 30, 30 },
2253 .vactive = { 768, 768, 768 },
2254 .vfront_porch = { 8, 8, 8 },
2255 .vback_porch = { 12, 12, 12 },
2256 .vsync_len = { 12, 12, 12 },
2257 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2260 static const struct panel_desc innolux_n116bge = {
2261 .timings = &innolux_n116bge_timing,
2270 static const struct drm_display_mode innolux_n125hce_gn1_mode = {
2273 .hsync_start = 1920 + 40,
2274 .hsync_end = 1920 + 40 + 40,
2275 .htotal = 1920 + 40 + 40 + 80,
2277 .vsync_start = 1080 + 4,
2278 .vsync_end = 1080 + 4 + 4,
2279 .vtotal = 1080 + 4 + 4 + 24,
2282 static const struct panel_desc innolux_n125hce_gn1 = {
2283 .modes = &innolux_n125hce_gn1_mode,
2290 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2291 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2292 .connector_type = DRM_MODE_CONNECTOR_eDP,
2295 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2298 .hsync_start = 1366 + 16,
2299 .hsync_end = 1366 + 16 + 34,
2300 .htotal = 1366 + 16 + 34 + 50,
2302 .vsync_start = 768 + 2,
2303 .vsync_end = 768 + 2 + 6,
2304 .vtotal = 768 + 2 + 6 + 12,
2307 static const struct panel_desc innolux_n156bge_l21 = {
2308 .modes = &innolux_n156bge_l21_mode,
2315 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2316 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2317 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2320 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2323 .hsync_start = 2160 + 48,
2324 .hsync_end = 2160 + 48 + 32,
2325 .htotal = 2160 + 48 + 32 + 80,
2327 .vsync_start = 1440 + 3,
2328 .vsync_end = 1440 + 3 + 10,
2329 .vtotal = 1440 + 3 + 10 + 27,
2330 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2333 static const struct panel_desc innolux_p120zdg_bf1 = {
2334 .modes = &innolux_p120zdg_bf1_mode,
2342 .hpd_absent_delay = 200,
2347 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2350 .hsync_start = 1024 + 128,
2351 .hsync_end = 1024 + 128 + 64,
2352 .htotal = 1024 + 128 + 64 + 128,
2354 .vsync_start = 600 + 16,
2355 .vsync_end = 600 + 16 + 4,
2356 .vtotal = 600 + 16 + 4 + 16,
2359 static const struct panel_desc innolux_zj070na_01p = {
2360 .modes = &innolux_zj070na_01p_mode,
2369 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2372 .hsync_start = 1920 + 24,
2373 .hsync_end = 1920 + 24 + 48,
2374 .htotal = 1920 + 24 + 48 + 88,
2376 .vsync_start = 1080 + 3,
2377 .vsync_end = 1080 + 3 + 12,
2378 .vtotal = 1080 + 3 + 12 + 17,
2379 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2382 static const struct panel_desc ivo_m133nwf4_r0 = {
2383 .modes = &ivo_m133nwf4_r0_mode,
2391 .hpd_absent_delay = 200,
2394 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2395 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2396 .connector_type = DRM_MODE_CONNECTOR_eDP,
2399 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2402 .hsync_start = 1366 + 40,
2403 .hsync_end = 1366 + 40 + 32,
2404 .htotal = 1366 + 40 + 32 + 62,
2406 .vsync_start = 768 + 5,
2407 .vsync_end = 768 + 5 + 5,
2408 .vtotal = 768 + 5 + 5 + 122,
2409 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2412 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2413 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2421 .hpd_absent_delay = 200,
2423 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2424 .connector_type = DRM_MODE_CONNECTOR_eDP,
2427 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2428 .pixelclock = { 5580000, 5850000, 6200000 },
2429 .hactive = { 320, 320, 320 },
2430 .hfront_porch = { 30, 30, 30 },
2431 .hback_porch = { 30, 30, 30 },
2432 .hsync_len = { 1, 5, 17 },
2433 .vactive = { 240, 240, 240 },
2434 .vfront_porch = { 6, 6, 6 },
2435 .vback_porch = { 5, 5, 5 },
2436 .vsync_len = { 1, 2, 11 },
2437 .flags = DISPLAY_FLAGS_DE_HIGH,
2440 static const struct panel_desc koe_tx14d24vm1bpa = {
2441 .timings = &koe_tx14d24vm1bpa_timing,
2450 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2451 .pixelclock = { 151820000, 156720000, 159780000 },
2452 .hactive = { 1920, 1920, 1920 },
2453 .hfront_porch = { 105, 130, 142 },
2454 .hback_porch = { 45, 70, 82 },
2455 .hsync_len = { 30, 30, 30 },
2456 .vactive = { 1200, 1200, 1200},
2457 .vfront_porch = { 3, 5, 10 },
2458 .vback_porch = { 2, 5, 10 },
2459 .vsync_len = { 5, 5, 5 },
2462 static const struct panel_desc koe_tx26d202vm0bwa = {
2463 .timings = &koe_tx26d202vm0bwa_timing,
2476 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2477 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2478 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2481 static const struct display_timing koe_tx31d200vm0baa_timing = {
2482 .pixelclock = { 39600000, 43200000, 48000000 },
2483 .hactive = { 1280, 1280, 1280 },
2484 .hfront_porch = { 16, 36, 56 },
2485 .hback_porch = { 16, 36, 56 },
2486 .hsync_len = { 8, 8, 8 },
2487 .vactive = { 480, 480, 480 },
2488 .vfront_porch = { 6, 21, 33 },
2489 .vback_porch = { 6, 21, 33 },
2490 .vsync_len = { 8, 8, 8 },
2491 .flags = DISPLAY_FLAGS_DE_HIGH,
2494 static const struct panel_desc koe_tx31d200vm0baa = {
2495 .timings = &koe_tx31d200vm0baa_timing,
2502 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2503 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2506 static const struct display_timing kyo_tcg121xglp_timing = {
2507 .pixelclock = { 52000000, 65000000, 71000000 },
2508 .hactive = { 1024, 1024, 1024 },
2509 .hfront_porch = { 2, 2, 2 },
2510 .hback_porch = { 2, 2, 2 },
2511 .hsync_len = { 86, 124, 244 },
2512 .vactive = { 768, 768, 768 },
2513 .vfront_porch = { 2, 2, 2 },
2514 .vback_porch = { 2, 2, 2 },
2515 .vsync_len = { 6, 34, 73 },
2516 .flags = DISPLAY_FLAGS_DE_HIGH,
2519 static const struct panel_desc kyo_tcg121xglp = {
2520 .timings = &kyo_tcg121xglp_timing,
2527 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2528 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2531 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2534 .hsync_start = 320 + 20,
2535 .hsync_end = 320 + 20 + 30,
2536 .htotal = 320 + 20 + 30 + 38,
2538 .vsync_start = 240 + 4,
2539 .vsync_end = 240 + 4 + 3,
2540 .vtotal = 240 + 4 + 3 + 15,
2543 static const struct panel_desc lemaker_bl035_rgb_002 = {
2544 .modes = &lemaker_bl035_rgb_002_mode,
2550 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2551 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2554 static const struct drm_display_mode lg_lb070wv8_mode = {
2557 .hsync_start = 800 + 88,
2558 .hsync_end = 800 + 88 + 80,
2559 .htotal = 800 + 88 + 80 + 88,
2561 .vsync_start = 480 + 10,
2562 .vsync_end = 480 + 10 + 25,
2563 .vtotal = 480 + 10 + 25 + 10,
2566 static const struct panel_desc lg_lb070wv8 = {
2567 .modes = &lg_lb070wv8_mode,
2574 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2575 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2578 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2581 .hsync_start = 1536 + 12,
2582 .hsync_end = 1536 + 12 + 16,
2583 .htotal = 1536 + 12 + 16 + 48,
2585 .vsync_start = 2048 + 8,
2586 .vsync_end = 2048 + 8 + 4,
2587 .vtotal = 2048 + 8 + 4 + 8,
2588 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2591 static const struct panel_desc lg_lp079qx1_sp0v = {
2592 .modes = &lg_lp079qx1_sp0v_mode,
2600 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2603 .hsync_start = 2048 + 150,
2604 .hsync_end = 2048 + 150 + 5,
2605 .htotal = 2048 + 150 + 5 + 5,
2607 .vsync_start = 1536 + 3,
2608 .vsync_end = 1536 + 3 + 1,
2609 .vtotal = 1536 + 3 + 1 + 9,
2612 static const struct panel_desc lg_lp097qx1_spa1 = {
2613 .modes = &lg_lp097qx1_spa1_mode,
2621 static const struct drm_display_mode lg_lp120up1_mode = {
2624 .hsync_start = 1920 + 40,
2625 .hsync_end = 1920 + 40 + 40,
2626 .htotal = 1920 + 40 + 40+ 80,
2628 .vsync_start = 1280 + 4,
2629 .vsync_end = 1280 + 4 + 4,
2630 .vtotal = 1280 + 4 + 4 + 12,
2633 static const struct panel_desc lg_lp120up1 = {
2634 .modes = &lg_lp120up1_mode,
2641 .connector_type = DRM_MODE_CONNECTOR_eDP,
2644 static const struct drm_display_mode lg_lp129qe_mode = {
2647 .hsync_start = 2560 + 48,
2648 .hsync_end = 2560 + 48 + 32,
2649 .htotal = 2560 + 48 + 32 + 80,
2651 .vsync_start = 1700 + 3,
2652 .vsync_end = 1700 + 3 + 10,
2653 .vtotal = 1700 + 3 + 10 + 36,
2656 static const struct panel_desc lg_lp129qe = {
2657 .modes = &lg_lp129qe_mode,
2666 static const struct display_timing logictechno_lt161010_2nh_timing = {
2667 .pixelclock = { 26400000, 33300000, 46800000 },
2668 .hactive = { 800, 800, 800 },
2669 .hfront_porch = { 16, 210, 354 },
2670 .hback_porch = { 46, 46, 46 },
2671 .hsync_len = { 1, 20, 40 },
2672 .vactive = { 480, 480, 480 },
2673 .vfront_porch = { 7, 22, 147 },
2674 .vback_porch = { 23, 23, 23 },
2675 .vsync_len = { 1, 10, 20 },
2676 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2677 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2678 DISPLAY_FLAGS_SYNC_POSEDGE,
2681 static const struct panel_desc logictechno_lt161010_2nh = {
2682 .timings = &logictechno_lt161010_2nh_timing,
2688 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2689 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2690 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2691 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2692 .connector_type = DRM_MODE_CONNECTOR_DPI,
2695 static const struct display_timing logictechno_lt170410_2whc_timing = {
2696 .pixelclock = { 68900000, 71100000, 73400000 },
2697 .hactive = { 1280, 1280, 1280 },
2698 .hfront_porch = { 23, 60, 71 },
2699 .hback_porch = { 23, 60, 71 },
2700 .hsync_len = { 15, 40, 47 },
2701 .vactive = { 800, 800, 800 },
2702 .vfront_porch = { 5, 7, 10 },
2703 .vback_porch = { 5, 7, 10 },
2704 .vsync_len = { 6, 9, 12 },
2705 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2706 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2707 DISPLAY_FLAGS_SYNC_POSEDGE,
2710 static const struct panel_desc logictechno_lt170410_2whc = {
2711 .timings = &logictechno_lt170410_2whc_timing,
2717 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2718 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2719 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2722 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2725 .hsync_start = 800 + 0,
2726 .hsync_end = 800 + 1,
2727 .htotal = 800 + 0 + 1 + 160,
2729 .vsync_start = 480 + 0,
2730 .vsync_end = 480 + 48 + 1,
2731 .vtotal = 480 + 48 + 1 + 0,
2732 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2735 static const struct drm_display_mode logicpd_type_28_mode = {
2738 .hsync_start = 480 + 3,
2739 .hsync_end = 480 + 3 + 42,
2740 .htotal = 480 + 3 + 42 + 2,
2743 .vsync_start = 272 + 2,
2744 .vsync_end = 272 + 2 + 11,
2745 .vtotal = 272 + 2 + 11 + 3,
2746 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2749 static const struct panel_desc logicpd_type_28 = {
2750 .modes = &logicpd_type_28_mode,
2763 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2764 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2765 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2766 .connector_type = DRM_MODE_CONNECTOR_DPI,
2769 static const struct panel_desc mitsubishi_aa070mc01 = {
2770 .modes = &mitsubishi_aa070mc01_mode,
2783 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2784 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2785 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2788 static const struct display_timing nec_nl12880bc20_05_timing = {
2789 .pixelclock = { 67000000, 71000000, 75000000 },
2790 .hactive = { 1280, 1280, 1280 },
2791 .hfront_porch = { 2, 30, 30 },
2792 .hback_porch = { 6, 100, 100 },
2793 .hsync_len = { 2, 30, 30 },
2794 .vactive = { 800, 800, 800 },
2795 .vfront_porch = { 5, 5, 5 },
2796 .vback_porch = { 11, 11, 11 },
2797 .vsync_len = { 7, 7, 7 },
2800 static const struct panel_desc nec_nl12880bc20_05 = {
2801 .timings = &nec_nl12880bc20_05_timing,
2812 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2813 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2816 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2819 .hsync_start = 480 + 2,
2820 .hsync_end = 480 + 2 + 41,
2821 .htotal = 480 + 2 + 41 + 2,
2823 .vsync_start = 272 + 2,
2824 .vsync_end = 272 + 2 + 4,
2825 .vtotal = 272 + 2 + 4 + 2,
2826 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2829 static const struct panel_desc nec_nl4827hc19_05b = {
2830 .modes = &nec_nl4827hc19_05b_mode,
2837 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2838 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2841 static const struct drm_display_mode netron_dy_e231732_mode = {
2844 .hsync_start = 1024 + 160,
2845 .hsync_end = 1024 + 160 + 70,
2846 .htotal = 1024 + 160 + 70 + 90,
2848 .vsync_start = 600 + 127,
2849 .vsync_end = 600 + 127 + 20,
2850 .vtotal = 600 + 127 + 20 + 3,
2853 static const struct panel_desc netron_dy_e231732 = {
2854 .modes = &netron_dy_e231732_mode,
2860 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2863 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2867 .hsync_start = 1920 + 48,
2868 .hsync_end = 1920 + 48 + 32,
2869 .htotal = 1920 + 48 + 32 + 80,
2871 .vsync_start = 1080 + 3,
2872 .vsync_end = 1080 + 3 + 5,
2873 .vtotal = 1080 + 3 + 5 + 23,
2874 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2878 .hsync_start = 1920 + 48,
2879 .hsync_end = 1920 + 48 + 32,
2880 .htotal = 1920 + 48 + 32 + 80,
2882 .vsync_start = 1080 + 3,
2883 .vsync_end = 1080 + 3 + 5,
2884 .vtotal = 1080 + 3 + 5 + 23,
2885 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2889 static const struct panel_desc neweast_wjfh116008a = {
2890 .modes = neweast_wjfh116008a_modes,
2902 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2903 .connector_type = DRM_MODE_CONNECTOR_eDP,
2906 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2909 .hsync_start = 480 + 2,
2910 .hsync_end = 480 + 2 + 41,
2911 .htotal = 480 + 2 + 41 + 2,
2913 .vsync_start = 272 + 2,
2914 .vsync_end = 272 + 2 + 10,
2915 .vtotal = 272 + 2 + 10 + 2,
2916 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2919 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2920 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2927 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2928 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2929 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2930 .connector_type = DRM_MODE_CONNECTOR_DPI,
2933 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2934 .pixelclock = { 130000000, 148350000, 163000000 },
2935 .hactive = { 1920, 1920, 1920 },
2936 .hfront_porch = { 80, 100, 100 },
2937 .hback_porch = { 100, 120, 120 },
2938 .hsync_len = { 50, 60, 60 },
2939 .vactive = { 1080, 1080, 1080 },
2940 .vfront_porch = { 12, 30, 30 },
2941 .vback_porch = { 4, 10, 10 },
2942 .vsync_len = { 4, 5, 5 },
2945 static const struct panel_desc nlt_nl192108ac18_02d = {
2946 .timings = &nlt_nl192108ac18_02d_timing,
2956 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2957 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2960 static const struct drm_display_mode nvd_9128_mode = {
2963 .hsync_start = 800 + 130,
2964 .hsync_end = 800 + 130 + 98,
2965 .htotal = 800 + 0 + 130 + 98,
2967 .vsync_start = 480 + 10,
2968 .vsync_end = 480 + 10 + 50,
2969 .vtotal = 480 + 0 + 10 + 50,
2972 static const struct panel_desc nvd_9128 = {
2973 .modes = &nvd_9128_mode,
2980 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2981 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2984 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2985 .pixelclock = { 30000000, 30000000, 40000000 },
2986 .hactive = { 800, 800, 800 },
2987 .hfront_porch = { 40, 40, 40 },
2988 .hback_porch = { 40, 40, 40 },
2989 .hsync_len = { 1, 48, 48 },
2990 .vactive = { 480, 480, 480 },
2991 .vfront_porch = { 13, 13, 13 },
2992 .vback_porch = { 29, 29, 29 },
2993 .vsync_len = { 3, 3, 3 },
2994 .flags = DISPLAY_FLAGS_DE_HIGH,
2997 static const struct panel_desc okaya_rs800480t_7x0gp = {
2998 .timings = &okaya_rs800480t_7x0gp_timing,
3011 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3014 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3017 .hsync_start = 480 + 5,
3018 .hsync_end = 480 + 5 + 30,
3019 .htotal = 480 + 5 + 30 + 10,
3021 .vsync_start = 272 + 8,
3022 .vsync_end = 272 + 8 + 5,
3023 .vtotal = 272 + 8 + 5 + 3,
3026 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3027 .modes = &olimex_lcd_olinuxino_43ts_mode,
3033 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3037 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3038 * pixel clocks, but this is the timing that was being used in the Adafruit
3039 * installation instructions.
3041 static const struct drm_display_mode ontat_yx700wv03_mode = {
3051 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3056 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3058 static const struct panel_desc ontat_yx700wv03 = {
3059 .modes = &ontat_yx700wv03_mode,
3066 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3069 static const struct drm_display_mode ortustech_com37h3m_mode = {
3072 .hsync_start = 480 + 40,
3073 .hsync_end = 480 + 40 + 10,
3074 .htotal = 480 + 40 + 10 + 40,
3076 .vsync_start = 640 + 4,
3077 .vsync_end = 640 + 4 + 2,
3078 .vtotal = 640 + 4 + 2 + 4,
3079 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3082 static const struct panel_desc ortustech_com37h3m = {
3083 .modes = &ortustech_com37h3m_mode,
3087 .width = 56, /* 56.16mm */
3088 .height = 75, /* 74.88mm */
3090 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3091 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3092 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3095 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3098 .hsync_start = 480 + 10,
3099 .hsync_end = 480 + 10 + 10,
3100 .htotal = 480 + 10 + 10 + 15,
3102 .vsync_start = 800 + 3,
3103 .vsync_end = 800 + 3 + 3,
3104 .vtotal = 800 + 3 + 3 + 3,
3107 static const struct panel_desc ortustech_com43h4m85ulc = {
3108 .modes = &ortustech_com43h4m85ulc_mode,
3115 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3116 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3117 .connector_type = DRM_MODE_CONNECTOR_DPI,
3120 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3123 .hsync_start = 800 + 210,
3124 .hsync_end = 800 + 210 + 30,
3125 .htotal = 800 + 210 + 30 + 16,
3127 .vsync_start = 480 + 22,
3128 .vsync_end = 480 + 22 + 13,
3129 .vtotal = 480 + 22 + 13 + 10,
3130 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3133 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3134 .modes = &osddisplays_osd070t1718_19ts_mode,
3141 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3142 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3143 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3144 .connector_type = DRM_MODE_CONNECTOR_DPI,
3147 static const struct drm_display_mode pda_91_00156_a0_mode = {
3150 .hsync_start = 800 + 1,
3151 .hsync_end = 800 + 1 + 64,
3152 .htotal = 800 + 1 + 64 + 64,
3154 .vsync_start = 480 + 1,
3155 .vsync_end = 480 + 1 + 23,
3156 .vtotal = 480 + 1 + 23 + 22,
3159 static const struct panel_desc pda_91_00156_a0 = {
3160 .modes = &pda_91_00156_a0_mode,
3166 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3169 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3172 .hsync_start = 800 + 54,
3173 .hsync_end = 800 + 54 + 2,
3174 .htotal = 800 + 54 + 2 + 44,
3176 .vsync_start = 480 + 49,
3177 .vsync_end = 480 + 49 + 2,
3178 .vtotal = 480 + 49 + 2 + 22,
3181 static const struct panel_desc powertip_ph800480t013_idf02 = {
3182 .modes = &powertip_ph800480t013_idf02_mode,
3188 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3189 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3190 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3191 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3192 .connector_type = DRM_MODE_CONNECTOR_DPI,
3195 static const struct drm_display_mode qd43003c0_40_mode = {
3198 .hsync_start = 480 + 8,
3199 .hsync_end = 480 + 8 + 4,
3200 .htotal = 480 + 8 + 4 + 39,
3202 .vsync_start = 272 + 4,
3203 .vsync_end = 272 + 4 + 10,
3204 .vtotal = 272 + 4 + 10 + 2,
3207 static const struct panel_desc qd43003c0_40 = {
3208 .modes = &qd43003c0_40_mode,
3215 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3218 static const struct display_timing rocktech_rk070er9427_timing = {
3219 .pixelclock = { 26400000, 33300000, 46800000 },
3220 .hactive = { 800, 800, 800 },
3221 .hfront_porch = { 16, 210, 354 },
3222 .hback_porch = { 46, 46, 46 },
3223 .hsync_len = { 1, 1, 1 },
3224 .vactive = { 480, 480, 480 },
3225 .vfront_porch = { 7, 22, 147 },
3226 .vback_porch = { 23, 23, 23 },
3227 .vsync_len = { 1, 1, 1 },
3228 .flags = DISPLAY_FLAGS_DE_HIGH,
3231 static const struct panel_desc rocktech_rk070er9427 = {
3232 .timings = &rocktech_rk070er9427_timing,
3245 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3248 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3251 .hsync_start = 1280 + 48,
3252 .hsync_end = 1280 + 48 + 32,
3253 .htotal = 1280 + 48 + 32 + 80,
3255 .vsync_start = 800 + 2,
3256 .vsync_end = 800 + 2 + 5,
3257 .vtotal = 800 + 2 + 5 + 16,
3260 static const struct panel_desc rocktech_rk101ii01d_ct = {
3261 .modes = &rocktech_rk101ii01d_ct_mode,
3271 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3272 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3273 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3276 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3279 .hsync_start = 2560 + 48,
3280 .hsync_end = 2560 + 48 + 32,
3281 .htotal = 2560 + 48 + 32 + 80,
3283 .vsync_start = 1600 + 2,
3284 .vsync_end = 1600 + 2 + 5,
3285 .vtotal = 1600 + 2 + 5 + 57,
3288 static const struct panel_desc samsung_lsn122dl01_c01 = {
3289 .modes = &samsung_lsn122dl01_c01_mode,
3297 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3300 .hsync_start = 1024 + 24,
3301 .hsync_end = 1024 + 24 + 136,
3302 .htotal = 1024 + 24 + 136 + 160,
3304 .vsync_start = 600 + 3,
3305 .vsync_end = 600 + 3 + 6,
3306 .vtotal = 600 + 3 + 6 + 61,
3309 static const struct panel_desc samsung_ltn101nt05 = {
3310 .modes = &samsung_ltn101nt05_mode,
3317 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3318 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3319 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3322 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3325 .hsync_start = 1366 + 64,
3326 .hsync_end = 1366 + 64 + 48,
3327 .htotal = 1366 + 64 + 48 + 128,
3329 .vsync_start = 768 + 2,
3330 .vsync_end = 768 + 2 + 5,
3331 .vtotal = 768 + 2 + 5 + 17,
3334 static const struct panel_desc samsung_ltn140at29_301 = {
3335 .modes = &samsung_ltn140at29_301_mode,
3344 static const struct display_timing satoz_sat050at40h12r2_timing = {
3345 .pixelclock = {33300000, 33300000, 50000000},
3346 .hactive = {800, 800, 800},
3347 .hfront_porch = {16, 210, 354},
3348 .hback_porch = {46, 46, 46},
3349 .hsync_len = {1, 1, 40},
3350 .vactive = {480, 480, 480},
3351 .vfront_porch = {7, 22, 147},
3352 .vback_porch = {23, 23, 23},
3353 .vsync_len = {1, 1, 20},
3356 static const struct panel_desc satoz_sat050at40h12r2 = {
3357 .timings = &satoz_sat050at40h12r2_timing,
3364 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3365 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3368 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3371 .hsync_start = 1920 + 48,
3372 .hsync_end = 1920 + 48 + 32,
3373 .htotal = 1920 + 48 + 32 + 80,
3375 .vsync_start = 1280 + 3,
3376 .vsync_end = 1280 + 3 + 10,
3377 .vtotal = 1280 + 3 + 10 + 57,
3378 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3381 static const struct panel_desc sharp_ld_d5116z01b = {
3382 .modes = &sharp_ld_d5116z01b_mode,
3389 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3390 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3393 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3396 .hsync_start = 800 + 64,
3397 .hsync_end = 800 + 64 + 128,
3398 .htotal = 800 + 64 + 128 + 64,
3400 .vsync_start = 480 + 8,
3401 .vsync_end = 480 + 8 + 2,
3402 .vtotal = 480 + 8 + 2 + 35,
3403 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3406 static const struct panel_desc sharp_lq070y3dg3b = {
3407 .modes = &sharp_lq070y3dg3b_mode,
3411 .width = 152, /* 152.4mm */
3412 .height = 91, /* 91.4mm */
3414 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3415 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3416 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3419 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3422 .hsync_start = 240 + 16,
3423 .hsync_end = 240 + 16 + 7,
3424 .htotal = 240 + 16 + 7 + 5,
3426 .vsync_start = 320 + 9,
3427 .vsync_end = 320 + 9 + 1,
3428 .vtotal = 320 + 9 + 1 + 7,
3431 static const struct panel_desc sharp_lq035q7db03 = {
3432 .modes = &sharp_lq035q7db03_mode,
3439 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3442 static const struct display_timing sharp_lq101k1ly04_timing = {
3443 .pixelclock = { 60000000, 65000000, 80000000 },
3444 .hactive = { 1280, 1280, 1280 },
3445 .hfront_porch = { 20, 20, 20 },
3446 .hback_porch = { 20, 20, 20 },
3447 .hsync_len = { 10, 10, 10 },
3448 .vactive = { 800, 800, 800 },
3449 .vfront_porch = { 4, 4, 4 },
3450 .vback_porch = { 4, 4, 4 },
3451 .vsync_len = { 4, 4, 4 },
3452 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3455 static const struct panel_desc sharp_lq101k1ly04 = {
3456 .timings = &sharp_lq101k1ly04_timing,
3463 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3464 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3467 static const struct display_timing sharp_lq123p1jx31_timing = {
3468 .pixelclock = { 252750000, 252750000, 266604720 },
3469 .hactive = { 2400, 2400, 2400 },
3470 .hfront_porch = { 48, 48, 48 },
3471 .hback_porch = { 80, 80, 84 },
3472 .hsync_len = { 32, 32, 32 },
3473 .vactive = { 1600, 1600, 1600 },
3474 .vfront_porch = { 3, 3, 3 },
3475 .vback_porch = { 33, 33, 120 },
3476 .vsync_len = { 10, 10, 10 },
3477 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3480 static const struct panel_desc sharp_lq123p1jx31 = {
3481 .timings = &sharp_lq123p1jx31_timing,
3495 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3499 .hsync_start = 240 + 58,
3500 .hsync_end = 240 + 58 + 1,
3501 .htotal = 240 + 58 + 1 + 1,
3503 .vsync_start = 160 + 24,
3504 .vsync_end = 160 + 24 + 10,
3505 .vtotal = 160 + 24 + 10 + 6,
3506 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3511 .hsync_start = 240 + 8,
3512 .hsync_end = 240 + 8 + 1,
3513 .htotal = 240 + 8 + 1 + 1,
3515 .vsync_start = 160 + 24,
3516 .vsync_end = 160 + 24 + 10,
3517 .vtotal = 160 + 24 + 10 + 6,
3518 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3522 static const struct panel_desc sharp_ls020b1dd01d = {
3523 .modes = sharp_ls020b1dd01d_modes,
3524 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3530 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3531 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3532 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3533 | DRM_BUS_FLAG_SHARP_SIGNALS,
3536 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3539 .hsync_start = 800 + 1,
3540 .hsync_end = 800 + 1 + 64,
3541 .htotal = 800 + 1 + 64 + 64,
3543 .vsync_start = 480 + 1,
3544 .vsync_end = 480 + 1 + 23,
3545 .vtotal = 480 + 1 + 23 + 22,
3548 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3549 .modes = &shelly_sca07010_bfn_lnn_mode,
3555 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3558 static const struct drm_display_mode starry_kr070pe2t_mode = {
3561 .hsync_start = 800 + 209,
3562 .hsync_end = 800 + 209 + 1,
3563 .htotal = 800 + 209 + 1 + 45,
3565 .vsync_start = 480 + 22,
3566 .vsync_end = 480 + 22 + 1,
3567 .vtotal = 480 + 22 + 1 + 22,
3570 static const struct panel_desc starry_kr070pe2t = {
3571 .modes = &starry_kr070pe2t_mode,
3578 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3579 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3580 .connector_type = DRM_MODE_CONNECTOR_DPI,
3583 static const struct drm_display_mode starry_kr122ea0sra_mode = {
3586 .hsync_start = 1920 + 16,
3587 .hsync_end = 1920 + 16 + 16,
3588 .htotal = 1920 + 16 + 16 + 32,
3590 .vsync_start = 1200 + 15,
3591 .vsync_end = 1200 + 15 + 2,
3592 .vtotal = 1200 + 15 + 2 + 18,
3593 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3596 static const struct panel_desc starry_kr122ea0sra = {
3597 .modes = &starry_kr122ea0sra_mode,
3604 .prepare = 10 + 200,
3606 .unprepare = 10 + 500,
3610 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3613 .hsync_start = 800 + 39,
3614 .hsync_end = 800 + 39 + 47,
3615 .htotal = 800 + 39 + 47 + 39,
3617 .vsync_start = 480 + 13,
3618 .vsync_end = 480 + 13 + 2,
3619 .vtotal = 480 + 13 + 2 + 29,
3622 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3623 .modes = &tfc_s9700rtwv43tr_01b_mode,
3630 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3631 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3634 static const struct display_timing tianma_tm070jdhg30_timing = {
3635 .pixelclock = { 62600000, 68200000, 78100000 },
3636 .hactive = { 1280, 1280, 1280 },
3637 .hfront_porch = { 15, 64, 159 },
3638 .hback_porch = { 5, 5, 5 },
3639 .hsync_len = { 1, 1, 256 },
3640 .vactive = { 800, 800, 800 },
3641 .vfront_porch = { 3, 40, 99 },
3642 .vback_porch = { 2, 2, 2 },
3643 .vsync_len = { 1, 1, 128 },
3644 .flags = DISPLAY_FLAGS_DE_HIGH,
3647 static const struct panel_desc tianma_tm070jdhg30 = {
3648 .timings = &tianma_tm070jdhg30_timing,
3655 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3656 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3659 static const struct panel_desc tianma_tm070jvhg33 = {
3660 .timings = &tianma_tm070jdhg30_timing,
3667 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3668 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3671 static const struct display_timing tianma_tm070rvhg71_timing = {
3672 .pixelclock = { 27700000, 29200000, 39600000 },
3673 .hactive = { 800, 800, 800 },
3674 .hfront_porch = { 12, 40, 212 },
3675 .hback_porch = { 88, 88, 88 },
3676 .hsync_len = { 1, 1, 40 },
3677 .vactive = { 480, 480, 480 },
3678 .vfront_porch = { 1, 13, 88 },
3679 .vback_porch = { 32, 32, 32 },
3680 .vsync_len = { 1, 1, 3 },
3681 .flags = DISPLAY_FLAGS_DE_HIGH,
3684 static const struct panel_desc tianma_tm070rvhg71 = {
3685 .timings = &tianma_tm070rvhg71_timing,
3692 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3693 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3696 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3700 .hsync_start = 320 + 50,
3701 .hsync_end = 320 + 50 + 6,
3702 .htotal = 320 + 50 + 6 + 38,
3704 .vsync_start = 240 + 3,
3705 .vsync_end = 240 + 3 + 1,
3706 .vtotal = 240 + 3 + 1 + 17,
3707 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3711 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3712 .modes = ti_nspire_cx_lcd_mode,
3719 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3720 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3723 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3727 .hsync_start = 320 + 6,
3728 .hsync_end = 320 + 6 + 6,
3729 .htotal = 320 + 6 + 6 + 6,
3731 .vsync_start = 240 + 0,
3732 .vsync_end = 240 + 0 + 1,
3733 .vtotal = 240 + 0 + 1 + 0,
3734 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3738 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3739 .modes = ti_nspire_classic_lcd_mode,
3741 /* The grayscale panel has 8 bit for the color .. Y (black) */
3747 /* This is the grayscale bus format */
3748 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3749 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3752 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3755 .hsync_start = 1280 + 192,
3756 .hsync_end = 1280 + 192 + 128,
3757 .htotal = 1280 + 192 + 128 + 64,
3759 .vsync_start = 768 + 20,
3760 .vsync_end = 768 + 20 + 7,
3761 .vtotal = 768 + 20 + 7 + 3,
3764 static const struct panel_desc toshiba_lt089ac29000 = {
3765 .modes = &toshiba_lt089ac29000_mode,
3771 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3772 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3773 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3776 static const struct drm_display_mode tpk_f07a_0102_mode = {
3779 .hsync_start = 800 + 40,
3780 .hsync_end = 800 + 40 + 128,
3781 .htotal = 800 + 40 + 128 + 88,
3783 .vsync_start = 480 + 10,
3784 .vsync_end = 480 + 10 + 2,
3785 .vtotal = 480 + 10 + 2 + 33,
3788 static const struct panel_desc tpk_f07a_0102 = {
3789 .modes = &tpk_f07a_0102_mode,
3795 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3798 static const struct drm_display_mode tpk_f10a_0102_mode = {
3801 .hsync_start = 1024 + 176,
3802 .hsync_end = 1024 + 176 + 5,
3803 .htotal = 1024 + 176 + 5 + 88,
3805 .vsync_start = 600 + 20,
3806 .vsync_end = 600 + 20 + 5,
3807 .vtotal = 600 + 20 + 5 + 25,
3810 static const struct panel_desc tpk_f10a_0102 = {
3811 .modes = &tpk_f10a_0102_mode,
3819 static const struct display_timing urt_umsh_8596md_timing = {
3820 .pixelclock = { 33260000, 33260000, 33260000 },
3821 .hactive = { 800, 800, 800 },
3822 .hfront_porch = { 41, 41, 41 },
3823 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3824 .hsync_len = { 71, 128, 128 },
3825 .vactive = { 480, 480, 480 },
3826 .vfront_porch = { 10, 10, 10 },
3827 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3828 .vsync_len = { 2, 2, 2 },
3829 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3830 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3833 static const struct panel_desc urt_umsh_8596md_lvds = {
3834 .timings = &urt_umsh_8596md_timing,
3841 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3842 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3845 static const struct panel_desc urt_umsh_8596md_parallel = {
3846 .timings = &urt_umsh_8596md_timing,
3853 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3856 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3859 .hsync_start = 800 + 210,
3860 .hsync_end = 800 + 210 + 20,
3861 .htotal = 800 + 210 + 20 + 46,
3863 .vsync_start = 480 + 22,
3864 .vsync_end = 480 + 22 + 10,
3865 .vtotal = 480 + 22 + 10 + 23,
3866 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3869 static const struct panel_desc vl050_8048nt_c01 = {
3870 .modes = &vl050_8048nt_c01_mode,
3877 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3878 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3881 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3884 .hsync_start = 320 + 20,
3885 .hsync_end = 320 + 20 + 30,
3886 .htotal = 320 + 20 + 30 + 38,
3888 .vsync_start = 240 + 4,
3889 .vsync_end = 240 + 4 + 3,
3890 .vtotal = 240 + 4 + 3 + 15,
3891 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3894 static const struct panel_desc winstar_wf35ltiacd = {
3895 .modes = &winstar_wf35ltiacd_mode,
3902 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3905 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
3908 .hsync_start = 1024 + 100,
3909 .hsync_end = 1024 + 100 + 100,
3910 .htotal = 1024 + 100 + 100 + 120,
3912 .vsync_start = 600 + 10,
3913 .vsync_end = 600 + 10 + 10,
3914 .vtotal = 600 + 10 + 10 + 15,
3915 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3918 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
3919 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
3926 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3927 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3928 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3931 static const struct drm_display_mode arm_rtsm_mode[] = {
3935 .hsync_start = 1024 + 24,
3936 .hsync_end = 1024 + 24 + 136,
3937 .htotal = 1024 + 24 + 136 + 160,
3939 .vsync_start = 768 + 3,
3940 .vsync_end = 768 + 3 + 6,
3941 .vtotal = 768 + 3 + 6 + 29,
3942 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3946 static const struct panel_desc arm_rtsm = {
3947 .modes = arm_rtsm_mode,
3954 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3957 static const struct of_device_id platform_of_match[] = {
3959 .compatible = "ampire,am-1280800n3tzqw-t00h",
3960 .data = &ire_am_1280800n3tzqw_t00h,
3962 .compatible = "ampire,am-480272h3tmqw-t01h",
3963 .data = &ire_am_480272h3tmqw_t01h,
3965 .compatible = "ampire,am800480r3tmqwa1h",
3966 .data = &ire_am800480r3tmqwa1h,
3968 .compatible = "arm,rtsm-display",
3971 .compatible = "armadeus,st0700-adapt",
3972 .data = &armadeus_st0700_adapt,
3974 .compatible = "auo,b101aw03",
3975 .data = &auo_b101aw03,
3977 .compatible = "auo,b101ean01",
3978 .data = &auo_b101ean01,
3980 .compatible = "auo,b101xtn01",
3981 .data = &auo_b101xtn01,
3983 .compatible = "auo,b116xa01",
3984 .data = &auo_b116xak01,
3986 .compatible = "auo,b116xw03",
3987 .data = &auo_b116xw03,
3989 .compatible = "auo,b133htn01",
3990 .data = &auo_b133htn01,
3992 .compatible = "auo,b133xtn01",
3993 .data = &auo_b133xtn01,
3995 .compatible = "auo,g070vvn01",
3996 .data = &auo_g070vvn01,
3998 .compatible = "auo,g101evn010",
3999 .data = &auo_g101evn010,
4001 .compatible = "auo,g104sn02",
4002 .data = &auo_g104sn02,
4004 .compatible = "auo,g121ean01",
4005 .data = &auo_g121ean01,
4007 .compatible = "auo,g133han01",
4008 .data = &auo_g133han01,
4010 .compatible = "auo,g156xtn01",
4011 .data = &auo_g156xtn01,
4013 .compatible = "auo,g185han01",
4014 .data = &auo_g185han01,
4016 .compatible = "auo,g190ean01",
4017 .data = &auo_g190ean01,
4019 .compatible = "auo,p320hvn03",
4020 .data = &auo_p320hvn03,
4022 .compatible = "auo,t215hvn01",
4023 .data = &auo_t215hvn01,
4025 .compatible = "avic,tm070ddh03",
4026 .data = &avic_tm070ddh03,
4028 .compatible = "bananapi,s070wv20-ct16",
4029 .data = &bananapi_s070wv20_ct16,
4031 .compatible = "boe,hv070wsa-100",
4032 .data = &boe_hv070wsa
4034 .compatible = "boe,nv101wxmn51",
4035 .data = &boe_nv101wxmn51,
4037 .compatible = "boe,nv133fhm-n61",
4038 .data = &boe_nv133fhm_n61,
4040 .compatible = "boe,nv133fhm-n62",
4041 .data = &boe_nv133fhm_n61,
4043 .compatible = "boe,nv140fhmn49",
4044 .data = &boe_nv140fhmn49,
4046 .compatible = "cdtech,s043wq26h-ct7",
4047 .data = &cdtech_s043wq26h_ct7,
4049 .compatible = "cdtech,s070pws19hp-fc21",
4050 .data = &cdtech_s070pws19hp_fc21,
4052 .compatible = "cdtech,s070swv29hg-dc44",
4053 .data = &cdtech_s070swv29hg_dc44,
4055 .compatible = "cdtech,s070wv95-ct16",
4056 .data = &cdtech_s070wv95_ct16,
4058 .compatible = "chefree,ch101olhlwh-002",
4059 .data = &chefree_ch101olhlwh_002,
4061 .compatible = "chunghwa,claa070wp03xg",
4062 .data = &chunghwa_claa070wp03xg,
4064 .compatible = "chunghwa,claa101wa01a",
4065 .data = &chunghwa_claa101wa01a
4067 .compatible = "chunghwa,claa101wb01",
4068 .data = &chunghwa_claa101wb01
4070 .compatible = "dataimage,scf0700c48ggu18",
4071 .data = &dataimage_scf0700c48ggu18,
4073 .compatible = "dlc,dlc0700yzg-1",
4074 .data = &dlc_dlc0700yzg_1,
4076 .compatible = "dlc,dlc1010gig",
4077 .data = &dlc_dlc1010gig,
4079 .compatible = "edt,et035012dm6",
4080 .data = &edt_et035012dm6,
4082 .compatible = "edt,etm043080dh6gp",
4083 .data = &edt_etm043080dh6gp,
4085 .compatible = "edt,etm0430g0dh6",
4086 .data = &edt_etm0430g0dh6,
4088 .compatible = "edt,et057090dhu",
4089 .data = &edt_et057090dhu,
4091 .compatible = "edt,et070080dh6",
4092 .data = &edt_etm0700g0dh6,
4094 .compatible = "edt,etm0700g0dh6",
4095 .data = &edt_etm0700g0dh6,
4097 .compatible = "edt,etm0700g0bdh6",
4098 .data = &edt_etm0700g0bdh6,
4100 .compatible = "edt,etm0700g0edh6",
4101 .data = &edt_etm0700g0bdh6,
4103 .compatible = "evervision,vgg804821",
4104 .data = &evervision_vgg804821,
4106 .compatible = "foxlink,fl500wvr00-a0t",
4107 .data = &foxlink_fl500wvr00_a0t,
4109 .compatible = "frida,frd350h54004",
4110 .data = &frida_frd350h54004,
4112 .compatible = "friendlyarm,hd702e",
4113 .data = &friendlyarm_hd702e,
4115 .compatible = "giantplus,gpg482739qs5",
4116 .data = &giantplus_gpg482739qs5
4118 .compatible = "giantplus,gpm940b0",
4119 .data = &giantplus_gpm940b0,
4121 .compatible = "hannstar,hsd070pww1",
4122 .data = &hannstar_hsd070pww1,
4124 .compatible = "hannstar,hsd100pxn1",
4125 .data = &hannstar_hsd100pxn1,
4127 .compatible = "hit,tx23d38vm0caa",
4128 .data = &hitachi_tx23d38vm0caa
4130 .compatible = "innolux,at043tn24",
4131 .data = &innolux_at043tn24,
4133 .compatible = "innolux,at070tn92",
4134 .data = &innolux_at070tn92,
4136 .compatible = "innolux,g070y2-l01",
4137 .data = &innolux_g070y2_l01,
4139 .compatible = "innolux,g101ice-l01",
4140 .data = &innolux_g101ice_l01
4142 .compatible = "innolux,g121i1-l01",
4143 .data = &innolux_g121i1_l01
4145 .compatible = "innolux,g121x1-l03",
4146 .data = &innolux_g121x1_l03,
4148 .compatible = "innolux,n116bge",
4149 .data = &innolux_n116bge,
4151 .compatible = "innolux,n125hce-gn1",
4152 .data = &innolux_n125hce_gn1,
4154 .compatible = "innolux,n156bge-l21",
4155 .data = &innolux_n156bge_l21,
4157 .compatible = "innolux,p120zdg-bf1",
4158 .data = &innolux_p120zdg_bf1,
4160 .compatible = "innolux,zj070na-01p",
4161 .data = &innolux_zj070na_01p,
4163 .compatible = "ivo,m133nwf4-r0",
4164 .data = &ivo_m133nwf4_r0,
4166 .compatible = "kingdisplay,kd116n21-30nv-a010",
4167 .data = &kingdisplay_kd116n21_30nv_a010,
4169 .compatible = "koe,tx14d24vm1bpa",
4170 .data = &koe_tx14d24vm1bpa,
4172 .compatible = "koe,tx26d202vm0bwa",
4173 .data = &koe_tx26d202vm0bwa,
4175 .compatible = "koe,tx31d200vm0baa",
4176 .data = &koe_tx31d200vm0baa,
4178 .compatible = "kyo,tcg121xglp",
4179 .data = &kyo_tcg121xglp,
4181 .compatible = "lemaker,bl035-rgb-002",
4182 .data = &lemaker_bl035_rgb_002,
4184 .compatible = "lg,lb070wv8",
4185 .data = &lg_lb070wv8,
4187 .compatible = "lg,lp079qx1-sp0v",
4188 .data = &lg_lp079qx1_sp0v,
4190 .compatible = "lg,lp097qx1-spa1",
4191 .data = &lg_lp097qx1_spa1,
4193 .compatible = "lg,lp120up1",
4194 .data = &lg_lp120up1,
4196 .compatible = "lg,lp129qe",
4197 .data = &lg_lp129qe,
4199 .compatible = "logicpd,type28",
4200 .data = &logicpd_type_28,
4202 .compatible = "logictechno,lt161010-2nhc",
4203 .data = &logictechno_lt161010_2nh,
4205 .compatible = "logictechno,lt161010-2nhr",
4206 .data = &logictechno_lt161010_2nh,
4208 .compatible = "logictechno,lt170410-2whc",
4209 .data = &logictechno_lt170410_2whc,
4211 .compatible = "mitsubishi,aa070mc01-ca1",
4212 .data = &mitsubishi_aa070mc01,
4214 .compatible = "nec,nl12880bc20-05",
4215 .data = &nec_nl12880bc20_05,
4217 .compatible = "nec,nl4827hc19-05b",
4218 .data = &nec_nl4827hc19_05b,
4220 .compatible = "netron-dy,e231732",
4221 .data = &netron_dy_e231732,
4223 .compatible = "neweast,wjfh116008a",
4224 .data = &neweast_wjfh116008a,
4226 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4227 .data = &newhaven_nhd_43_480272ef_atxl,
4229 .compatible = "nlt,nl192108ac18-02d",
4230 .data = &nlt_nl192108ac18_02d,
4232 .compatible = "nvd,9128",
4235 .compatible = "okaya,rs800480t-7x0gp",
4236 .data = &okaya_rs800480t_7x0gp,
4238 .compatible = "olimex,lcd-olinuxino-43-ts",
4239 .data = &olimex_lcd_olinuxino_43ts,
4241 .compatible = "ontat,yx700wv03",
4242 .data = &ontat_yx700wv03,
4244 .compatible = "ortustech,com37h3m05dtc",
4245 .data = &ortustech_com37h3m,
4247 .compatible = "ortustech,com37h3m99dtc",
4248 .data = &ortustech_com37h3m,
4250 .compatible = "ortustech,com43h4m85ulc",
4251 .data = &ortustech_com43h4m85ulc,
4253 .compatible = "osddisplays,osd070t1718-19ts",
4254 .data = &osddisplays_osd070t1718_19ts,
4256 .compatible = "pda,91-00156-a0",
4257 .data = &pda_91_00156_a0,
4259 .compatible = "powertip,ph800480t013-idf02",
4260 .data = &powertip_ph800480t013_idf02,
4262 .compatible = "qiaodian,qd43003c0-40",
4263 .data = &qd43003c0_40,
4265 .compatible = "rocktech,rk070er9427",
4266 .data = &rocktech_rk070er9427,
4268 .compatible = "rocktech,rk101ii01d-ct",
4269 .data = &rocktech_rk101ii01d_ct,
4271 .compatible = "samsung,lsn122dl01-c01",
4272 .data = &samsung_lsn122dl01_c01,
4274 .compatible = "samsung,ltn101nt05",
4275 .data = &samsung_ltn101nt05,
4277 .compatible = "samsung,ltn140at29-301",
4278 .data = &samsung_ltn140at29_301,
4280 .compatible = "satoz,sat050at40h12r2",
4281 .data = &satoz_sat050at40h12r2,
4283 .compatible = "sharp,ld-d5116z01b",
4284 .data = &sharp_ld_d5116z01b,
4286 .compatible = "sharp,lq035q7db03",
4287 .data = &sharp_lq035q7db03,
4289 .compatible = "sharp,lq070y3dg3b",
4290 .data = &sharp_lq070y3dg3b,
4292 .compatible = "sharp,lq101k1ly04",
4293 .data = &sharp_lq101k1ly04,
4295 .compatible = "sharp,lq123p1jx31",
4296 .data = &sharp_lq123p1jx31,
4298 .compatible = "sharp,ls020b1dd01d",
4299 .data = &sharp_ls020b1dd01d,
4301 .compatible = "shelly,sca07010-bfn-lnn",
4302 .data = &shelly_sca07010_bfn_lnn,
4304 .compatible = "starry,kr070pe2t",
4305 .data = &starry_kr070pe2t,
4307 .compatible = "starry,kr122ea0sra",
4308 .data = &starry_kr122ea0sra,
4310 .compatible = "tfc,s9700rtwv43tr-01b",
4311 .data = &tfc_s9700rtwv43tr_01b,
4313 .compatible = "tianma,tm070jdhg30",
4314 .data = &tianma_tm070jdhg30,
4316 .compatible = "tianma,tm070jvhg33",
4317 .data = &tianma_tm070jvhg33,
4319 .compatible = "tianma,tm070rvhg71",
4320 .data = &tianma_tm070rvhg71,
4322 .compatible = "ti,nspire-cx-lcd-panel",
4323 .data = &ti_nspire_cx_lcd_panel,
4325 .compatible = "ti,nspire-classic-lcd-panel",
4326 .data = &ti_nspire_classic_lcd_panel,
4328 .compatible = "toshiba,lt089ac29000",
4329 .data = &toshiba_lt089ac29000,
4331 .compatible = "tpk,f07a-0102",
4332 .data = &tpk_f07a_0102,
4334 .compatible = "tpk,f10a-0102",
4335 .data = &tpk_f10a_0102,
4337 .compatible = "urt,umsh-8596md-t",
4338 .data = &urt_umsh_8596md_parallel,
4340 .compatible = "urt,umsh-8596md-1t",
4341 .data = &urt_umsh_8596md_parallel,
4343 .compatible = "urt,umsh-8596md-7t",
4344 .data = &urt_umsh_8596md_parallel,
4346 .compatible = "urt,umsh-8596md-11t",
4347 .data = &urt_umsh_8596md_lvds,
4349 .compatible = "urt,umsh-8596md-19t",
4350 .data = &urt_umsh_8596md_lvds,
4352 .compatible = "urt,umsh-8596md-20t",
4353 .data = &urt_umsh_8596md_parallel,
4355 .compatible = "vxt,vl050-8048nt-c01",
4356 .data = &vl050_8048nt_c01,
4358 .compatible = "winstar,wf35ltiacd",
4359 .data = &winstar_wf35ltiacd,
4361 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4362 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4364 /* Must be the last entry */
4365 .compatible = "panel-dpi",
4371 MODULE_DEVICE_TABLE(of, platform_of_match);
4373 static int panel_simple_platform_probe(struct platform_device *pdev)
4375 const struct of_device_id *id;
4377 id = of_match_node(platform_of_match, pdev->dev.of_node);
4381 return panel_simple_probe(&pdev->dev, id->data);
4384 static int panel_simple_platform_remove(struct platform_device *pdev)
4386 return panel_simple_remove(&pdev->dev);
4389 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4391 panel_simple_shutdown(&pdev->dev);
4394 static struct platform_driver panel_simple_platform_driver = {
4396 .name = "panel-simple",
4397 .of_match_table = platform_of_match,
4399 .probe = panel_simple_platform_probe,
4400 .remove = panel_simple_platform_remove,
4401 .shutdown = panel_simple_platform_shutdown,
4404 struct panel_desc_dsi {
4405 struct panel_desc desc;
4407 unsigned long flags;
4408 enum mipi_dsi_pixel_format format;
4412 static const struct drm_display_mode auo_b080uan01_mode = {
4415 .hsync_start = 1200 + 62,
4416 .hsync_end = 1200 + 62 + 4,
4417 .htotal = 1200 + 62 + 4 + 62,
4419 .vsync_start = 1920 + 9,
4420 .vsync_end = 1920 + 9 + 2,
4421 .vtotal = 1920 + 9 + 2 + 8,
4424 static const struct panel_desc_dsi auo_b080uan01 = {
4426 .modes = &auo_b080uan01_mode,
4433 .connector_type = DRM_MODE_CONNECTOR_DSI,
4435 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4436 .format = MIPI_DSI_FMT_RGB888,
4440 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4443 .hsync_start = 1200 + 120,
4444 .hsync_end = 1200 + 120 + 20,
4445 .htotal = 1200 + 120 + 20 + 21,
4447 .vsync_start = 1920 + 21,
4448 .vsync_end = 1920 + 21 + 3,
4449 .vtotal = 1920 + 21 + 3 + 18,
4450 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4453 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4455 .modes = &boe_tv080wum_nl0_mode,
4461 .connector_type = DRM_MODE_CONNECTOR_DSI,
4463 .flags = MIPI_DSI_MODE_VIDEO |
4464 MIPI_DSI_MODE_VIDEO_BURST |
4465 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4466 .format = MIPI_DSI_FMT_RGB888,
4470 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4473 .hsync_start = 800 + 32,
4474 .hsync_end = 800 + 32 + 1,
4475 .htotal = 800 + 32 + 1 + 57,
4477 .vsync_start = 1280 + 28,
4478 .vsync_end = 1280 + 28 + 1,
4479 .vtotal = 1280 + 28 + 1 + 14,
4482 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4484 .modes = &lg_ld070wx3_sl01_mode,
4491 .connector_type = DRM_MODE_CONNECTOR_DSI,
4493 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4494 .format = MIPI_DSI_FMT_RGB888,
4498 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4501 .hsync_start = 720 + 12,
4502 .hsync_end = 720 + 12 + 4,
4503 .htotal = 720 + 12 + 4 + 112,
4505 .vsync_start = 1280 + 8,
4506 .vsync_end = 1280 + 8 + 4,
4507 .vtotal = 1280 + 8 + 4 + 12,
4510 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4512 .modes = &lg_lh500wx1_sd03_mode,
4519 .connector_type = DRM_MODE_CONNECTOR_DSI,
4521 .flags = MIPI_DSI_MODE_VIDEO,
4522 .format = MIPI_DSI_FMT_RGB888,
4526 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4529 .hsync_start = 1920 + 154,
4530 .hsync_end = 1920 + 154 + 16,
4531 .htotal = 1920 + 154 + 16 + 32,
4533 .vsync_start = 1200 + 17,
4534 .vsync_end = 1200 + 17 + 2,
4535 .vtotal = 1200 + 17 + 2 + 16,
4538 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4540 .modes = &panasonic_vvx10f004b00_mode,
4547 .connector_type = DRM_MODE_CONNECTOR_DSI,
4549 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4550 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4551 .format = MIPI_DSI_FMT_RGB888,
4555 static const struct drm_display_mode lg_acx467akm_7_mode = {
4558 .hsync_start = 1080 + 2,
4559 .hsync_end = 1080 + 2 + 2,
4560 .htotal = 1080 + 2 + 2 + 2,
4562 .vsync_start = 1920 + 2,
4563 .vsync_end = 1920 + 2 + 2,
4564 .vtotal = 1920 + 2 + 2 + 2,
4567 static const struct panel_desc_dsi lg_acx467akm_7 = {
4569 .modes = &lg_acx467akm_7_mode,
4576 .connector_type = DRM_MODE_CONNECTOR_DSI,
4579 .format = MIPI_DSI_FMT_RGB888,
4583 static const struct drm_display_mode osd101t2045_53ts_mode = {
4586 .hsync_start = 1920 + 112,
4587 .hsync_end = 1920 + 112 + 16,
4588 .htotal = 1920 + 112 + 16 + 32,
4590 .vsync_start = 1200 + 16,
4591 .vsync_end = 1200 + 16 + 2,
4592 .vtotal = 1200 + 16 + 2 + 16,
4593 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4596 static const struct panel_desc_dsi osd101t2045_53ts = {
4598 .modes = &osd101t2045_53ts_mode,
4605 .connector_type = DRM_MODE_CONNECTOR_DSI,
4607 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4608 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4609 MIPI_DSI_MODE_EOT_PACKET,
4610 .format = MIPI_DSI_FMT_RGB888,
4614 static const struct of_device_id dsi_of_match[] = {
4616 .compatible = "auo,b080uan01",
4617 .data = &auo_b080uan01
4619 .compatible = "boe,tv080wum-nl0",
4620 .data = &boe_tv080wum_nl0
4622 .compatible = "lg,ld070wx3-sl01",
4623 .data = &lg_ld070wx3_sl01
4625 .compatible = "lg,lh500wx1-sd03",
4626 .data = &lg_lh500wx1_sd03
4628 .compatible = "panasonic,vvx10f004b00",
4629 .data = &panasonic_vvx10f004b00
4631 .compatible = "lg,acx467akm-7",
4632 .data = &lg_acx467akm_7
4634 .compatible = "osddisplays,osd101t2045-53ts",
4635 .data = &osd101t2045_53ts
4640 MODULE_DEVICE_TABLE(of, dsi_of_match);
4642 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4644 const struct panel_desc_dsi *desc;
4645 const struct of_device_id *id;
4648 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4654 err = panel_simple_probe(&dsi->dev, &desc->desc);
4658 dsi->mode_flags = desc->flags;
4659 dsi->format = desc->format;
4660 dsi->lanes = desc->lanes;
4662 err = mipi_dsi_attach(dsi);
4664 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4666 drm_panel_remove(&panel->base);
4672 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4676 err = mipi_dsi_detach(dsi);
4678 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4680 return panel_simple_remove(&dsi->dev);
4683 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4685 panel_simple_shutdown(&dsi->dev);
4688 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4690 .name = "panel-simple-dsi",
4691 .of_match_table = dsi_of_match,
4693 .probe = panel_simple_dsi_probe,
4694 .remove = panel_simple_dsi_remove,
4695 .shutdown = panel_simple_dsi_shutdown,
4698 static int __init panel_simple_init(void)
4702 err = platform_driver_register(&panel_simple_platform_driver);
4706 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4707 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4709 platform_driver_unregister(&panel_simple_platform_driver);
4716 module_init(panel_simple_init);
4718 static void __exit panel_simple_exit(void)
4720 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4721 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4723 platform_driver_unregister(&panel_simple_platform_driver);
4725 module_exit(panel_simple_exit);
4727 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4728 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4729 MODULE_LICENSE("GPL and additional rights");