2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
60 const struct display_timing *timings;
61 unsigned int num_timings;
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
89 unsigned int hpd_absent_delay;
92 unsigned int unprepare;
100 struct panel_simple {
101 struct drm_panel base;
106 const struct panel_desc *desc;
108 struct regulator *supply;
109 struct i2c_adapter *ddc;
111 struct gpio_desc *enable_gpio;
112 struct gpio_desc *hpd_gpio;
114 struct drm_display_mode override_mode;
117 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
119 return container_of(panel, struct panel_simple, base);
122 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
123 struct drm_connector *connector)
125 struct drm_display_mode *mode;
126 unsigned int i, num = 0;
128 for (i = 0; i < panel->desc->num_timings; i++) {
129 const struct display_timing *dt = &panel->desc->timings[i];
132 videomode_from_timing(dt, &vm);
133 mode = drm_mode_create(connector->dev);
135 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
136 dt->hactive.typ, dt->vactive.typ);
140 drm_display_mode_from_videomode(&vm, mode);
142 mode->type |= DRM_MODE_TYPE_DRIVER;
144 if (panel->desc->num_timings == 1)
145 mode->type |= DRM_MODE_TYPE_PREFERRED;
147 drm_mode_probed_add(connector, mode);
154 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
155 struct drm_connector *connector)
157 struct drm_display_mode *mode;
158 unsigned int i, num = 0;
160 for (i = 0; i < panel->desc->num_modes; i++) {
161 const struct drm_display_mode *m = &panel->desc->modes[i];
163 mode = drm_mode_duplicate(connector->dev, m);
165 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
166 m->hdisplay, m->vdisplay,
167 drm_mode_vrefresh(m));
171 mode->type |= DRM_MODE_TYPE_DRIVER;
173 if (panel->desc->num_modes == 1)
174 mode->type |= DRM_MODE_TYPE_PREFERRED;
176 drm_mode_set_name(mode);
178 drm_mode_probed_add(connector, mode);
185 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
186 struct drm_connector *connector)
188 struct drm_display_mode *mode;
189 bool has_override = panel->override_mode.type;
190 unsigned int num = 0;
196 mode = drm_mode_duplicate(connector->dev,
197 &panel->override_mode);
199 drm_mode_probed_add(connector, mode);
202 dev_err(panel->base.dev, "failed to add override mode\n");
206 /* Only add timings if override was not there or failed to validate */
207 if (num == 0 && panel->desc->num_timings)
208 num = panel_simple_get_timings_modes(panel, connector);
211 * Only add fixed modes if timings/override added no mode.
213 * We should only ever have either the display timings specified
214 * or a fixed mode. Anything else is rather bogus.
216 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
218 num = panel_simple_get_display_modes(panel, connector);
220 connector->display_info.bpc = panel->desc->bpc;
221 connector->display_info.width_mm = panel->desc->size.width;
222 connector->display_info.height_mm = panel->desc->size.height;
223 if (panel->desc->bus_format)
224 drm_display_info_set_bus_formats(&connector->display_info,
225 &panel->desc->bus_format, 1);
226 connector->display_info.bus_flags = panel->desc->bus_flags;
231 static int panel_simple_disable(struct drm_panel *panel)
233 struct panel_simple *p = to_panel_simple(panel);
238 if (p->desc->delay.disable)
239 msleep(p->desc->delay.disable);
246 static int panel_simple_unprepare(struct drm_panel *panel)
248 struct panel_simple *p = to_panel_simple(panel);
253 gpiod_set_value_cansleep(p->enable_gpio, 0);
255 regulator_disable(p->supply);
257 if (p->desc->delay.unprepare)
258 msleep(p->desc->delay.unprepare);
265 static int panel_simple_get_hpd_gpio(struct device *dev,
266 struct panel_simple *p, bool from_probe)
270 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
271 if (IS_ERR(p->hpd_gpio)) {
272 err = PTR_ERR(p->hpd_gpio);
275 * If we're called from probe we won't consider '-EPROBE_DEFER'
276 * to be an error--we'll leave the error code in "hpd_gpio".
277 * When we try to use it we'll try again. This allows for
278 * circular dependencies where the component providing the
279 * hpd gpio needs the panel to init before probing.
281 if (err != -EPROBE_DEFER || !from_probe) {
282 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
290 static int panel_simple_prepare(struct drm_panel *panel)
292 struct panel_simple *p = to_panel_simple(panel);
300 err = regulator_enable(p->supply);
302 dev_err(panel->dev, "failed to enable supply: %d\n", err);
306 gpiod_set_value_cansleep(p->enable_gpio, 1);
308 delay = p->desc->delay.prepare;
310 delay += p->desc->delay.hpd_absent_delay;
315 if (IS_ERR(p->hpd_gpio)) {
316 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
321 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
322 hpd_asserted, hpd_asserted,
324 if (hpd_asserted < 0)
329 "error waiting for hpd GPIO: %d\n", err);
339 static int panel_simple_enable(struct drm_panel *panel)
341 struct panel_simple *p = to_panel_simple(panel);
346 if (p->desc->delay.enable)
347 msleep(p->desc->delay.enable);
354 static int panel_simple_get_modes(struct drm_panel *panel,
355 struct drm_connector *connector)
357 struct panel_simple *p = to_panel_simple(panel);
360 /* probe EDID if a DDC bus is available */
362 struct edid *edid = drm_get_edid(connector, p->ddc);
364 drm_connector_update_edid_property(connector, edid);
366 num += drm_add_edid_modes(connector, edid);
371 /* add hard-coded panel modes */
372 num += panel_simple_get_non_edid_modes(p, connector);
377 static int panel_simple_get_timings(struct drm_panel *panel,
378 unsigned int num_timings,
379 struct display_timing *timings)
381 struct panel_simple *p = to_panel_simple(panel);
384 if (p->desc->num_timings < num_timings)
385 num_timings = p->desc->num_timings;
388 for (i = 0; i < num_timings; i++)
389 timings[i] = p->desc->timings[i];
391 return p->desc->num_timings;
394 static const struct drm_panel_funcs panel_simple_funcs = {
395 .disable = panel_simple_disable,
396 .unprepare = panel_simple_unprepare,
397 .prepare = panel_simple_prepare,
398 .enable = panel_simple_enable,
399 .get_modes = panel_simple_get_modes,
400 .get_timings = panel_simple_get_timings,
403 static struct panel_desc panel_dpi;
405 static int panel_dpi_probe(struct device *dev,
406 struct panel_simple *panel)
408 struct display_timing *timing;
409 const struct device_node *np;
410 struct panel_desc *desc;
411 unsigned int bus_flags;
416 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
420 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
424 ret = of_get_display_timing(np, "panel-timing", timing);
426 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
431 desc->timings = timing;
432 desc->num_timings = 1;
434 of_property_read_u32(np, "width-mm", &desc->size.width);
435 of_property_read_u32(np, "height-mm", &desc->size.height);
437 /* Extract bus_flags from display_timing */
439 vm.flags = timing->flags;
440 drm_bus_flags_from_videomode(&vm, &bus_flags);
441 desc->bus_flags = bus_flags;
443 /* We do not know the connector for the DT node, so guess it */
444 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
451 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
452 (to_check->field.typ >= bounds->field.min && \
453 to_check->field.typ <= bounds->field.max)
454 static void panel_simple_parse_panel_timing_node(struct device *dev,
455 struct panel_simple *panel,
456 const struct display_timing *ot)
458 const struct panel_desc *desc = panel->desc;
462 if (WARN_ON(desc->num_modes)) {
463 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
466 if (WARN_ON(!desc->num_timings)) {
467 dev_err(dev, "Reject override mode: no timings specified\n");
471 for (i = 0; i < panel->desc->num_timings; i++) {
472 const struct display_timing *dt = &panel->desc->timings[i];
474 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
475 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
476 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
477 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
478 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
479 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
484 if (ot->flags != dt->flags)
487 videomode_from_timing(ot, &vm);
488 drm_display_mode_from_videomode(&vm, &panel->override_mode);
489 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
490 DRM_MODE_TYPE_PREFERRED;
494 if (WARN_ON(!panel->override_mode.type))
495 dev_err(dev, "Reject override mode: No display_timing found\n");
498 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
500 struct panel_simple *panel;
501 struct display_timing dt;
502 struct device_node *ddc;
505 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
509 panel->enabled = false;
510 panel->prepared = false;
513 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
514 if (!panel->no_hpd) {
515 err = panel_simple_get_hpd_gpio(dev, panel, true);
520 panel->supply = devm_regulator_get(dev, "power");
521 if (IS_ERR(panel->supply))
522 return PTR_ERR(panel->supply);
524 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
526 if (IS_ERR(panel->enable_gpio)) {
527 err = PTR_ERR(panel->enable_gpio);
528 if (err != -EPROBE_DEFER)
529 dev_err(dev, "failed to request GPIO: %d\n", err);
533 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
535 panel->ddc = of_find_i2c_adapter_by_node(ddc);
539 return -EPROBE_DEFER;
542 if (desc == &panel_dpi) {
543 /* Handle the generic panel-dpi binding */
544 err = panel_dpi_probe(dev, panel);
548 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
549 panel_simple_parse_panel_timing_node(dev, panel, &dt);
552 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) {
553 /* Catch common mistakes for LVDS panels. */
554 WARN_ON(desc->bus_flags &
555 ~(DRM_BUS_FLAG_DE_LOW |
556 DRM_BUS_FLAG_DE_HIGH |
557 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
558 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
559 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
560 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
561 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
562 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
564 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
565 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
569 drm_panel_init(&panel->base, dev, &panel_simple_funcs,
570 desc->connector_type);
572 err = drm_panel_of_backlight(&panel->base);
576 err = drm_panel_add(&panel->base);
580 dev_set_drvdata(dev, panel);
586 put_device(&panel->ddc->dev);
591 static int panel_simple_remove(struct device *dev)
593 struct panel_simple *panel = dev_get_drvdata(dev);
595 drm_panel_remove(&panel->base);
596 drm_panel_disable(&panel->base);
597 drm_panel_unprepare(&panel->base);
600 put_device(&panel->ddc->dev);
605 static void panel_simple_shutdown(struct device *dev)
607 struct panel_simple *panel = dev_get_drvdata(dev);
609 drm_panel_disable(&panel->base);
610 drm_panel_unprepare(&panel->base);
613 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
616 .hsync_start = 480 + 2,
617 .hsync_end = 480 + 2 + 41,
618 .htotal = 480 + 2 + 41 + 2,
620 .vsync_start = 272 + 2,
621 .vsync_end = 272 + 2 + 10,
622 .vtotal = 272 + 2 + 10 + 2,
623 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
626 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
627 .modes = &ire_am_480272h3tmqw_t01h_mode,
634 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
637 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
640 .hsync_start = 800 + 0,
641 .hsync_end = 800 + 0 + 255,
642 .htotal = 800 + 0 + 255 + 0,
644 .vsync_start = 480 + 2,
645 .vsync_end = 480 + 2 + 45,
646 .vtotal = 480 + 2 + 45 + 0,
647 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
650 static const struct panel_desc ampire_am800480r3tmqwa1h = {
651 .modes = &ire_am800480r3tmqwa1h_mode,
658 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
661 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
662 .pixelclock = { 26400000, 33300000, 46800000 },
663 .hactive = { 800, 800, 800 },
664 .hfront_porch = { 16, 210, 354 },
665 .hback_porch = { 45, 36, 6 },
666 .hsync_len = { 1, 10, 40 },
667 .vactive = { 480, 480, 480 },
668 .vfront_porch = { 7, 22, 147 },
669 .vback_porch = { 22, 13, 3 },
670 .vsync_len = { 1, 10, 20 },
671 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
672 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
675 static const struct panel_desc armadeus_st0700_adapt = {
676 .timings = &santek_st0700i5y_rbslw_f_timing,
683 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
684 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
687 static const struct drm_display_mode auo_b101aw03_mode = {
690 .hsync_start = 1024 + 156,
691 .hsync_end = 1024 + 156 + 8,
692 .htotal = 1024 + 156 + 8 + 156,
694 .vsync_start = 600 + 16,
695 .vsync_end = 600 + 16 + 6,
696 .vtotal = 600 + 16 + 6 + 16,
699 static const struct panel_desc auo_b101aw03 = {
700 .modes = &auo_b101aw03_mode,
707 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
708 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
709 .connector_type = DRM_MODE_CONNECTOR_LVDS,
712 static const struct display_timing auo_b101ean01_timing = {
713 .pixelclock = { 65300000, 72500000, 75000000 },
714 .hactive = { 1280, 1280, 1280 },
715 .hfront_porch = { 18, 119, 119 },
716 .hback_porch = { 21, 21, 21 },
717 .hsync_len = { 32, 32, 32 },
718 .vactive = { 800, 800, 800 },
719 .vfront_porch = { 4, 4, 4 },
720 .vback_porch = { 8, 8, 8 },
721 .vsync_len = { 18, 20, 20 },
724 static const struct panel_desc auo_b101ean01 = {
725 .timings = &auo_b101ean01_timing,
734 static const struct drm_display_mode auo_b101xtn01_mode = {
737 .hsync_start = 1366 + 20,
738 .hsync_end = 1366 + 20 + 70,
739 .htotal = 1366 + 20 + 70,
741 .vsync_start = 768 + 14,
742 .vsync_end = 768 + 14 + 42,
743 .vtotal = 768 + 14 + 42,
744 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
747 static const struct panel_desc auo_b101xtn01 = {
748 .modes = &auo_b101xtn01_mode,
757 static const struct drm_display_mode auo_b116xak01_mode = {
760 .hsync_start = 1366 + 48,
761 .hsync_end = 1366 + 48 + 32,
762 .htotal = 1366 + 48 + 32 + 10,
764 .vsync_start = 768 + 4,
765 .vsync_end = 768 + 4 + 6,
766 .vtotal = 768 + 4 + 6 + 15,
767 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
770 static const struct panel_desc auo_b116xak01 = {
771 .modes = &auo_b116xak01_mode,
779 .hpd_absent_delay = 200,
781 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
782 .connector_type = DRM_MODE_CONNECTOR_eDP,
785 static const struct drm_display_mode auo_b116xw03_mode = {
788 .hsync_start = 1366 + 40,
789 .hsync_end = 1366 + 40 + 40,
790 .htotal = 1366 + 40 + 40 + 32,
792 .vsync_start = 768 + 10,
793 .vsync_end = 768 + 10 + 12,
794 .vtotal = 768 + 10 + 12 + 6,
797 static const struct panel_desc auo_b116xw03 = {
798 .modes = &auo_b116xw03_mode,
807 static const struct drm_display_mode auo_b133xtn01_mode = {
810 .hsync_start = 1366 + 48,
811 .hsync_end = 1366 + 48 + 32,
812 .htotal = 1366 + 48 + 32 + 20,
814 .vsync_start = 768 + 3,
815 .vsync_end = 768 + 3 + 6,
816 .vtotal = 768 + 3 + 6 + 13,
819 static const struct panel_desc auo_b133xtn01 = {
820 .modes = &auo_b133xtn01_mode,
829 static const struct drm_display_mode auo_b133htn01_mode = {
832 .hsync_start = 1920 + 172,
833 .hsync_end = 1920 + 172 + 80,
834 .htotal = 1920 + 172 + 80 + 60,
836 .vsync_start = 1080 + 25,
837 .vsync_end = 1080 + 25 + 10,
838 .vtotal = 1080 + 25 + 10 + 10,
841 static const struct panel_desc auo_b133htn01 = {
842 .modes = &auo_b133htn01_mode,
856 static const struct display_timing auo_g070vvn01_timings = {
857 .pixelclock = { 33300000, 34209000, 45000000 },
858 .hactive = { 800, 800, 800 },
859 .hfront_porch = { 20, 40, 200 },
860 .hback_porch = { 87, 40, 1 },
861 .hsync_len = { 1, 48, 87 },
862 .vactive = { 480, 480, 480 },
863 .vfront_porch = { 5, 13, 200 },
864 .vback_porch = { 31, 31, 29 },
865 .vsync_len = { 1, 1, 3 },
868 static const struct panel_desc auo_g070vvn01 = {
869 .timings = &auo_g070vvn01_timings,
884 static const struct drm_display_mode auo_g101evn010_mode = {
887 .hsync_start = 1280 + 82,
888 .hsync_end = 1280 + 82 + 2,
889 .htotal = 1280 + 82 + 2 + 84,
891 .vsync_start = 800 + 8,
892 .vsync_end = 800 + 8 + 2,
893 .vtotal = 800 + 8 + 2 + 6,
896 static const struct panel_desc auo_g101evn010 = {
897 .modes = &auo_g101evn010_mode,
904 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
905 .connector_type = DRM_MODE_CONNECTOR_LVDS,
908 static const struct drm_display_mode auo_g104sn02_mode = {
911 .hsync_start = 800 + 40,
912 .hsync_end = 800 + 40 + 216,
913 .htotal = 800 + 40 + 216 + 128,
915 .vsync_start = 600 + 10,
916 .vsync_end = 600 + 10 + 35,
917 .vtotal = 600 + 10 + 35 + 2,
920 static const struct panel_desc auo_g104sn02 = {
921 .modes = &auo_g104sn02_mode,
930 static const struct drm_display_mode auo_g121ean01_mode = {
933 .hsync_start = 1280 + 58,
934 .hsync_end = 1280 + 58 + 8,
935 .htotal = 1280 + 58 + 8 + 70,
937 .vsync_start = 800 + 6,
938 .vsync_end = 800 + 6 + 4,
939 .vtotal = 800 + 6 + 4 + 10,
942 static const struct panel_desc auo_g121ean01 = {
943 .modes = &auo_g121ean01_mode,
950 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
951 .connector_type = DRM_MODE_CONNECTOR_LVDS,
954 static const struct display_timing auo_g133han01_timings = {
955 .pixelclock = { 134000000, 141200000, 149000000 },
956 .hactive = { 1920, 1920, 1920 },
957 .hfront_porch = { 39, 58, 77 },
958 .hback_porch = { 59, 88, 117 },
959 .hsync_len = { 28, 42, 56 },
960 .vactive = { 1080, 1080, 1080 },
961 .vfront_porch = { 3, 8, 11 },
962 .vback_porch = { 5, 14, 19 },
963 .vsync_len = { 4, 14, 19 },
966 static const struct panel_desc auo_g133han01 = {
967 .timings = &auo_g133han01_timings,
980 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
981 .connector_type = DRM_MODE_CONNECTOR_LVDS,
984 static const struct drm_display_mode auo_g156xtn01_mode = {
987 .hsync_start = 1366 + 33,
988 .hsync_end = 1366 + 33 + 67,
991 .vsync_start = 768 + 4,
992 .vsync_end = 768 + 4 + 4,
996 static const struct panel_desc auo_g156xtn01 = {
997 .modes = &auo_g156xtn01_mode,
1004 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1005 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1008 static const struct display_timing auo_g185han01_timings = {
1009 .pixelclock = { 120000000, 144000000, 175000000 },
1010 .hactive = { 1920, 1920, 1920 },
1011 .hfront_porch = { 36, 120, 148 },
1012 .hback_porch = { 24, 88, 108 },
1013 .hsync_len = { 20, 48, 64 },
1014 .vactive = { 1080, 1080, 1080 },
1015 .vfront_porch = { 6, 10, 40 },
1016 .vback_porch = { 2, 5, 20 },
1017 .vsync_len = { 2, 5, 20 },
1020 static const struct panel_desc auo_g185han01 = {
1021 .timings = &auo_g185han01_timings,
1034 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1035 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1038 static const struct display_timing auo_g190ean01_timings = {
1039 .pixelclock = { 90000000, 108000000, 135000000 },
1040 .hactive = { 1280, 1280, 1280 },
1041 .hfront_porch = { 126, 184, 1266 },
1042 .hback_porch = { 84, 122, 844 },
1043 .hsync_len = { 70, 102, 704 },
1044 .vactive = { 1024, 1024, 1024 },
1045 .vfront_porch = { 4, 26, 76 },
1046 .vback_porch = { 2, 8, 25 },
1047 .vsync_len = { 2, 8, 25 },
1050 static const struct panel_desc auo_g190ean01 = {
1051 .timings = &auo_g190ean01_timings,
1064 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1065 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1068 static const struct display_timing auo_p320hvn03_timings = {
1069 .pixelclock = { 106000000, 148500000, 164000000 },
1070 .hactive = { 1920, 1920, 1920 },
1071 .hfront_porch = { 25, 50, 130 },
1072 .hback_porch = { 25, 50, 130 },
1073 .hsync_len = { 20, 40, 105 },
1074 .vactive = { 1080, 1080, 1080 },
1075 .vfront_porch = { 8, 17, 150 },
1076 .vback_porch = { 8, 17, 150 },
1077 .vsync_len = { 4, 11, 100 },
1080 static const struct panel_desc auo_p320hvn03 = {
1081 .timings = &auo_p320hvn03_timings,
1093 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1094 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1097 static const struct drm_display_mode auo_t215hvn01_mode = {
1100 .hsync_start = 1920 + 88,
1101 .hsync_end = 1920 + 88 + 44,
1102 .htotal = 1920 + 88 + 44 + 148,
1104 .vsync_start = 1080 + 4,
1105 .vsync_end = 1080 + 4 + 5,
1106 .vtotal = 1080 + 4 + 5 + 36,
1109 static const struct panel_desc auo_t215hvn01 = {
1110 .modes = &auo_t215hvn01_mode,
1123 static const struct drm_display_mode avic_tm070ddh03_mode = {
1126 .hsync_start = 1024 + 160,
1127 .hsync_end = 1024 + 160 + 4,
1128 .htotal = 1024 + 160 + 4 + 156,
1130 .vsync_start = 600 + 17,
1131 .vsync_end = 600 + 17 + 1,
1132 .vtotal = 600 + 17 + 1 + 17,
1135 static const struct panel_desc avic_tm070ddh03 = {
1136 .modes = &avic_tm070ddh03_mode,
1150 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1153 .hsync_start = 800 + 40,
1154 .hsync_end = 800 + 40 + 48,
1155 .htotal = 800 + 40 + 48 + 40,
1157 .vsync_start = 480 + 13,
1158 .vsync_end = 480 + 13 + 3,
1159 .vtotal = 480 + 13 + 3 + 29,
1162 static const struct panel_desc bananapi_s070wv20_ct16 = {
1163 .modes = &bananapi_s070wv20_ct16_mode,
1172 static const struct drm_display_mode boe_hv070wsa_mode = {
1175 .hsync_start = 1024 + 30,
1176 .hsync_end = 1024 + 30 + 30,
1177 .htotal = 1024 + 30 + 30 + 30,
1179 .vsync_start = 600 + 10,
1180 .vsync_end = 600 + 10 + 10,
1181 .vtotal = 600 + 10 + 10 + 10,
1184 static const struct panel_desc boe_hv070wsa = {
1185 .modes = &boe_hv070wsa_mode,
1193 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1197 .hsync_start = 1280 + 48,
1198 .hsync_end = 1280 + 48 + 32,
1199 .htotal = 1280 + 48 + 32 + 80,
1201 .vsync_start = 800 + 3,
1202 .vsync_end = 800 + 3 + 5,
1203 .vtotal = 800 + 3 + 5 + 24,
1208 .hsync_start = 1280 + 48,
1209 .hsync_end = 1280 + 48 + 32,
1210 .htotal = 1280 + 48 + 32 + 80,
1212 .vsync_start = 800 + 3,
1213 .vsync_end = 800 + 3 + 5,
1214 .vtotal = 800 + 3 + 5 + 24,
1218 static const struct panel_desc boe_nv101wxmn51 = {
1219 .modes = boe_nv101wxmn51_modes,
1220 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1233 /* Also used for boe_nv133fhm_n62 */
1234 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1237 .hsync_start = 1920 + 48,
1238 .hsync_end = 1920 + 48 + 32,
1239 .htotal = 1920 + 48 + 32 + 200,
1241 .vsync_start = 1080 + 3,
1242 .vsync_end = 1080 + 3 + 6,
1243 .vtotal = 1080 + 3 + 6 + 31,
1246 /* Also used for boe_nv133fhm_n62 */
1247 static const struct panel_desc boe_nv133fhm_n61 = {
1248 .modes = &boe_nv133fhm_n61_modes,
1256 .hpd_absent_delay = 200,
1259 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1260 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1261 .connector_type = DRM_MODE_CONNECTOR_eDP,
1264 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1268 .hsync_start = 1920 + 48,
1269 .hsync_end = 1920 + 48 + 32,
1272 .vsync_start = 1080 + 3,
1273 .vsync_end = 1080 + 3 + 5,
1278 static const struct panel_desc boe_nv140fhmn49 = {
1279 .modes = boe_nv140fhmn49_modes,
1280 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1291 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1292 .connector_type = DRM_MODE_CONNECTOR_eDP,
1295 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1298 .hsync_start = 480 + 5,
1299 .hsync_end = 480 + 5 + 5,
1300 .htotal = 480 + 5 + 5 + 40,
1302 .vsync_start = 272 + 8,
1303 .vsync_end = 272 + 8 + 8,
1304 .vtotal = 272 + 8 + 8 + 8,
1305 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1308 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1309 .modes = &cdtech_s043wq26h_ct7_mode,
1316 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1319 /* S070PWS19HP-FC21 2017/04/22 */
1320 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1323 .hsync_start = 1024 + 160,
1324 .hsync_end = 1024 + 160 + 20,
1325 .htotal = 1024 + 160 + 20 + 140,
1327 .vsync_start = 600 + 12,
1328 .vsync_end = 600 + 12 + 3,
1329 .vtotal = 600 + 12 + 3 + 20,
1330 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1333 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1334 .modes = &cdtech_s070pws19hp_fc21_mode,
1341 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1342 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1343 .connector_type = DRM_MODE_CONNECTOR_DPI,
1346 /* S070SWV29HG-DC44 2017/09/21 */
1347 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1350 .hsync_start = 800 + 210,
1351 .hsync_end = 800 + 210 + 2,
1352 .htotal = 800 + 210 + 2 + 44,
1354 .vsync_start = 480 + 22,
1355 .vsync_end = 480 + 22 + 2,
1356 .vtotal = 480 + 22 + 2 + 21,
1357 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1360 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1361 .modes = &cdtech_s070swv29hg_dc44_mode,
1368 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1369 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1370 .connector_type = DRM_MODE_CONNECTOR_DPI,
1373 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1376 .hsync_start = 800 + 40,
1377 .hsync_end = 800 + 40 + 40,
1378 .htotal = 800 + 40 + 40 + 48,
1380 .vsync_start = 480 + 29,
1381 .vsync_end = 480 + 29 + 13,
1382 .vtotal = 480 + 29 + 13 + 3,
1383 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1386 static const struct panel_desc cdtech_s070wv95_ct16 = {
1387 .modes = &cdtech_s070wv95_ct16_mode,
1396 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1399 .hsync_start = 800 + 49,
1400 .hsync_end = 800 + 49 + 33,
1401 .htotal = 800 + 49 + 33 + 17,
1403 .vsync_start = 1280 + 1,
1404 .vsync_end = 1280 + 1 + 7,
1405 .vtotal = 1280 + 1 + 7 + 15,
1406 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1409 static const struct panel_desc chunghwa_claa070wp03xg = {
1410 .modes = &chunghwa_claa070wp03xg_mode,
1417 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1418 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1419 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1422 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1425 .hsync_start = 1366 + 58,
1426 .hsync_end = 1366 + 58 + 58,
1427 .htotal = 1366 + 58 + 58 + 58,
1429 .vsync_start = 768 + 4,
1430 .vsync_end = 768 + 4 + 4,
1431 .vtotal = 768 + 4 + 4 + 4,
1434 static const struct panel_desc chunghwa_claa101wa01a = {
1435 .modes = &chunghwa_claa101wa01a_mode,
1442 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1443 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1444 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1447 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1450 .hsync_start = 1366 + 48,
1451 .hsync_end = 1366 + 48 + 32,
1452 .htotal = 1366 + 48 + 32 + 20,
1454 .vsync_start = 768 + 16,
1455 .vsync_end = 768 + 16 + 8,
1456 .vtotal = 768 + 16 + 8 + 16,
1459 static const struct panel_desc chunghwa_claa101wb01 = {
1460 .modes = &chunghwa_claa101wb01_mode,
1467 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1468 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1469 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1472 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1475 .hsync_start = 800 + 40,
1476 .hsync_end = 800 + 40 + 128,
1477 .htotal = 800 + 40 + 128 + 88,
1479 .vsync_start = 480 + 10,
1480 .vsync_end = 480 + 10 + 2,
1481 .vtotal = 480 + 10 + 2 + 33,
1482 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1485 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1486 .modes = &dataimage_scf0700c48ggu18_mode,
1493 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1494 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1497 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1498 .pixelclock = { 45000000, 51200000, 57000000 },
1499 .hactive = { 1024, 1024, 1024 },
1500 .hfront_porch = { 100, 106, 113 },
1501 .hback_porch = { 100, 106, 113 },
1502 .hsync_len = { 100, 108, 114 },
1503 .vactive = { 600, 600, 600 },
1504 .vfront_porch = { 8, 11, 15 },
1505 .vback_porch = { 8, 11, 15 },
1506 .vsync_len = { 9, 13, 15 },
1507 .flags = DISPLAY_FLAGS_DE_HIGH,
1510 static const struct panel_desc dlc_dlc0700yzg_1 = {
1511 .timings = &dlc_dlc0700yzg_1_timing,
1523 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1524 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1527 static const struct display_timing dlc_dlc1010gig_timing = {
1528 .pixelclock = { 68900000, 71100000, 73400000 },
1529 .hactive = { 1280, 1280, 1280 },
1530 .hfront_porch = { 43, 53, 63 },
1531 .hback_porch = { 43, 53, 63 },
1532 .hsync_len = { 44, 54, 64 },
1533 .vactive = { 800, 800, 800 },
1534 .vfront_porch = { 5, 8, 11 },
1535 .vback_porch = { 5, 8, 11 },
1536 .vsync_len = { 5, 7, 11 },
1537 .flags = DISPLAY_FLAGS_DE_HIGH,
1540 static const struct panel_desc dlc_dlc1010gig = {
1541 .timings = &dlc_dlc1010gig_timing,
1554 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1555 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1558 static const struct drm_display_mode edt_et035012dm6_mode = {
1561 .hsync_start = 320 + 20,
1562 .hsync_end = 320 + 20 + 30,
1563 .htotal = 320 + 20 + 68,
1565 .vsync_start = 240 + 4,
1566 .vsync_end = 240 + 4 + 4,
1567 .vtotal = 240 + 4 + 4 + 14,
1568 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1571 static const struct panel_desc edt_et035012dm6 = {
1572 .modes = &edt_et035012dm6_mode,
1579 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1580 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1583 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1586 .hsync_start = 480 + 8,
1587 .hsync_end = 480 + 8 + 4,
1588 .htotal = 480 + 8 + 4 + 41,
1591 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1596 .vsync_start = 288 + 2,
1597 .vsync_end = 288 + 2 + 4,
1598 .vtotal = 288 + 2 + 4 + 10,
1601 static const struct panel_desc edt_etm043080dh6gp = {
1602 .modes = &edt_etm043080dh6gp_mode,
1609 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1610 .connector_type = DRM_MODE_CONNECTOR_DPI,
1613 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1616 .hsync_start = 480 + 2,
1617 .hsync_end = 480 + 2 + 41,
1618 .htotal = 480 + 2 + 41 + 2,
1620 .vsync_start = 272 + 2,
1621 .vsync_end = 272 + 2 + 10,
1622 .vtotal = 272 + 2 + 10 + 2,
1623 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1626 static const struct panel_desc edt_etm0430g0dh6 = {
1627 .modes = &edt_etm0430g0dh6_mode,
1636 static const struct drm_display_mode edt_et057090dhu_mode = {
1639 .hsync_start = 640 + 16,
1640 .hsync_end = 640 + 16 + 30,
1641 .htotal = 640 + 16 + 30 + 114,
1643 .vsync_start = 480 + 10,
1644 .vsync_end = 480 + 10 + 3,
1645 .vtotal = 480 + 10 + 3 + 32,
1646 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1649 static const struct panel_desc edt_et057090dhu = {
1650 .modes = &edt_et057090dhu_mode,
1657 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1658 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1659 .connector_type = DRM_MODE_CONNECTOR_DPI,
1662 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1665 .hsync_start = 800 + 40,
1666 .hsync_end = 800 + 40 + 128,
1667 .htotal = 800 + 40 + 128 + 88,
1669 .vsync_start = 480 + 10,
1670 .vsync_end = 480 + 10 + 2,
1671 .vtotal = 480 + 10 + 2 + 33,
1672 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1675 static const struct panel_desc edt_etm0700g0dh6 = {
1676 .modes = &edt_etm0700g0dh6_mode,
1683 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1684 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1687 static const struct panel_desc edt_etm0700g0bdh6 = {
1688 .modes = &edt_etm0700g0dh6_mode,
1695 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1696 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1699 static const struct display_timing evervision_vgg804821_timing = {
1700 .pixelclock = { 27600000, 33300000, 50000000 },
1701 .hactive = { 800, 800, 800 },
1702 .hfront_porch = { 40, 66, 70 },
1703 .hback_porch = { 40, 67, 70 },
1704 .hsync_len = { 40, 67, 70 },
1705 .vactive = { 480, 480, 480 },
1706 .vfront_porch = { 6, 10, 10 },
1707 .vback_porch = { 7, 11, 11 },
1708 .vsync_len = { 7, 11, 11 },
1709 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1710 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1711 DISPLAY_FLAGS_SYNC_NEGEDGE,
1714 static const struct panel_desc evervision_vgg804821 = {
1715 .timings = &evervision_vgg804821_timing,
1722 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1723 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1726 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1729 .hsync_start = 800 + 168,
1730 .hsync_end = 800 + 168 + 64,
1731 .htotal = 800 + 168 + 64 + 88,
1733 .vsync_start = 480 + 37,
1734 .vsync_end = 480 + 37 + 2,
1735 .vtotal = 480 + 37 + 2 + 8,
1738 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1739 .modes = &foxlink_fl500wvr00_a0t_mode,
1746 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1749 static const struct drm_display_mode frida_frd350h54004_mode = {
1752 .hsync_start = 320 + 44,
1753 .hsync_end = 320 + 44 + 16,
1754 .htotal = 320 + 44 + 16 + 20,
1756 .vsync_start = 240 + 2,
1757 .vsync_end = 240 + 2 + 6,
1758 .vtotal = 240 + 2 + 6 + 2,
1759 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1762 static const struct panel_desc frida_frd350h54004 = {
1763 .modes = &frida_frd350h54004_mode,
1770 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1771 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1772 .connector_type = DRM_MODE_CONNECTOR_DPI,
1775 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1778 .hsync_start = 800 + 20,
1779 .hsync_end = 800 + 20 + 24,
1780 .htotal = 800 + 20 + 24 + 20,
1782 .vsync_start = 1280 + 4,
1783 .vsync_end = 1280 + 4 + 8,
1784 .vtotal = 1280 + 4 + 8 + 4,
1785 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1788 static const struct panel_desc friendlyarm_hd702e = {
1789 .modes = &friendlyarm_hd702e_mode,
1797 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1800 .hsync_start = 480 + 5,
1801 .hsync_end = 480 + 5 + 1,
1802 .htotal = 480 + 5 + 1 + 40,
1804 .vsync_start = 272 + 8,
1805 .vsync_end = 272 + 8 + 1,
1806 .vtotal = 272 + 8 + 1 + 8,
1809 static const struct panel_desc giantplus_gpg482739qs5 = {
1810 .modes = &giantplus_gpg482739qs5_mode,
1817 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1820 static const struct display_timing giantplus_gpm940b0_timing = {
1821 .pixelclock = { 13500000, 27000000, 27500000 },
1822 .hactive = { 320, 320, 320 },
1823 .hfront_porch = { 14, 686, 718 },
1824 .hback_porch = { 50, 70, 255 },
1825 .hsync_len = { 1, 1, 1 },
1826 .vactive = { 240, 240, 240 },
1827 .vfront_porch = { 1, 1, 179 },
1828 .vback_porch = { 1, 21, 31 },
1829 .vsync_len = { 1, 1, 6 },
1830 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1833 static const struct panel_desc giantplus_gpm940b0 = {
1834 .timings = &giantplus_gpm940b0_timing,
1841 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1842 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1845 static const struct display_timing hannstar_hsd070pww1_timing = {
1846 .pixelclock = { 64300000, 71100000, 82000000 },
1847 .hactive = { 1280, 1280, 1280 },
1848 .hfront_porch = { 1, 1, 10 },
1849 .hback_porch = { 1, 1, 10 },
1851 * According to the data sheet, the minimum horizontal blanking interval
1852 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1853 * minimum working horizontal blanking interval to be 60 clocks.
1855 .hsync_len = { 58, 158, 661 },
1856 .vactive = { 800, 800, 800 },
1857 .vfront_porch = { 1, 1, 10 },
1858 .vback_porch = { 1, 1, 10 },
1859 .vsync_len = { 1, 21, 203 },
1860 .flags = DISPLAY_FLAGS_DE_HIGH,
1863 static const struct panel_desc hannstar_hsd070pww1 = {
1864 .timings = &hannstar_hsd070pww1_timing,
1871 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1872 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1875 static const struct display_timing hannstar_hsd100pxn1_timing = {
1876 .pixelclock = { 55000000, 65000000, 75000000 },
1877 .hactive = { 1024, 1024, 1024 },
1878 .hfront_porch = { 40, 40, 40 },
1879 .hback_porch = { 220, 220, 220 },
1880 .hsync_len = { 20, 60, 100 },
1881 .vactive = { 768, 768, 768 },
1882 .vfront_porch = { 7, 7, 7 },
1883 .vback_porch = { 21, 21, 21 },
1884 .vsync_len = { 10, 10, 10 },
1885 .flags = DISPLAY_FLAGS_DE_HIGH,
1888 static const struct panel_desc hannstar_hsd100pxn1 = {
1889 .timings = &hannstar_hsd100pxn1_timing,
1896 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1897 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1900 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1903 .hsync_start = 800 + 85,
1904 .hsync_end = 800 + 85 + 86,
1905 .htotal = 800 + 85 + 86 + 85,
1907 .vsync_start = 480 + 16,
1908 .vsync_end = 480 + 16 + 13,
1909 .vtotal = 480 + 16 + 13 + 16,
1912 static const struct panel_desc hitachi_tx23d38vm0caa = {
1913 .modes = &hitachi_tx23d38vm0caa_mode,
1926 static const struct drm_display_mode innolux_at043tn24_mode = {
1929 .hsync_start = 480 + 2,
1930 .hsync_end = 480 + 2 + 41,
1931 .htotal = 480 + 2 + 41 + 2,
1933 .vsync_start = 272 + 2,
1934 .vsync_end = 272 + 2 + 10,
1935 .vtotal = 272 + 2 + 10 + 2,
1936 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1939 static const struct panel_desc innolux_at043tn24 = {
1940 .modes = &innolux_at043tn24_mode,
1947 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1948 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1951 static const struct drm_display_mode innolux_at070tn92_mode = {
1954 .hsync_start = 800 + 210,
1955 .hsync_end = 800 + 210 + 20,
1956 .htotal = 800 + 210 + 20 + 46,
1958 .vsync_start = 480 + 22,
1959 .vsync_end = 480 + 22 + 10,
1960 .vtotal = 480 + 22 + 23 + 10,
1963 static const struct panel_desc innolux_at070tn92 = {
1964 .modes = &innolux_at070tn92_mode,
1970 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1973 static const struct display_timing innolux_g070y2_l01_timing = {
1974 .pixelclock = { 28000000, 29500000, 32000000 },
1975 .hactive = { 800, 800, 800 },
1976 .hfront_porch = { 61, 91, 141 },
1977 .hback_porch = { 60, 90, 140 },
1978 .hsync_len = { 12, 12, 12 },
1979 .vactive = { 480, 480, 480 },
1980 .vfront_porch = { 4, 9, 30 },
1981 .vback_porch = { 4, 8, 28 },
1982 .vsync_len = { 2, 2, 2 },
1983 .flags = DISPLAY_FLAGS_DE_HIGH,
1986 static const struct panel_desc innolux_g070y2_l01 = {
1987 .timings = &innolux_g070y2_l01_timing,
2000 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2001 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2004 static const struct display_timing innolux_g101ice_l01_timing = {
2005 .pixelclock = { 60400000, 71100000, 74700000 },
2006 .hactive = { 1280, 1280, 1280 },
2007 .hfront_porch = { 41, 80, 100 },
2008 .hback_porch = { 40, 79, 99 },
2009 .hsync_len = { 1, 1, 1 },
2010 .vactive = { 800, 800, 800 },
2011 .vfront_porch = { 5, 11, 14 },
2012 .vback_porch = { 4, 11, 14 },
2013 .vsync_len = { 1, 1, 1 },
2014 .flags = DISPLAY_FLAGS_DE_HIGH,
2017 static const struct panel_desc innolux_g101ice_l01 = {
2018 .timings = &innolux_g101ice_l01_timing,
2029 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2030 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2033 static const struct display_timing innolux_g121i1_l01_timing = {
2034 .pixelclock = { 67450000, 71000000, 74550000 },
2035 .hactive = { 1280, 1280, 1280 },
2036 .hfront_porch = { 40, 80, 160 },
2037 .hback_porch = { 39, 79, 159 },
2038 .hsync_len = { 1, 1, 1 },
2039 .vactive = { 800, 800, 800 },
2040 .vfront_porch = { 5, 11, 100 },
2041 .vback_porch = { 4, 11, 99 },
2042 .vsync_len = { 1, 1, 1 },
2045 static const struct panel_desc innolux_g121i1_l01 = {
2046 .timings = &innolux_g121i1_l01_timing,
2057 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2058 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2061 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2064 .hsync_start = 1024 + 0,
2065 .hsync_end = 1024 + 1,
2066 .htotal = 1024 + 0 + 1 + 320,
2068 .vsync_start = 768 + 38,
2069 .vsync_end = 768 + 38 + 1,
2070 .vtotal = 768 + 38 + 1 + 0,
2071 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2074 static const struct panel_desc innolux_g121x1_l03 = {
2075 .modes = &innolux_g121x1_l03_mode,
2090 * Datasheet specifies that at 60 Hz refresh rate:
2091 * - total horizontal time: { 1506, 1592, 1716 }
2092 * - total vertical time: { 788, 800, 868 }
2094 * ...but doesn't go into exactly how that should be split into a front
2095 * porch, back porch, or sync length. For now we'll leave a single setting
2096 * here which allows a bit of tweaking of the pixel clock at the expense of
2099 static const struct display_timing innolux_n116bge_timing = {
2100 .pixelclock = { 72600000, 76420000, 80240000 },
2101 .hactive = { 1366, 1366, 1366 },
2102 .hfront_porch = { 136, 136, 136 },
2103 .hback_porch = { 60, 60, 60 },
2104 .hsync_len = { 30, 30, 30 },
2105 .vactive = { 768, 768, 768 },
2106 .vfront_porch = { 8, 8, 8 },
2107 .vback_porch = { 12, 12, 12 },
2108 .vsync_len = { 12, 12, 12 },
2109 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2112 static const struct panel_desc innolux_n116bge = {
2113 .timings = &innolux_n116bge_timing,
2122 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2125 .hsync_start = 1366 + 16,
2126 .hsync_end = 1366 + 16 + 34,
2127 .htotal = 1366 + 16 + 34 + 50,
2129 .vsync_start = 768 + 2,
2130 .vsync_end = 768 + 2 + 6,
2131 .vtotal = 768 + 2 + 6 + 12,
2134 static const struct panel_desc innolux_n156bge_l21 = {
2135 .modes = &innolux_n156bge_l21_mode,
2142 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2143 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2144 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2147 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2150 .hsync_start = 2160 + 48,
2151 .hsync_end = 2160 + 48 + 32,
2152 .htotal = 2160 + 48 + 32 + 80,
2154 .vsync_start = 1440 + 3,
2155 .vsync_end = 1440 + 3 + 10,
2156 .vtotal = 1440 + 3 + 10 + 27,
2157 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2160 static const struct panel_desc innolux_p120zdg_bf1 = {
2161 .modes = &innolux_p120zdg_bf1_mode,
2169 .hpd_absent_delay = 200,
2174 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2177 .hsync_start = 1024 + 128,
2178 .hsync_end = 1024 + 128 + 64,
2179 .htotal = 1024 + 128 + 64 + 128,
2181 .vsync_start = 600 + 16,
2182 .vsync_end = 600 + 16 + 4,
2183 .vtotal = 600 + 16 + 4 + 16,
2186 static const struct panel_desc innolux_zj070na_01p = {
2187 .modes = &innolux_zj070na_01p_mode,
2196 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2199 .hsync_start = 1920 + 24,
2200 .hsync_end = 1920 + 24 + 48,
2201 .htotal = 1920 + 24 + 48 + 88,
2203 .vsync_start = 1080 + 3,
2204 .vsync_end = 1080 + 3 + 12,
2205 .vtotal = 1080 + 3 + 12 + 17,
2206 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2209 static const struct panel_desc ivo_m133nwf4_r0 = {
2210 .modes = &ivo_m133nwf4_r0_mode,
2218 .hpd_absent_delay = 200,
2221 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2222 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2223 .connector_type = DRM_MODE_CONNECTOR_eDP,
2226 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2227 .pixelclock = { 5580000, 5850000, 6200000 },
2228 .hactive = { 320, 320, 320 },
2229 .hfront_porch = { 30, 30, 30 },
2230 .hback_porch = { 30, 30, 30 },
2231 .hsync_len = { 1, 5, 17 },
2232 .vactive = { 240, 240, 240 },
2233 .vfront_porch = { 6, 6, 6 },
2234 .vback_porch = { 5, 5, 5 },
2235 .vsync_len = { 1, 2, 11 },
2236 .flags = DISPLAY_FLAGS_DE_HIGH,
2239 static const struct panel_desc koe_tx14d24vm1bpa = {
2240 .timings = &koe_tx14d24vm1bpa_timing,
2249 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2250 .pixelclock = { 151820000, 156720000, 159780000 },
2251 .hactive = { 1920, 1920, 1920 },
2252 .hfront_porch = { 105, 130, 142 },
2253 .hback_porch = { 45, 70, 82 },
2254 .hsync_len = { 30, 30, 30 },
2255 .vactive = { 1200, 1200, 1200},
2256 .vfront_porch = { 3, 5, 10 },
2257 .vback_porch = { 2, 5, 10 },
2258 .vsync_len = { 5, 5, 5 },
2261 static const struct panel_desc koe_tx26d202vm0bwa = {
2262 .timings = &koe_tx26d202vm0bwa_timing,
2275 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2276 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2277 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2280 static const struct display_timing koe_tx31d200vm0baa_timing = {
2281 .pixelclock = { 39600000, 43200000, 48000000 },
2282 .hactive = { 1280, 1280, 1280 },
2283 .hfront_porch = { 16, 36, 56 },
2284 .hback_porch = { 16, 36, 56 },
2285 .hsync_len = { 8, 8, 8 },
2286 .vactive = { 480, 480, 480 },
2287 .vfront_porch = { 6, 21, 33 },
2288 .vback_porch = { 6, 21, 33 },
2289 .vsync_len = { 8, 8, 8 },
2290 .flags = DISPLAY_FLAGS_DE_HIGH,
2293 static const struct panel_desc koe_tx31d200vm0baa = {
2294 .timings = &koe_tx31d200vm0baa_timing,
2301 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2302 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2305 static const struct display_timing kyo_tcg121xglp_timing = {
2306 .pixelclock = { 52000000, 65000000, 71000000 },
2307 .hactive = { 1024, 1024, 1024 },
2308 .hfront_porch = { 2, 2, 2 },
2309 .hback_porch = { 2, 2, 2 },
2310 .hsync_len = { 86, 124, 244 },
2311 .vactive = { 768, 768, 768 },
2312 .vfront_porch = { 2, 2, 2 },
2313 .vback_porch = { 2, 2, 2 },
2314 .vsync_len = { 6, 34, 73 },
2315 .flags = DISPLAY_FLAGS_DE_HIGH,
2318 static const struct panel_desc kyo_tcg121xglp = {
2319 .timings = &kyo_tcg121xglp_timing,
2326 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2327 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2330 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2333 .hsync_start = 320 + 20,
2334 .hsync_end = 320 + 20 + 30,
2335 .htotal = 320 + 20 + 30 + 38,
2337 .vsync_start = 240 + 4,
2338 .vsync_end = 240 + 4 + 3,
2339 .vtotal = 240 + 4 + 3 + 15,
2342 static const struct panel_desc lemaker_bl035_rgb_002 = {
2343 .modes = &lemaker_bl035_rgb_002_mode,
2349 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2350 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2353 static const struct drm_display_mode lg_lb070wv8_mode = {
2356 .hsync_start = 800 + 88,
2357 .hsync_end = 800 + 88 + 80,
2358 .htotal = 800 + 88 + 80 + 88,
2360 .vsync_start = 480 + 10,
2361 .vsync_end = 480 + 10 + 25,
2362 .vtotal = 480 + 10 + 25 + 10,
2365 static const struct panel_desc lg_lb070wv8 = {
2366 .modes = &lg_lb070wv8_mode,
2373 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2374 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2377 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2380 .hsync_start = 1536 + 12,
2381 .hsync_end = 1536 + 12 + 16,
2382 .htotal = 1536 + 12 + 16 + 48,
2384 .vsync_start = 2048 + 8,
2385 .vsync_end = 2048 + 8 + 4,
2386 .vtotal = 2048 + 8 + 4 + 8,
2387 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2390 static const struct panel_desc lg_lp079qx1_sp0v = {
2391 .modes = &lg_lp079qx1_sp0v_mode,
2399 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2402 .hsync_start = 2048 + 150,
2403 .hsync_end = 2048 + 150 + 5,
2404 .htotal = 2048 + 150 + 5 + 5,
2406 .vsync_start = 1536 + 3,
2407 .vsync_end = 1536 + 3 + 1,
2408 .vtotal = 1536 + 3 + 1 + 9,
2411 static const struct panel_desc lg_lp097qx1_spa1 = {
2412 .modes = &lg_lp097qx1_spa1_mode,
2420 static const struct drm_display_mode lg_lp120up1_mode = {
2423 .hsync_start = 1920 + 40,
2424 .hsync_end = 1920 + 40 + 40,
2425 .htotal = 1920 + 40 + 40+ 80,
2427 .vsync_start = 1280 + 4,
2428 .vsync_end = 1280 + 4 + 4,
2429 .vtotal = 1280 + 4 + 4 + 12,
2432 static const struct panel_desc lg_lp120up1 = {
2433 .modes = &lg_lp120up1_mode,
2440 .connector_type = DRM_MODE_CONNECTOR_eDP,
2443 static const struct drm_display_mode lg_lp129qe_mode = {
2446 .hsync_start = 2560 + 48,
2447 .hsync_end = 2560 + 48 + 32,
2448 .htotal = 2560 + 48 + 32 + 80,
2450 .vsync_start = 1700 + 3,
2451 .vsync_end = 1700 + 3 + 10,
2452 .vtotal = 1700 + 3 + 10 + 36,
2455 static const struct panel_desc lg_lp129qe = {
2456 .modes = &lg_lp129qe_mode,
2465 static const struct display_timing logictechno_lt161010_2nh_timing = {
2466 .pixelclock = { 26400000, 33300000, 46800000 },
2467 .hactive = { 800, 800, 800 },
2468 .hfront_porch = { 16, 210, 354 },
2469 .hback_porch = { 46, 46, 46 },
2470 .hsync_len = { 1, 20, 40 },
2471 .vactive = { 480, 480, 480 },
2472 .vfront_porch = { 7, 22, 147 },
2473 .vback_porch = { 23, 23, 23 },
2474 .vsync_len = { 1, 10, 20 },
2475 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2476 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2477 DISPLAY_FLAGS_SYNC_POSEDGE,
2480 static const struct panel_desc logictechno_lt161010_2nh = {
2481 .timings = &logictechno_lt161010_2nh_timing,
2487 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2488 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2489 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2490 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2491 .connector_type = DRM_MODE_CONNECTOR_DPI,
2494 static const struct display_timing logictechno_lt170410_2whc_timing = {
2495 .pixelclock = { 68900000, 71100000, 73400000 },
2496 .hactive = { 1280, 1280, 1280 },
2497 .hfront_porch = { 23, 60, 71 },
2498 .hback_porch = { 23, 60, 71 },
2499 .hsync_len = { 15, 40, 47 },
2500 .vactive = { 800, 800, 800 },
2501 .vfront_porch = { 5, 7, 10 },
2502 .vback_porch = { 5, 7, 10 },
2503 .vsync_len = { 6, 9, 12 },
2504 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2505 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2506 DISPLAY_FLAGS_SYNC_POSEDGE,
2509 static const struct panel_desc logictechno_lt170410_2whc = {
2510 .timings = &logictechno_lt170410_2whc_timing,
2516 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2517 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2518 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2521 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2524 .hsync_start = 800 + 0,
2525 .hsync_end = 800 + 1,
2526 .htotal = 800 + 0 + 1 + 160,
2528 .vsync_start = 480 + 0,
2529 .vsync_end = 480 + 48 + 1,
2530 .vtotal = 480 + 48 + 1 + 0,
2531 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2534 static const struct drm_display_mode logicpd_type_28_mode = {
2537 .hsync_start = 480 + 3,
2538 .hsync_end = 480 + 3 + 42,
2539 .htotal = 480 + 3 + 42 + 2,
2542 .vsync_start = 272 + 2,
2543 .vsync_end = 272 + 2 + 11,
2544 .vtotal = 272 + 2 + 11 + 3,
2545 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2548 static const struct panel_desc logicpd_type_28 = {
2549 .modes = &logicpd_type_28_mode,
2562 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2563 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2564 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2567 static const struct panel_desc mitsubishi_aa070mc01 = {
2568 .modes = &mitsubishi_aa070mc01_mode,
2581 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2582 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2583 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2586 static const struct display_timing nec_nl12880bc20_05_timing = {
2587 .pixelclock = { 67000000, 71000000, 75000000 },
2588 .hactive = { 1280, 1280, 1280 },
2589 .hfront_porch = { 2, 30, 30 },
2590 .hback_porch = { 6, 100, 100 },
2591 .hsync_len = { 2, 30, 30 },
2592 .vactive = { 800, 800, 800 },
2593 .vfront_porch = { 5, 5, 5 },
2594 .vback_porch = { 11, 11, 11 },
2595 .vsync_len = { 7, 7, 7 },
2598 static const struct panel_desc nec_nl12880bc20_05 = {
2599 .timings = &nec_nl12880bc20_05_timing,
2610 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2611 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2614 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2617 .hsync_start = 480 + 2,
2618 .hsync_end = 480 + 2 + 41,
2619 .htotal = 480 + 2 + 41 + 2,
2621 .vsync_start = 272 + 2,
2622 .vsync_end = 272 + 2 + 4,
2623 .vtotal = 272 + 2 + 4 + 2,
2624 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2627 static const struct panel_desc nec_nl4827hc19_05b = {
2628 .modes = &nec_nl4827hc19_05b_mode,
2635 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2636 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2639 static const struct drm_display_mode netron_dy_e231732_mode = {
2642 .hsync_start = 1024 + 160,
2643 .hsync_end = 1024 + 160 + 70,
2644 .htotal = 1024 + 160 + 70 + 90,
2646 .vsync_start = 600 + 127,
2647 .vsync_end = 600 + 127 + 20,
2648 .vtotal = 600 + 127 + 20 + 3,
2651 static const struct panel_desc netron_dy_e231732 = {
2652 .modes = &netron_dy_e231732_mode,
2658 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2661 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2665 .hsync_start = 1920 + 48,
2666 .hsync_end = 1920 + 48 + 32,
2667 .htotal = 1920 + 48 + 32 + 80,
2669 .vsync_start = 1080 + 3,
2670 .vsync_end = 1080 + 3 + 5,
2671 .vtotal = 1080 + 3 + 5 + 23,
2672 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2676 .hsync_start = 1920 + 48,
2677 .hsync_end = 1920 + 48 + 32,
2678 .htotal = 1920 + 48 + 32 + 80,
2680 .vsync_start = 1080 + 3,
2681 .vsync_end = 1080 + 3 + 5,
2682 .vtotal = 1080 + 3 + 5 + 23,
2683 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2687 static const struct panel_desc neweast_wjfh116008a = {
2688 .modes = neweast_wjfh116008a_modes,
2700 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2701 .connector_type = DRM_MODE_CONNECTOR_eDP,
2704 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2707 .hsync_start = 480 + 2,
2708 .hsync_end = 480 + 2 + 41,
2709 .htotal = 480 + 2 + 41 + 2,
2711 .vsync_start = 272 + 2,
2712 .vsync_end = 272 + 2 + 10,
2713 .vtotal = 272 + 2 + 10 + 2,
2714 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2717 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2718 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2725 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2726 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2727 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2730 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2731 .pixelclock = { 130000000, 148350000, 163000000 },
2732 .hactive = { 1920, 1920, 1920 },
2733 .hfront_porch = { 80, 100, 100 },
2734 .hback_porch = { 100, 120, 120 },
2735 .hsync_len = { 50, 60, 60 },
2736 .vactive = { 1080, 1080, 1080 },
2737 .vfront_porch = { 12, 30, 30 },
2738 .vback_porch = { 4, 10, 10 },
2739 .vsync_len = { 4, 5, 5 },
2742 static const struct panel_desc nlt_nl192108ac18_02d = {
2743 .timings = &nlt_nl192108ac18_02d_timing,
2753 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2754 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2757 static const struct drm_display_mode nvd_9128_mode = {
2760 .hsync_start = 800 + 130,
2761 .hsync_end = 800 + 130 + 98,
2762 .htotal = 800 + 0 + 130 + 98,
2764 .vsync_start = 480 + 10,
2765 .vsync_end = 480 + 10 + 50,
2766 .vtotal = 480 + 0 + 10 + 50,
2769 static const struct panel_desc nvd_9128 = {
2770 .modes = &nvd_9128_mode,
2777 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2778 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2781 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2782 .pixelclock = { 30000000, 30000000, 40000000 },
2783 .hactive = { 800, 800, 800 },
2784 .hfront_porch = { 40, 40, 40 },
2785 .hback_porch = { 40, 40, 40 },
2786 .hsync_len = { 1, 48, 48 },
2787 .vactive = { 480, 480, 480 },
2788 .vfront_porch = { 13, 13, 13 },
2789 .vback_porch = { 29, 29, 29 },
2790 .vsync_len = { 3, 3, 3 },
2791 .flags = DISPLAY_FLAGS_DE_HIGH,
2794 static const struct panel_desc okaya_rs800480t_7x0gp = {
2795 .timings = &okaya_rs800480t_7x0gp_timing,
2808 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2811 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2814 .hsync_start = 480 + 5,
2815 .hsync_end = 480 + 5 + 30,
2816 .htotal = 480 + 5 + 30 + 10,
2818 .vsync_start = 272 + 8,
2819 .vsync_end = 272 + 8 + 5,
2820 .vtotal = 272 + 8 + 5 + 3,
2823 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2824 .modes = &olimex_lcd_olinuxino_43ts_mode,
2830 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2834 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2835 * pixel clocks, but this is the timing that was being used in the Adafruit
2836 * installation instructions.
2838 static const struct drm_display_mode ontat_yx700wv03_mode = {
2848 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2853 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2855 static const struct panel_desc ontat_yx700wv03 = {
2856 .modes = &ontat_yx700wv03_mode,
2863 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2866 static const struct drm_display_mode ortustech_com37h3m_mode = {
2869 .hsync_start = 480 + 40,
2870 .hsync_end = 480 + 40 + 10,
2871 .htotal = 480 + 40 + 10 + 40,
2873 .vsync_start = 640 + 4,
2874 .vsync_end = 640 + 4 + 2,
2875 .vtotal = 640 + 4 + 2 + 4,
2876 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2879 static const struct panel_desc ortustech_com37h3m = {
2880 .modes = &ortustech_com37h3m_mode,
2884 .width = 56, /* 56.16mm */
2885 .height = 75, /* 74.88mm */
2887 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2888 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2889 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2892 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2895 .hsync_start = 480 + 10,
2896 .hsync_end = 480 + 10 + 10,
2897 .htotal = 480 + 10 + 10 + 15,
2899 .vsync_start = 800 + 3,
2900 .vsync_end = 800 + 3 + 3,
2901 .vtotal = 800 + 3 + 3 + 3,
2904 static const struct panel_desc ortustech_com43h4m85ulc = {
2905 .modes = &ortustech_com43h4m85ulc_mode,
2912 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2913 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2914 .connector_type = DRM_MODE_CONNECTOR_DPI,
2917 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2920 .hsync_start = 800 + 210,
2921 .hsync_end = 800 + 210 + 30,
2922 .htotal = 800 + 210 + 30 + 16,
2924 .vsync_start = 480 + 22,
2925 .vsync_end = 480 + 22 + 13,
2926 .vtotal = 480 + 22 + 13 + 10,
2927 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2930 static const struct panel_desc osddisplays_osd070t1718_19ts = {
2931 .modes = &osddisplays_osd070t1718_19ts_mode,
2938 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2939 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2940 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2941 .connector_type = DRM_MODE_CONNECTOR_DPI,
2944 static const struct drm_display_mode pda_91_00156_a0_mode = {
2947 .hsync_start = 800 + 1,
2948 .hsync_end = 800 + 1 + 64,
2949 .htotal = 800 + 1 + 64 + 64,
2951 .vsync_start = 480 + 1,
2952 .vsync_end = 480 + 1 + 23,
2953 .vtotal = 480 + 1 + 23 + 22,
2956 static const struct panel_desc pda_91_00156_a0 = {
2957 .modes = &pda_91_00156_a0_mode,
2963 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2967 static const struct drm_display_mode qd43003c0_40_mode = {
2970 .hsync_start = 480 + 8,
2971 .hsync_end = 480 + 8 + 4,
2972 .htotal = 480 + 8 + 4 + 39,
2974 .vsync_start = 272 + 4,
2975 .vsync_end = 272 + 4 + 10,
2976 .vtotal = 272 + 4 + 10 + 2,
2979 static const struct panel_desc qd43003c0_40 = {
2980 .modes = &qd43003c0_40_mode,
2987 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2990 static const struct display_timing rocktech_rk070er9427_timing = {
2991 .pixelclock = { 26400000, 33300000, 46800000 },
2992 .hactive = { 800, 800, 800 },
2993 .hfront_porch = { 16, 210, 354 },
2994 .hback_porch = { 46, 46, 46 },
2995 .hsync_len = { 1, 1, 1 },
2996 .vactive = { 480, 480, 480 },
2997 .vfront_porch = { 7, 22, 147 },
2998 .vback_porch = { 23, 23, 23 },
2999 .vsync_len = { 1, 1, 1 },
3000 .flags = DISPLAY_FLAGS_DE_HIGH,
3003 static const struct panel_desc rocktech_rk070er9427 = {
3004 .timings = &rocktech_rk070er9427_timing,
3017 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3020 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3023 .hsync_start = 1280 + 48,
3024 .hsync_end = 1280 + 48 + 32,
3025 .htotal = 1280 + 48 + 32 + 80,
3027 .vsync_start = 800 + 2,
3028 .vsync_end = 800 + 2 + 5,
3029 .vtotal = 800 + 2 + 5 + 16,
3032 static const struct panel_desc rocktech_rk101ii01d_ct = {
3033 .modes = &rocktech_rk101ii01d_ct_mode,
3043 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3044 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3045 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3048 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3051 .hsync_start = 2560 + 48,
3052 .hsync_end = 2560 + 48 + 32,
3053 .htotal = 2560 + 48 + 32 + 80,
3055 .vsync_start = 1600 + 2,
3056 .vsync_end = 1600 + 2 + 5,
3057 .vtotal = 1600 + 2 + 5 + 57,
3060 static const struct panel_desc samsung_lsn122dl01_c01 = {
3061 .modes = &samsung_lsn122dl01_c01_mode,
3069 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3072 .hsync_start = 1024 + 24,
3073 .hsync_end = 1024 + 24 + 136,
3074 .htotal = 1024 + 24 + 136 + 160,
3076 .vsync_start = 600 + 3,
3077 .vsync_end = 600 + 3 + 6,
3078 .vtotal = 600 + 3 + 6 + 61,
3081 static const struct panel_desc samsung_ltn101nt05 = {
3082 .modes = &samsung_ltn101nt05_mode,
3089 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3090 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3091 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3094 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3097 .hsync_start = 1366 + 64,
3098 .hsync_end = 1366 + 64 + 48,
3099 .htotal = 1366 + 64 + 48 + 128,
3101 .vsync_start = 768 + 2,
3102 .vsync_end = 768 + 2 + 5,
3103 .vtotal = 768 + 2 + 5 + 17,
3106 static const struct panel_desc samsung_ltn140at29_301 = {
3107 .modes = &samsung_ltn140at29_301_mode,
3116 static const struct display_timing satoz_sat050at40h12r2_timing = {
3117 .pixelclock = {33300000, 33300000, 50000000},
3118 .hactive = {800, 800, 800},
3119 .hfront_porch = {16, 210, 354},
3120 .hback_porch = {46, 46, 46},
3121 .hsync_len = {1, 1, 40},
3122 .vactive = {480, 480, 480},
3123 .vfront_porch = {7, 22, 147},
3124 .vback_porch = {23, 23, 23},
3125 .vsync_len = {1, 1, 20},
3128 static const struct panel_desc satoz_sat050at40h12r2 = {
3129 .timings = &satoz_sat050at40h12r2_timing,
3136 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3137 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3140 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3143 .hsync_start = 1920 + 48,
3144 .hsync_end = 1920 + 48 + 32,
3145 .htotal = 1920 + 48 + 32 + 80,
3147 .vsync_start = 1280 + 3,
3148 .vsync_end = 1280 + 3 + 10,
3149 .vtotal = 1280 + 3 + 10 + 57,
3150 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3153 static const struct panel_desc sharp_ld_d5116z01b = {
3154 .modes = &sharp_ld_d5116z01b_mode,
3161 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3162 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3165 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3168 .hsync_start = 800 + 64,
3169 .hsync_end = 800 + 64 + 128,
3170 .htotal = 800 + 64 + 128 + 64,
3172 .vsync_start = 480 + 8,
3173 .vsync_end = 480 + 8 + 2,
3174 .vtotal = 480 + 8 + 2 + 35,
3175 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3178 static const struct panel_desc sharp_lq070y3dg3b = {
3179 .modes = &sharp_lq070y3dg3b_mode,
3183 .width = 152, /* 152.4mm */
3184 .height = 91, /* 91.4mm */
3186 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3187 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
3188 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3191 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3194 .hsync_start = 240 + 16,
3195 .hsync_end = 240 + 16 + 7,
3196 .htotal = 240 + 16 + 7 + 5,
3198 .vsync_start = 320 + 9,
3199 .vsync_end = 320 + 9 + 1,
3200 .vtotal = 320 + 9 + 1 + 7,
3203 static const struct panel_desc sharp_lq035q7db03 = {
3204 .modes = &sharp_lq035q7db03_mode,
3211 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3214 static const struct display_timing sharp_lq101k1ly04_timing = {
3215 .pixelclock = { 60000000, 65000000, 80000000 },
3216 .hactive = { 1280, 1280, 1280 },
3217 .hfront_porch = { 20, 20, 20 },
3218 .hback_porch = { 20, 20, 20 },
3219 .hsync_len = { 10, 10, 10 },
3220 .vactive = { 800, 800, 800 },
3221 .vfront_porch = { 4, 4, 4 },
3222 .vback_porch = { 4, 4, 4 },
3223 .vsync_len = { 4, 4, 4 },
3224 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3227 static const struct panel_desc sharp_lq101k1ly04 = {
3228 .timings = &sharp_lq101k1ly04_timing,
3235 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3236 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3239 static const struct display_timing sharp_lq123p1jx31_timing = {
3240 .pixelclock = { 252750000, 252750000, 266604720 },
3241 .hactive = { 2400, 2400, 2400 },
3242 .hfront_porch = { 48, 48, 48 },
3243 .hback_porch = { 80, 80, 84 },
3244 .hsync_len = { 32, 32, 32 },
3245 .vactive = { 1600, 1600, 1600 },
3246 .vfront_porch = { 3, 3, 3 },
3247 .vback_porch = { 33, 33, 120 },
3248 .vsync_len = { 10, 10, 10 },
3249 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3252 static const struct panel_desc sharp_lq123p1jx31 = {
3253 .timings = &sharp_lq123p1jx31_timing,
3267 static const struct display_timing sharp_ls020b1dd01d_timing = {
3268 .pixelclock = { 2000000, 4200000, 5000000 },
3269 .hactive = { 240, 240, 240 },
3270 .hfront_porch = { 66, 66, 66 },
3271 .hback_porch = { 1, 1, 1 },
3272 .hsync_len = { 1, 1, 1 },
3273 .vactive = { 160, 160, 160 },
3274 .vfront_porch = { 52, 52, 52 },
3275 .vback_porch = { 6, 6, 6 },
3276 .vsync_len = { 10, 10, 10 },
3277 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
3280 static const struct panel_desc sharp_ls020b1dd01d = {
3281 .timings = &sharp_ls020b1dd01d_timing,
3288 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3289 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3290 | DRM_BUS_FLAG_PIXDATA_NEGEDGE
3291 | DRM_BUS_FLAG_SHARP_SIGNALS,
3294 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3297 .hsync_start = 800 + 1,
3298 .hsync_end = 800 + 1 + 64,
3299 .htotal = 800 + 1 + 64 + 64,
3301 .vsync_start = 480 + 1,
3302 .vsync_end = 480 + 1 + 23,
3303 .vtotal = 480 + 1 + 23 + 22,
3306 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3307 .modes = &shelly_sca07010_bfn_lnn_mode,
3313 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3316 static const struct drm_display_mode starry_kr070pe2t_mode = {
3319 .hsync_start = 800 + 209,
3320 .hsync_end = 800 + 209 + 1,
3321 .htotal = 800 + 209 + 1 + 45,
3323 .vsync_start = 480 + 22,
3324 .vsync_end = 480 + 22 + 1,
3325 .vtotal = 480 + 22 + 1 + 22,
3328 static const struct panel_desc starry_kr070pe2t = {
3329 .modes = &starry_kr070pe2t_mode,
3336 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3337 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3338 .connector_type = DRM_MODE_CONNECTOR_DPI,
3341 static const struct drm_display_mode starry_kr122ea0sra_mode = {
3344 .hsync_start = 1920 + 16,
3345 .hsync_end = 1920 + 16 + 16,
3346 .htotal = 1920 + 16 + 16 + 32,
3348 .vsync_start = 1200 + 15,
3349 .vsync_end = 1200 + 15 + 2,
3350 .vtotal = 1200 + 15 + 2 + 18,
3351 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3354 static const struct panel_desc starry_kr122ea0sra = {
3355 .modes = &starry_kr122ea0sra_mode,
3362 .prepare = 10 + 200,
3364 .unprepare = 10 + 500,
3368 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3371 .hsync_start = 800 + 39,
3372 .hsync_end = 800 + 39 + 47,
3373 .htotal = 800 + 39 + 47 + 39,
3375 .vsync_start = 480 + 13,
3376 .vsync_end = 480 + 13 + 2,
3377 .vtotal = 480 + 13 + 2 + 29,
3380 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3381 .modes = &tfc_s9700rtwv43tr_01b_mode,
3388 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3389 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3392 static const struct display_timing tianma_tm070jdhg30_timing = {
3393 .pixelclock = { 62600000, 68200000, 78100000 },
3394 .hactive = { 1280, 1280, 1280 },
3395 .hfront_porch = { 15, 64, 159 },
3396 .hback_porch = { 5, 5, 5 },
3397 .hsync_len = { 1, 1, 256 },
3398 .vactive = { 800, 800, 800 },
3399 .vfront_porch = { 3, 40, 99 },
3400 .vback_porch = { 2, 2, 2 },
3401 .vsync_len = { 1, 1, 128 },
3402 .flags = DISPLAY_FLAGS_DE_HIGH,
3405 static const struct panel_desc tianma_tm070jdhg30 = {
3406 .timings = &tianma_tm070jdhg30_timing,
3413 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3414 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3417 static const struct panel_desc tianma_tm070jvhg33 = {
3418 .timings = &tianma_tm070jdhg30_timing,
3425 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3426 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3429 static const struct display_timing tianma_tm070rvhg71_timing = {
3430 .pixelclock = { 27700000, 29200000, 39600000 },
3431 .hactive = { 800, 800, 800 },
3432 .hfront_porch = { 12, 40, 212 },
3433 .hback_porch = { 88, 88, 88 },
3434 .hsync_len = { 1, 1, 40 },
3435 .vactive = { 480, 480, 480 },
3436 .vfront_porch = { 1, 13, 88 },
3437 .vback_porch = { 32, 32, 32 },
3438 .vsync_len = { 1, 1, 3 },
3439 .flags = DISPLAY_FLAGS_DE_HIGH,
3442 static const struct panel_desc tianma_tm070rvhg71 = {
3443 .timings = &tianma_tm070rvhg71_timing,
3450 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3451 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3454 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3458 .hsync_start = 320 + 50,
3459 .hsync_end = 320 + 50 + 6,
3460 .htotal = 320 + 50 + 6 + 38,
3462 .vsync_start = 240 + 3,
3463 .vsync_end = 240 + 3 + 1,
3464 .vtotal = 240 + 3 + 1 + 17,
3465 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3469 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3470 .modes = ti_nspire_cx_lcd_mode,
3477 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3478 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
3481 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3485 .hsync_start = 320 + 6,
3486 .hsync_end = 320 + 6 + 6,
3487 .htotal = 320 + 6 + 6 + 6,
3489 .vsync_start = 240 + 0,
3490 .vsync_end = 240 + 0 + 1,
3491 .vtotal = 240 + 0 + 1 + 0,
3492 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3496 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3497 .modes = ti_nspire_classic_lcd_mode,
3499 /* The grayscale panel has 8 bit for the color .. Y (black) */
3505 /* This is the grayscale bus format */
3506 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3507 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
3510 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3513 .hsync_start = 1280 + 192,
3514 .hsync_end = 1280 + 192 + 128,
3515 .htotal = 1280 + 192 + 128 + 64,
3517 .vsync_start = 768 + 20,
3518 .vsync_end = 768 + 20 + 7,
3519 .vtotal = 768 + 20 + 7 + 3,
3522 static const struct panel_desc toshiba_lt089ac29000 = {
3523 .modes = &toshiba_lt089ac29000_mode,
3529 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3530 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3531 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3534 static const struct drm_display_mode tpk_f07a_0102_mode = {
3537 .hsync_start = 800 + 40,
3538 .hsync_end = 800 + 40 + 128,
3539 .htotal = 800 + 40 + 128 + 88,
3541 .vsync_start = 480 + 10,
3542 .vsync_end = 480 + 10 + 2,
3543 .vtotal = 480 + 10 + 2 + 33,
3546 static const struct panel_desc tpk_f07a_0102 = {
3547 .modes = &tpk_f07a_0102_mode,
3553 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3556 static const struct drm_display_mode tpk_f10a_0102_mode = {
3559 .hsync_start = 1024 + 176,
3560 .hsync_end = 1024 + 176 + 5,
3561 .htotal = 1024 + 176 + 5 + 88,
3563 .vsync_start = 600 + 20,
3564 .vsync_end = 600 + 20 + 5,
3565 .vtotal = 600 + 20 + 5 + 25,
3568 static const struct panel_desc tpk_f10a_0102 = {
3569 .modes = &tpk_f10a_0102_mode,
3577 static const struct display_timing urt_umsh_8596md_timing = {
3578 .pixelclock = { 33260000, 33260000, 33260000 },
3579 .hactive = { 800, 800, 800 },
3580 .hfront_porch = { 41, 41, 41 },
3581 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3582 .hsync_len = { 71, 128, 128 },
3583 .vactive = { 480, 480, 480 },
3584 .vfront_porch = { 10, 10, 10 },
3585 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3586 .vsync_len = { 2, 2, 2 },
3587 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3588 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3591 static const struct panel_desc urt_umsh_8596md_lvds = {
3592 .timings = &urt_umsh_8596md_timing,
3599 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3600 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3603 static const struct panel_desc urt_umsh_8596md_parallel = {
3604 .timings = &urt_umsh_8596md_timing,
3611 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3614 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3617 .hsync_start = 800 + 210,
3618 .hsync_end = 800 + 210 + 20,
3619 .htotal = 800 + 210 + 20 + 46,
3621 .vsync_start = 480 + 22,
3622 .vsync_end = 480 + 22 + 10,
3623 .vtotal = 480 + 22 + 10 + 23,
3624 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3627 static const struct panel_desc vl050_8048nt_c01 = {
3628 .modes = &vl050_8048nt_c01_mode,
3635 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3636 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3639 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3642 .hsync_start = 320 + 20,
3643 .hsync_end = 320 + 20 + 30,
3644 .htotal = 320 + 20 + 30 + 38,
3646 .vsync_start = 240 + 4,
3647 .vsync_end = 240 + 4 + 3,
3648 .vtotal = 240 + 4 + 3 + 15,
3649 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3652 static const struct panel_desc winstar_wf35ltiacd = {
3653 .modes = &winstar_wf35ltiacd_mode,
3660 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3663 static const struct drm_display_mode arm_rtsm_mode[] = {
3667 .hsync_start = 1024 + 24,
3668 .hsync_end = 1024 + 24 + 136,
3669 .htotal = 1024 + 24 + 136 + 160,
3671 .vsync_start = 768 + 3,
3672 .vsync_end = 768 + 3 + 6,
3673 .vtotal = 768 + 3 + 6 + 29,
3674 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3678 static const struct panel_desc arm_rtsm = {
3679 .modes = arm_rtsm_mode,
3686 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3689 static const struct of_device_id platform_of_match[] = {
3691 .compatible = "ampire,am-480272h3tmqw-t01h",
3692 .data = &ire_am_480272h3tmqw_t01h,
3694 .compatible = "ampire,am800480r3tmqwa1h",
3695 .data = &ire_am800480r3tmqwa1h,
3697 .compatible = "arm,rtsm-display",
3700 .compatible = "armadeus,st0700-adapt",
3701 .data = &armadeus_st0700_adapt,
3703 .compatible = "auo,b101aw03",
3704 .data = &auo_b101aw03,
3706 .compatible = "auo,b101ean01",
3707 .data = &auo_b101ean01,
3709 .compatible = "auo,b101xtn01",
3710 .data = &auo_b101xtn01,
3712 .compatible = "auo,b116xa01",
3713 .data = &auo_b116xak01,
3715 .compatible = "auo,b116xw03",
3716 .data = &auo_b116xw03,
3718 .compatible = "auo,b133htn01",
3719 .data = &auo_b133htn01,
3721 .compatible = "auo,b133xtn01",
3722 .data = &auo_b133xtn01,
3724 .compatible = "auo,g070vvn01",
3725 .data = &auo_g070vvn01,
3727 .compatible = "auo,g101evn010",
3728 .data = &auo_g101evn010,
3730 .compatible = "auo,g104sn02",
3731 .data = &auo_g104sn02,
3733 .compatible = "auo,g121ean01",
3734 .data = &auo_g121ean01,
3736 .compatible = "auo,g133han01",
3737 .data = &auo_g133han01,
3739 .compatible = "auo,g156xtn01",
3740 .data = &auo_g156xtn01,
3742 .compatible = "auo,g185han01",
3743 .data = &auo_g185han01,
3745 .compatible = "auo,g190ean01",
3746 .data = &auo_g190ean01,
3748 .compatible = "auo,p320hvn03",
3749 .data = &auo_p320hvn03,
3751 .compatible = "auo,t215hvn01",
3752 .data = &auo_t215hvn01,
3754 .compatible = "avic,tm070ddh03",
3755 .data = &avic_tm070ddh03,
3757 .compatible = "bananapi,s070wv20-ct16",
3758 .data = &bananapi_s070wv20_ct16,
3760 .compatible = "boe,hv070wsa-100",
3761 .data = &boe_hv070wsa
3763 .compatible = "boe,nv101wxmn51",
3764 .data = &boe_nv101wxmn51,
3766 .compatible = "boe,nv133fhm-n61",
3767 .data = &boe_nv133fhm_n61,
3769 .compatible = "boe,nv133fhm-n62",
3770 .data = &boe_nv133fhm_n61,
3772 .compatible = "boe,nv140fhmn49",
3773 .data = &boe_nv140fhmn49,
3775 .compatible = "cdtech,s043wq26h-ct7",
3776 .data = &cdtech_s043wq26h_ct7,
3778 .compatible = "cdtech,s070pws19hp-fc21",
3779 .data = &cdtech_s070pws19hp_fc21,
3781 .compatible = "cdtech,s070swv29hg-dc44",
3782 .data = &cdtech_s070swv29hg_dc44,
3784 .compatible = "cdtech,s070wv95-ct16",
3785 .data = &cdtech_s070wv95_ct16,
3787 .compatible = "chunghwa,claa070wp03xg",
3788 .data = &chunghwa_claa070wp03xg,
3790 .compatible = "chunghwa,claa101wa01a",
3791 .data = &chunghwa_claa101wa01a
3793 .compatible = "chunghwa,claa101wb01",
3794 .data = &chunghwa_claa101wb01
3796 .compatible = "dataimage,scf0700c48ggu18",
3797 .data = &dataimage_scf0700c48ggu18,
3799 .compatible = "dlc,dlc0700yzg-1",
3800 .data = &dlc_dlc0700yzg_1,
3802 .compatible = "dlc,dlc1010gig",
3803 .data = &dlc_dlc1010gig,
3805 .compatible = "edt,et035012dm6",
3806 .data = &edt_et035012dm6,
3808 .compatible = "edt,etm043080dh6gp",
3809 .data = &edt_etm043080dh6gp,
3811 .compatible = "edt,etm0430g0dh6",
3812 .data = &edt_etm0430g0dh6,
3814 .compatible = "edt,et057090dhu",
3815 .data = &edt_et057090dhu,
3817 .compatible = "edt,et070080dh6",
3818 .data = &edt_etm0700g0dh6,
3820 .compatible = "edt,etm0700g0dh6",
3821 .data = &edt_etm0700g0dh6,
3823 .compatible = "edt,etm0700g0bdh6",
3824 .data = &edt_etm0700g0bdh6,
3826 .compatible = "edt,etm0700g0edh6",
3827 .data = &edt_etm0700g0bdh6,
3829 .compatible = "evervision,vgg804821",
3830 .data = &evervision_vgg804821,
3832 .compatible = "foxlink,fl500wvr00-a0t",
3833 .data = &foxlink_fl500wvr00_a0t,
3835 .compatible = "frida,frd350h54004",
3836 .data = &frida_frd350h54004,
3838 .compatible = "friendlyarm,hd702e",
3839 .data = &friendlyarm_hd702e,
3841 .compatible = "giantplus,gpg482739qs5",
3842 .data = &giantplus_gpg482739qs5
3844 .compatible = "giantplus,gpm940b0",
3845 .data = &giantplus_gpm940b0,
3847 .compatible = "hannstar,hsd070pww1",
3848 .data = &hannstar_hsd070pww1,
3850 .compatible = "hannstar,hsd100pxn1",
3851 .data = &hannstar_hsd100pxn1,
3853 .compatible = "hit,tx23d38vm0caa",
3854 .data = &hitachi_tx23d38vm0caa
3856 .compatible = "innolux,at043tn24",
3857 .data = &innolux_at043tn24,
3859 .compatible = "innolux,at070tn92",
3860 .data = &innolux_at070tn92,
3862 .compatible = "innolux,g070y2-l01",
3863 .data = &innolux_g070y2_l01,
3865 .compatible = "innolux,g101ice-l01",
3866 .data = &innolux_g101ice_l01
3868 .compatible = "innolux,g121i1-l01",
3869 .data = &innolux_g121i1_l01
3871 .compatible = "innolux,g121x1-l03",
3872 .data = &innolux_g121x1_l03,
3874 .compatible = "innolux,n116bge",
3875 .data = &innolux_n116bge,
3877 .compatible = "innolux,n156bge-l21",
3878 .data = &innolux_n156bge_l21,
3880 .compatible = "innolux,p120zdg-bf1",
3881 .data = &innolux_p120zdg_bf1,
3883 .compatible = "innolux,zj070na-01p",
3884 .data = &innolux_zj070na_01p,
3886 .compatible = "ivo,m133nwf4-r0",
3887 .data = &ivo_m133nwf4_r0,
3889 .compatible = "koe,tx14d24vm1bpa",
3890 .data = &koe_tx14d24vm1bpa,
3892 .compatible = "koe,tx26d202vm0bwa",
3893 .data = &koe_tx26d202vm0bwa,
3895 .compatible = "koe,tx31d200vm0baa",
3896 .data = &koe_tx31d200vm0baa,
3898 .compatible = "kyo,tcg121xglp",
3899 .data = &kyo_tcg121xglp,
3901 .compatible = "lemaker,bl035-rgb-002",
3902 .data = &lemaker_bl035_rgb_002,
3904 .compatible = "lg,lb070wv8",
3905 .data = &lg_lb070wv8,
3907 .compatible = "lg,lp079qx1-sp0v",
3908 .data = &lg_lp079qx1_sp0v,
3910 .compatible = "lg,lp097qx1-spa1",
3911 .data = &lg_lp097qx1_spa1,
3913 .compatible = "lg,lp120up1",
3914 .data = &lg_lp120up1,
3916 .compatible = "lg,lp129qe",
3917 .data = &lg_lp129qe,
3919 .compatible = "logicpd,type28",
3920 .data = &logicpd_type_28,
3922 .compatible = "logictechno,lt161010-2nhc",
3923 .data = &logictechno_lt161010_2nh,
3925 .compatible = "logictechno,lt161010-2nhr",
3926 .data = &logictechno_lt161010_2nh,
3928 .compatible = "logictechno,lt170410-2whc",
3929 .data = &logictechno_lt170410_2whc,
3931 .compatible = "mitsubishi,aa070mc01-ca1",
3932 .data = &mitsubishi_aa070mc01,
3934 .compatible = "nec,nl12880bc20-05",
3935 .data = &nec_nl12880bc20_05,
3937 .compatible = "nec,nl4827hc19-05b",
3938 .data = &nec_nl4827hc19_05b,
3940 .compatible = "netron-dy,e231732",
3941 .data = &netron_dy_e231732,
3943 .compatible = "neweast,wjfh116008a",
3944 .data = &neweast_wjfh116008a,
3946 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3947 .data = &newhaven_nhd_43_480272ef_atxl,
3949 .compatible = "nlt,nl192108ac18-02d",
3950 .data = &nlt_nl192108ac18_02d,
3952 .compatible = "nvd,9128",
3955 .compatible = "okaya,rs800480t-7x0gp",
3956 .data = &okaya_rs800480t_7x0gp,
3958 .compatible = "olimex,lcd-olinuxino-43-ts",
3959 .data = &olimex_lcd_olinuxino_43ts,
3961 .compatible = "ontat,yx700wv03",
3962 .data = &ontat_yx700wv03,
3964 .compatible = "ortustech,com37h3m05dtc",
3965 .data = &ortustech_com37h3m,
3967 .compatible = "ortustech,com37h3m99dtc",
3968 .data = &ortustech_com37h3m,
3970 .compatible = "ortustech,com43h4m85ulc",
3971 .data = &ortustech_com43h4m85ulc,
3973 .compatible = "osddisplays,osd070t1718-19ts",
3974 .data = &osddisplays_osd070t1718_19ts,
3976 .compatible = "pda,91-00156-a0",
3977 .data = &pda_91_00156_a0,
3979 .compatible = "qiaodian,qd43003c0-40",
3980 .data = &qd43003c0_40,
3982 .compatible = "rocktech,rk070er9427",
3983 .data = &rocktech_rk070er9427,
3985 .compatible = "rocktech,rk101ii01d-ct",
3986 .data = &rocktech_rk101ii01d_ct,
3988 .compatible = "samsung,lsn122dl01-c01",
3989 .data = &samsung_lsn122dl01_c01,
3991 .compatible = "samsung,ltn101nt05",
3992 .data = &samsung_ltn101nt05,
3994 .compatible = "samsung,ltn140at29-301",
3995 .data = &samsung_ltn140at29_301,
3997 .compatible = "satoz,sat050at40h12r2",
3998 .data = &satoz_sat050at40h12r2,
4000 .compatible = "sharp,ld-d5116z01b",
4001 .data = &sharp_ld_d5116z01b,
4003 .compatible = "sharp,lq035q7db03",
4004 .data = &sharp_lq035q7db03,
4006 .compatible = "sharp,lq070y3dg3b",
4007 .data = &sharp_lq070y3dg3b,
4009 .compatible = "sharp,lq101k1ly04",
4010 .data = &sharp_lq101k1ly04,
4012 .compatible = "sharp,lq123p1jx31",
4013 .data = &sharp_lq123p1jx31,
4015 .compatible = "sharp,ls020b1dd01d",
4016 .data = &sharp_ls020b1dd01d,
4018 .compatible = "shelly,sca07010-bfn-lnn",
4019 .data = &shelly_sca07010_bfn_lnn,
4021 .compatible = "starry,kr070pe2t",
4022 .data = &starry_kr070pe2t,
4024 .compatible = "starry,kr122ea0sra",
4025 .data = &starry_kr122ea0sra,
4027 .compatible = "tfc,s9700rtwv43tr-01b",
4028 .data = &tfc_s9700rtwv43tr_01b,
4030 .compatible = "tianma,tm070jdhg30",
4031 .data = &tianma_tm070jdhg30,
4033 .compatible = "tianma,tm070jvhg33",
4034 .data = &tianma_tm070jvhg33,
4036 .compatible = "tianma,tm070rvhg71",
4037 .data = &tianma_tm070rvhg71,
4039 .compatible = "ti,nspire-cx-lcd-panel",
4040 .data = &ti_nspire_cx_lcd_panel,
4042 .compatible = "ti,nspire-classic-lcd-panel",
4043 .data = &ti_nspire_classic_lcd_panel,
4045 .compatible = "toshiba,lt089ac29000",
4046 .data = &toshiba_lt089ac29000,
4048 .compatible = "tpk,f07a-0102",
4049 .data = &tpk_f07a_0102,
4051 .compatible = "tpk,f10a-0102",
4052 .data = &tpk_f10a_0102,
4054 .compatible = "urt,umsh-8596md-t",
4055 .data = &urt_umsh_8596md_parallel,
4057 .compatible = "urt,umsh-8596md-1t",
4058 .data = &urt_umsh_8596md_parallel,
4060 .compatible = "urt,umsh-8596md-7t",
4061 .data = &urt_umsh_8596md_parallel,
4063 .compatible = "urt,umsh-8596md-11t",
4064 .data = &urt_umsh_8596md_lvds,
4066 .compatible = "urt,umsh-8596md-19t",
4067 .data = &urt_umsh_8596md_lvds,
4069 .compatible = "urt,umsh-8596md-20t",
4070 .data = &urt_umsh_8596md_parallel,
4072 .compatible = "vxt,vl050-8048nt-c01",
4073 .data = &vl050_8048nt_c01,
4075 .compatible = "winstar,wf35ltiacd",
4076 .data = &winstar_wf35ltiacd,
4078 /* Must be the last entry */
4079 .compatible = "panel-dpi",
4085 MODULE_DEVICE_TABLE(of, platform_of_match);
4087 static int panel_simple_platform_probe(struct platform_device *pdev)
4089 const struct of_device_id *id;
4091 id = of_match_node(platform_of_match, pdev->dev.of_node);
4095 return panel_simple_probe(&pdev->dev, id->data);
4098 static int panel_simple_platform_remove(struct platform_device *pdev)
4100 return panel_simple_remove(&pdev->dev);
4103 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4105 panel_simple_shutdown(&pdev->dev);
4108 static struct platform_driver panel_simple_platform_driver = {
4110 .name = "panel-simple",
4111 .of_match_table = platform_of_match,
4113 .probe = panel_simple_platform_probe,
4114 .remove = panel_simple_platform_remove,
4115 .shutdown = panel_simple_platform_shutdown,
4118 struct panel_desc_dsi {
4119 struct panel_desc desc;
4121 unsigned long flags;
4122 enum mipi_dsi_pixel_format format;
4126 static const struct drm_display_mode auo_b080uan01_mode = {
4129 .hsync_start = 1200 + 62,
4130 .hsync_end = 1200 + 62 + 4,
4131 .htotal = 1200 + 62 + 4 + 62,
4133 .vsync_start = 1920 + 9,
4134 .vsync_end = 1920 + 9 + 2,
4135 .vtotal = 1920 + 9 + 2 + 8,
4138 static const struct panel_desc_dsi auo_b080uan01 = {
4140 .modes = &auo_b080uan01_mode,
4147 .connector_type = DRM_MODE_CONNECTOR_DSI,
4149 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4150 .format = MIPI_DSI_FMT_RGB888,
4154 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4157 .hsync_start = 1200 + 120,
4158 .hsync_end = 1200 + 120 + 20,
4159 .htotal = 1200 + 120 + 20 + 21,
4161 .vsync_start = 1920 + 21,
4162 .vsync_end = 1920 + 21 + 3,
4163 .vtotal = 1920 + 21 + 3 + 18,
4164 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4167 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4169 .modes = &boe_tv080wum_nl0_mode,
4175 .connector_type = DRM_MODE_CONNECTOR_DSI,
4177 .flags = MIPI_DSI_MODE_VIDEO |
4178 MIPI_DSI_MODE_VIDEO_BURST |
4179 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4180 .format = MIPI_DSI_FMT_RGB888,
4184 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4187 .hsync_start = 800 + 32,
4188 .hsync_end = 800 + 32 + 1,
4189 .htotal = 800 + 32 + 1 + 57,
4191 .vsync_start = 1280 + 28,
4192 .vsync_end = 1280 + 28 + 1,
4193 .vtotal = 1280 + 28 + 1 + 14,
4196 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4198 .modes = &lg_ld070wx3_sl01_mode,
4205 .connector_type = DRM_MODE_CONNECTOR_DSI,
4207 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4208 .format = MIPI_DSI_FMT_RGB888,
4212 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4215 .hsync_start = 720 + 12,
4216 .hsync_end = 720 + 12 + 4,
4217 .htotal = 720 + 12 + 4 + 112,
4219 .vsync_start = 1280 + 8,
4220 .vsync_end = 1280 + 8 + 4,
4221 .vtotal = 1280 + 8 + 4 + 12,
4224 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4226 .modes = &lg_lh500wx1_sd03_mode,
4233 .connector_type = DRM_MODE_CONNECTOR_DSI,
4235 .flags = MIPI_DSI_MODE_VIDEO,
4236 .format = MIPI_DSI_FMT_RGB888,
4240 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4243 .hsync_start = 1920 + 154,
4244 .hsync_end = 1920 + 154 + 16,
4245 .htotal = 1920 + 154 + 16 + 32,
4247 .vsync_start = 1200 + 17,
4248 .vsync_end = 1200 + 17 + 2,
4249 .vtotal = 1200 + 17 + 2 + 16,
4252 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4254 .modes = &panasonic_vvx10f004b00_mode,
4261 .connector_type = DRM_MODE_CONNECTOR_DSI,
4263 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4264 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4265 .format = MIPI_DSI_FMT_RGB888,
4269 static const struct drm_display_mode lg_acx467akm_7_mode = {
4272 .hsync_start = 1080 + 2,
4273 .hsync_end = 1080 + 2 + 2,
4274 .htotal = 1080 + 2 + 2 + 2,
4276 .vsync_start = 1920 + 2,
4277 .vsync_end = 1920 + 2 + 2,
4278 .vtotal = 1920 + 2 + 2 + 2,
4281 static const struct panel_desc_dsi lg_acx467akm_7 = {
4283 .modes = &lg_acx467akm_7_mode,
4290 .connector_type = DRM_MODE_CONNECTOR_DSI,
4293 .format = MIPI_DSI_FMT_RGB888,
4297 static const struct drm_display_mode osd101t2045_53ts_mode = {
4300 .hsync_start = 1920 + 112,
4301 .hsync_end = 1920 + 112 + 16,
4302 .htotal = 1920 + 112 + 16 + 32,
4304 .vsync_start = 1200 + 16,
4305 .vsync_end = 1200 + 16 + 2,
4306 .vtotal = 1200 + 16 + 2 + 16,
4307 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4310 static const struct panel_desc_dsi osd101t2045_53ts = {
4312 .modes = &osd101t2045_53ts_mode,
4319 .connector_type = DRM_MODE_CONNECTOR_DSI,
4321 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4322 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4323 MIPI_DSI_MODE_EOT_PACKET,
4324 .format = MIPI_DSI_FMT_RGB888,
4328 static const struct of_device_id dsi_of_match[] = {
4330 .compatible = "auo,b080uan01",
4331 .data = &auo_b080uan01
4333 .compatible = "boe,tv080wum-nl0",
4334 .data = &boe_tv080wum_nl0
4336 .compatible = "lg,ld070wx3-sl01",
4337 .data = &lg_ld070wx3_sl01
4339 .compatible = "lg,lh500wx1-sd03",
4340 .data = &lg_lh500wx1_sd03
4342 .compatible = "panasonic,vvx10f004b00",
4343 .data = &panasonic_vvx10f004b00
4345 .compatible = "lg,acx467akm-7",
4346 .data = &lg_acx467akm_7
4348 .compatible = "osddisplays,osd101t2045-53ts",
4349 .data = &osd101t2045_53ts
4354 MODULE_DEVICE_TABLE(of, dsi_of_match);
4356 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4358 const struct panel_desc_dsi *desc;
4359 const struct of_device_id *id;
4362 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4368 err = panel_simple_probe(&dsi->dev, &desc->desc);
4372 dsi->mode_flags = desc->flags;
4373 dsi->format = desc->format;
4374 dsi->lanes = desc->lanes;
4376 err = mipi_dsi_attach(dsi);
4378 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4380 drm_panel_remove(&panel->base);
4386 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4390 err = mipi_dsi_detach(dsi);
4392 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4394 return panel_simple_remove(&dsi->dev);
4397 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4399 panel_simple_shutdown(&dsi->dev);
4402 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4404 .name = "panel-simple-dsi",
4405 .of_match_table = dsi_of_match,
4407 .probe = panel_simple_dsi_probe,
4408 .remove = panel_simple_dsi_remove,
4409 .shutdown = panel_simple_dsi_shutdown,
4412 static int __init panel_simple_init(void)
4416 err = platform_driver_register(&panel_simple_platform_driver);
4420 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4421 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4428 module_init(panel_simple_init);
4430 static void __exit panel_simple_exit(void)
4432 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4433 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4435 platform_driver_unregister(&panel_simple_platform_driver);
4437 module_exit(panel_simple_exit);
4439 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4440 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4441 MODULE_LICENSE("GPL and additional rights");