1 // SPDX-License-Identifier: GPL-2.0-only
3 * Ilitek ILI9322 TFT LCD drm_panel driver.
5 * This panel can be configured to support:
6 * - 8-bit serial RGB interface
7 * - 24-bit parallel RGB interface
8 * - 8-bit ITU-R BT.601 interface
9 * - 8-bit ITU-R BT.656 interface
10 * - Up to 320RGBx240 dots resolution TFT LCD displays
11 * - Scaling, brightness and contrast
13 * The scaling means that the display accepts a 640x480 or 720x480
14 * input and rescales it to fit to the 320x240 display. So what we
15 * present to the system is something else than what comes out on the
18 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
19 * Derived from drivers/drm/gpu/panel/panel-samsung-ld9040.c
23 #include <drm/drm_panel.h>
25 #include <linux/of_device.h>
26 #include <linux/bitops.h>
27 #include <linux/gpio/consumer.h>
28 #include <linux/module.h>
29 #include <linux/regmap.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/spi/spi.h>
33 #include <video/mipi_display.h>
34 #include <video/of_videomode.h>
35 #include <video/videomode.h>
37 #define ILI9322_CHIP_ID 0x00
38 #define ILI9322_CHIP_ID_MAGIC 0x96
41 * Voltage on the communication interface, from 0.7 (0x00)
42 * to 1.32 (0x1f) times the VREG1OUT voltage in 2% increments.
43 * 1.00 (0x0f) is the default.
45 #define ILI9322_VCOM_AMP 0x01
48 * High voltage on the communication signals, from 0.37 (0x00) to
49 * 1.0 (0x3f) times the VREGOUT1 voltage in 1% increments.
50 * 0.83 (0x2e) is the default.
52 #define ILI9322_VCOM_HIGH 0x02
55 * VREG1 voltage regulator from 3.6V (0x00) to 6.0V (0x18) in 0.1V
56 * increments. 5.4V (0x12) is the default. This is the reference
57 * voltage for the VCOM levels and the greyscale level.
59 #define ILI9322_VREG1_VOLTAGE 0x03
61 /* Describes the incoming signal */
62 #define ILI9322_ENTRY 0x06
63 /* 0 = right-to-left, 1 = left-to-right (default), horizontal flip */
64 #define ILI9322_ENTRY_HDIR BIT(0)
65 /* 0 = down-to-up, 1 = up-to-down (default), vertical flip */
66 #define ILI9322_ENTRY_VDIR BIT(1)
67 /* NTSC, PAL or autodetect */
68 #define ILI9322_ENTRY_NTSC (0 << 2)
69 #define ILI9322_ENTRY_PAL (1 << 2)
70 #define ILI9322_ENTRY_AUTODETECT (3 << 2)
72 #define ILI9322_ENTRY_SERIAL_RGB_THROUGH (0 << 4)
73 #define ILI9322_ENTRY_SERIAL_RGB_ALIGNED (1 << 4)
74 #define ILI9322_ENTRY_SERIAL_RGB_DUMMY_320X240 (2 << 4)
75 #define ILI9322_ENTRY_SERIAL_RGB_DUMMY_360X240 (3 << 4)
76 #define ILI9322_ENTRY_DISABLE_1 (4 << 4)
77 #define ILI9322_ENTRY_PARALLEL_RGB_THROUGH (5 << 4)
78 #define ILI9322_ENTRY_PARALLEL_RGB_ALIGNED (6 << 4)
79 #define ILI9322_ENTRY_YUV_640Y_320CBCR_25_54_MHZ (7 << 4)
80 #define ILI9322_ENTRY_YUV_720Y_360CBCR_27_MHZ (8 << 4)
81 #define ILI9322_ENTRY_DISABLE_2 (9 << 4)
82 #define ILI9322_ENTRY_ITU_R_BT_656_720X360 (10 << 4)
83 #define ILI9322_ENTRY_ITU_R_BT_656_640X320 (11 << 4)
86 #define ILI9322_POW_CTRL 0x07
87 #define ILI9322_POW_CTRL_STB BIT(0) /* 0 = standby, 1 = normal */
88 #define ILI9322_POW_CTRL_VGL BIT(1) /* 0 = off, 1 = on */
89 #define ILI9322_POW_CTRL_VGH BIT(2) /* 0 = off, 1 = on */
90 #define ILI9322_POW_CTRL_DDVDH BIT(3) /* 0 = off, 1 = on */
91 #define ILI9322_POW_CTRL_VCOM BIT(4) /* 0 = off, 1 = on */
92 #define ILI9322_POW_CTRL_VCL BIT(5) /* 0 = off, 1 = on */
93 #define ILI9322_POW_CTRL_AUTO BIT(6) /* 0 = interactive, 1 = auto */
94 #define ILI9322_POW_CTRL_STANDBY (ILI9322_POW_CTRL_VGL | \
95 ILI9322_POW_CTRL_VGH | \
96 ILI9322_POW_CTRL_DDVDH | \
97 ILI9322_POW_CTRL_VCL | \
98 ILI9322_POW_CTRL_AUTO | \
100 #define ILI9322_POW_CTRL_DEFAULT (ILI9322_POW_CTRL_STANDBY | \
101 ILI9322_POW_CTRL_STB)
103 /* Vertical back porch bits 0..5 */
104 #define ILI9322_VBP 0x08
106 /* Horizontal back porch, 8 bits */
107 #define ILI9322_HBP 0x09
111 * 1 = positive polarity
112 * 0 = negative polarity
114 #define ILI9322_POL 0x0a
115 #define ILI9322_POL_DCLK BIT(0) /* 1 default */
116 #define ILI9322_POL_HSYNC BIT(1) /* 0 default */
117 #define ILI9322_POL_VSYNC BIT(2) /* 0 default */
118 #define ILI9322_POL_DE BIT(3) /* 1 default */
120 * 0 means YCBCR are ordered Cb0,Y0,Cr0,Y1,Cb2,Y2,Cr2,Y3 (default)
121 * in RGB mode this means RGB comes in RGBRGB
122 * 1 means YCBCR are ordered Cr0,Y0,Cb0,Y1,Cr2,Y2,Cb2,Y3
123 * in RGB mode this means RGB comes in BGRBGR
125 #define ILI9322_POL_YCBCR_MODE BIT(4)
126 /* Formula A for YCbCR->RGB = 0, Formula B = 1 */
127 #define ILI9322_POL_FORMULA BIT(5)
128 /* Reverse polarity: 0 = 0..255, 1 = 255..0 */
129 #define ILI9322_POL_REV BIT(6)
131 #define ILI9322_IF_CTRL 0x0b
132 #define ILI9322_IF_CTRL_HSYNC_VSYNC 0x00
133 #define ILI9322_IF_CTRL_HSYNC_VSYNC_DE BIT(2)
134 #define ILI9322_IF_CTRL_DE_ONLY BIT(3)
135 #define ILI9322_IF_CTRL_SYNC_DISABLED (BIT(2) | BIT(3))
136 #define ILI9322_IF_CTRL_LINE_INVERSION BIT(0) /* Not set means frame inv */
138 #define ILI9322_GLOBAL_RESET 0x04
139 #define ILI9322_GLOBAL_RESET_ASSERT 0x00 /* bit 0 = 0 -> reset */
142 * 4+4 bits of negative and positive gamma correction
143 * Upper nybble, bits 4-7 are negative gamma
144 * Lower nybble, bits 0-3 are positive gamma
146 #define ILI9322_GAMMA_1 0x10
147 #define ILI9322_GAMMA_2 0x11
148 #define ILI9322_GAMMA_3 0x12
149 #define ILI9322_GAMMA_4 0x13
150 #define ILI9322_GAMMA_5 0x14
151 #define ILI9322_GAMMA_6 0x15
152 #define ILI9322_GAMMA_7 0x16
153 #define ILI9322_GAMMA_8 0x17
156 * enum ili9322_input - the format of the incoming signal to the panel
158 * The panel can be connected to various input streams and four of them can
159 * be selected by electronic straps on the display. However it is possible
160 * to select another mode or override the electronic default with this
164 ILI9322_INPUT_SRGB_THROUGH = 0x0,
165 ILI9322_INPUT_SRGB_ALIGNED = 0x1,
166 ILI9322_INPUT_SRGB_DUMMY_320X240 = 0x2,
167 ILI9322_INPUT_SRGB_DUMMY_360X240 = 0x3,
168 ILI9322_INPUT_DISABLED_1 = 0x4,
169 ILI9322_INPUT_PRGB_THROUGH = 0x5,
170 ILI9322_INPUT_PRGB_ALIGNED = 0x6,
171 ILI9322_INPUT_YUV_640X320_YCBCR = 0x7,
172 ILI9322_INPUT_YUV_720X360_YCBCR = 0x8,
173 ILI9322_INPUT_DISABLED_2 = 0x9,
174 ILI9322_INPUT_ITU_R_BT656_720X360_YCBCR = 0xa,
175 ILI9322_INPUT_ITU_R_BT656_640X320_YCBCR = 0xb,
176 ILI9322_INPUT_UNKNOWN = 0xc,
179 static const char * const ili9322_inputs[] = {
180 "8 bit serial RGB through",
181 "8 bit serial RGB aligned",
182 "8 bit serial RGB dummy 320x240",
183 "8 bit serial RGB dummy 360x240",
185 "24 bit parallel RGB through",
186 "24 bit parallel RGB aligned",
187 "24 bit YUV 640Y 320CbCr",
188 "24 bit YUV 720Y 360CbCr",
190 "8 bit ITU-R BT.656 720Y 360CbCr",
191 "8 bit ITU-R BT.656 640Y 320CbCr",
195 * struct ili9322_config - the system specific ILI9322 configuration
196 * @width_mm: physical panel width [mm]
197 * @height_mm: physical panel height [mm]
198 * @flip_horizontal: flip the image horizontally (right-to-left scan)
199 * (only in RGB and YUV modes)
200 * @flip_vertical: flip the image vertically (down-to-up scan)
201 * (only in RGB and YUV modes)
202 * @input: the input/entry type used in this system, if this is set to
203 * ILI9322_INPUT_UNKNOWN the driver will try to figure it out by probing
205 * @vreg1out_mv: the output in microvolts for the VREGOUT1 regulator used
206 * to drive the physical display. Valid ranges are 3600 thru 6000 in 100
207 * microvolt increments. If not specified, hardware defaults will be
209 * @vcom_high_percent: the percentage of VREGOUT1 used for the peak
210 * voltage on the communications link. Valid ranges are 37 thru 100
211 * percent. If not specified, hardware defaults will be used (91%).
212 * @vcom_amplitude_percent: the percentage of VREGOUT1 used for the
213 * peak-to-peak amplitude of the communcation signals to the physical
214 * display. Valid ranges are 70 thru 132 percent in increments if two
215 * percent. Odd percentages will be truncated. If not specified, hardware
216 * defaults will be used (114%).
217 * @dclk_active_high: data/pixel clock active high, data will be clocked
218 * in on the rising edge of the DCLK (this is usually the case).
219 * @syncmode: The synchronization mode, what sync signals are emitted.
220 * See the enum for details.
221 * @de_active_high: DE (data entry) is active high
222 * @hsync_active_high: HSYNC is active high
223 * @vsync_active_high: VSYNC is active high
224 * @gamma_corr_pos: a set of 8 nybbles describing positive
225 * gamma correction for voltages V1 thru V8. Valid range 0..15
226 * @gamma_corr_neg: a set of 8 nybbles describing negative
227 * gamma correction for voltages V1 thru V8. Valid range 0..15
229 * These adjust what grayscale voltage will be output for input data V1 = 0,
230 * V2 = 16, V3 = 48, V4 = 96, V5 = 160, V6 = 208, V7 = 240 and V8 = 255.
231 * The curve is shaped like this:
242 * +----------------------------------------------------------->
243 * 0 16 48 96 160 208 240 255
245 * The negative and postive gamma values adjust the V1 thru V8 up/down
246 * according to the datasheet specifications. This is a property of the
247 * physical display connected to the display controller and may vary.
248 * If defined, both arrays must be supplied in full. If the properties
249 * are not supplied, hardware defaults will be used.
251 struct ili9322_config {
254 bool flip_horizontal;
256 enum ili9322_input input;
258 u32 vcom_high_percent;
259 u32 vcom_amplitude_percent;
260 bool dclk_active_high;
262 bool hsync_active_high;
263 bool vsync_active_high;
265 u8 gamma_corr_pos[8];
266 u8 gamma_corr_neg[8];
271 const struct ili9322_config *conf;
272 struct drm_panel panel;
273 struct regmap *regmap;
274 struct regulator_bulk_data supplies[3];
275 struct gpio_desc *reset_gpio;
276 enum ili9322_input input;
284 static inline struct ili9322 *panel_to_ili9322(struct drm_panel *panel)
286 return container_of(panel, struct ili9322, panel);
289 static int ili9322_regmap_spi_write(void *context, const void *data,
292 struct device *dev = context;
293 struct spi_device *spi = to_spi_device(dev);
296 /* Clear bit 7 to write */
297 memcpy(buf, data, 2);
300 dev_dbg(dev, "WRITE: %02x %02x\n", buf[0], buf[1]);
301 return spi_write_then_read(spi, buf, 2, NULL, 0);
304 static int ili9322_regmap_spi_read(void *context, const void *reg,
305 size_t reg_size, void *val, size_t val_size)
307 struct device *dev = context;
308 struct spi_device *spi = to_spi_device(dev);
311 /* Set bit 7 to 1 to read */
313 dev_dbg(dev, "READ: %02x reg size = %zu, val size = %zu\n",
314 buf[0], reg_size, val_size);
317 return spi_write_then_read(spi, buf, 1, val, 1);
320 static struct regmap_bus ili9322_regmap_bus = {
321 .write = ili9322_regmap_spi_write,
322 .read = ili9322_regmap_spi_read,
323 .reg_format_endian_default = REGMAP_ENDIAN_BIG,
324 .val_format_endian_default = REGMAP_ENDIAN_BIG,
327 static bool ili9322_volatile_reg(struct device *dev, unsigned int reg)
332 static bool ili9322_writeable_reg(struct device *dev, unsigned int reg)
334 /* Just register 0 is read-only */
340 static const struct regmap_config ili9322_regmap_config = {
343 .max_register = 0x44,
344 .cache_type = REGCACHE_RBTREE,
345 .volatile_reg = ili9322_volatile_reg,
346 .writeable_reg = ili9322_writeable_reg,
349 static int ili9322_init(struct drm_panel *panel, struct ili9322 *ili)
351 struct drm_connector *connector = panel->connector;
357 ret = regmap_write(ili->regmap, ILI9322_GLOBAL_RESET,
358 ILI9322_GLOBAL_RESET_ASSERT);
360 dev_err(ili->dev, "can't issue GRESET (%d)\n", ret);
364 /* Set up the main voltage regulator */
365 if (ili->vreg1out != U8_MAX) {
366 ret = regmap_write(ili->regmap, ILI9322_VREG1_VOLTAGE,
369 dev_err(ili->dev, "can't set up VREG1OUT (%d)\n", ret);
374 if (ili->vcom_amplitude != U8_MAX) {
375 ret = regmap_write(ili->regmap, ILI9322_VCOM_AMP,
376 ili->vcom_amplitude);
379 "can't set up VCOM amplitude (%d)\n", ret);
384 if (ili->vcom_high != U8_MAX) {
385 ret = regmap_write(ili->regmap, ILI9322_VCOM_HIGH,
388 dev_err(ili->dev, "can't set up VCOM high (%d)\n", ret);
393 /* Set up gamma correction */
394 for (i = 0; i < ARRAY_SIZE(ili->gamma); i++) {
395 ret = regmap_write(ili->regmap, ILI9322_GAMMA_1 + i,
399 "can't write gamma V%d to 0x%02x (%d)\n",
400 i + 1, ILI9322_GAMMA_1 + i, ret);
406 * Polarity and inverted color order for RGB input.
407 * None of this applies in the BT.656 mode.
409 if (ili->conf->dclk_active_high) {
410 reg = ILI9322_POL_DCLK;
411 connector->display_info.bus_flags |=
412 DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
415 connector->display_info.bus_flags |=
416 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
418 if (ili->conf->de_active_high) {
419 reg |= ILI9322_POL_DE;
420 connector->display_info.bus_flags |=
421 DRM_BUS_FLAG_DE_HIGH;
423 connector->display_info.bus_flags |=
426 if (ili->conf->hsync_active_high)
427 reg |= ILI9322_POL_HSYNC;
428 if (ili->conf->vsync_active_high)
429 reg |= ILI9322_POL_VSYNC;
430 ret = regmap_write(ili->regmap, ILI9322_POL, reg);
432 dev_err(ili->dev, "can't write POL register (%d)\n", ret);
437 * Set up interface control.
438 * This is not used in the BT.656 mode (no H/Vsync or DE signals).
440 reg = ili->conf->syncmode;
441 reg |= ILI9322_IF_CTRL_LINE_INVERSION;
442 ret = regmap_write(ili->regmap, ILI9322_IF_CTRL, reg);
444 dev_err(ili->dev, "can't write IF CTRL register (%d)\n", ret);
448 /* Set up the input mode */
449 reg = (ili->input << 4);
450 /* These are inverted, setting to 1 is the default, clearing flips */
451 if (!ili->conf->flip_horizontal)
452 reg |= ILI9322_ENTRY_HDIR;
453 if (!ili->conf->flip_vertical)
454 reg |= ILI9322_ENTRY_VDIR;
455 reg |= ILI9322_ENTRY_AUTODETECT;
456 ret = regmap_write(ili->regmap, ILI9322_ENTRY, reg);
458 dev_err(ili->dev, "can't write ENTRY reg (%d)\n", ret);
461 dev_info(ili->dev, "display is in %s mode, syncmode %02x\n",
462 ili9322_inputs[ili->input],
463 ili->conf->syncmode);
465 dev_info(ili->dev, "initialized display\n");
471 * This power-on sequence if from the datasheet, page 57.
473 static int ili9322_power_on(struct ili9322 *ili)
478 gpiod_set_value(ili->reset_gpio, 1);
480 ret = regulator_bulk_enable(ARRAY_SIZE(ili->supplies), ili->supplies);
482 dev_err(ili->dev, "unable to enable regulators\n");
487 /* De-assert RESET */
488 gpiod_set_value(ili->reset_gpio, 0);
495 static int ili9322_power_off(struct ili9322 *ili)
497 return regulator_bulk_disable(ARRAY_SIZE(ili->supplies), ili->supplies);
500 static int ili9322_disable(struct drm_panel *panel)
502 struct ili9322 *ili = panel_to_ili9322(panel);
505 ret = regmap_write(ili->regmap, ILI9322_POW_CTRL,
506 ILI9322_POW_CTRL_STANDBY);
508 dev_err(ili->dev, "unable to go to standby mode\n");
515 static int ili9322_unprepare(struct drm_panel *panel)
517 struct ili9322 *ili = panel_to_ili9322(panel);
519 return ili9322_power_off(ili);
522 static int ili9322_prepare(struct drm_panel *panel)
524 struct ili9322 *ili = panel_to_ili9322(panel);
527 ret = ili9322_power_on(ili);
531 ret = ili9322_init(panel, ili);
533 ili9322_unprepare(panel);
538 static int ili9322_enable(struct drm_panel *panel)
540 struct ili9322 *ili = panel_to_ili9322(panel);
543 ret = regmap_write(ili->regmap, ILI9322_POW_CTRL,
544 ILI9322_POW_CTRL_DEFAULT);
546 dev_err(ili->dev, "unable to enable panel\n");
553 /* Serial RGB modes */
554 static const struct drm_display_mode srgb_320x240_mode = {
557 .hsync_start = 320 + 359,
558 .hsync_end = 320 + 359 + 1,
559 .htotal = 320 + 359 + 1 + 241,
561 .vsync_start = 240 + 4,
562 .vsync_end = 240 + 4 + 1,
568 static const struct drm_display_mode srgb_360x240_mode = {
571 .hsync_start = 360 + 35,
572 .hsync_end = 360 + 35 + 1,
573 .htotal = 360 + 35 + 1 + 241,
575 .vsync_start = 240 + 21,
576 .vsync_end = 240 + 21 + 1,
582 /* This is the only mode listed for parallel RGB in the datasheet */
583 static const struct drm_display_mode prgb_320x240_mode = {
586 .hsync_start = 320 + 38,
587 .hsync_end = 320 + 38 + 1,
588 .htotal = 320 + 38 + 1 + 50,
590 .vsync_start = 240 + 4,
591 .vsync_end = 240 + 4 + 1,
598 static const struct drm_display_mode yuv_640x320_mode = {
601 .hsync_start = 640 + 252,
602 .hsync_end = 640 + 252 + 1,
603 .htotal = 640 + 252 + 1 + 28,
605 .vsync_start = 320 + 4,
606 .vsync_end = 320 + 4 + 1,
607 .vtotal = 320 + 4 + 1 + 18,
612 static const struct drm_display_mode yuv_720x360_mode = {
615 .hsync_start = 720 + 252,
616 .hsync_end = 720 + 252 + 1,
617 .htotal = 720 + 252 + 1 + 24,
619 .vsync_start = 360 + 4,
620 .vsync_end = 360 + 4 + 1,
621 .vtotal = 360 + 4 + 1 + 18,
626 /* BT.656 VGA mode, 640x480 */
627 static const struct drm_display_mode itu_r_bt_656_640_mode = {
630 .hsync_start = 640 + 3,
631 .hsync_end = 640 + 3 + 1,
632 .htotal = 640 + 3 + 1 + 272,
634 .vsync_start = 480 + 4,
635 .vsync_end = 480 + 4 + 1,
641 /* BT.656 D1 mode 720x480 */
642 static const struct drm_display_mode itu_r_bt_656_720_mode = {
645 .hsync_start = 720 + 3,
646 .hsync_end = 720 + 3 + 1,
647 .htotal = 720 + 3 + 1 + 272,
649 .vsync_start = 480 + 4,
650 .vsync_end = 480 + 4 + 1,
656 static int ili9322_get_modes(struct drm_panel *panel)
658 struct drm_connector *connector = panel->connector;
659 struct ili9322 *ili = panel_to_ili9322(panel);
660 struct drm_display_mode *mode;
662 connector->display_info.width_mm = ili->conf->width_mm;
663 connector->display_info.height_mm = ili->conf->height_mm;
665 switch (ili->input) {
666 case ILI9322_INPUT_SRGB_DUMMY_320X240:
667 mode = drm_mode_duplicate(panel->drm, &srgb_320x240_mode);
669 case ILI9322_INPUT_SRGB_DUMMY_360X240:
670 mode = drm_mode_duplicate(panel->drm, &srgb_360x240_mode);
672 case ILI9322_INPUT_PRGB_THROUGH:
673 case ILI9322_INPUT_PRGB_ALIGNED:
674 mode = drm_mode_duplicate(panel->drm, &prgb_320x240_mode);
676 case ILI9322_INPUT_YUV_640X320_YCBCR:
677 mode = drm_mode_duplicate(panel->drm, &yuv_640x320_mode);
679 case ILI9322_INPUT_YUV_720X360_YCBCR:
680 mode = drm_mode_duplicate(panel->drm, &yuv_720x360_mode);
682 case ILI9322_INPUT_ITU_R_BT656_720X360_YCBCR:
683 mode = drm_mode_duplicate(panel->drm, &itu_r_bt_656_720_mode);
685 case ILI9322_INPUT_ITU_R_BT656_640X320_YCBCR:
686 mode = drm_mode_duplicate(panel->drm, &itu_r_bt_656_640_mode);
693 DRM_ERROR("bad mode or failed to add mode\n");
696 drm_mode_set_name(mode);
698 * This is the preferred mode because most people are going
699 * to want to use the display with VGA type graphics.
701 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
703 /* Set up the polarity */
704 if (ili->conf->hsync_active_high)
705 mode->flags |= DRM_MODE_FLAG_PHSYNC;
707 mode->flags |= DRM_MODE_FLAG_NHSYNC;
708 if (ili->conf->vsync_active_high)
709 mode->flags |= DRM_MODE_FLAG_PVSYNC;
711 mode->flags |= DRM_MODE_FLAG_NVSYNC;
713 mode->width_mm = ili->conf->width_mm;
714 mode->height_mm = ili->conf->height_mm;
715 drm_mode_probed_add(connector, mode);
717 return 1; /* Number of modes */
720 static const struct drm_panel_funcs ili9322_drm_funcs = {
721 .disable = ili9322_disable,
722 .unprepare = ili9322_unprepare,
723 .prepare = ili9322_prepare,
724 .enable = ili9322_enable,
725 .get_modes = ili9322_get_modes,
728 static int ili9322_probe(struct spi_device *spi)
730 struct device *dev = &spi->dev;
732 const struct regmap_config *regmap_config;
738 ili = devm_kzalloc(dev, sizeof(struct ili9322), GFP_KERNEL);
742 spi_set_drvdata(spi, ili);
747 * Every new incarnation of this display must have a unique
748 * data entry for the system in this driver.
750 ili->conf = of_device_get_match_data(dev);
752 dev_err(dev, "missing device configuration\n");
756 val = ili->conf->vreg1out_mv;
758 /* Default HW value, do not touch (should be 4.5V) */
759 ili->vreg1out = U8_MAX;
762 dev_err(dev, "too low VREG1OUT\n");
766 dev_err(dev, "too high VREG1OUT\n");
769 if ((val % 100) != 0) {
770 dev_err(dev, "VREG1OUT is no even 100 microvolt\n");
775 dev_dbg(dev, "VREG1OUT = 0x%02x\n", val);
779 val = ili->conf->vcom_high_percent;
781 /* Default HW value, do not touch (should be 91%) */
782 ili->vcom_high = U8_MAX;
785 dev_err(dev, "too low VCOM high\n");
789 dev_err(dev, "too high VCOM high\n");
793 dev_dbg(dev, "VCOM high = 0x%02x\n", val);
794 ili->vcom_high = val;
797 val = ili->conf->vcom_amplitude_percent;
799 /* Default HW value, do not touch (should be 114%) */
800 ili->vcom_high = U8_MAX;
803 dev_err(dev, "too low VCOM amplitude\n");
807 dev_err(dev, "too high VCOM amplitude\n");
811 val >>= 1; /* Increments of 2% */
812 dev_dbg(dev, "VCOM amplitude = 0x%02x\n", val);
813 ili->vcom_amplitude = val;
816 for (i = 0; i < ARRAY_SIZE(ili->gamma); i++) {
817 val = ili->conf->gamma_corr_neg[i];
819 dev_err(dev, "negative gamma %u > 15, capping\n", val);
823 val = ili->conf->gamma_corr_pos[i];
825 dev_err(dev, "positive gamma %u > 15, capping\n", val);
829 ili->gamma[i] = gamma;
830 dev_dbg(dev, "gamma V%d: 0x%02x\n", i + 1, gamma);
833 ili->supplies[0].supply = "vcc"; /* 2.7-3.6 V */
834 ili->supplies[1].supply = "iovcc"; /* 1.65-3.6V */
835 ili->supplies[2].supply = "vci"; /* 2.7-3.6V */
836 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ili->supplies),
840 ret = regulator_set_voltage(ili->supplies[0].consumer,
844 ret = regulator_set_voltage(ili->supplies[1].consumer,
848 ret = regulator_set_voltage(ili->supplies[2].consumer,
853 ili->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
854 if (IS_ERR(ili->reset_gpio)) {
855 dev_err(dev, "failed to get RESET GPIO\n");
856 return PTR_ERR(ili->reset_gpio);
859 spi->bits_per_word = 8;
860 ret = spi_setup(spi);
862 dev_err(dev, "spi setup failed.\n");
865 regmap_config = &ili9322_regmap_config;
866 ili->regmap = devm_regmap_init(dev, &ili9322_regmap_bus, dev,
868 if (IS_ERR(ili->regmap)) {
869 dev_err(dev, "failed to allocate register map\n");
870 return PTR_ERR(ili->regmap);
873 ret = regmap_read(ili->regmap, ILI9322_CHIP_ID, &val);
875 dev_err(dev, "can't get chip ID (%d)\n", ret);
878 if (val != ILI9322_CHIP_ID_MAGIC) {
879 dev_err(dev, "chip ID 0x%0x2, expected 0x%02x\n", val,
880 ILI9322_CHIP_ID_MAGIC);
884 /* Probe the system to find the display setting */
885 if (ili->conf->input == ILI9322_INPUT_UNKNOWN) {
886 ret = regmap_read(ili->regmap, ILI9322_ENTRY, &val);
888 dev_err(dev, "can't get entry setting (%d)\n", ret);
891 /* Input enum corresponds to HW setting */
892 ili->input = (val >> 4) & 0x0f;
893 if (ili->input >= ILI9322_INPUT_UNKNOWN)
894 ili->input = ILI9322_INPUT_UNKNOWN;
896 ili->input = ili->conf->input;
899 drm_panel_init(&ili->panel);
900 ili->panel.dev = dev;
901 ili->panel.funcs = &ili9322_drm_funcs;
903 return drm_panel_add(&ili->panel);
906 static int ili9322_remove(struct spi_device *spi)
908 struct ili9322 *ili = spi_get_drvdata(spi);
910 ili9322_power_off(ili);
911 drm_panel_remove(&ili->panel);
917 * The D-Link DIR-685 panel is marked LM918A01-1A SY-B4-091116-E0199
919 static const struct ili9322_config ili9322_dir_685 = {
922 .input = ILI9322_INPUT_ITU_R_BT656_640X320_YCBCR,
924 .vcom_high_percent = 91,
925 .vcom_amplitude_percent = 114,
926 .syncmode = ILI9322_IF_CTRL_SYNC_DISABLED,
927 .dclk_active_high = true,
928 .gamma_corr_neg = { 0xa, 0x5, 0x7, 0x7, 0x7, 0x5, 0x1, 0x6 },
929 .gamma_corr_pos = { 0x7, 0x7, 0x3, 0x2, 0x3, 0x5, 0x7, 0x2 },
932 static const struct of_device_id ili9322_of_match[] = {
934 .compatible = "dlink,dir-685-panel",
935 .data = &ili9322_dir_685,
938 .compatible = "ilitek,ili9322",
943 MODULE_DEVICE_TABLE(of, ili9322_of_match);
945 static struct spi_driver ili9322_driver = {
946 .probe = ili9322_probe,
947 .remove = ili9322_remove,
949 .name = "panel-ilitek-ili9322",
950 .of_match_table = ili9322_of_match,
953 module_spi_driver(ili9322_driver);
955 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
956 MODULE_DESCRIPTION("ILI9322 LCD panel driver");
957 MODULE_LICENSE("GPL v2");