1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
4 * Author: Rob Clark <rob.clark@linaro.org>
10 struct list_head node;
16 /* call with wait_lock and dispc runtime held */
17 static void omap_irq_update(struct drm_device *dev)
19 struct omap_drm_private *priv = dev->dev_private;
20 struct omap_irq_wait *wait;
21 u32 irqmask = priv->irq_mask;
23 assert_spin_locked(&priv->wait_lock);
25 list_for_each_entry(wait, &priv->wait_list, node)
26 irqmask |= wait->irqmask;
28 DBG("irqmask=%08x", irqmask);
30 priv->dispc_ops->write_irqenable(priv->dispc, irqmask);
33 static void omap_irq_wait_handler(struct omap_irq_wait *wait)
39 struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev,
40 u32 irqmask, int count)
42 struct omap_drm_private *priv = dev->dev_private;
43 struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL);
46 init_waitqueue_head(&wait->wq);
47 wait->irqmask = irqmask;
50 spin_lock_irqsave(&priv->wait_lock, flags);
51 list_add(&wait->node, &priv->wait_list);
53 spin_unlock_irqrestore(&priv->wait_lock, flags);
58 int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait,
59 unsigned long timeout)
61 struct omap_drm_private *priv = dev->dev_private;
65 ret = wait_event_timeout(wait->wq, (wait->count <= 0), timeout);
67 spin_lock_irqsave(&priv->wait_lock, flags);
68 list_del(&wait->node);
70 spin_unlock_irqrestore(&priv->wait_lock, flags);
74 return ret == 0 ? -1 : 0;
78 * enable_vblank - enable vblank interrupt events
80 * @pipe: which irq to enable
82 * Enable vblank interrupts for @crtc. If the device doesn't have
83 * a hardware vblank counter, this routine should be a no-op, since
84 * interrupts will have to stay on to keep the count accurate.
87 * Zero on success, appropriate errno if the given @crtc's vblank
88 * interrupt cannot be enabled.
90 int omap_irq_enable_vblank(struct drm_crtc *crtc)
92 struct drm_device *dev = crtc->dev;
93 struct omap_drm_private *priv = dev->dev_private;
95 enum omap_channel channel = omap_crtc_channel(crtc);
97 DBG("dev=%p, crtc=%u", dev, channel);
99 spin_lock_irqsave(&priv->wait_lock, flags);
100 priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(priv->dispc,
102 omap_irq_update(dev);
103 spin_unlock_irqrestore(&priv->wait_lock, flags);
109 * disable_vblank - disable vblank interrupt events
111 * @pipe: which irq to enable
113 * Disable vblank interrupts for @crtc. If the device doesn't have
114 * a hardware vblank counter, this routine should be a no-op, since
115 * interrupts will have to stay on to keep the count accurate.
117 void omap_irq_disable_vblank(struct drm_crtc *crtc)
119 struct drm_device *dev = crtc->dev;
120 struct omap_drm_private *priv = dev->dev_private;
122 enum omap_channel channel = omap_crtc_channel(crtc);
124 DBG("dev=%p, crtc=%u", dev, channel);
126 spin_lock_irqsave(&priv->wait_lock, flags);
127 priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(priv->dispc,
129 omap_irq_update(dev);
130 spin_unlock_irqrestore(&priv->wait_lock, flags);
133 static void omap_irq_fifo_underflow(struct omap_drm_private *priv,
136 static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL,
137 DEFAULT_RATELIMIT_BURST);
138 static const struct {
142 { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW },
143 { "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW },
144 { "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW },
145 { "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW },
148 const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW
149 | DISPC_IRQ_VID1_FIFO_UNDERFLOW
150 | DISPC_IRQ_VID2_FIFO_UNDERFLOW
151 | DISPC_IRQ_VID3_FIFO_UNDERFLOW;
154 spin_lock(&priv->wait_lock);
155 irqstatus &= priv->irq_mask & mask;
156 spin_unlock(&priv->wait_lock);
161 if (!__ratelimit(&_rs))
164 DRM_ERROR("FIFO underflow on ");
166 for (i = 0; i < ARRAY_SIZE(sources); ++i) {
167 if (sources[i].mask & irqstatus)
168 pr_cont("%s ", sources[i].name);
171 pr_cont("(0x%08x)\n", irqstatus);
174 static void omap_irq_ocp_error_handler(struct drm_device *dev,
177 if (!(irqstatus & DISPC_IRQ_OCP_ERR))
180 dev_err_ratelimited(dev->dev, "OCP error\n");
183 static irqreturn_t omap_irq_handler(int irq, void *arg)
185 struct drm_device *dev = (struct drm_device *) arg;
186 struct omap_drm_private *priv = dev->dev_private;
187 struct omap_irq_wait *wait, *n;
192 irqstatus = priv->dispc_ops->read_irqstatus(priv->dispc);
193 priv->dispc_ops->clear_irqstatus(priv->dispc, irqstatus);
194 priv->dispc_ops->read_irqstatus(priv->dispc); /* flush posted write */
196 VERB("irqs: %08x", irqstatus);
198 for (id = 0; id < priv->num_pipes; id++) {
199 struct drm_crtc *crtc = priv->pipes[id].crtc;
200 enum omap_channel channel = omap_crtc_channel(crtc);
202 if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel)) {
203 drm_handle_vblank(dev, id);
204 omap_crtc_vblank_irq(crtc);
207 if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, channel))
208 omap_crtc_error_irq(crtc, irqstatus);
211 omap_irq_ocp_error_handler(dev, irqstatus);
212 omap_irq_fifo_underflow(priv, irqstatus);
214 spin_lock_irqsave(&priv->wait_lock, flags);
215 list_for_each_entry_safe(wait, n, &priv->wait_list, node) {
216 if (wait->irqmask & irqstatus)
217 omap_irq_wait_handler(wait);
219 spin_unlock_irqrestore(&priv->wait_lock, flags);
224 static const u32 omap_underflow_irqs[] = {
225 [OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW,
226 [OMAP_DSS_VIDEO1] = DISPC_IRQ_VID1_FIFO_UNDERFLOW,
227 [OMAP_DSS_VIDEO2] = DISPC_IRQ_VID2_FIFO_UNDERFLOW,
228 [OMAP_DSS_VIDEO3] = DISPC_IRQ_VID3_FIFO_UNDERFLOW,
232 * We need a special version, instead of just using drm_irq_install(),
233 * because we need to register the irq via omapdss. Once omapdss and
234 * omapdrm are merged together we can assign the dispc hwmod data to
235 * ourselves and drop these and just use drm_irq_{install,uninstall}()
238 int omap_drm_irq_install(struct drm_device *dev)
240 struct omap_drm_private *priv = dev->dev_private;
241 unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
242 unsigned int max_planes;
246 spin_lock_init(&priv->wait_lock);
247 INIT_LIST_HEAD(&priv->wait_list);
249 priv->irq_mask = DISPC_IRQ_OCP_ERR;
251 max_planes = min(ARRAY_SIZE(priv->planes),
252 ARRAY_SIZE(omap_underflow_irqs));
253 for (i = 0; i < max_planes; ++i) {
255 priv->irq_mask |= omap_underflow_irqs[i];
258 for (i = 0; i < num_mgrs; ++i)
259 priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, i);
261 priv->dispc_ops->runtime_get(priv->dispc);
262 priv->dispc_ops->clear_irqstatus(priv->dispc, 0xffffffff);
263 priv->dispc_ops->runtime_put(priv->dispc);
265 ret = priv->dispc_ops->request_irq(priv->dispc, omap_irq_handler, dev);
269 dev->irq_enabled = true;
274 void omap_drm_irq_uninstall(struct drm_device *dev)
276 struct omap_drm_private *priv = dev->dev_private;
278 if (!dev->irq_enabled)
281 dev->irq_enabled = false;
283 priv->dispc_ops->free_irq(priv->dispc, dev);