2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
23 #include <subdev/fb.h>
25 #include <core/device.h>
29 struct gk20a_instobj_priv {
30 struct nvkm_instobj base;
31 /* Must be second member here - see nouveau_gpuobj_map_vm() */
37 struct nvkm_mm_node r;
40 struct gk20a_instmem_priv {
41 struct nvkm_instmem base;
47 gk20a_instobj_rd32(struct nvkm_object *object, u64 offset)
49 struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(object);
50 struct gk20a_instobj_priv *node = (void *)object;
52 u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
53 u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
56 spin_lock_irqsave(&priv->lock, flags);
57 if (unlikely(priv->addr != base)) {
58 nv_wr32(priv, 0x001700, base >> 16);
61 data = nv_rd32(priv, 0x700000 + addr);
62 spin_unlock_irqrestore(&priv->lock, flags);
67 gk20a_instobj_wr32(struct nvkm_object *object, u64 offset, u32 data)
69 struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(object);
70 struct gk20a_instobj_priv *node = (void *)object;
72 u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
73 u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
75 spin_lock_irqsave(&priv->lock, flags);
76 if (unlikely(priv->addr != base)) {
77 nv_wr32(priv, 0x001700, base >> 16);
80 nv_wr32(priv, 0x700000 + addr, data);
81 spin_unlock_irqrestore(&priv->lock, flags);
85 gk20a_instobj_dtor(struct nvkm_object *object)
87 struct gk20a_instobj_priv *node = (void *)object;
88 struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(node);
89 struct device *dev = nv_device_base(nv_device(priv));
91 if (unlikely(!node->handle))
94 dma_free_coherent(dev, node->mem->size << PAGE_SHIFT, node->cpuaddr,
97 nvkm_instobj_destroy(&node->base);
101 gk20a_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
102 struct nvkm_oclass *oclass, void *data, u32 _size,
103 struct nvkm_object **pobject)
105 struct nvkm_instobj_args *args = data;
106 struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(parent);
107 struct device *dev = nv_device_base(nv_device(priv));
108 struct gk20a_instobj_priv *node;
113 nv_debug(parent, "%s: size: %x align: %x\n", __func__,
114 args->size, args->align);
116 size = max((args->size + 4095) & ~4095, (u32)4096);
117 align = max((args->align + 4095) & ~4095, (u32)4096);
119 npages = size >> PAGE_SHIFT;
121 ret = nvkm_instobj_create_(parent, engine, oclass, sizeof(*node),
123 *pobject = nv_object(node);
127 node->mem = &node->_mem;
129 node->cpuaddr = dma_alloc_coherent(dev, npages << PAGE_SHIFT,
130 &node->handle, GFP_KERNEL);
131 if (!node->cpuaddr) {
132 nv_error(priv, "cannot allocate DMA memory\n");
136 /* alignment check */
137 if (unlikely(node->handle & (align - 1)))
138 nv_warn(priv, "memory not aligned as requested: %pad (0x%x)\n",
139 &node->handle, align);
141 node->mem->offset = node->handle;
142 node->mem->size = size >> 12;
143 node->mem->memtype = 0;
144 node->mem->page_shift = 12;
145 INIT_LIST_HEAD(&node->mem->regions);
148 node->r.offset = node->handle >> 12;
149 node->r.length = npages;
150 list_add_tail(&node->r.rl_entry, &node->mem->regions);
152 node->base.addr = node->mem->offset;
153 node->base.size = size;
155 nv_debug(parent, "alloc size: 0x%x, align: 0x%x, gaddr: 0x%llx\n",
156 size, align, node->mem->offset);
161 static struct nvkm_instobj_impl
162 gk20a_instobj_oclass = {
163 .base.ofuncs = &(struct nvkm_ofuncs) {
164 .ctor = gk20a_instobj_ctor,
165 .dtor = gk20a_instobj_dtor,
166 .init = _nvkm_instobj_init,
167 .fini = _nvkm_instobj_fini,
168 .rd32 = gk20a_instobj_rd32,
169 .wr32 = gk20a_instobj_wr32,
176 gk20a_instmem_fini(struct nvkm_object *object, bool suspend)
178 struct gk20a_instmem_priv *priv = (void *)object;
180 return nvkm_instmem_fini(&priv->base, suspend);
184 gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
185 struct nvkm_oclass *oclass, void *data, u32 size,
186 struct nvkm_object **pobject)
188 struct gk20a_instmem_priv *priv;
191 ret = nvkm_instmem_create(parent, engine, oclass, &priv);
192 *pobject = nv_object(priv);
196 spin_lock_init(&priv->lock);
202 gk20a_instmem_oclass = &(struct nvkm_instmem_impl) {
203 .base.handle = NV_SUBDEV(INSTMEM, 0xea),
204 .base.ofuncs = &(struct nvkm_ofuncs) {
205 .ctor = gk20a_instmem_ctor,
206 .dtor = _nvkm_instmem_dtor,
207 .init = _nvkm_instmem_init,
208 .fini = gk20a_instmem_fini,
210 .instobj = &gk20a_instobj_oclass.base,