drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c

   1 /*
   2  * Copyright 2019 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "priv.h"
  23
  24 #include <core/falcon.h>
  25 #include <core/firmware.h>
  26 #include <core/memory.h>
  27 #include <subdev/mc.h>
  28 #include <subdev/mmu.h>
  29 #include <subdev/pmu.h>
  30 #include <subdev/timer.h>
  31
  32 #include <nvfw/acr.h>
  33 #include <nvfw/flcn.h>
  34
  35 const struct nvkm_acr_func
  36 gm200_acr = {
  37 };
  38
  39 int
  40 gm200_acr_nofw(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
  41 {
  42         nvkm_warn(&acr->subdev, "firmware unavailable\n");
  43         return 0;
  44 }
  45
  46 int
  47 gm200_acr_init(struct nvkm_acr *acr)
  48 {
  49         return nvkm_acr_hsf_boot(acr, "load");
  50 }
  51
  52 void
  53 gm200_acr_wpr_check(struct nvkm_acr *acr, u64 *start, u64 *limit)
  54 {
  55         struct nvkm_device *device = acr->subdev.device;
  56
  57         nvkm_wr32(device, 0x100cd4, 2);
  58         *start = (u64)(nvkm_rd32(device, 0x100cd4) & 0xffffff00) << 8;
  59         nvkm_wr32(device, 0x100cd4, 3);
  60         *limit = (u64)(nvkm_rd32(device, 0x100cd4) & 0xffffff00) << 8;
  61         *limit = *limit + 0x20000;
  62 }
  63
  64 void
  65 gm200_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust)
  66 {
  67         struct nvkm_subdev *subdev = &acr->subdev;
  68         struct wpr_header hdr;
  69         struct lsb_header lsb;
  70         struct nvkm_acr_lsf *lsfw;
  71         u32 offset = 0;
  72
  73         do {
  74                 nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr));
  75                 wpr_header_dump(subdev, &hdr);
  76
  77                 list_for_each_entry(lsfw, &acr->lsfw, head) {
  78                         if (lsfw->id != hdr.falcon_id)
  79                                 continue;
  80
  81                         nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb));
  82                         lsb_header_dump(subdev, &lsb);
  83
  84                         lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust);
  85                         break;
  86                 }
  87                 offset += sizeof(hdr);
  88         } while (hdr.falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID);
  89 }
  90
  91 void
  92 gm200_acr_wpr_build_lsb_tail(struct nvkm_acr_lsfw *lsfw,
  93                              struct lsb_header_tail *hdr)
  94 {
  95         hdr->ucode_off = lsfw->offset.img;
  96         hdr->ucode_size = lsfw->ucode_size;
  97         hdr->data_size = lsfw->data_size;
  98         hdr->bl_code_size = lsfw->bootloader_size;
  99         hdr->bl_imem_off = lsfw->bootloader_imem_offset;
 100         hdr->bl_data_off = lsfw->offset.bld;
 101         hdr->bl_data_size = lsfw->bl_data_size;
 102         hdr->app_code_off = lsfw->app_start_offset +
 103                            lsfw->app_resident_code_offset;
 104         hdr->app_code_size = lsfw->app_resident_code_size;
 105         hdr->app_data_off = lsfw->app_start_offset +
 106                            lsfw->app_resident_data_offset;
 107         hdr->app_data_size = lsfw->app_resident_data_size;
 108         hdr->flags = lsfw->func->flags;
 109 }
 110
 111 static int
 112 gm200_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw)
 113 {
 114         struct lsb_header hdr;
 115
 116         if (WARN_ON(lsfw->sig->size != sizeof(hdr.signature)))
 117                 return -EINVAL;
 118
 119         memcpy(&hdr.signature, lsfw->sig->data, lsfw->sig->size);
 120         gm200_acr_wpr_build_lsb_tail(lsfw, &hdr.tail);
 121
 122         nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr));
 123         return 0;
 124 }
 125
 126 int
 127 gm200_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos)
 128 {
 129         struct nvkm_acr_lsfw *lsfw;
 130         u32 offset = 0;
 131         int ret;
 132
 133         /* Fill per-LSF structures. */
 134         list_for_each_entry(lsfw, &acr->lsfw, head) {
 135                 struct wpr_header hdr = {
 136                         .falcon_id = lsfw->id,
 137                         .lsb_offset = lsfw->offset.lsb,
 138                         .bootstrap_owner = NVKM_ACR_LSF_PMU,
 139                         .lazy_bootstrap = rtos && lsfw->id != rtos->id,
 140                         .status = WPR_HEADER_V0_STATUS_COPY,
 141                 };
 142
 143                 /* Write WPR header. */
 144                 nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
 145                 offset += sizeof(hdr);
 146
 147                 /* Write LSB header. */
 148                 ret = gm200_acr_wpr_build_lsb(acr, lsfw);
 149                 if (ret)
 150                         return ret;
 151
 152                 /* Write ucode image. */
 153                 nvkm_wobj(acr->wpr, lsfw->offset.img,
 154                                     lsfw->img.data,
 155                                     lsfw->img.size);
 156
 157                 /* Write bootloader data. */
 158                 lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw);
 159         }
 160
 161         /* Finalise WPR. */
 162         nvkm_wo32(acr->wpr, offset, WPR_HEADER_V0_FALCON_ID_INVALID);
 163         return 0;
 164 }
 165
 166 static int
 167 gm200_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size)
 168 {
 169         int ret = nvkm_memory_new(acr->subdev.device, NVKM_MEM_TARGET_INST,
 170                                   ALIGN(wpr_size, 0x40000), 0x40000, true,
 171                                   &acr->wpr);
 172         if (ret)
 173                 return ret;
 174
 175         acr->wpr_start = nvkm_memory_addr(acr->wpr);
 176         acr->wpr_end = acr->wpr_start + nvkm_memory_size(acr->wpr);
 177         return 0;
 178 }
 179
 180 u32
 181 gm200_acr_wpr_layout(struct nvkm_acr *acr)
 182 {
 183         struct nvkm_acr_lsfw *lsfw;
 184         u32 wpr = 0;
 185
 186         wpr += 11 /* MAX_LSF */ * sizeof(struct wpr_header);
 187
 188         list_for_each_entry(lsfw, &acr->lsfw, head) {
 189                 wpr  = ALIGN(wpr, 256);
 190                 lsfw->offset.lsb = wpr;
 191                 wpr += sizeof(struct lsb_header);
 192
 193                 wpr  = ALIGN(wpr, 4096);
 194                 lsfw->offset.img = wpr;
 195                 wpr += lsfw->img.size;
 196
 197                 wpr  = ALIGN(wpr, 256);
 198                 lsfw->offset.bld = wpr;
 199                 lsfw->bl_data_size = ALIGN(lsfw->func->bld_size, 256);
 200                 wpr += lsfw->bl_data_size;
 201         }
 202
 203         return wpr;
 204 }
 205
 206 int
 207 gm200_acr_wpr_parse(struct nvkm_acr *acr)
 208 {
 209         const struct wpr_header *hdr = (void *)acr->wpr_fw->data;
 210
 211         while (hdr->falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID) {
 212                 wpr_header_dump(&acr->subdev, hdr);
 213                 if (!nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id))
 214                         return -ENOMEM;
 215         }
 216
 217         return 0;
 218 }
 219
 220 void
 221 gm200_acr_hsfw_bld(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
 222 {
 223         struct flcn_bl_dmem_desc_v1 hsdesc = {
 224                 .ctx_dma = FALCON_DMAIDX_VIRT,
 225                 .code_dma_base = hsf->vma->addr,
 226                 .non_sec_code_off = hsf->non_sec_addr,
 227                 .non_sec_code_size = hsf->non_sec_size,
 228                 .sec_code_off = hsf->sec_addr,
 229                 .sec_code_size = hsf->sec_size,
 230                 .code_entry_point = 0,
 231                 .data_dma_base = hsf->vma->addr + hsf->data_addr,
 232                 .data_size = hsf->data_size,
 233         };
 234
 235         flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hsdesc);
 236
 237         nvkm_falcon_load_dmem(hsf->falcon, &hsdesc, 0, sizeof(hsdesc), 0);
 238 }
 239
 240 int
 241 gm200_acr_hsfw_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf,
 242                     u32 intr_clear, u32 mbox0_ok)
 243 {
 244         struct nvkm_subdev *subdev = &acr->subdev;
 245         struct nvkm_device *device = subdev->device;
 246         struct nvkm_falcon *falcon = hsf->falcon;
 247         u32 mbox0, mbox1;
 248         int ret;
 249
 250         /* Reset falcon. */
 251         nvkm_falcon_reset(falcon);
 252         nvkm_falcon_bind_context(falcon, acr->inst);
 253
 254         /* Load bootloader into IMEM. */
 255         nvkm_falcon_load_imem(falcon, hsf->imem,
 256                                       falcon->code.limit - hsf->imem_size,
 257                                       hsf->imem_size,
 258                                       hsf->imem_tag,
 259                                       0, false);
 260
 261         /* Load bootloader data into DMEM. */
 262         hsf->func->bld(acr, hsf);
 263
 264         /* Boot the falcon. */
 265         nvkm_mc_intr_mask(device, falcon->owner->index, false);
 266
 267         nvkm_falcon_wr32(falcon, 0x040, 0xdeada5a5);
 268         nvkm_falcon_set_start_addr(falcon, hsf->imem_tag << 8);
 269         nvkm_falcon_start(falcon);
 270         ret = nvkm_falcon_wait_for_halt(falcon, 100);
 271         if (ret)
 272                 return ret;
 273
 274         /* Check for successful completion. */
 275         mbox0 = nvkm_falcon_rd32(falcon, 0x040);
 276         mbox1 = nvkm_falcon_rd32(falcon, 0x044);
 277         nvkm_debug(subdev, "mailbox %08x %08x\n", mbox0, mbox1);
 278         if (mbox0 && mbox0 != mbox0_ok)
 279                 return -EIO;
 280
 281         nvkm_falcon_clear_interrupt(falcon, intr_clear);
 282         nvkm_mc_intr_mask(device, falcon->owner->index, true);
 283         return ret;
 284 }
 285
 286 int
 287 gm200_acr_hsfw_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw,
 288                     struct nvkm_falcon *falcon)
 289 {
 290         struct nvkm_subdev *subdev = &acr->subdev;
 291         struct nvkm_acr_hsf *hsf;
 292         int ret;
 293
 294         /* Patch the appropriate signature (production/debug) into the FW
 295          * image, as determined by the mode the falcon is in.
 296          */
 297         ret = nvkm_falcon_get(falcon, subdev);
 298         if (ret)
 299                 return ret;
 300
 301         if (hsfw->sig.patch_loc) {
 302                 if (!falcon->debug) {
 303                         nvkm_debug(subdev, "patching production signature\n");
 304                         memcpy(hsfw->image + hsfw->sig.patch_loc,
 305                                hsfw->sig.prod.data,
 306                                hsfw->sig.prod.size);
 307                 } else {
 308                         nvkm_debug(subdev, "patching debug signature\n");
 309                         memcpy(hsfw->image + hsfw->sig.patch_loc,
 310                                hsfw->sig.dbg.data,
 311                                hsfw->sig.dbg.size);
 312                 }
 313         }
 314
 315         nvkm_falcon_put(falcon, subdev);
 316
 317         if (!(hsf = kzalloc(sizeof(*hsf), GFP_KERNEL)))
 318                 return -ENOMEM;
 319         hsf->func = hsfw->func;
 320         hsf->name = hsfw->name;
 321         list_add_tail(&hsf->head, &acr->hsf);
 322
 323         hsf->imem_size = hsfw->imem_size;
 324         hsf->imem_tag = hsfw->imem_tag;
 325         hsf->imem = kmemdup(hsfw->imem, hsfw->imem_size, GFP_KERNEL);
 326         if (!hsf->imem)
 327                 return -ENOMEM;
 328
 329         hsf->non_sec_addr = hsfw->non_sec_addr;
 330         hsf->non_sec_size = hsfw->non_sec_size;
 331         hsf->sec_addr = hsfw->sec_addr;
 332         hsf->sec_size = hsfw->sec_size;
 333         hsf->data_addr = hsfw->data_addr;
 334         hsf->data_size = hsfw->data_size;
 335
 336         /* Make the FW image accessible to the HS bootloader. */
 337         ret = nvkm_memory_new(subdev->device, NVKM_MEM_TARGET_INST,
 338                               hsfw->image_size, 0x1000, false, &hsf->ucode);
 339         if (ret)
 340                 return ret;
 341
 342         nvkm_kmap(hsf->ucode);
 343         nvkm_wobj(hsf->ucode, 0, hsfw->image, hsfw->image_size);
 344         nvkm_done(hsf->ucode);
 345
 346         ret = nvkm_vmm_get(acr->vmm, 12, nvkm_memory_size(hsf->ucode),
 347                            &hsf->vma);
 348         if (ret)
 349                 return ret;
 350
 351         ret = nvkm_memory_map(hsf->ucode, 0, acr->vmm, hsf->vma, NULL, 0);
 352         if (ret)
 353                 return ret;
 354
 355         hsf->falcon = falcon;
 356         return 0;
 357 }
 358
 359 int
 360 gm200_acr_unload_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
 361 {
 362         return gm200_acr_hsfw_boot(acr, hsf, 0, 0x1d);
 363 }
 364
 365 int
 366 gm200_acr_unload_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw)
 367 {
 368         return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->pmu->falcon);
 369 }
 370
 371 const struct nvkm_acr_hsf_func
 372 gm200_acr_unload_0 = {
 373         .load = gm200_acr_unload_load,
 374         .boot = gm200_acr_unload_boot,
 375         .bld = gm200_acr_hsfw_bld,
 376 };
 377
 378 MODULE_FIRMWARE("nvidia/gm200/acr/ucode_unload.bin");
 379 MODULE_FIRMWARE("nvidia/gm204/acr/ucode_unload.bin");
 380 MODULE_FIRMWARE("nvidia/gm206/acr/ucode_unload.bin");
 381 MODULE_FIRMWARE("nvidia/gp100/acr/ucode_unload.bin");
 382
 383 static const struct nvkm_acr_hsf_fwif
 384 gm200_acr_unload_fwif[] = {
 385         { 0, nvkm_acr_hsfw_load, &gm200_acr_unload_0 },
 386         {}
 387 };
 388
 389 int
 390 gm200_acr_load_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
 391 {
 392         return gm200_acr_hsfw_boot(acr, hsf, 0x10, 0);
 393 }
 394
 395 static int
 396 gm200_acr_load_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw)
 397 {
 398         struct flcn_acr_desc *desc = (void *)&hsfw->image[hsfw->data_addr];
 399
 400         desc->wpr_region_id = 1;
 401         desc->regions.no_regions = 2;
 402         desc->regions.region_props[0].start_addr = acr->wpr_start >> 8;
 403         desc->regions.region_props[0].end_addr = acr->wpr_end >> 8;
 404         desc->regions.region_props[0].region_id = 1;
 405         desc->regions.region_props[0].read_mask = 0xf;
 406         desc->regions.region_props[0].write_mask = 0xc;
 407         desc->regions.region_props[0].client_mask = 0x2;
 408         flcn_acr_desc_dump(&acr->subdev, desc);
 409
 410         return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->pmu->falcon);
 411 }
 412
 413 static const struct nvkm_acr_hsf_func
 414 gm200_acr_load_0 = {
 415         .load = gm200_acr_load_load,
 416         .boot = gm200_acr_load_boot,
 417         .bld = gm200_acr_hsfw_bld,
 418 };
 419
 420 MODULE_FIRMWARE("nvidia/gm200/acr/bl.bin");
 421 MODULE_FIRMWARE("nvidia/gm200/acr/ucode_load.bin");
 422
 423 MODULE_FIRMWARE("nvidia/gm204/acr/bl.bin");
 424 MODULE_FIRMWARE("nvidia/gm204/acr/ucode_load.bin");
 425
 426 MODULE_FIRMWARE("nvidia/gm206/acr/bl.bin");
 427 MODULE_FIRMWARE("nvidia/gm206/acr/ucode_load.bin");
 428
 429 MODULE_FIRMWARE("nvidia/gp100/acr/bl.bin");
 430 MODULE_FIRMWARE("nvidia/gp100/acr/ucode_load.bin");
 431
 432 static const struct nvkm_acr_hsf_fwif
 433 gm200_acr_load_fwif[] = {
 434         { 0, nvkm_acr_hsfw_load, &gm200_acr_load_0 },
 435         {}
 436 };
 437
 438 static const struct nvkm_acr_func
 439 gm200_acr_0 = {
 440         .load = gm200_acr_load_fwif,
 441         .unload = gm200_acr_unload_fwif,
 442         .wpr_parse = gm200_acr_wpr_parse,
 443         .wpr_layout = gm200_acr_wpr_layout,
 444         .wpr_alloc = gm200_acr_wpr_alloc,
 445         .wpr_build = gm200_acr_wpr_build,
 446         .wpr_patch = gm200_acr_wpr_patch,
 447         .wpr_check = gm200_acr_wpr_check,
 448         .init = gm200_acr_init,
 449 };
 450
 451 static int
 452 gm200_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
 453 {
 454         struct nvkm_subdev *subdev = &acr->subdev;
 455         const struct nvkm_acr_hsf_fwif *hsfwif;
 456
 457         hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad",
 458                                     acr, "acr/bl", "acr/ucode_load", "load");
 459         if (IS_ERR(hsfwif))
 460                 return PTR_ERR(hsfwif);
 461
 462         hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload",
 463                                     acr, "acr/bl", "acr/ucode_unload",
 464                                     "unload");
 465         if (IS_ERR(hsfwif))
 466                 return PTR_ERR(hsfwif);
 467
 468         return 0;
 469 }
 470
 471 static const struct nvkm_acr_fwif
 472 gm200_acr_fwif[] = {
 473         {  0, gm200_acr_load, &gm200_acr_0 },
 474         { -1, gm200_acr_nofw, &gm200_acr },
 475         {}
 476 };
 477
 478 int
 479 gm200_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr)
 480 {
 481         return nvkm_acr_new_(gm200_acr_fwif, device, index, pacr);
 482 }